Semiconductor device

Abstract

Semiconductor device, exhibiting: - an n-type drift layer (1); - a p-type anode layer (2, 19) formed on an upper surface of the n-type drift layer (1); - a cathode layer (3, 13) formed on a lower surface of the n-type drift layer (1); and - an n-type buffer layer (4, 14) formed between the n-type drift layer (1) and the cathode layer (3, 13), where: - the highest impurity concentration in the n-type buffer layer (4, 14) is higher than that in the n-type drift layer (1) and lower than that in the cathode layer (3, 13), and - a gradient of charge carrier concentration in the n-type buffer layer (4, 14) at a connection between the n-type drift layer (1) and the n-type buffer layer (4, 14) over 20 cm -1 up to 2000 cm -1 is determined.

Description

Technical area

[0001] The present invention relates to a semiconductor device such as a diode for use in a power module with high withstand voltage (≥ 600 V). State of the art

[0002] Since the dawn of semiconductor technology in the 1950s, various studies have been conducted on a high-frequency oscillation phenomenon (see, for example, Non-Patent Literature 1) and a failure phenomenon (see, for example, Non-Patent Literature 2) in Si-based PIN diodes. These phenomena in power devices capable of operating at increasingly higher speeds lead to malfunctions of surrounding circuits and surge failures of the devices. In recent years, these phenomena have attracted renewed attention (see, for example, Non-Patent Literature 3).

[0003] It is known that in a high-speed recovery diode, these phenomena are noticeable under harsh recovery conditions, such as high Vcc, high wiring inductance (Ls), low operating temperature, and low current density (JA) (see, for example, Non-Patent Literature 5 and 11). Solutions to the above-described problem with high-speed recovery diodes have been achieved by enabling "soft recovery," e.g., by inserting a thick n - -type drift layer or a thick n-type buffer layer and applying a lifetime control technique (see, for example, Non-Patent Literature 5 to 7). However, these methods involve trade-offs between EMI (electromagnetic compatibility) noise, failure tolerance, and total loss, and it is difficult to ensure a high degree of compatibility between them.

[0004] On the other hand, the main properties of diodes have been remarkably improved by measures in which diodes have a p + -type layer in their back surfaces (see, for example, Non-Patent Literatures 4, 8, and 9), including RFC diodes (see, for example, Non-Patent Literatures 10 to 14). However, other development problems remain: difficulty in expanding the operating temperature range on the high-temperature side by reducing a leakage current, difficulty in improving the maximum destruction current density by reducing VF (a diode-on voltage drop) in a high-current-density region, and difficulty in improving surge discharge tolerance by strengthening the buffer structure.

[0005] A diode that connects a --type drift layer and an n-type cathode layer and an n-type buffer layer and an average impurity concentration between those of the n - -type drift layer and the n-type cathode layer has been proposed (see, for example, Non-Patent Literature 1 and 2). Although Patent Literature 1 does not describe a specific numerical value of the difference coefficient in the n-type buffer layer, a concentration gradient of 8 × 10 3 cm -4 out of Fig. 3 in Patent Literature 1. The n-type buffer layer in Patent Literature 2 consists of the structure described in Non-Patent Literature 10, and the concentration gradient therein is 1 × 10 5 cm -4 . Literature listPatent literature Patent Literature 1: Japanese Patent Application JP 2007- 158 320 A Patent Literature 2: Japanese Patent Application JP 2010- 283 132 A Non-patent literature Non-Patent Literature 1: WT READ, Jr. “A Proposed High-Frequency, Negative-Resistance Diode,” The Bell system technical journal, pp. 401-446 (March 1958) Non-Patent Literature 2: H. Egawa, “Avalanche Characteristics and Failure Mechanism of High Voltage Diodes,” IEEE Trans. Electron Devices, Issue ED-13, No.11, pp. 754-758 (1966) Non-Patent Literature 3: R. Siemieniec, P. Mourick, J. Lutz, M. Netzel, “Analysis of Plasma Extraction Transit Time Oscillations in Bipolar Power Devices,” Proc. ISPSD'04, pp. 249–252, Kitakyushu, Japan (2004) Non-Patent Literature 4: K. Satoh, K. Morishita, Y. Yamaguchi, N. Hirano, H. Iwamoto and A. Kawakami, "A Newly Structured High Voltage Diode Highlighting Oscillation Free Function in Recovery Process," Proc. ISPSD'2000, pp. 249-252, Toulouse, France (2000) Nicht-Patentliteratur 5: M.T. Rahimo and N. Y. A. Shammas, „Optimization of the Reverse Recovery Behavior of Fast Power Diodes Using Injection Efficiency And Lifetime Control Techniques,“ Proc. EPE'97, S. 2099-2104, Trondheim, Norwegen (1997) Nicht-Patentliteratur 6: M. Nemoto, T. Naito, A. Nishihara, K. Ueno, „MBBL diode: a novel soft recovery diode,“ Proc. ISPSD'04, S. 433-436, Kitakyushu, Japan Nicht-Patentliteratur 7: H. Fujii, M. Inoue, K. Hatade and Y. Tomomatsu, „A Novel Buffer Structure and lifetime control Technique with Poly-Si for Thin Wafer Diode,“ Proc. ISPSD'09, S. 140-143, Barcelona, Spain (2009) Nicht-Patentliteratur 8: A. Kopta and M. Rahimo, „The Field Charge Extraction (FCE) Diode A Novel Technology for Soft Recovery High Voltage Diodes,“ Proc. ISPSD'05, S. 83-86, Santa Barbara, Kalifornien, USA (2005) Nicht-Patentliteratur 9: H. P. Felsl, M. Pfaffenlehner, H. Schulze, J. Biermann, Th. Gutt, H. - J. Schulze, M. Chen and J. Luts, „The CIBH Diode - Great Improvement for Ruggedness and Softness of High Voltage Diodes,“ Proc. ISPSD'08, S. 173-176, Orlando, Florida, USA (2008) Nicht-Patentliteratur 10: K. Nakamura, Y. Hisamoto, T. Matsumura, T. Minato and J. Moritani, „The Second Stage of a Thin Wafer IGBT Low Loss 1200V LPT-CSTBTTM with a Backside Doping Optimization Process,“ Proc. ISPSD'06, S. 133-136, Neapel, Italien (2006) Nicht-Patentliteratur 11: K. Nakamura, H. Iwanaga, H. Okabe, S. Saito and K. Hatade, „Evaluation of Oscillatory Phenomena in Reverse Operation for High Voltage Diodes,“ Proc. ISPSD'09, S. 156-159, Barcelona, Spanien (2009) Nicht-Patentliteratur 12: K. Nakamura, F. Masuoka, A. Nishii, K. Sadamatsu, S. Kitajima and K. Hatade, „Advanced RFC Technology with New Cathode Structure of Field Limiting Rings for High Voltage Planar Diode,“ Proc. ISPSD'10, pp. 133-136, Hiroshima, Japan (2010) Nicht-Patentliteratur 13: A. Nishii, K. Nakamura, F. Masuoka and T. Terashima, „Relaxation of Current Filament due to RFC Technology and Ballast Resistor for Robust FWD Operation,“ Proc. ISPSD'11, S. 96-99, San Diego, Kalifornien, USA (2011) Nicht-Patentliteratur 14: F. Masuoka, K. Nakamura, A. Nishii and T. Terashima, „Great Impact of RFC Technology on Fast Recovery Diode towards 600 V for Low Loss and High Dynamic Ruggedness,“ Proc. ISPSD'12, S. 373-376, Bruges, Belgien (2012)

[0006] US 2010 / 0 203 710 A1 describes a method for manufacturing a semiconductor device by thinning a substrate by grinding and performing ion implantation. In a diode in which a P-anode layer and an anode electrode are formed on one side of a front surface of an N-drift layer and an N + -cathode layer and a cathode electrode are formed on a back side of the N-drift layer, an N-cathode buffer layer is thick compared to the N + -type cathode layer between the N - -type drift layer and the N + -cathode layer is formed, with the buffer layer having a high concentration compared to the N drift layer and a low concentration compared to the N + -cathode layer. When a reverse bias is applied, a depletion layer in the center of the N-cathode buffer layer is stopped and thus prevented from +-cathode layer so that leakage current is suppressed. Summary of the inventionTechnical problem

[0007] In conventional semiconductor devices, the gradient of the charge carrier concentration in the junction between the n - -type drift layer and the n-type buffer layer as steep as 8 × 10 3 cm -4 or 8 × 10 5 cm -4 , and therefore, as the intensity of the electric field increases, a snap-off occurs at the junction. Another problem is that a snap-off triggers high-frequency oscillation.

[0008] The VF recovery loss and EREC compensation characteristics of conventional diodes have been adjusted by a lifetime control method using heavy metal diffusion or electron or ion irradiation. However, variations in VF and EREC are increased depending on, for example, the irradiation angle and the temperature of the irradiated part at the time of electron or ion irradiation. Furthermore, crystal lattice defects are altered by self-heating during chip excitation operation, causing changes in electrical properties. Furthermore, thermal runaway occurs during high-temperature operation due to high leakage current caused by crystal lattice defects. Therefore, there has been a need to introduce a method for controlling VF and EREC compensation characteristics without depending on the lifetime control method.

[0009] Power devices have been used for various applications, and a need has arisen for surge-tolerance performance of IGBTs, diodes, etc. However, a semiconductor device having a parasitic bipolar transistor structure exhibits reduced surge-tolerance performance compared to semiconductor devices that do not have such a structure. If the thickness of the n--type drift layer is reduced to improve VF-EREC characteristics, the surge-tolerance performance is significantly reduced. Furthermore, a semiconductor device having a parasitic bipolar transistor structure exhibits a reduced maximum controllable current density compared to semiconductor devices that do not have such a structure.

[0010] The present invention has been realized to solve the problems described above. A first object of the present invention is to provide a semiconductor device capable of achieving high oscillation tolerance. A second object of the present invention is to provide a semiconductor device capable of increasing surge discharge tolerance and maximum controllable current density by improving a VF-EREC compensation characteristic without depending on the lifetime control method. Means to solve the problems

[0011] The object underlying the invention is achieved in a semiconductor device according to the invention with the features of claim 1 and alternatively in a semiconductor device according to the invention with the features of claim 13. Advantageous further developments are the subject of the respective dependent claims.

[0012] A semiconductor device according to a first aspect of the present invention comprises: an n-type drift layer; a p-type anode layer formed on an upper surface of the n-type drift layer; a cathode layer formed on a lower surface of the n-type drift layer; and an n-type buffer layer formed between the n-type drift layer and the cathode layer, wherein a highest impurity concentration in the n-type buffer layer is higher than that in the n-type drift layer and lower than that in the cathode layer, and a gradient of a carrier concentration in the n-type buffer layer at a junction between the n-type drift layer and the n-type buffer layer is 20 cm -4 up to 2000 cm -4 is.

[0013] A semiconductor device according to an alternative aspect of the present invention includes: an n-type drift layer, a p-type base layer formed on an upper surface of the n-type drift layer, an n-type emitter layer partially formed on the p-type base layer, a trench gate formed to extend through the n-type emitter layer and the p-type base layer, a p-type collector layer formed on a lower surface of the n-type drift layer, and an n-type buffer layer formed between the n-type drift layer and the p-type collector layer. A peak impurity concentration in the n-type buffer layer is higher than that in the n-type drift layer and lower than that in the p-type collector layer. Furthermore, a gradient of a carrier concentration in the n-type buffer layer at a junction between the n-type drift layer and the n-type buffer layer is 20 cm -1up to 2000 cm -1 set. Advantageous effects of the invention

[0014] The present invention makes it possible to achieve a high vibration tolerance. Short description of the drawings Fig. 1 and Fig. 2 are a plan view and a bottom view of a semiconductor device according to Embodiment 1 of the present invention, respectively. Fig. 3 is a sectional view taken along a line I-II in Fig. 1 and Fig. 2. Fig. Figure 4 is a graph showing charge carrier concentrations as a function of depth. Fig. 5 is a graph showing V F , E REC , V snap-off and J A(break) depending on a difference coefficient ∇n buffer the charge carrier concentration. Fig. 6 is a sectional view of a semiconductor device according to Embodiment 2 of the present invention. Fig. 7 is a sectional view of a semiconductor device according to Embodiment 3 of the present invention. Fig. 8 is a sectional view of a semiconductor device according to a comparative example. Fig. Figure 9 is a graph showing the highest impurity concentration and diffusion depth in an n-type buffer layer used for a simulation. Fig. 10 is a graph showing the results of simulation of the dependence of the withstand voltage characteristic on the buffer layer thickness in the comparative example and the embodiment 3. Fig. 11 and Fig. 12 are graphs showing the results of simulation of the Vcc dependence on the snappy recovery waveform in the comparative example and in Embodiment 3. Fig. 13 is a view of a back surface of a semiconductor device according to Embodiment 4 of the present invention. Fig. 14 is a sectional view taken along a line I-II in Fig. 13. Fig. 15 is a sectional view taken along a line III-IV in Fig. 13. Fig. 16 is a bottom view of a modified example 1 of the semiconductor device according to Embodiment 4 of the present invention. Fig. 17 is a bottom view of a modified example 2 of the semiconductor device according to Embodiment 4 of the present invention. Fig. 18 is a sectional view of a semiconductor device according to Embodiment 5 of the present invention. Fig. 19 is a sectional view of a semiconductor device according to Embodiment 6 of the present invention. Fig. 20 is a sectional view of a semiconductor device according to Embodiment 7 of the present invention. Fig. 21 is a sectional view of a semiconductor device according to Embodiment 8 of the present invention. Fig. 22 is a sectional view of a semiconductor device according to Embodiment 9 of the present invention. Fig. 23 is a sectional view of a semiconductor device according to Embodiment 10 of the present invention. Fig. 24 is a sectional view of a semiconductor device according to Embodiment 11 of the present invention. Fig. 25 is a sectional view of a semiconductor device according to Embodiment 12 of the present invention. Fig. 26 is a sectional view of a semiconductor device according to Embodiment 13 of the present invention. Description of the embodiments

[0015] A semiconductor device according to embodiments of the present invention will be described with reference to the drawings. The same components are denoted by the same reference numerals, and repeated descriptions thereof may be omitted. Embodiment 1

[0016] Fig. 1 and Fig. 2 are a plan view and a bottom view of a semiconductor device according to Embodiment 1 of the present invention, respectively. Fig. 3 is a sectional view taken along a line I-II in Fig. 1 and Fig. 2. A p-type anode layer 2 is deposited on an upper surface of an n - -type drift layer 1. An n-type cathode layer 3 is provided on a lower surface of the n - -Type drift layer 1 is provided.

[0017] An n-type buffer layer 4 is between the n --type drift layer 1 and the n-type cathode layer 3. The highest impurity concentration in the n-type buffer layer 4 is higher than that in the n-type drift layer 1 and lower than that in the n-type cathode layer 3. An anode electrode 5 has ohmic contact with the p-type anode layer 2, while a cathode electrode 6 has ohmic contact with the n-type cathode layer 3.

[0018] Fig. Figure 4 is a graph showing charge carrier concentration as a function of depth. The depth of the n-type buffer layer 4 is given by D buffer the gradient of the charge carrier concentration at the junction between the n - -type drift layer and the n-type buffer layer, the term ∇n buffer [cm -1] is a difference coefficient of the function expressing the natural logarithm of the carrier concentration, ie, the gradient of the natural logarithm of the carrier concentration; an effective dose in the n-type buffer layer 4 is Φ eff [cm -2 ]; and the charge carrier concentration in the n - -Type drift layer 1 is n0 [cm -3 ]. The relationship between them is expressed by the following equation: ϕeff=∫0Dbuffern0exp(∇nbuffer⋅x)dx≈1×1012∼5×1012(cm−2)

[0019] Fig. 5 is a graph showing V F , E REC , V snap-off and J A(break) depending on the difference coefficient ∇n buffer the charge carrier concentration. V F is a voltage drop in the ON state; E REC is a recovery loss; V snap-off is an overvoltage at the time of a recovery; and J A(break)is the maximum controllable current density. The difference coefficient ∇n buffer is at 20cm -1 up to 2000cm -1 determined, based on this data, by V F , E REC and V snap-off to increase and J A(break) In the state of the art, the difference coefficient is about 10 5 cm -1 and is steeper than that in the present embodiment.

[0020] A deep buffer structure in which the charge carrier concentration at the junction between the n -The layer thickness gradually and extensively distributed between the n-type drift layer 1 and the n-type buffer layer 4 as in the present embodiment is called a CPL (Controlling Plasma Layer). This CPL buffer structure enables limiting an increase in electric field strength at this boundary at the time of recovery. As a result, snap-off caused by the increase in electric field strength on the cathode side and high-frequency oscillation triggered by the snap-off can be prevented, thus achieving high oscillation tolerance.

[0021] In addition, the effective dose Φ eff in the n-type buffer layer 4 to 1 × 10 12 cm -2 up to 5 × 10 12 cm -2 higher than those in the n - -type drift layer 1. The total dose in the n-type buffer layer 4 is thus essentially the total dose in the n --Type drift layer 1, so that the dielectric strength with each of the n - -type drift layer 1 and the n-type buffer layer 4 can be maintained. As a result, compared to the case where the n-type buffer layer 4 is not present, the thickness of the n - -Type drift layer 1, which is necessary to maintain the same withstand voltage, can be reduced, and the total loss can be reduced.

[0022] The charge carrier concentration n0 in the n - -type drift layer 1 is determined depending on the dielectric strength class. For example, in the case of a 600 V to 6500 V class, the charge carrier concentration n0 is 1 × 10 12 cm -3 up to 1 × 10 15 cm -3 . The surface concentration in the n-type cathode layer 3 is 1 × 10 19 cm -3 up to 5 × 10 20 cm -3and the diffusion depth in the n-type cathode layer 3 is 0.5 µm to 2 µm. The thickness D buffer the n-type buffer layer 4 is a function of n0, ∇n buffer and Φ eff , as shown in the equation above.

[0023] The ratio of the highest impurity concentration in the n-type buffer layer 4 and the highest impurity concentration in the n - -Type drift layer 1 is 1 × 10 -4 up to 5 × 10 -1 . The ratio of the depths of the n-type buffer layer 4 and the n - -Type drift layer 1 is 0.1 to 10. Embodiment 2

[0024] Fig. 6 is a sectional view of a semiconductor device according to Embodiment 2 of the present invention. While Embodiment 1 is a diode, the present embodiment is an IGBT (Insulated Gate Bipolar Transistor).

[0025] The p-type anode layer 2 is a p-type base layer, and the highest impurity concentration therein is 1.0 × 10 16 cm -3 up to 1.0 × 10 18 cm -3 . A p + -type diffusion layer 7 and an n + -type emitter layer 8 are partially formed in a wafer surface area on the p-type anode layer 2. The highest impurity concentration in the n + -type emitter layer 8 is 1.0 × 10 18 cm -3 up to 1.0 × 10 21 cm -3 , and the depth of the n + -Type emitter layer 8 is 0.2 µm to 1.0 µm.

[0026] A + -type layer 9 is between the p-type anode layer 2 and the n - -type drift layer 1. The highest impurity concentration in the n + -Type layer 9 is 1.0 × 10 15 cm -3 up to 1.0 × 10 17 cm -3 . The n +-Type layer 9 is 0.5 µm to 1.0 µm deeper than the p-type anode layer 2.

[0027] A trench gate 10 is provided in such a way that it extends through the n + -type emitter layer 8, the p-type anode layer 2 and the n + -type layer 9. An interlayer insulation layer 11 is provided on the trench gate 10. The anode electrode 5 is an emitter electrode connected to the p + -type diffusion layer 7. A p-type collector layer 12 is provided in place of the n-type cathode layer 3. The cathode electrode 6 is a collector electrode that has ohmic contact with the p-type collector layer 12.

[0028] The highest impurity concentration in the n-type buffer layer 4 is higher than that in the n - -type drift layer 1 and lower than that in the p-type collector layer 12. The difference coefficient of a carrier concentration at the junction between the n --type drift layer 1 and the n-type buffer layer 4 is on 20 cm -1 up to 2000 cm -1 as in embodiment 1. In addition, the effective dose Φ eff in the n-type buffer layer 4 to 1.0 × 10 12 cm -2 up to 5 × 10 12 cm -2 higher than the effective dose in the n - -type drift layer 1. The same effects as those of Embodiment 1 can thus be achieved even in the case of the IGBT. Embodiment 3

[0029] Fig. 7 is a sectional view of a semiconductor device according to Embodiment 3 of the present invention. The n-type cathode layer 3 and a p-type cathode layer 13 are alternately arranged side by side, instead of the single n-type cathode layer 3 in Embodiment 1. The cathode electrode 6 has ohmic contact with the n-type cathode layer 3 and the p-type cathode layer 13. Therefore, the p-type cathode layer 13 is short-circuited to the n-type cathode layer 3 by the cathode electrode 6. The maximum impurity concentration in the n-type cathode layer 3 is higher than that in the p-type cathode layer 13.

[0030] The relationship shown below is between the depth tn - the n - -type drift layer 1, the width Wn of the n-type cathode layer 3 and the width Wp of the p-type cathode layer 13. 2tn−≥(Wn+Wp)≥tn− / 10.

[0031] The effects of the present embodiment will be described in comparison with a comparative example. Specifically, the dependence of the peak impurity concentration and the diffusion depth in the n-type buffer layer 4 on Vrrm, snap-off tolerance, and recovery tolerance in the present embodiment designed to have a withstand voltage of 1700 V and a diode in the comparative example will be described. Fig. Figure 8 is a sectional view of the semiconductor device according to the comparative example. In the comparative example, the n-type buffer layer 4 is absent, and the n-type cathode layer 3 is a single layer.

[0032] The degree of tolerance of a recovery condition with respect to the peak voltage V snap-off in Fig. 4 of Non-Patent Literature 14 is referred to as snap-off tolerance. When the snap-off tolerance is larger, operation can be permitted under harsh recovery conditions such as higher applied voltage, lower current, lower temperature, and faster power cutoff. In addition, a safe operating range, which, as described in Fig. 7 of Non-Patent Literature 14, the recovery tolerance formed by the applied voltage Vcc and the maximum break current density JA(break) is referred to as the recovery tolerance. When the recovery tolerance is larger, recovery operation can be permitted under conditions of higher applied voltage and higher current density.

[0033] Fig. Figure 9 is a graph showing the maximum impurity concentration and diffusion depth in an n-type buffer layer used for a simulation. As shown in the graph, the n-type buffer layer 4 was approximated as a Gaussian distribution with the dose set to 3.75 × 10 12 cm -2 and setting a maximum impurity concentration and a diffusion depth, which are set by a triangular simulation. The thickness of the n - -type drift layer 1 was set constant, regardless of the thickness of the n-type buffer layer 4.

[0034] Fig. 10 is a graph showing the results of a simulation of the dependence of the withstand voltage curve on the buffer layer thickness in Comparative Example and Embodiment 3. Each diode was designed to have a withstand voltage of 1700 V. Fig. 11 and Fig. 12 are graphs showing the results of simulations of the Vcc dependence on the rapid recovery behavior in the comparative example and the embodiment 3. The highest impurity concentration in the n-type buffer layer 4 is 5 × 10 16 cm -3 and the thickness of the n-type buffer layer 4 is 1.5 µm for the Fig. 11 and 50 µm for the results shown in Fig. 12 results shown.

[0035] In the comparative example, electrons generated by impact ionization due to an increase in an electric field strength at the main junction flow under the high electric field in the n --type drift layer 1 to the cathode side. The electron concentration is thus higher than the charge carrier concentration in the buffer layer, so that the electric field gradient in the n-type buffer layer 4 is reversed according to Poisson's equation, and the electric field strength is increased both at the cathode side and at the main junction. In the comparative example, a negative differential resistance characteristic NDR of approximately JR = 10 A / cm appears more clearly. 2 , when the thickness of the n-type buffer layer 4 is increased. At approximately JR = 100 A / cm 2 up to 1000 A / cm 2 impact ionization is caused at both the main junction and the cathode side, and electrons and positive holes are transferred from the main junction side and the cathode side into the n - -type drift layer, resulting in secondary collapse.

[0036] On the other hand, in the present embodiment, a secondary breakdown appears at about JR = 1 A / cm 2 in the withstand voltage curve when no NDR characteristic appears in the withstand voltage curve, and when the thickness of the n-type buffer layer 4 is small. A secondary breakdown in this small current range leads to a reduction in a maximum turn-off current density and to a reduction in a surge discharge tolerance in a recovery SOA of the diode. Therefore, there is a need to increase the current at the point of occurrence of a secondary breakdown. In a diode structure that tends to exhibit an NDR characteristic, with an increase in the electric field on the cathode side at the time of recovery, a voltage surge and snap-off occur, and a high-frequency oscillation triggered thereby can easily occur (see Fig. 11 and Fig. 12). Therefore, it is necessary to bring the voltage withstand curve of the diode closer to a straight line so that an S-shaped curve due to an NDR characteristic and a secondary breakdown are not shown. By reading from Fig. 10, it can be said that thickening the n-type buffer layer 4 is preferable.

[0037] If the n-type buffer layer 4 is simply made thicker, while the thickness of the n - -type drift layer 1 remains unchanged, however, the resistance component in the ON state is increased, resulting in an increase (deterioration) of VF. In the present embodiment, therefore, the difference coefficient of a carrier concentration at the junction between the n - -type drift layer 1 and the n-type buffer layer 4 to 20 cm -1 up to 2000 cm -1gradual change of the concentration at the junction allows limiting the increase of the electric field strength at the junction at the time of recovery, while preventing secondary breakdown and NDR in the withstand voltage profile and limiting the increase of VF. As a result, snap-off caused by the increase of the electric field strength at the cathode side and high-frequency oscillation that occurs due to being triggered thereby can be prevented, thus achieving high oscillation tolerance.

[0038] The width expressed by (Wn + Wp) is called an RFC cell gap. If the RFC cell gap is set small, VF is increased and EREC is reduced. That is, the VF-EREC compensation curve is shifted to the high-speed side. Therefore, in a case where the present invention is applied to a freewheeling diode to be used in an inverter, the VF-EREC compensation characteristic can be adjusted by adjusting the RFC cell gap according to the use. However, if the RFC cell gap is set excessively small, the snap-off tolerance is reduced. Conversely, if the RFC cell gap is set excessively large, the recovery tolerance is reduced.

[0039] The ratio expressed by (Wp / (Wn + Wp)) is called the RFC cell short rate. When the RFC cell short rate is reduced, VF is increased and EREC is reduced. That is, the VF-EREC compensation curve is shifted to the high-speed side. Therefore, in a case where the present invention is applied to a freewheeling diode to be used in an inverter, the VF-EREC compensation characteristic can be adjusted by adjusting the RFC cell short rate according to the use. However, if the RFC cell short rate is set excessively small, the snap-off tolerance is reduced and the cutoff point is increased. Conversely, if the RFC cell short rate is set excessively large, the recovery tolerance is reduced.

[0040] Thus, in the present embodiment, the VF-EREC equalization characteristic can be controlled by adjusting the RFC cell gap or the RFC cell short rate without depending on the lifetime control method.

[0041] When the dose in the p-type cathode layer 13 is reduced, the snap-off tolerance is reduced. However, EREC and leakage current can be limited. When the dose in the p-type cathode layer 13 is increased, the opposite result is obtained. In this regard, in the present embodiment, the snap-off tolerance and recovery tolerance can be ensured, and the allowable adjustable range of the dose in the p-type cathode layer 13 can be expanded.

[0042] In a simple pn junction, the temperature dependence of VF is substantially positive, and current can flow more easily as the temperature is increased. When unevenness occurs in a temperature distribution of power chips connected in parallel in a high-power power module, positive feedback may occur, so that the current flowing through one of the chips, thereby generating more heat, is further increased, thus generating heat, and there is a possibility of resulting module failure. Therefore, it is desirable that the current value (crossing point) at which a room-temperature VF curve and a high-temperature VF curve intersect each other be lower. In the present embodiment, the efficiency of carrier injection from the anode and cathode can be reduced by reducing the effective doses in the anode and cathode.The crossing point at a lower current value can therefore be reached.

[0043] Alternatively, the arrangement may be such that the cathode electrode 6 has ohmic contact with the n-type cathode layer 3 and Schottky contact with the p-type cathode layer 13. Because the Schottky barrier difference between the cathode electrode 6 and the p-type cathode layer 13 is large, a state similar to that in a case where a resistance component is added to the parasitic PNP transistor is achieved, thereby enabling the current in the vertical device direction generated by the operation of the parasitic PNP transistor to be limited. As a result, a high recovery SOA and high surge discharge tolerance can be achieved. Embodiment 4

[0044] Fig. 13 is a back surface view of a semiconductor device according to Embodiment 4 of the present invention. Fig. 14 is a sectional view taken along a line I-II in Fig. 13. The n-type buffer layer 4 and the n-type buffer layer 14 are alternately disposed by being arranged side by side instead of the single n-type buffer layer 4 in Embodiment 3. The n-type buffer layer 4 is disposed between the n - -type drift layer 1 and the n-type cathode layer 3, while the n-type buffer layer 14 is provided between the n - -type drift layer 1 and the p-type cathode layer 13. The highest impurity concentration in the n-type buffer layers 4 and 14 is higher than that in the n --type drift layer 1 and lower than that in the n-type cathode layer 3. The peak impurity density in the n-type buffer layer 4 is higher than that in the n-type buffer layer 14. Otherwise, the structure is the same as that in Embodiment 3.

[0045] Fig. 15 is a sectional view taken along a line III-IV in Fig. 13. A region where the p-type anode layer 2 is provided is an active region. A region outside the active region is a terminal region. A conventional p-type guard ring layer 15 is provided in the terminal region on an anode side, and an n-type channel stopper layer 16 is provided in an outermost peripheral part of the terminal region. The highest impurity concentration in the p-type guard ring layer 15 is higher than that in the p-type anode layer 2. The highest impurity concentration in the n-type channel stopper layer 16 is higher than that in the n - -Type drift layer 1.

[0046] A cathode structure in the terminal region extends from a position at a distance WGR: 10 µm to 500 µm on the active region side from an outermost peripheral part of the p-type anode layer 2. The cathode structure in the terminal region consists of a two-layer structure formed of an n-type layer 17 and a p-type layer 18.

[0047] In the present embodiment, the efficiency of electron injection from the cathode side in the ON state is improved by increasing the dose in the n-type buffer layer 4 on the n-type cathode layer 3. When an electromotive force induced in an L-load circuit is applied to cause the device to enter a surge discharge state, it is difficult for the depletion layer to reach the p-type cathode layer 13, and NDR (Secondary Breakdown) in the withstand voltage curve is prevented. As a result, low VF and high surge tolerance can be achieved. The degree of tolerance of a surge discharge state is referred to as surge tolerance.

[0048] The n-type cathode layer 3 and the p-type cathode layer 13 form a stripe pattern. A pattern reflecting an assumed ratio of the n-type cathode layer 3 and the p-type cathode layer 13 can therefore be easily designed.

[0049] Fig. 16 is a bottom view of a modified example 1 of the semiconductor device according to Embodiment 4 of the present invention. Even in a case where the cathode in the terminal region is n-type, as in this example, the same effects as those described above can also be achieved.

[0050] Fig. 17 is a bottom view of a modified example 2 of the semiconductor device according to Embodiment 4 of the present invention. The n-type cathode layer 3 is a dot pattern. This enables pattern design that also considers the corner regions to realize uniform device operation. As a result, a high recovery SOA can be achieved. Even in the case where the p-type cathode layer 13 is a dot pattern, the same effects can be achieved. Embodiment 5

[0051] Fig. 18 is a sectional view of a semiconductor device according to Embodiment 5 of the present invention. The depth of the n-type buffer layer 4 is greater than that of the n-type buffer layer 14. Otherwise, the structure is the same as that of Embodiment 4. In this case, too, the same effects as those of Embodiment 4 can be achieved. Embodiment 6

[0052] Fig. 19 is a sectional view of a semiconductor device according to Embodiment 6 of the present invention. The p-type anode layer 2 and a p-type anode layer 19 are alternately disposed by being arranged side by side, instead of the single p-type anode layer 2 in Embodiment 4. The anode electrode 5 has ohmic contact with the p-type anode layers 2 and 19. Therefore, the p-type anode layer 19 is short-circuited to the p-type anode layer 2 by the anode electrode 5. The peak impurity concentration in the p-type anode layer 19 is lower than that in the p-type anode layer 2. The ratio of the peak impurity concentration of the p-type anode layer 2 to that of the p-type anode layer 19 is more than 1.0 to 500.

[0053] As a result of providing the p-type anode layer 19 with a low concentration, the injection efficiency on the anode side in the ON state is limited, and the carrier concentration on the anode side in the ON state is therefore reduced, thereby enabling a limitation of an increase in an electric field strength on the cathode side, which acts as an oscillation stimulus. In addition, the carrier in the n - -type drift layer 1 in the ON state is reduced. A phenomenon in which the carrier is concentrated at the boundary between the terminal region and the active region at the time of recovery, thus causing failure, can therefore be prevented. As a result, high recovery SOA, high oscillation tolerance, low VF, low crossover point, and high surge current tolerance can be achieved. Embodiment 7

[0054] Fig. 20 is a sectional view of a semiconductor device according to Embodiment 7 of the present invention. The p-type anode layer 19 is provided only in a portion of the upper surface of the p-type anode layer 2. The ratio of the depth of the p-type anode layer 19 to the depth of the p-type anode layer 2 is 0.1 to 0.9. In this case, the same effects as those of Embodiment 6 can be achieved. Embodiment 8

[0055] Fig. Fig. 21 is a sectional view of a semiconductor device according to Embodiment 8 of the present invention. Only the single n-type layer 17 is formed on the bottom surface of the n - -type drift layer 1 is provided in the connection region. The cathode electrode 6 is electrically connected by making contact with the n-type layer 17. The n-type layer 17 has a maximum impurity concentration of 1 × 10 15 cm -3 up to 1 × 10 16 cm -3The contact resistance of the n-type buffer layer 14 to the cathode electrode 6 is thereby increased. Electron injection from the cathode side of the terminal region in the ON state can therefore be limited to improve recovery SOA. Embodiment 9

[0056] Fig. 22 is a sectional view of a semiconductor device according to Embodiment 9 of the present invention. The n-type buffer layer 4 is a single layer. The n-type layer 17 in the cathode structure in the terminal region is also a single layer. Thus, the structure can be further simplified from that in Embodiment 8. Embodiment 10

[0057] Fig. 23 is a sectional view of a semiconductor device according to Embodiment 10 of the present invention. An n-type channel stopper buffer layer 20 is provided in an outermost peripheral part of the terminal region. An n-type channel stopper layer 21 and a p-type channel stopper layer 22 are provided in the n-type channel stopper buffer layer 20. The highest impurity concentration in the n-type channel stopper buffer layer 20 is higher than that in the n-type channel stopper buffer layer 20. - -type drift layer 1. The highest impurity concentration in the n-type channel stopper layer 21 is higher than that in the n-type channel stopper buffer layer 20 and than that in the p-type channel stopper layer 22. Thereby, a high recovery SOA can be achieved. Embodiment 11

[0058] Fig. 24 is a cross-sectional view of a semiconductor device according to Embodiment 11 of the present invention. A LNFLR (Linearly Narrowed Field Limiting Ring) structure 23 is provided instead of the conventional p-type guard ring layer 15. The LNFLR structure 23 is a plurality of p-type layers periodically arranged in parallel from the active region toward the terminal region. The plurality of p-type layers has a linear concentration gradient toward the terminal region.

[0059] A RESURF (Reduced Surface Field) structure 24 is provided between the p-type anode layer 2 in the active region and the LNFLR structure 23. The RESURF structure 24 has a deep p-type layer formed at the end of the active region and a p-type layer of the same diffusion depth as that of the diffusion layer in the LNFLR structure 23. The dose in the RESURF structure 24 is 2 × 10 12 m -2, and the width of the RESURF structure 24 is 5 µm to 100 µm. The steepness of the peak value of the electric field strength at the time of recovery can be reduced by providing the RESURF structure 24. Embodiment 12

[0060] Fig. 25 is a sectional view of a semiconductor device according to Embodiment 12 of the present invention. In the present embodiment, a VLD (Variation of Lateral Doping) structure 25 is provided instead of the RESURF structure 24 in Embodiment 11. The VLD structure 25 includes a deep p-type layer formed at the end of the active region and a gradient p-type layer for connecting the depth of the deep p-type layer to the depth of the LNFLR diffusion layer. Embodiment 13

[0061] Fig.26 is a sectional view of a semiconductor device according to Embodiment 13 of the present invention. An IGBT is provided in the active region, while the LNFLR structure 23 is provided in the terminal region. In this case, the same effects as those of Embodiment 11 can be achieved.

[0062] The semiconductor device in the present application is not limited to those formed of silicon. The semiconductor device in the present application may also be a device formed of a wide-bandgap semiconductor having a bandgap larger than that of silicon. The wide-bandgap semiconductor is, for example, silicon carbide, a gallium nitride-based material, or diamond. A semiconductor device formed of such a wide-bandgap semiconductor has high withstand voltage characteristics and allowable current density and can therefore be made small. This small-sized device can be used to enable the semiconductor module incorporating this device to be made small.Because the thermal resistance of the element is high, the heat-dissipating fins of the heat sink can be reduced in size, and a water-cooled part can be replaced with an air-cooled part. The semiconductor module can therefore be further reduced in size. The power loss in the element is also low, and the efficiency of the element is high. The efficiency of the semiconductor module can therefore be improved.

[0063] Although devices in a lower or middle class, such as the 1200 V or 1700 V class, have been described by way of example in the descriptions of the embodiments, the effects described above can be achieved regardless of the withstand voltage class. Description of reference symbols

[0064] 1 n --type drift layer; 2, 19 p-type anode layer; 3 n-type cathode layer; 4, 14 n-type buffer layer; 6 cathode electrode; 12 p-type collector layer; 13 p-type cathode layer; 17 n-type layer; 20 n-type channel stopper buffer layer; 21 n-type channel stopper layer; 22 p-type channel stopper layer; 23 LNFLR structure; 24 RESURF structure; 25 VLD structure

Claims

[1] Semiconductor device, comprising: - an n-type drift layer (1); - a p-type anode layer (2, 19) formed on an upper surface of the n-type drift layer (1); - a cathode layer (3, 13) formed on a lower surface of the n-type drift layer (1); and - an n-type buffer layer (4, 14) formed between the n-type drift layer (1) and the cathode layer (3, 13), where: - a maximum impurity concentration in the n-type buffer layer (4, 14) is higher than that in the n-type drift layer (1) and lower than that in the cathode layer (3, 13), and - a gradient of a charge carrier concentration in the n-type buffer layer (4, 14) at a junction between the n-type drift layer (1) and the n-type buffer layer (4, 14) to 20 cm -1 up to 2000 cm -1 is set. [2] A semiconductor device according to claim 1, wherein the cathode layer (3, 13) is either of an n-type or a p-type. [3] A semiconductor device according to claim 1 or 2, wherein the cathode layer (3, 13) comprises an n-type cathode layer (3) and a p-type cathode layer (13) which are alternately formed and arranged side by side. [4] A semiconductor device according to claim 3, wherein: - the n-type buffer layer (4, 14) comprises a first n-type buffer layer (4) formed between the n-type drift layer (1) and the n-type cathode layer (3), and a second n-type buffer layer (14) formed between the n-type drift layer (1) and the p-type cathode layer (13), and - a highest impurity concentration in the first n-type buffer layer (4) is higher than that in the second n-type buffer layer (14). [5] A semiconductor device according to claim 3 or 4, further comprising a cathode electrode (6) having an ohmic contact with the n-type cathode layer (3) and a Schottky contact with the p-type cathode layer (13). [6] A semiconductor device according to any one of claims 3 to 5, wherein the n-type cathode layer (3) and the p-type cathode layer (13) form a stripe pattern. [7] A semiconductor device according to any one of claims 3 to 5, wherein the n-type cathode layer (3) or the p-type cathode layer (13) forms a dot pattern. [8] A semiconductor device according to any one of the preceding claims, wherein: - the p-type anode layer (2, 19) comprises a first p-type anode layer (2) and a second p-type anode layer (19) having a lower maximum impurity concentration than the first p-type anode layer (2), and - a ratio of a highest impurity concentration in the first p-type anode layer (2) to that in the second p-type anode layer (19) is more than 1.0 to 500. [9] A semiconductor device according to claim 8, wherein a ratio of a depth of the second p-type anode layer (19) to a depth of the first p-type anode layer (2) is 0.1 to 0.

9. [10] A semiconductor device according to any one of the preceding claims, comprising: - an n-type layer (17) formed on a lower surface of the n-type drift layer (1) in a terminal region and having a highest impurity concentration of 1.0 × 10 15 cm -3 up to 1.0 × 10 16 cm -3 has; and - a cathode electrode (6) which is electrically connected to the cathode layer and the n-type layer (17) by being brought into contact. [11] Semiconductor device according to one of the preceding claims, comprising: - an n-type channel stopper buffer layer (20) formed in an outermost peripheral part of a terminal region; and - an n-type channel stopper layer (21) and a p-type channel stopper layer (22) formed in the n-type channel stopper buffer layer (20), where: - a maximum impurity concentration in the n-type channel stopper buffer layer (20) is higher than that in the n-type drift layer (1), and - a highest impurity concentration in the n-type channel stopper layer (21) is higher than that in the n-type channel stopper buffer layer (20) and that in the p-type channel stopper layer (22). [12] A semiconductor device according to any one of claims 1 to 11, further comprising: - an LNFLR structure (23) formed in a connection region; and - a VLD structure (25) formed in an outer end part of the p-type anode layer (2, 19). [13] Semiconductor device, comprising: - an n-type drift layer (1); - a p-type base layer (2) formed on an upper surface of the n-type drift layer (1); - an n-type emitter layer (8) partially formed on the p-type base layer (2), - a trench gate (10) which is designed to extend through the n-type emitter layer (8) and the p-type base layer (2), - a p-type collector layer (12) formed on a lower surface of the n-type drift layer (1), and - an n-type buffer layer (4, 14) formed between the n-type drift layer (1) and the p-type collector layer (12), where: - a maximum impurity concentration in the n-type buffer layer (4, 14) is higher than that in the n-type drift layer (1) and lower than that in the p-type collector layer (12), and - a gradient of a charge carrier concentration in the n-type buffer layer (4, 14) at a junction between the n-type drift layer (1) and the n-type buffer layer (4, 14) to 20 cm -1 up to 2000 cm -1 is set. [14] A semiconductor device according to claim 1 or 13, wherein an effective dose in said n-type buffer layer (4, 14) is 1 × 10 12 cm -2 up to 5 × 10 12 cm -2 higher than that in the n-type drift layer (1). [15] A semiconductor device according to any one of claims 1 to 11 or 13, further comprising: - an LNFLR structure (23) formed in a connection region; and - a RESURF structure (24) formed in an outer end part, in particular of the p-type anode layer (2, 19) or the p-type base layer (2).

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