Displays with silicon and semiconductor oxide thin-film transistors

Abstract

Display (14), comprising: - a substrate (24); - an array of display pixels (22) on the substrate (24); - a display driver circuit formed from thin-film transistors on the substrate (24), wherein the display driver circuit includes a silicon thin-film transistor (216) and wherein the array of display pixels (22) includes at least one semiconductor oxide thin-film transistor (240); - a first metal layer structured to form a gate (218) for the silicon thin-film transistor (216) and a gate (228) for the semiconductor oxide thin-film transistor (240); - a second metal layer structured to form source / drain contacts (222, 226) for the at least one semiconductor oxide thin-film transistor (240); - a third metal layer (504) structured to form at least is coupled to one of the source / drain contacts (222, 226);- a first dielectric layer (232B) arranged between the second and third metal layers (504), wherein the first dielectric layer (232B) is an organic dielectric layer; - a fourth metal layer structured to form display pixel electrodes (230); - a fifth metal layer structured to form a common electrode (234); and - a second dielectric layer (232A) arranged between the third metal layer (504) and the fourth metal layer, wherein the second dielectric layer (232A) is an organic dielectric layer.

Description

[0001] This application claims priority over US Continuation-in-part patent application No. 14 / 249,716, filed on April 10, 2014, US patent application No. 14,228,098, filed on March 27, 2014, US patent application No. 14 / 229,232, filed on March 28, 2014, US patent application No. 14,228,070, filed on March 27, 2014, and provisional patent application No. 61 / 869,937, filed on August 26, 2013, which are hereby incorporated in their entirety by reference. BACKGROUND

[0002] This generally refers to electronic devices, and in particular electronic devices with displays that have thin-film transistors.

[0003] Electronic devices often include displays. For example, mobile phones and portable computers include displays to show information to users.

[0004] Displays such as liquid crystal displays (LCDs) are composed of multiple layers. For example, an LCD might have top and bottom polarizer layers, a color filter layer containing an array of color filter elements, a thin-film transistor layer enclosing thin-film transistors and display pixel electrodes, and a layer of liquid crystal material sandwiched between the color filter layer and the thin-film transistor layer. Each display pixel typically includes a thin-film transistor to control the application of a signal to the pixel electrode structures within the display pixel.

[0005] Displays such as organic light-emitting diode (OLED) displays have an array of LED-based display pixels. In this type of display, each pixel contains an LED and thin-film transistors to control the application of a signal to the LED.

[0006] Thin-film display driver circuits are frequently included in displays. For example, gate driver circuits and demultiplexer circuits in a display can be formed from thin-film transistors.

[0007] Careless handling of thin-film transistor circuits in display pixels and display driver circuits can lead to inconsistencies, excessive leakage currents, insufficient driver strength, poor area efficiency, hysteresis, and other problems. Therefore, it would be desirable to be able to provide improved displays for electronic devices. SUMMARY

[0008] An electronic device can be equipped with a display. The display can consist of an array of display pixels on a substrate. The display pixels can be organic light-emitting diode (OLED) pixels or display pixels in a liquid crystal display.

[0009] Organic light-emitting diode (OLED) displays can employ hybrid thin-film transistor structures, including semiconductor oxide thin-film transistors, silicon thin-film transistors, and capacitor structures. The capacitor structures can overlap the semiconductor oxide thin-film transistors. Capacitor structures can also consist of multiple overlapping electrode layers made up of source-drain metal layers, and a polysilicon layer and a gate metal layer can be used.

[0010] OLED display pixels can contain combinations of oxide and silicon transistors. Transistors such as driver transistors coupled to light-emitting diodes can be formed from oxide transistor structures, and switching transistors can be formed from silicon transistor structures.

[0011] In a liquid crystal display, a display driver circuit may include a silicon thin-film transistor circuit, and display pixels may be based on oxide thin-film transistors. A single layer or two different gate metal layers may be used in the formation of silicon transistor gates and oxide transistor gates. A silicon transistor may have a gate that overlaps a floating-gate structure. Oxide transistors may be incorporated into display driver circuits.

[0012] Display driver circuits can be configured to expose silicon transistor circuits in an array of display pixels to lower voltage fluctuations than oxide transistor circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Fig. Figure 1 is a diagram of an exemplary display, such as an organic light-emitting diode display, which has an array of OLED display pixels or a liquid crystal display with an array of display pixels according to one embodiment.

[0014] Fig. Figure 2 is a diagram of an exemplary OLED display pixel of the type that can be used in an organic light-emitting diode with semiconductor oxide thin-film transistors and silicon thin-film transistors according to one embodiment.

[0015] Fig. Figure 3 is a side cross-sectional view of exemplary thin-film transistor structures according to one embodiment.

[0016] Fig. Figure 4 is a side view of additional exemplary thin-film transistor structures according to one embodiment.

[0017] Fig. Figure 5 is a diagram of an exemplary OLED display pixel of the type which may include oxide thin-film transistors and silicon thin-film transistors according to one embodiment.

[0018] Fig. 6, Fig. 7 and Fig. Figure 8 shows cross-sectional views of exemplary thin-film transistor circuits in a liquid crystal display according to one embodiment.

[0019] Fig. Figure 9 is a diagram of an exemplary complementary metal oxide semiconductor transistor inverter of the type that can be formed from a hybrid silicon oxide transistor structure according to one embodiment.

[0020] Fig. Figure 10 is a side cross-sectional view of an exemplary thin-film transistor structure of the type that can be used to form a complementary hybrid silicon oxide transistor inverter according to one embodiment.

[0021] Fig. Figure 11 is a circuit diagram of a gate driver circuit in thin-film display driver circuits according to one embodiment.

[0022] Fig. Figure 12 is a diagram of a level converter of the type used in the gate driver circuit. Fig. 11 can be used in display driver circuits in a display according to one embodiment.

[0023] Fig. Figure 13 is a circuit diagram of an exemplary circuit which can be used to prevent transistors in the display driver circuit of a display from being subjected to excessive voltages according to one embodiment.

[0024] Fig. Figure 14 is a side cross-sectional view of an exemplary thin-film transistor circuit in a liquid crystal display according to one embodiment.

[0025] Fig. Figure 15 is a side cross-sectional view of an exemplary thin-film transistor circuit including an upper gate semiconductor oxide transistor in a liquid crystal display according to one embodiment.

[0026] Fig. Figure 16 is a side cross-sectional view of an exemplary thin-film transistor circuit incorporating an upper gate semiconductor oxide transistor with a light shield in a liquid crystal display according to one embodiment.

[0027] Fig. Figure 17 is a side cross-sectional view of an exemplary thin-film transistor circuit including an upper gate semiconductor oxide transistor in a liquid crystal display according to one embodiment.

[0028] Fig. Figure 18 is a side cross-sectional view of an exemplary thin-film transistor circuit incorporating an upper gate semiconductor oxide transistor in an organic light-emitting diode display according to one embodiment. DETAILED DESCRIPTION

[0029] A display in an electronic device can be provided with driver circuitry for displaying images via an array of display pixels. An example display is shown in Fig. 1 shown. According to the illustration in Fig. 1. Can the display 14 one or more layers, such as a substrate 24 have layers like the substrate 24 They can be formed from flat, rectangular layers of material, such as flat layers of glass. The display 14 can be an array of display pixels 22 to display images for a user. The array of display pixels 22can consist of rows and columns with display pixel structures on a substrate 24 It can be formed with any suitable number of rows and columns in the array of display pixels. 22 give (e.g. ten or more, one hundred or more, or one thousand or more).

[0030] Display driver circuitry such as integrated display driver circuitry 16 can be connected to conductive traces such as metal traces on the substrate 24 It must be coupled using solder or conductive adhesive. The integrated display driver circuit 16 (occasionally referred to as a timing controller chip) can be a communication circuit for communicating with the system control circuit via a path 25 contained. The path 25It can be formed from traces on a flexible printed circuit board or other cable. The control circuitry can be located on a mainboard in an electronic device such as a mobile phone, computer, set-top box, media player, portable electronic device, or other electronic device that controls the display. 14 is used. During operation, the control circuit can use the integrated display driver circuit. 16 provide information about images displayed on the screen 14 to be displayed. To display the images on the display pixels. 22 can the integrated display driver circuit 16 It directs the corresponding image data to the data lines D, while sending clock signals and other control signals to the supporting thin-film transistor display driver circuit, such as the gate driver circuit. 18 and the demultiplexer circuit20 spends.

[0031] The gate driver circuit 18 can be applied to the substrate 24 be formed (e.g., on the right and left edges of the display) 14 , on only one edge of the display 14 or elsewhere on the display 14 The demultiplexer circuit 20 can be used to obtain data signals from the integrated display driver circuit 16 to unbundle a large number of corresponding data lines D. In the exemplary arrangement of Fig. 1. The data lines D run vertically through the display. 14 Each data line D corresponds to a specific column of display pixels. 22 assigned. The gate lines G run horizontally through the display. 14 Each gate line G corresponds to a row of display pixels. 22 The gate driver circuit is assigned. 18 can be shown in the illustration Fig. 1 on the left side of the display 14 , on the right side of the display 14 or both on the left and right sides of the display 14 be arranged as in Fig. 1. shown.

[0032] The gate driver circuit 18 Gate signals (occasionally referred to as sampling signals) can be displayed on the gate lines G. 14 For example, the gate driver circuit can determine this. 18 Clock signals and other control signals from the integrated display driver circuit 16 received and, in response to the received signals, sequentially and starting with the gate line signal G in the first row of display pixels 22 Detect a gate signal on the gate lines G. Upon detection of each gate line, the corresponding display pixels in the row where the gate line is detected show the display data that occurs on the data lines D.

[0033] Display driver circuits such as the demultiplexer circuit 20 and the gate line driver circuit 18 can be made from thin-film transistors on the substrate 24 Thin-film transistors can also be used in the formation of circuits in display pixels. 22 can be used. To improve display performance, the following can be done with the display: 14 Thin-film transistor structures are used that meet desired criteria, such as leakage current, switching speed, driver strength, uniformity, etc. The thin-film transistors in the display 14 can generally be formed using any type of thin-film transistor technology (e.g. silicon-based, semiconductor oxide-based, etc.).

[0034] With a suitable arrangement, occasionally described herein as an example, the channel region (active region) of some thin-film transistors is on the display 14formed from silicon (e.g. silicon such as polysilicon deposited using a low-temperature process, sometimes referred to as LTPS or low-temperature polysilicon), and the channel region in other thin-film transistors at the display 14is formed from a semiconductor oxide material (e.g., amorphous indium gallium zinc oxide, sometimes referred to as IGZO). If required, other semiconductor types can be used to form the thin-film transistors, such as other amorphous silicon semiconductor oxides besides IGZO, etc. In a hybrid display configuration of this type, silicon transistors (e.g., LTPS transistors) can be used if attributes such as high or low light sensitivity are desired. B. switching speed and good driver strength are desired (e.g. for gate drivers in liquid crystal diode displays or in sections of an OLED display pixel where switching speed matters), while oxide transistors (e.g. IGZO transistors) can be used when low leakage current is desired (e.g. in liquid crystal diode display pixels and display driver circuits) or when high uniformity between individual pixels is desired (in an array of OLED display pixels).Other aspects can also be taken into account (e.g., aspects relating to electricity consumption, space requirements, hysteresis, etc.).

[0035] Oxide transistors, such as IGZO thin-film transistors, are generally n-channel devices (i.e., NMOS transistors). Silicon transistors can be fabricated using p-channel or n-channel designs (i.e., LTPS devices can be either PMOS or NMOS). Combinations of these thin-film transistor structures can provide optimal performance.

[0036] In an organic light-emitting diode (OLED) display, each display pixel contains a corresponding organic light-emitting diode. A schematic diagram of an example OLED display pixel. 22-1 is in Fig. 2. shown. According to the illustration in Fig. 2 can be the display pixel 22-1 a light-emitting diode 26Include a positive power supply voltage ELVDD. 34 a ground power supply voltage (ELVSS) can be connected to the ground power supply terminal. 36 be guided. The status of the driver transistor 28 controls the amount of current flowing through the diode 26 flows and thus the amount of data from the display pixel 22-1 emitted light 40 .

[0037] To ensure that the transistor 28 If a pixel is held in a desired state between successive data frames, it can be used to... 22-1 Include a storage capacitor, such as the storage capacitor Cst. The voltage across the storage capacitor Cst is applied to the gate of the transistor. 28 at node A for controlling the transistor 28 Data can be processed using one or more switching transistors, such as the switching transistor.30 are charged into the storage capacitor Cst. When the switching transistor 30 When switched off, the data line D is isolated from the storage capacitor Cst, and the gate voltage at terminal A is equal to the data value stored in the storage capacitor Cst (i.e., the data value from the previous frame displayed). 14 (displayed display data). If the gate line G (occasionally referred to as the sampling line) is in the display pixel 22-1 The assigned line is claimed, the switching transistor 30 The transistor is switched on, and a new data signal on data line D is loaded into the storage capacitor Cst. The new signal at capacitor Cst then activates the gate of the transistor. 28 applied to node A, thereby changing the status of the transistor. 28 and the corresponding amount of light emitted by the LED 26 emitting light 40 be adapted.

[0038] OLED display pixels like the pixel 22-1 out of Fig. 2. The thin-film transistor structures of the in Fig. 3. Use the type shown. This type of structure uses two different types of semiconductors. As shown in Fig. 3 can the circuit 72 Include display pixel structures, such as the LED cathode connector. 42 and the LED anode connection 44 Emissive OLED material 47 can be between the cathode 42 and the anode 44 be inserted. The dielectric layer 46 It can be used to define the layout of the display pixels and is sometimes referred to as the pixel definition layer. The planarization layer 50 can be achieved via thin-film transistor structures 52 be trained. The thin-film transistor structures 52 can on the buffer layer 54 on the substrate24 be trained.

[0039] The thin-film transistor structures 52 can the silicon transistor 58 include the transistor 58 It can be an LTPS transistor designed with a “top-gate” configuration, and it can serve as a switching transistor in an OLED display pixel (see, for example, the transistor). 30 in the pixel 22-1 out of Fig. 2) The transistor 58 can form a polysilicon channel 62 have, which passes through the gate insulating layer 64 is covered (e.g., with a silicon dioxide layer). The gate 66 It can be formed from structured metal (for example, molybdenum). The gate 66 may be covered by a dielectric intermediate layer (e.g., a silicon nitride layer). 68 and a silicon dioxide layer 70 Source-drain contacts 74 and 76 opposite sides of the polysilicon layer can 62contact us to discuss the silicon thin-film transistor 58 to form.

[0040] The thin-film transistor structures 52 Thin-film transistor and capacitor structures are also possible 60 include the structures 60 can include a storage capacitor (i.e., the storage capacitor Cst from Fig. 2) and an oxide thin-film transistor structure. The storage capacitor may have a first terminal (occasionally referred to as a plate, electrode, or electrode layer) consisting of the polysilicon layer. 62' is formed (as part of the same layer as the layer 62 structured). The gate insulating layer 64' , which is an extended section of the gate insulating layer 64 It may be, the connection 62' cover. The capacitor may have a second terminal made from the metal layer. 66' is formed. The metal layer 66'can be structured from the same metal layer used to form the gate 66 of the transistor 58 is used. The dielectric layers 68 and 70 can the metal layer 66' cover. The thin-film transistor in the structures 60 It could be a "bottom-gate" oxide transistor. The layer 66' , which serves as the second terminal of the capacitor Cst (i.e., as node A from Fig. 2) can also serve as the gate of the oxide transistor. The oxide transistor can be used as a driver transistor. 28 out of Fig. 2. serve. The “gate insulator” of the oxide transistor can be formed from the dielectric intermediate layer (i.e., from the layers). 68 and 70 The channel semiconductor of the oxide transistor can be extracted from the oxide layer. 80 may be formed (e.g., IGZO). The oxide layer 80 can the electrode layer 62'The polysilicon capacitor overlaps (i.e., the oxide transistor can overlap the capacitor), thus saving space. Source-drain connections 82 and 84 can be made of metal, which forms the opposite end of the semiconductor oxide layer 80 contacted.

[0041] Transistors such as LTPS transistors and oxide transistors can be designed with different layouts. For example, LTPS transistors tend to have high carrier mobilities. Accordingly, LTPS transistors can have relatively long gate lengths (L) and relatively short gate widths to ensure correspondingly low W / L ratios to compensate for the relatively high mobility of these transistors. This can make LTPS transistors relatively inefficient for pixel layout. Oxide transistors can be designed with smaller W / L ratios (e.g., 4 / 4 for oxide versus 3 / 30 for LTPS). Because of these layout efficiency considerations, oxide transistors may be preferred as driver transistors in display pixels. 22-1to use. Thanks to the relatively fast switching speed provided by LTPS transistors, it may be preferable to use LTPS transistors for switching a transistor such as the transistor 30 out of Fig. 2. to use.

[0042] For display pixels with more transistors (e.g., three or more, four or more, five or more, six or more, seven or more, or eight or more), the selection of which transistors are implemented with LTPS technology and which transistors with oxide technology can be made to compensate for performance differences between the two transistor types.

[0043] When implementing driver transistors, LTPS transistors tend to have a larger scope (longer channel length) than oxide transistors; they tend to have higher dark currents than oxide transistors; and they can exhibit poorer uniformity than oxide transistors. LTPS driver transistors can also have more hysteresis than oxide driver transistors. As a result of these factors, it can often be advantageous to implement driver transistors in an OLED display pixel using oxide transistors. The oxide driver transistors can exhibit lower leakage current with minimal hysteresis.

[0044] When implementing switching transistors, LTPS transistors can be smaller than oxide transistors; they can exhibit smaller amounts of parasitic capacitance than oxide transistors; and they can have lower current consumption than oxide transistors. As a result of factors like these, it can often be advantageous to implement switching transistors in an OLED display pixel using LTPS transistors. LTPS switching transistors can exhibit high switching speeds and low parasitic capacitance.

[0045] An exemplary hybrid thin-film transistor structure that can be used when implementing both LTPS and oxide transistors in a single OLED display pixel (e.g., when implementing a circuit such as the display pixel circuit). 22-1 out of Fig. 2), is in Fig. 4. Shown. Hybrid thin-film transistor structures 114 out of Fig. 4 close the silicon thin-film transistor 108, the capacitor (Cst) 110 and the oxide transistor 112 one. The silicon transistor 108 is made from the polysilicon layer 90 formed. The gate insulating layer 92 covers the polysilicon layer 90 A layer of gate metal is placed over the gate insulating layer. 92 structured to open the gate 94 , the capacitor electrode 96 and the gate electrode 98 to form an intermediate layer of dielectric material, such as a silicon nitride layer. 116 and a silicon dioxide layer 118 can cover the formed gate metal structures. Source-drain contacts 100 and 94 for the silicon transistor 108 can the polysilicon layer 90 near the canal region 106 contact (i.e., be short-circuited). The gate 94 of the transistor 108can serve as an implantation mask to facilitate the formation of low-density drain implants in the polysilicon layer 90 in regions 104 next to the polysilicon channel region 106 of the transistor 108 to enable.

[0046] Source / Drain 100 and 102 of the silicon transistor 108 , the capacitor electrode 102 and Source / Drain 122 and 124 of the oxide transistor 112 can consist of structured sections of a common metal layer on the dielectric intermediate layer 116 and 118 be educated.

[0047] The capacitor 110 may have a first connection consisting of a metal electrode 120 and from a section 126 the polysilicon layer 90 is formed. The capacitor 110 can have a second connection made from the metal electrode 96 is trained.

[0048] The oxide transistor 112 can a semiconductor oxide layer such as an IGZO layer 128 , Source / Drain contacts 122 and 124 and a gate 98 have. The gate 98 is due to the dielectric materials 116 and 118 from the semiconductor oxide 128 separated, which serves as a channel region for the transistor 112 serves as a dielectric material. 116 and 118 It therefore serves as a gate insulator for the oxide transistor. 112 .

[0049] Fig. Figure 5 is a circuit diagram of another exemplary OLED display pixel circuit used in the display 14 can be used. The pixel 22-2 closes the driver transistor 28 to supply current to the light-emitting diode 26 The storage capacitor Cst is used to store signals at the gate of the transistor. 28to store data between frames. The SENSING test line is used to implement a compensation scheme for pixel-to-pixel changes in transistor power. The SCAN and SCAN2 gate lines are used when the switching transistors are driven. 30-1 and 30-2 used with control signals.

[0050] To optimize performance at the display pixel 22-2 It may be desirable to use hybrid structures of the in Fig. 3 and Fig. The 4 types shown, or other configurations, can be used to form silicon and / or oxide thin-film transistors and capacitors. For example, it may be desirable to use the driver transistor 28 to be formed from an oxide transistor (e.g., an NMOS oxide transistor), while switching transistors such as transistors 30-1 and 30-2formed from silicon transistors or from a mixture of silicon (NMOS and / or PMOS) and oxide (NMOS) transistors.

[0051] In a first exemplary configuration, the transistor 30-1 an oxide transistor, the transistor 30-2 is an oxide transistor, and the transistor 28 is an oxide transistor. In a second exemplary configuration, the transistor is 30-1 a silicon transistor, the transistor 30-2 is a silicon transistor, and the transistor 28 is an oxide transistor. A hybrid transistor structure like the structure from Fig. 3 or the structure made up of Fig. 4 can be used in this scenario (e.g., to implement the transistors). 30-1 and 28 and the capacitor Cst). In a third exemplary configuration, the transistor 30-1 a silicon transistor, the transistor 30-2is an oxide transistor, and the transistor 28 is an oxide transistor. As with the second example configuration, a hybrid transistor structure such as the structure made of can be used. Fig. 3 or the structure made up of Fig. 4 are used to connect the transistors 30-1 and 28 and to implement the capacitor Cst.

[0052] If needed, the display can 14 It could be a liquid crystal display. In this scenario type, each pixel of the display can be used. 14 The circuit includes an electrode structure for applying an electric field to a designated area of ​​a liquid crystal layer in the display, a capacitor for storing charge on the electrode between frames of image data, and a thin-film transistor for controlling the application of the electric field to the electrodes. With a suitable arrangement, the gate driver circuit can be 18 and the demultiplexer circuit 20 ( Fig. 1) be formed in the liquid crystal display from silicon transistors, and the thin-film transistors in the display pixels 22 They can be formed from oxide transistors. The silicon transistors have channel regions with high mobility and are well suited for fast switching speeds and high drive currents, while operating at low voltages and low power. The oxide thin-film transistors in the display pixels 22 exhibit low leakage currents.

[0053] Thin-film transistor structures of the type that can be used in the formation of a liquid crystal display with both silicon and oxide transistors are in Fig. 6. shown. According to the illustration in Fig. 6. Thin-film transistor structures 242 Silicon thin-film transistor structures 216 include (e.g., for forming parts of peripheral circuits such as the display driver circuit) 18and the demultiplexer circuit 20 ) as well as oxide thin-film transistor structures 240 (e.g., for forming display pixels) 22 in a liquid crystal display with a layout of the display 14 out of Fig. 1 of the type shown).

[0054] The structures 216 and 240 can on the buffer layer 202 on the substrate 24 be formed. The polysilicon layer 204 can be on the buffer 202 It must be applied. The gate insulating layer 206 can be applied to the polysilicon layer 204 be formed. A common metal layer can be structured to create metal structures. 218 , 220 and 228 to form the structure 218 can serve as a gate for a silicon transistor, which connects the source / drain contacts. 212 and 214 includes a channel formed from polysilicon 204 The metal structure228 can serve as a gate for an oxide transistor made from the semiconductor oxide layer 224 (e.g. IGZO) and the source / drain connections 222 and 226 is formed. The metal structure 228 It can also serve as a light shield, which is helpful to reduce backlighting on the display. 14 to prevent the oxide layer 224 to achieve this, so that no separate light-shielding structures are required in the structures 240 must be incorporated. An intermediate layer of dielectric material, such as a silicon nitride layer. 208 and 210 can the gate 218 in the structure 216 cover and act as a gate insulator for the gate 228 in the oxide transistor of the structures 240 serve.

[0055] The metal 230 contacts the source / drain 226 of the display pixel thin-film transistor, which consists of the oxide layer 224 is trained. The metal230 can pass through an organic layer 232 be supported. On the surface of the organic layer 232 can the metal 230 form an electrode with several fingers. The dielectric layer 236 can the electrode 230 from the common electrode (Vcom) 234 insulate. During operation, electric fields are generated between the electrode and the electrode. 230 and the electrode 234 These fields are generated. They pass through the liquid crystal material in the display. If needed, they can be generated in the display. 14 Capacitive touch-sensitive sensors are integrated, consisting of sections of the Vcom electrode. 234 are formed. With this configuration type, metal conductors such as the conductor can be used arbitrarily. 238 can be used to reduce the resistance of the electrode to form the electrode. 234to support the material used (which could be, for example, a slightly resistive conductive material such as indium tin oxide).

[0056] The thickness of the layers 208 and 210 It can be approximately 6000 Å. This relatively large thickness can be used to minimize the capacitance between the gate and the 218 and nearby metal structures such as source / drain 214 It can be helpful, but it can limit the switching speeds in the oxide transistor. To address this drawback, a design based on the structures can be used. 242' out of Fig. 7 types are used. In the arrangement of Fig. 7. An additional semiconductor fabrication mask can be used to create a gate for the oxide transistor, consisting of one of the materials used to form the gate. 218 The metal layer used is a separate metal layer. In this approach, only a single dielectric layer is formed.210' used with 3000 Å (formed e.g. from silicon nitride and silicon oxide) to form the oxide transistor gate 228' from the oxide layer 224 to separate them, so that the switching speed of the oxide transistor can be improved. The arrangement of structures 242' out of Fig. 7 makes it possible to open the gate 218 and the gate 228' to be formed from different metals. For example, the gate can be made from different metals. 218 formed from a refractory metal such as Mo to withstand the elevated temperatures associated with the activation of the silicon transistor, while the gate 228' It may be formed from a metal with lower resistance, such as copper.

[0057] In some applications, it may be necessary to investigate the handling of high drive voltages (gate-to-source and gate-to-drain). The transistor structures 242'' out of Fig. 8 can be used in scenarios where it is desirable to handle relatively large voltage swings (e.g., 20 V) at the silicon transistor gate. In this situation, the gate insulating layer can 206 It may be insufficient to withstand damage from a 20V signal. For example, the gate insulator may 206 It should be approximately 800 Å thick, which may be insufficient to reliably handle 20 V driver voltages. To ensure that the gate insulating layer 206 The gate structure is not subjected to excessive stress. 218 be converted into an (electrically insulated) floating metal structure, and an additional metal layer (i.e., part of the same metal layer used to form the gate). 228' of the oxide transistor 240 (is structured) can lead to the formation of the silicon transistor gate. 218' can be used. The Floating Gate 218can be retained to serve as a mask for implants with a slightly doped drain (LDD) that are inserted into the source / drain contact sections of the polysilicon layer 204 can be used even if the floating gate 218 during the operation of the silicon transistor 216 It is not operated with control signals.

[0058] In a hybrid silicon / oxide liquid crystal display, it is not necessary to have display driver circuitry such as the gate driver circuitry. 18 and the demultiplexer circuit 20 to be formed from silicon transistors. If required, some of these display driver circuits can be formed from oxide transistors. For example, low-current CMOS-type circuits can be used in the peripheral circuitry of the display. 14 like the exemplary CMOS inverter 300 out of Fig. 9 oxide transistors are included. The formation of PMOS oxide transistors can be a difficult task, so circuits such as the inverter 300 can be formed, if required, using an NMOS oxide transistor and a PMOS silicon transistor (as an example).

[0059] Hybrid oxide-silicon thin-film transistor structures such as the exemplary thin-film transistor structures 302 out of Fig. 10 can be used in the formation of CMOS-type circuits in display driver circuits such as the gate driver circuit. 18 and the demultiplexer circuit 20 can be used. According to the representation in Fig. 10 can the structures 302 a polysilicon layer 308 have, which are on the substrate 24 is trained. The active area 310 of the P-channel can be accessed under the gate 312 be trained. The gate insulating layer 306 (e.g. silicon oxide) can be the gate 312from the silicon canal region 310 in the silicon layer 308 separate the dielectric layer 302 (e.g., sublayers of silicon oxide and silicon mitride) can be used to create the gate 312 cover the dielectric layer 306 can the gate 312 separate in such a way that it does not remove the oxide layer 312 overlaps. The oxide layer 312 It can be a semiconductor oxide such as IGZO material. The gate 312 It can be formed from a first structured metal layer. A second structured metal layer can be added during the formation of the output connector. 322 , of the source port 316 and the drain connection 318 can be used. The passivation layer 320 can the connections 316 and 312 cover the gate 312It can be formed from materials such as molybdenum, molybdenum-tungsten, tungsten, or other metals. Metals are used to form structures such as metallic structures. 322 , 316 and 318 can be formed from metals such as aluminum, molybdenum, etc.

[0060] In the arrangement from Fig. Gate 10 serves as the gateway 314 as a shared gate for two transistors. In particular, the gate serves as 314 (see e.g. connection Vin from) Fig. 9) both as a gate for a PMOS silicon transistor (transistor TP from Fig. 9), which is made from the silicon layer 308 is formed, as well as serving as a gate for an NMOS oxide transistor (transistor TN from Fig. 9), which is from the oxide layer 312 is formed. The oxide layer 312 is above the gate 314 arranged, and the silicon layer 310 is below the gate 314 arranged. The split gate arrangement from Fig. 10 enables the fully compact implementation of a CMOS inverter of the in Fig. 9 types shown.

[0061] Fig. Figure 11 shows an example gate driver circuit 18 , which can be used in a liquid crystal display. The circuit 18 It can use signals with a relatively small voltage swing (e.g., a 15 V or 16 V swing) for silicon transistors, while gate signals G are generated with a larger voltage swing (e.g., a 20 V swing or greater) to ensure satisfactory operation of the oxide thin-film transistors in the display pixels. 22 to ensure that they are controlled by the gate signals.

[0062] According to the representation in Fig. 11 can the circuit 18 have a shift register consisting of a series of linked SR latches 400 or other register circuits. Each line of the circuit in Fig. 11 is a separate row of display pixels. 22 assigned to a liquid crystal display, it provides a corresponding gate signal G for the relevant row of display pixels. During operation, the latch can be located in the first row of the shift register in the circuit. 18 The shift register is supplied with the trigger signal TRIGGER, while the shift register is supplied with a clock signal LOAD CLOCK. The trigger signal causes a cascading signal to attenuate through the shift register. In response, each latch is then occupied. 400 Each line of the gate driver circuit successively outputs its OUT signal. 18 has an associated level converter 404 and buffers 404 , which receive the output signal OUT.

[0063] The output signal OUT ranges from a high voltage of 15 V (or another suitable voltage) to 0 V (or another suitable voltage). The 15 V swing associated with this configuration type is provided by the silicon thin-film transistors in the latches. 400 Small voltage swings are tolerated, while larger voltage swings, such as 20V swings, could overload the silicon transistors. The level shifter 402 shifts the 15V to 0V signal OUT from the latch 400 , so that the output at the path 406 from the level converter 402 ranges from 5 V to -11 V (i.e. a swing of 16 V, which is achieved by the silicon transistors in the level shifter) 402 can be tolerated). The buffer 404 receives the 15V to 0V signal OUT from the latch. 400 The buffer receives the 5V-to-11V signal as input signal IN_H and the 5V-to-11V signal as input signal IN_L. 404 preferably contains silicon thin-film transistors. The buffer design 404allows the buffer 404 , to generate an output signal (gate line signal G) with a larger voltage swing (e.g., 15 V to 11 V) than the type used for controlling oxide transistors in the array of display pixels 22 suitable for liquid crystal displays.

[0064] Fig. Figure 12 is a circuit diagram of an exemplary circuit of the type used to implement the level converter. 402 can be used. Signals from the OUT output of the latch. 400 can be used as input 410 of the level converter 402 are received, and corresponding level-shifted output signals (signals IN-L) for the buffer. 404 can at the exit 412 of the level converter 402 be provided. If required, the level converter can be used. 402 Other level-changing designs are used. The configuration consists of Fig. Figure 12 is purely an example. Silicon thin-film transistors can be used to form the level shifter. 402 be used.

[0065] The circuit 404 out of Fig. 13 is an example of a design that is used when implementing the buffer. 404 out of Fig. 11. can be applied. In this design, the IN_H and IN_L signals are identical rectangular pulses, each with different voltage ranges. The IN_H signal ranges from 15 V to 0 V. The IN_L signal ranges from 5 V to -11 V. The corresponding output signal (gate line signal) G in this example is a rectangular pulse ranging from 15 V to -11 V and therefore has a range of more than 20 V.

[0066] The gates of transistors T2 and T3 are energized by the ground voltage (GND). This limits the current flowing through the transistors in the circuit. 414 Maximum applied voltage of less than approximately 16 V, even if the output swing of the circuit 414more than 20 V. The ground voltage GND at the gates of transistors T2 and T3 causes these transistors to switch off to protect transistors T1 and T4 when an excessive voltage swing is detected at the source terminal. Consider, for example, transistors T1 and T2. Transistor T2 can be characterized by a threshold voltage Vth. If the source terminal S of transistor T1 begins to fall below the voltage GND-Vth, transistor T2 switches off and isolates transistor T1. Transistors T3 and T4 operate in the same way. Using this arrangement, none of the transistors in the buffer will be damaged. 414 exposed to excessive voltage fluctuations, so that transistors T1, T2, T3 and T4 can be formed from silicon thin-film transistors.

[0067] If necessary, other circuit configurations can be used to adapt it to the gate driver circuit. 18to enable operation in an environment where the gate line signal G has a large voltage swing, to protect oxide transistors in display pixels 22 to include. For example, a subset of the level-shifting transistors and a subset of the output buffer transistors can be implemented using oxide thin-film transistor structures in addition to using silicon thin-film transistor structures.

[0068] Fig. Figure 14 shows a side cross-sectional view of an additional thin-film transistor circuit of the type that can be used in a liquid crystal display. As shown in Fig. 14 thin-film transistor structures 242 Silicon thin-film transistor structures 216 include (e.g., for forming parts of peripheral circuits such as the display driver circuit) 18 and the demultiplexer circuit 20 ) as well as oxide thin-film transistor structures240 (e.g., for forming display pixels) 22 in a liquid crystal display with a layout of the display 14 out of Fig. 1 of the type shown).

[0069] The structures 216 and 240 can on the buffer layer 202 on the substrate 24 be formed. The polysilicon layer 204 can be on the buffer 202 It must be applied. The gate insulating layer 206 can be applied to the polysilicon layer 204 be formed. A common metal layer can be structured to create metal structures. 218 , 220 and 228 to form the structure 218 can serve as a gate for a silicon transistor, which connects the source / drain contacts. 212 and 214 includes a channel formed from polysilicon 204 The metal structure 228 can serve as a gate for an oxide transistor made from the semiconductor oxide layer224 (e.g. IGZO) and the source / drain connections 222 and 226 is formed. The metal structure 228 It can also serve as a light shield, which is helpful to reduce backlighting on the display. 14 to prevent the oxide layer 224 to achieve this, so that no separate light-shielding structures are required in the structures 240 must be incorporated. An intermediate layer of dielectric material, such as a silicon nitride layer. 208 and 210 can the gate 218 in the structure 216 cover and act as a gate insulator for the gate 228 in the oxide transistor of the structures 240 serve.

[0070] Metal structures 218 , 220 and 228 and routing lines such as the connecting line 502 can be formed from a first metal layer (sometimes referred to as the M1 layer). The metals 222 and 226, the source / drain contacts for the oxide transistor of the structures 240 form, and routing lines such as the connecting line 500 can be formed from a second metal layer (occasionally referred to as the SD1 layer). The metal structures 212 , 214 and routing lines such as the connecting line 506 can be formed from a third metal layer (occasionally referred to as the SD2 layer). Dielectric layers 232B can separate the second metal layer from the third metal layer. The dielectric layer 232A can the third metal layer of metal structures such as the metal layer 234 separate.

[0071] The metal 230 contacts the metal layer 504 and is therefore connected to the source / drain 226 coupled to the display pixel thin-film transistor, which consists of the oxide layer 224 is trained. The metal 230can pass through the organic layer 232B be worn. On the surface of the organic layer 232B can the metal 230 form an electrode with several fingers. The dielectric layer 236 can the electrode 230 from the common electrode (Vcom) 234 insulate. During operation, electric fields are generated between the electrode and the electrode. 230 and the electrode 234 These fields are generated. They pass through the liquid crystal material in the display. If needed, they can be generated in the display. 14 Capacitive touch-sensitive sensors are integrated, consisting of sections of the Vcom electrode. 234 are formed. With this configuration type, metal conductors such as the conductor can be used arbitrarily. 238 can be used to reduce the resistance of the electrode to form the electrode. 234to support the material used (which could be, for example, a slightly resistive conductive material such as indium tin oxide).

[0072] The capacitive coupling between the routing lines in the display 14 This can lead to switching losses. For example, the source-drain structure can 222 with the data line in the display 14 be coupled. The voltage on this line switches relative to Vcom (electrode). 234 ) and can lead to power losses. The presence of dielectric layers 232A and 232B This can help reduce capacitive coupling between the data line and the Vcom electrode, thus reducing power losses. The presence of these dielectric layers can also reduce capacitive coupling between routing lines in the display. 14reduce (e.g., capacitive coupling between routing lines and other structures of the first and second metal layers, the first and third metal layers, etc.). The layers 232A and 232B They can be formed from organic dielectric material with a low dielectric constant or other dielectric material. For example, the layers can 232A and 232B These may include acrylic polymers, other polymers, dielectrics of the type sometimes referred to as spin-on-glass (e.g., spin-on-glass polymers deposited via slit-coating tools, etc.), siloxane-based materials, etc.

[0073] Fig. Figure 15 is a side cross-sectional view of an exemplary thin-film transistor circuit for a liquid crystal display, including a top-gate semiconductor oxide transistor. As shown in Fig. 15. The thin-film transistor structures 242 Silicon thin-film transistor structures216 and semiconductor oxide thin-film transistor structures 240 include the silicon thin-film transistor structures. 216 can be used in peripheral circuits such as the display driver circuit 18 and the demultiplexer circuit 20 can be used, and / or they can be used in the formation of circuits for display pixels 22 They are used in liquid crystal displays. The semiconductor oxide thin-film transistor structures 240 can be used in peripheral circuits such as the display driver circuit 18 and the demultiplexer circuit 20 can be used, and / or they can be used in the formation of circuits for display pixels 22 They are used in liquid crystal displays. Transistors such as the silicon (polysilicon) transistor 216 They can be n-channel or p-channel devices. Transistors such as the semiconductor oxide transistor. 240 They can be n-channel or p-channel devices.

[0074] The structures 216 and 240 can on the buffer layer 202 on the substrate 24 be formed. The buffer layer 202 It can be formed from a dielectric, such as an organic dielectric. The buffer layer 202 can be helpful to remove ions from the substrate 24 migration into the structures 216 and 240 to prevent.

[0075] The polysilicon layer 204 can be on the buffer 202 It must be applied. The gate insulating layer 206 can be applied to the polysilicon layer 204 be trained. The gate insulating layer 206 It can be formed from a dielectric such as silicon oxide (e.g., a 100 nm silicon oxide layer). A common metal layer can be structured to form metal structures. 218 , 220 and 228 to form the structure 218can serve as a gate for a silicon transistor, which connects the source / drain contacts. 212 and 214 includes a channel formed from polysilicon 204 The metal structure 228 can serve as a gate for a top-gate oxide transistor (i.e., a semiconductor oxide transistor) made from the semiconductor oxide layer 224 (e.g. IGZO) and the source / drain connections 222 and 226 is formed. One or more dielectric intermediate layers (ILDs) can form the metal structures. 218 , 220 and 228 cover. For example, a first dielectric layer such as the layer 208 and a second dielectric layer such as the layer 210 the metal structures 218 , 220 and 228 cover the layer 208 It could, for example, be a silicon nitride layer, and the layer 210It could be a silicon oxide layer. Since there is no lateral overlap between the gate 228 and the source / drain electrodes 222 and 226 There is a parasitic capacity between the gate 228 and the source / drain structures 222 and 226 can be minimized. Furthermore, the layers can be minimized. 208 and 210 of the oxide transistor Fig. be 15 times thicker than the layers 208 and 210 in the bottom-gate oxide transistor Fig. 14 and thereby further reduce the parasitic capacities.

[0076] The metal structures 218 , 220 , and 228 can be formed from a first metal layer (sometimes referred to as the M1 layer). The metals 222 and 226 , the source / drain contacts for the oxide transistor of the structures 240 form, and the metals 212 and 214, the source / drain contacts for the silicon transistor of the structures 216 Metal structures can be formed from a second metal layer (occasionally referred to as the SD1 layer or M2 layer). Metal structures such as metal conductors 238 can be formed from a third metal layer (occasionally referred to as the M3 layer). The dielectric 232 (e.g. an organic dielectric layer such as a polymer layer) can separate the second metal layer from the third metal layer.

[0077] The metal 230 contacts the source / drain 226 of the display pixel thin-film transistor, which consists of the oxide layer 224 is trained. The metal 230 can pass through an organic layer 232 be supported. On the surface of the organic layer 232 can the metal 230to form an electrode with multiple fingers (e.g., a pixel electrode for a display pixel in the display). The dielectric layer 236 can the electrode 230 from the common electrode (Vcom) 234 insulate. During operation, electric fields are generated between the electrode and the electrode. 230 and the electrode 234 These fields traverse the liquid crystal material in the display, which is located above the structures made of Fig. 15 is formed. If necessary, the display can be used. 14 Capacitive touch-sensitive sensors are integrated, consisting of sections of the Vcom electrode. 234 are formed. With this configuration type, metal conductors such as the conductor can be used arbitrarily. 238 can be used to reduce the resistance of the electrode to form the electrode. 234 to support the material used (which could be, for example, a slightly resistive conductive material such as indium tin oxide).

[0078] According to the representation in Fig. 16 can be found under the semiconductor oxide transistor 240 or at another location in the display, an optional light-shielding structure such as the light shield 520 be trained. The sun protection 520 It can be made of an opaque material such as a metal, an oxidized metal, a dark polymer, or other light-blocking materials. The presence of light protection 520 can be helpful in preventing stray light from interfering with the operation of semiconductor oxide transistor structures. 240 or to prevent other overlapping structures.

[0079] In the example from Fig. 17 is the dielectric layer 232 out of Fig. 15 divided into two dielectric layers 232A and 232B The layer 232A can the source / drain electrodes of the transistors 216 and 240overlap. The layer 232B can occur between the source / drain electrodes and other metal structures formed in the source-drain metal layer and the layers 208 and 210 be inserted. According to the description in conjunction with Fig. 14. This type of two-layer approach can enable capacitive coupling between the metal structures of the facilities. 216 and 240 reduce. A side cross-sectional view of an exemplary thin-film transistor circuit, including a top-gate semiconductor oxide transistor in an OLED display, is shown in Fig. 18 shown. According to the illustration in Fig. 18 can the circuit 72 Display pixel structures include, for example, the LED cathode connector. 42 and the LED anode connection 44 Emissive OLED material 47 can be between the cathode 42 and the anode 44It should be inserted. The pixel definition layer. 46 can a dielectric layer 46 It is the layer that serves to define the layout of the display pixel. 46 It can be formed from a polymer such as a black polymer to assist in blocking scattered light.

[0080] The planarization layer 50 can be achieved via thin-film transistor structures 52 be trained. The thin-film transistor structures 52 can on the buffer layer 54 on the substrate 24 be formed. The substrate 24 It can be made of metal, glass, polymer, other materials, or combinations of these materials. The buffer layer 54 can be formed from an inorganic dielectric layer, which is helpful in storing ions in the substrate 24 to prevent the operation of the structures 52 to interrupt. An optional functional layer522 can between the buffer layer 54 and the substrate 24 be inserted. The functional layer 522 It can be a stress relief layer, a light barrier layer, a layer for use in the formation of components such as capacitors (e.g., capacitor electrodes for pixel circuits and / or peripheral circuits), etc.

[0081] The thin-film transistor structures 52 can the silicon transistor 58 include the transistor 58 It can be an LTPS transistor designed with a “top-gate” configuration, and it can serve as a switching transistor in an OLED display pixel (see, for example, the transistor). 30 in the pixel 22-1 out of Fig. 2) serve. The transistor 58 It can also be used in peripheral circuits (e.g., in the driver circuit). 18 and the demultiplexer circuit 20 ).

[0082] The transistor 58can form a polysilicon channel 62 have, which passes through the gate insulating layer 64 is covered (e.g., with a silicon oxide layer 100 nm thick or another suitable thickness). The gate 66 It can be formed from structured metal (for example, molybdenum). The gate 66 may be covered by a dielectric intermediate layer (e.g., a silicon nitride layer). 68 and a silicon dioxide layer 70 Source-drain contacts 74 and 76 opposite sides of the polysilicon layer can 62 contact us to discuss the silicon thin-film transistor 58 to form.

[0083] The dielectric layer 526 can the source / drain structures 74 and 76 cover. An optional metal layer 524 can on the layer 526 be trained, and it can be accessed via vias if required (see e.g. vias).528 ) contact underlying metal structures. The structure 66 can be formed in a first metal layer (“M1”). The source / drain electrodes 74 and 76 can be formed in a second metal layer. The metal layer 524 can be formed as part of a third metal layer (“M3”). The layer 524 can sections of the transistor 58 and / or the transistor 60 overlap and are used to form capacitors or signal link lines (i.e., routing). The layer 524 can pass through the layer of emissive material 47 overlap and form light-blocking structures that deflect scattered light from emissive material 47 to prevent reaching the underlying transistor structures, etc.

[0084] Thin-film transistor structures such as semiconductor oxide thin-film transistor structures 60and silicon thin-film transistor structures 58 They can be used to form part of a pixel circuit in an OLED display, and / or they can be used to form parts of peripheral circuits. 18 and 20 to form. The thin-film transistor 60 out of Fig. 18 can be a top-gate semiconductor oxide transistor. The gate insulating layer 64 , which serves as a gate insulator for the silicon transistor 58 It also acts as a gate insulator for the oxide transistor. 60 .

[0085] The Metal Gate 532 forms the gate of the oxide transistor 60 The channel semiconductor of the oxide transistor can be made from the semiconductor oxide layer. 128 be formed (e.g., IGZO). Source-drain connections 534 and 536 can be made of metal, which forms the opposite end of the semiconductor oxide layer 128 contacted. Metal structures 530 and 538can be used for routing, and they can be formed from the same metal layer used to form the gates. 66 and 532 It is structured. Structures such as source / drain structures. 534 and 536 can be formed from the same metal layer that forms the source / drain structures 74 and 76 is used.

[0086] According to one embodiment, a liquid crystal display is provided, which includes a substrate and an array of display pixels on the substrate; and a display driver circuit formed from thin-film transistors on the substrate, wherein the display driver circuit includes a silicon thin-film transistor and the array of display pixels includes a semiconductor oxide thin-film transistor, and a layer of gate metal structured to form a common gate that serves as a gate for the silicon thin-film transistor and as a gate for the semiconductor oxide thin-film transistor.

[0087] According to another embodiment, the semiconductor oxide thin-film transistor has a semiconductor oxide layer, and the common gate is located below the semiconductor oxide layer.

[0088] According to another embodiment, there is a layer of polysilicon on the substrate, which forms a silicon channel for the silicon thin-film transistor, and the common gate is located above the polysilicon layer.

[0089] According to another embodiment, the liquid crystal display includes a layer of silicon nitride and a layer of silicon oxide, which are inserted between the gate of the semiconductor oxide thin-film transistor and the semiconductor oxide layer.

[0090] According to one embodiment, a liquid crystal display is provided which includes a substrate, an array of display pixels on the substrate, and a display driver circuit formed from thin-film transistors on the substrate, wherein the display driver circuit includes a silicon thin-film transistor and the array of display pixels includes a semiconductor oxide thin-film transistor, and a layer of polysilicon on the substrate which forms a silicon channel for the silicon thin-film transistor, and a first layer of gate metal which forms a gate for the silicon thin-film transistor, and a second layer of gate metal which is different from the first layer of gate metal and which forms a gate for the semiconductor oxide thin-film transistor.

[0091] According to one embodiment, a liquid crystal display is provided which includes a substrate, an array of display pixels on the substrate, and a display driver circuit formed from thin-film transistors on the substrate, wherein the display driver circuit includes a silicon thin-film transistor and the array of display pixels includes a semiconductor oxide thin-film transistor, and a layer of polysilicon on the substrate which forms a silicon channel for the silicon thin-film transistor, and a first layer of gate metal which forms a floating gate for the silicon thin-film transistor, and a second layer of gate metal which forms a gate for the silicon thin-film transistor which overlaps this floating gate and which is separated from the floating gate by a layer of dielectric, wherein a section of the second layer of gate metal forms a gate for the semiconductor oxide thin-film transistor.

[0092] According to one embodiment, a liquid crystal display is provided which includes a substrate, an array of display pixels on the substrate, and display driver circuitry, wherein the display driver circuitry controls signals into the array of display pixel circuitry, wherein the display driver circuitry is formed from thin-film transistors on the substrate, and wherein the display driver circuitry includes a silicon thin-film transistor and a semiconductor oxide thin-film transistor.

[0093] According to another embodiment, the liquid crystal display includes a metal layer that forms a shared gate for both the silicon thin-film transistor and the semiconductor oxide thin-film transistor.

[0094] According to another embodiment, the semiconductor oxide thin-film transistor has a semiconductor oxide layer above the split gate.

[0095] According to another embodiment, the silicon thin-film transistor has a polysilicon layer below the split gate.

[0096] According to another embodiment, the silicon thin-film transistor and the semiconductor oxide thin-film transistor form an inverter.

[0097] According to one embodiment, a liquid crystal display is provided which includes a substrate, an array of display pixels on the substrate, and a display driver circuit formed from thin-film transistors on the substrate, wherein the display driver circuit includes a silicon thin-film transistor and the array of display pixels includes a semiconductor oxide thin-film transistor, and a first structured metal layer which includes a gate for the silicon thin-film transistor and a gate for the semiconductor oxide thin-film transistor, as well as a second structured metal layer which includes source / drain contacts for the semiconductor oxide thin-film transistor, and a third structured metal layer which includes a structure coupled to at least one of the source / drain contacts, and a dielectric layer between the second and the third structured metal layer.

[0098] According to another embodiment, the liquid crystal display includes a fourth structured metal layer that encloses display pixel electrodes.

[0099] According to another embodiment, the liquid crystal display includes an additional dielectric layer between the third and fourth structured metal layers.

[0100] According to another embodiment, the dielectric layer between the second and the third structured metal layer is an organic dielectric layer.

[0101] According to another embodiment, the dielectric layer between the third and fourth structured metal layers is an organic dielectric layer.

[0102] According to another embodiment, the liquid crystal display includes an inorganic dielectric layer between the first and the second structured metal layer.

[0103] According to another embodiment, the first structured metal layer includes routing lines.

[0104] According to another embodiment, the second structured metal layer includes routing lines.

[0105] According to another embodiment, the third structured metal layer includes routing lines.

[0106] According to one embodiment, a display pixel circuit is provided in a display pixel in an OLED display, which includes a light-emitting diode, a semiconductor oxide thin-film transistor coupled to the light-emitting diode, and a silicon thin-film transistor.

[0107] According to another embodiment, the semiconductor oxide thin-film transistor includes a driver transistor with a gate, wherein the display pixel includes a capacitor coupled between the gate and the light-emitting diode.

[0108] According to another embodiment, the silicon thin-film transistor has a polysilicon channel and is coupled to the capacitor.

[0109] According to another embodiment, the display pixel circuit includes a metal layer, wherein the capacitor has a first and a second electrode, the first electrode and the gate being formed from a section of the metal layer, and wherein the silicon thin-film transistor has a gate formed from another section of the metal layer.

[0110] According to another embodiment, the silicon thin-film transistor has a channel formed from a section of a polysilicon layer, wherein the second electrode is formed from an additional section of the polysilicon layer, and wherein the oxide transistor has a channel formed from semiconductor oxide, and wherein the channel formed from the semiconductor oxide layer overlaps the additional section of the polysilicon layer.

[0111] According to one embodiment, a hybrid thin-film transistor structure is provided which includes a silicon layer for a silicon thin-film transistor, a semiconductor oxide layer for an oxide transistor, and a metal layer, wherein the metal layer is structured to form a first gate for the silicon thin-film transistor and is structured to form a second gate for the oxide transistor.

[0112] According to another embodiment, the hybrid thin-film transistor structure includes a capacitor with an electrode layer formed from a section of the metal layer.

[0113] According to another embodiment, the hybrid thin-film transistor structure includes an additional metal layer with sections forming source / drain contacts for the silicon thin-film transistor, as well as sections forming source / drain contacts for the oxide thin-film transistor and sections forming an electrode layer in the capacitor.

[0114] According to another embodiment, the capacitor has an additional electrode layer formed from a section of the metal layer that is structured to form the first gate.

[0115] According to another embodiment, the silicon layer encloses a polysilicon layer, and a section of the polysilicon layer forms an electrode layer for the capacitor, which is reduced to the sections of the additional metal layer that form the electrode layer in the capacitor.

[0116] According to one embodiment, an OLED display is provided which includes a light-emitting diode and thin-film transistors coupled to the light-emitting diode, wherein the thin-film transistors include at least one semiconductor oxide channel region and at least one silicon channel region.

[0117] According to another embodiment, the thin-film transistors include a semiconductor oxide thin-film transistor formed from the semiconductor oxide channel region and coupled to the light-emitting diode.

[0118] According to another embodiment, the thin-film transistors include a silicon thin-film transistor formed from the silicon channel region.

[0119] According to another embodiment, the thin-film transistors include a semiconductor oxide thin-film transistor formed from the semiconductor oxide channel region and coupled to the light-emitting diode, and a silicon thin-film transistor formed from the silicon channel region.

[0120] According to another embodiment, the semiconductor oxide thin-film transistor includes a driver transistor with a gate.

[0121] According to another embodiment, the OLED display includes a capacitor coupled between the gate and the light-emitting diode.

[0122] According to another embodiment, the silicon channel region includes a polysilicon channel region that is coupled to the capacitor.

[0123] According to another embodiment, the OLED display includes a metal layer, wherein the capacitor has a first and a second electrode, the first electrode and the gate being formed from a section of the metal layer, and wherein the silicon thin-film transistor has a gate formed from another section of the metal layer.

[0124] According to another embodiment, the thin-film transistors include a silicon thin-film transistor and a semiconductor oxide thin-film transistor, wherein the silicon channel region is formed from a section of a polysilicon layer and forms part of the silicon thin-film transistor, and wherein the second electrode is formed from an additional section of the polysilicon layer.

[0125] According to another embodiment, the semiconductor oxide channel region forms part of the semiconductor oxide thin-film transistor, and the semiconductor oxide channel region overlaps the additional section of the polysilicon layer.

[0126] According to one embodiment, a liquid crystal display is provided which includes a substrate, an array of display pixels on the substrate, and display driver circuitry, wherein the display driver circuitry controls the signals into the array of display pixel circuitry, and wherein the display driver circuitry includes level converter circuitry.

[0127] According to another embodiment, the array of display pixel circuits includes a semiconductor oxide thin-film transistor circuit.

[0128] According to another embodiment, the display driver circuit includes a silicon thin-film transistor formed on the substrate.

[0129] According to another embodiment, the display driver circuit includes gate driver circuitry, and the level converter circuitry forms part of the gate driver circuitry.

[0130] According to another embodiment, the gate driver circuit further includes a shift register.

[0131] According to another embodiment, the level converter circuit is coupled to the shift register.

[0132] According to another embodiment, the gate driver circuit includes a buffer circuit.

[0133] According to another embodiment, the buffer circuit is coupled to the level converter circuit and generates the gate line signals.

[0134] According to another embodiment, the shift register provides signals with a first voltage swing, the level converter adapts the first voltage swing to a second voltage swing, and the buffer circuit receives the signals from the shift register with the first voltage swing, and it receives signals from the level converter with the second voltage swing.

[0135] According to another embodiment, the shift register provides signals with a first voltage swing, and the level converter adapts the first voltage swing to a second voltage swing.

[0136] According to another embodiment, the display driver circuit includes a buffer circuit that receives the signals from the shift register with the first voltage stroke.

[0137] According to one embodiment, a liquid crystal display is provided which includes a substrate, an array of display pixel circuits on the substrate, wherein the display pixel circuits include semiconductor oxide thin-film transistors, wherein the display driver circuit is formed from silicon thin-film transistors on the substrate, wherein the display driver circuit includes a gate driver circuit, and wherein the gate driver circuit includes a level converter circuit that receives signals with a first voltage swing and adapts the first voltage swing to a second voltage swing.

[0138] According to another embodiment, the gate driver circuit includes gate line signals in the array of display pixel circuits.

[0139] According to another embodiment, the semiconductor oxide thin-film transistors each have a semiconductor oxide channel region, and the silicon thin-film transistors each have a polysilicon channel region.

[0140] According to another embodiment, the display driver circuit further includes a shift register, and the level converter circuit is coupled to the shift register.

[0141] According to another embodiment, the gate driver circuit includes a buffer circuit that receives the signals from the shift register with the first voltage swing and receives the signals from the level converter with the second voltage swing.

[0142] According to one embodiment, a liquid crystal display is provided which includes an array of semiconductor oxide thin-film transistor display pixel circuits on a substrate, as well as a silicon thin-film transistor gate driver circuit on the substrate which includes a level shifter that receives signals with a first voltage swing and that adapts the first voltage swing to a second voltage swing, wherein the silicon thin-film transistor gate driver circuit controls the array of semiconductor oxide thin-film transistor display pixel circuits.

[0143] According to another embodiment, the silicon thin-film transistor circuit includes silicon thin-film transistors, each having a polysilicon channel region, and the silicon thin-film transistor gate driver circuit includes a shift register.

[0144] According to another embodiment, the silicon thin-film transistor gate driver circuit includes a buffer circuit.

[0145] According to another embodiment, the liquid crystal display includes a shift register circuit coupled to the level shifter, wherein the buffer circuit receives signals from the level shifter and the shift register and provides gate line signals to the array of semiconductor oxide thin-film transistor display pixel circuits.

[0146] According to one embodiment, a liquid crystal display is provided which includes a substrate, an array of display pixels on the substrate, and display driver circuitry on the substrate, wherein the display driver circuitry and the display pixels include thin-film transistors, and the thin-film transistors include at least one top-gate semiconductor oxide transistor and at least one silicon transistor.

[0147] According to another embodiment, the liquid crystal display includes a gate metal layer that is structured to form a first gate for the silicon transistor and a second gate for the top-gate semiconductor oxide transistor.

[0148] According to another embodiment, the liquid crystal display includes a layer of polysilicon on the substrate, which forms a silicon channel for the silicon transistor, with the first gate being above the polysilicon layer.

[0149] According to another embodiment, the liquid crystal display includes a semiconductor oxide layer on the substrate, which forms a semiconductor oxide channel for the top-gate semiconductor oxide transistor, with the second gate being located above the semiconductor oxide layer.

[0150] According to another embodiment, the liquid crystal display includes a gate insulating layer.

[0151] According to another embodiment, a first section of the gate insulating layer is inserted between the first gate and the polysilicon layer.

[0152] According to another embodiment, a second section of the gate insulating layer is inserted between the second gate and the semiconductor oxide layer.

[0153] According to another embodiment, the liquid crystal display includes source / drain electrodes for the thin-film transistors, wherein the source / drain electrodes are formed from a structured metal layer.

[0154] According to another embodiment, the liquid crystal display includes a silicon oxide layer inserted between the metal layer from which the source / drain electrodes are formed and the first and second gates.

[0155] According to another embodiment, the liquid crystal display includes a silicon nitride layer inserted between the metal layer from which the source / drain electrodes are formed and the first and second gates.

[0156] According to another embodiment, the liquid crystal display includes a display pixel electrode and an organic layer inserted between the display pixel electrode and the source / drain electrodes.

[0157] According to another embodiment, the liquid crystal display includes a display pixel electrode, a first organic layer inserted between the display pixel electrode and the source / drain electrodes, and a second organic layer inserted between the source / drain electrodes and the silicon oxide layer.

[0158] According to one embodiment, the liquid crystal display includes a light shield below the semiconductor oxide layer.

[0159] According to one embodiment, an OLED display is provided which includes a light-emitting diode, a top-gate semiconductor oxide thin-film transistor coupled to the light-emitting diode, and a silicon thin-film transistor.

[0160] According to another embodiment, the OLED display includes a gate metal layer that is structured to form a first gate for the silicon thin-film transistor and a second gate for the top-gate semiconductor oxide thin-film transistor.

[0161] According to another embodiment, the OLED display includes a polysilicon layer forming a silicon channel for the silicon transistor, wherein the first gate is above the polysilicon layer, and a semiconductor oxide layer forming a semiconductor oxide channel for the top-gate semiconductor oxide transistor, wherein the second gate is above the semiconductor oxide layer.

[0162] According to another embodiment, the light-emitting diode includes a cathode, an anode and an organic emissive layer between the anode and the cathode, wherein the organic light-emitting diode has a gate insulator with a first section inserted between the first gate and the polysilicon layer and with a second section inserted between the second gate and the semiconductor oxide layer, as well as a source / drain electrode in the semiconductor oxide thin-film transistor coupled to the anode.

[0163] According to one embodiment, an OLED display is provided which includes a light-emitting diode as well as a silicon thin-film transistor, a semiconductor oxide thin-film transistor with source / drain electrodes, wherein a semiconductor oxide layer is coupled to the source / drain electrodes, and with a gate and a light barrier layer which overlaps at least a part of the silicon thin-film transistor and at least a part of the semiconductor oxide thin-film transistor.

[0164] According to another embodiment, the light-emitting diode includes a cathode, an anode and an organic emissive layer between the anode and the cathode, wherein the organic emissive layer overlaps the light barrier layer and wherein the organic light-emitting diode includes a gate insulating layer with a first section serving as a gate insulator for the silicon thin-film transistor and with a second section serving as a gate insulator for the semiconductor oxide thin-film transistor.

[0165] According to another embodiment, the OLED display includes a source / drain electrode in the semiconductor oxide thin-film transistor, which is coupled to the anode.

[0166] The foregoing serves only for illustration, and various modifications can be made by those skilled in the field without deviating from the scope of protection and spirit of the described embodiments. The foregoing embodiments can be implemented individually or in any combination.

Claims

[1] Liquid crystal display, comprising the following: a substrate; an array of display pixels on the substrate; Display driver circuit formed from thin-film transistors on the substrate, wherein the display driver circuit includes a silicon thin-film transistor and wherein the array of display pixels includes a semiconductor oxide thin-film transistor; and a gate metal layer that is structured to form a common gate that serves as a gate for the silicon thin-film transistor and as a gate for the semiconductor oxide thin-film transistor. [2] Liquid crystal display according to claim 1, wherein the semiconductor oxide thin-film transistor has a semiconductor oxide layer and wherein the common gate is below the semiconductor oxide layer. [3] Liquid crystal display according to claim 2, wherein a polysilicon layer is applied to the substrate, forming a silicon channel for the silicon thin-film transistor, and wherein the common gate is located above the polysilicon layer. [4] Liquid crystal display according to claim 3, further comprising a silicon nitride layer and a silicon oxide layer inserted between the gate of the semiconductor oxide thin-film transistor and the semiconductor oxide layer. [5] Liquid crystal display according to claim 1, wherein the display driver circuit and the display pixels include at least one top-gate semiconductor oxide transistor. [6] Liquid crystal display according to claim 5, further comprising a light barrier layer that overlaps at least a part of the silicon thin-film transistor and at least a part of the semiconductor oxide thin-film transistor. [7] Display pixel circuitry in a display pixel in an organic light-emitting diode (OLED) display, comprising the following: a light-emitting diode; a semiconductor oxide thin-film transistor coupled to the light-emitting diode; a silicon thin-film transistor, wherein the semiconductor oxide thin-film transistor comprises a driver transistor with a gate. [8] Display pixel circuit according to claim 7, further comprising a capacitor coupled between the gate and the light-emitting diode. [9] Display pixel circuit according to claim 7, wherein the silicon thin-film transistor has a polysilicon channel and is coupled to the capacitor and further comprises a metal layer, wherein the capacitor has first and second electrodes, wherein the first electrode and the gate are formed from a section of the metal layer and wherein the silicon thin-film transistor has a gate formed from another section of the metal layer. [10] Display pixel circuit according to claim 9, wherein the silicon thin-film transistor has a channel formed from a section of a polysilicon layer, wherein the second electrode is formed from an additional section of the polysilicon layer, and wherein the oxide transistor has a channel formed from a semiconductor oxide layer, and wherein the channel formed from the semiconductor oxide layer overlaps the additional section of the polysilicon layer. [11] Display pixel circuit according to claim 7, further comprising: a top-gate semiconductor oxide thin-film transistor coupled to the light-emitting diode. [12] Display pixel circuit according to claim 7, further comprising: a light barrier layer that overlaps at least part of the silicon thin-film transistor and at least part of the semiconductor oxide thin-film transistor. [13] Liquid crystal display, comprising the following: a substrate; an array of display pixel circuits on the substrate; and Display driver circuit that controls gate line signals into the array of display pixel circuits, wherein the display driver circuit includes a level shifter circuit and wherein the display driver circuit includes a silicon thin-film transistor formed on the substrate. [14] Liquid crystal display according to claim 13, wherein the array of display pixel circuits includes a semiconductor oxide thin-film transistor circuit. [15] Liquid crystal display according to claim 14, wherein the display driver circuit includes gate driver circuit and wherein the level converter circuit forms part of the gate driver circuit. [16] Liquid crystal display according to claim 15, wherein the gate driver circuit further comprises a shift register. [17] Liquid crystal display according to claim 16, wherein the level converter circuit is coupled to the shift register. [18] Liquid crystal display according to claim 17, wherein the gate driver circuit includes a buffer circuit. [19] Liquid crystal display according to claim 18, wherein the buffer circuit is coupled to the level converter circuit and generates the gate line signals, and wherein the shift register provides signals with a first voltage swing, wherein the level converter adapts the first voltage swing to a second voltage swing, and wherein the buffer circuit receives the signals from the shift register with the first voltage swing and receives signals from the level converter with the second voltage swing. [20] Liquid crystal display according to claim 16, wherein the shift register provides signals with a first voltage swing, wherein the level converter adapts the first voltage swing to a second voltage swing, and wherein the gate driver circuit includes a buffer circuit that receives the signals from the shift register with the first voltage swing.