Optoelectronic semiconductor chip

Abstract

Optoelectronic semiconductor chip (1) comprising - a semiconductor layer sequence (2) containing semiconductor material, comprising a first semiconductor region (3) of a first conductivity type and a second semiconductor region (4) of a second conductivity type and an active zone (5) with a pn junction formed between the first and the second semiconductor region (3, 4), - a support (6) on which the semiconductor layer sequence (2) is arranged, - a first contact (7) which is provided for electrically connecting the first semiconductor region (3), - a second contact (8) different from the first contact (7), which is provided for electrically connecting the second semiconductor area (4), - a bridging element (9) connected in parallel or antiparallel to the semiconductor layer sequence (2), which has a non-linear electrical resistance that is higher than the electrical resistance of the semiconductor layer sequence (2) in the forward direction at an operating voltage of the optoelectronic semiconductor chip (1) and lower than the electrical resistance of the semiconductor layer sequence (2) in the reverse direction at overvoltages, so that electrical charge is dissipated via the bridging element (9) in the event of overvoltages, wherein the bridging element (9) has at least one bridging layer (9A) which is arranged outside the semiconductor material of the semiconductor layer sequence (2), wherein - the bridging element (9) is provided on the semiconductor layer sequence (2) and the bridging element (9) is in direct physical contact with the semiconductor layer sequence (2), and the bridging element (9) is directly adjacent to the first semiconductor region (3), the active zone (5) and / or the second semiconductor region (4), and wherein - the bridging element (9) is provided on the support (6), and wherein the support (6) has a base body (15) and at least one first connection element (16) and a second connection element (17) which are at least partially embedded in and / or arranged on the base body (15), - the first connecting element (16) is electrically connected to the first contact (7), - the second terminal element (17) is electrically connected to the second contact (8), and wherein the first and second terminal elements (16, 17) are connected to each other by the bridging element (9).

Description

[0001] An optoelectronic semiconductor chip is specified, which is specifically intended for radiation emission.

[0002] Document DE 10 2009 053 064 A1 describes a thin-film semiconductor device with an active region designed for generating radiation and featuring a protective diode structure. Document JP 2005 - 136 177 A describes a III-V nitride semiconductor device, in particular a structure with high electrical breakdown strength.

[0003] Protective measures are advantageous in order to enable stable operation of an optoelectronic component and to largely avoid permanent damage to the component even in the event of electrostatic discharges or electrical overload.

[0004] For example, publication WO 2012 / 146668 A1 describes a protective measure involving the inclusion of an epitaxial protective layer in the semiconductor layer sequence of a semiconductor chip. This protective layer features intentionally introduced crystal defects, and during operation of the semiconductor chip, the reverse breakdown behavior of the semiconductor layer sequence differs between regions with crystal defects and regions without. Furthermore, during electrostatic discharge pulses, electrical charge is dissipated homogeneously across the regions with crystal defects. Additionally, publication WO 2011 / 080219 A1 describes an optoelectronic semiconductor chip with a semiconductor layer sequence comprising a multitude of microdiodes, where the microdiodes provide ESD (electrostatic discharge) protection. However, such protective measures in the semiconductor layer sequence result in a loss of the semiconductor chip's optical efficiency.

[0005] Furthermore, it is known, for example, from publication DE 103 29 082 A1, to use a separate protective element, such as a protection diode, and to connect it to the semiconductor chip. However, this requires additional space and costs.

[0006] One of the tasks to be solved here is to specify an improved optoelectronic semiconductor chip with integrated ESD protection.

[0007] This problem is solved, among other things, by an optoelectronic semiconductor chip according to claim 1. Further embodiments are the subject of the dependent claims.

[0008] The optoelectronic semiconductor chip comprises a sequence of semiconductor layers containing a semiconductor material and featuring a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, and an active zone with a pn junction formed between the first and second semiconductor regions. In particular, the active zone can be designed to generate radiation.

[0009] Furthermore, the first conductivity can be a p-type conductivity and the second conductivity an n-type conductivity. For example, the first semiconductor region can be arranged on the side of the active zone facing a support. And the second semiconductor region can be arranged on the side of the active zone facing away from the support. Preferably, the first semiconductor region comprises at least one semiconductor layer having a doping of the first conductivity type. Correspondingly, the second semiconductor region particularly comprises at least one semiconductor layer having a doping of the second conductivity type.

[0010] Suitable materials for the semiconductor layers include, for example, materials based on nitride compound semiconductors. In this context, "based on nitride compound semiconductors" means that the semiconductor layer sequence, or at least one layer thereof, is a nitride III / V compound semiconductor material, preferably Al. n Ga m In 1-n-m N comprises, where 0 ≤ n ≤ 1, 0 ≤ m ≤ 1, and n+m ≤ 1. This material does not necessarily have to have a mathematically exact composition according to the formula above. Rather, it can contain one or more dopants as well as additional components that exhibit the characteristic physical properties of Al. n Ga m In 1-n-m The N-materials do not change in essence. For the sake of simplicity, however, the formula above only includes the essential components of the crystal lattice (Al, Ga, In, N), even though these may be partially replaced by small amounts of other substances.

[0011] The optoelectronic semiconductor chip comprises a substrate on which the semiconductor layer sequence is arranged. For example, the semiconductor chip can be a thin-film semiconductor chip in which a growth substrate, on which the semiconductor layer sequence was grown, has been at least partially removed. For example, the growth substrate can be replaced by the substrate.

[0012] The optoelectronic semiconductor chip further comprises a first contact, which is provided for the electrical connection of the first semiconductor area, and a second contact, distinct from the first contact, which is provided for the electrical connection of the second semiconductor area. Specifically, the first contact is a p-contact and the second contact is an n-contact.

[0013] The optoelectronic semiconductor chip includes a bridging element. The bridging element is connected in parallel or antiparallel to the semiconductor layer sequence. For example, the bridging element can exhibit the current / voltage characteristics of a diode. In this case, the bridging element is preferably connected antiparallel to the semiconductor layer sequence. Furthermore, the bridging element can exhibit the current / voltage characteristics of a varistor. In this case, the bridging element can be connected in parallel or antiparallel to the semiconductor layer sequence. The current / voltage characteristics of the varistor can be nearly identical in the forward and reverse directions. This allows overvoltages to be limited in both the reverse and forward directions.

[0014] The bridging element exhibits a non-linear electrical resistance. This resistance is higher than the electrical resistance of the semiconductor layer sequence when the optoelectronic semiconductor chip is operating in the forward direction, and lower than the electrical resistance of the semiconductor layer sequence when subjected to overvoltages in the reverse direction. This allows electrical charge to be dissipated via the bridging element during overvoltages. As a result, the semiconductor layer sequence can be protected from electrostatic discharge pulses, thus largely preventing damage to the semiconductor chip.

[0015] According to at least one embodiment, the bridging element comprises a polycrystalline electroceramic material. Suitable electroceramic materials include, for example, sintered semiconductor materials. In particular, materials such as zinc oxide, strontium oxide, strontium titanate, titanium oxide, and silicon carbide are suitable for the bridging element. The resistance can be influenced by the grain size of the material used. When such materials are used, the bridging element exhibits characteristics similar to a varistor.

[0016] Furthermore, the bridging element can contain material additives, for example oxides such as bismuth, antimony, cobalt, manganese, nickel, chromium, or silicon oxides. Advantageously, the nonlinear resistance behavior of the bridging element can be specifically adjusted by means of one or more of these material additives.

[0017] In a preferred embodiment, the bridging element has two bridging layers separated by an interface. For example, the concentration of material additives at the interface can be higher than in the two bridging layers. Upon reaching the breakdown stress, the breakdown occurs, in particular, transversely, preferably perpendicularly, to the interface. The breakdown can occur in a horizontal or vertical direction. The vertical direction can be perpendicular to a plane in which the beam extends. Similarly, the horizontal direction can be parallel to a plane in which the beam extends.

[0018] In particular, the bridging element can have more than two bridging layers, each separated from the other by an interface. Within the manufacturing tolerances, a principal extent plane of the interface can run parallel to a principal extent plane of the bridging layers.

[0019] Furthermore, the bridging element can contain one or more dopants.

[0020] According to another embodiment, the bridging element can contain or consist of a metal or a metallic compound. Suitable materials include, for example, Ti, Ag, Pt, Au, or Cu. When such materials are used, the bridging element exhibits, in particular, the characteristics of a diode.

[0021] The bridging element comprises at least one bridging layer. In particular, the bridging element consists of at least one bridging layer. The bridging layer is located outside the semiconductor material of the semiconductor layer sequence. This means, in particular, that the bridging layer is not an epitaxial layer. This reduces optical losses in the semiconductor layer sequence. Alternatively or additionally, "outside the semiconductor material of the semiconductor layer sequence" can mean that the bridging layer is not completely covered by the semiconductor material of the semiconductor layer sequence at its outer surfaces. The bridging layer can, for example, be applied to and / or on an outer surface of the semiconductor layer sequence. The bridging layer can, for example, contain or consist of a polycrystalline electroceramic material.

[0022] In an advantageous embodiment, the bridging layer is structured and has several bridging areas that are separated from each other by gaps in which the bridging layer is interrupted.

[0023] According to at least one embodiment, the bridging element is provided on the semiconductor layer sequence. "Provided on the semiconductor layer sequence" here and in the following can mean that the bridging element is in direct physical contact with the semiconductor layer sequence. In particular, the bridging element can be directly adjacent to the first semiconductor region, the active zone, and / or the second semiconductor region.

[0024] In a preferred embodiment, the bridging element connects the first and second semiconductor regions to each other and / or a semiconductor region to the respective contact. In particular, the bridging element can directly connect the first and second semiconductor regions. It is possible for the bridging element to be in direct contact with at least one of the two semiconductor regions. Specifically, the bridging element can cover the pn junction. Furthermore, the bridging element can connect the first and second contacts to each other. "Covering" here and in the following means that the bridging element at least partially covers the pn junction in a side view. In particular, it is possible for the bridging element to extend laterally from the first semiconductor region, across the active zone, to the second semiconductor region.“A lateral view” can, in this context and in the following, in particular be a view perpendicular to a principal extension plane of the semiconductor layer sequence.

[0025] In a preferred embodiment, the bridging element has a bridging layer deposited on the semiconductor layer sequence. Preferably, the bridging layer is in direct contact with the semiconductor layer sequence. The bridging layer can extend from the first contact to the second contact and laterally cover the pn junction. The current-voltage behavior of the bridging element is determined in particular by the interaction of the semiconductor layer sequence and the bridging layer. For example, the bridging layer can form a contact with the second semiconductor region of the second conductivity type with ohmic resistance and a contact with the first semiconductor region of the first conductivity type with non-linear resistance. In this case, the current-voltage behavior of the bridging element can exhibit the characteristics of a Schottky diode.In particular, the bridging element exhibits a breakdown voltage that is above the operating voltage of the semiconductor layer sequence in the forward direction and below the breakdown voltage of the semiconductor layer sequence in the reverse direction. During reverse-bias discharge pulses, these are advantageously dissipated via the bridging element and not via the active region. Furthermore, the current-voltage behavior of the bridging element can exhibit the characteristics of a varistor. Advantageously, the breakdown voltage of the varistor is below the breakdown voltage of the active region in both the forward and reverse directions.

[0026] According to at least one embodiment, the semiconductor layer sequence has a first main surface facing the substrate and a second main surface facing away from the substrate, and at least one side surface that is inclined, i.e., not parallel, to the first and second main surfaces. The first and second main surfaces can extend along a principal plane of the semiconductor layer sequence.

[0027] In a preferred embodiment, the bridging element or bridging layer is arranged on a side face of the semiconductor layer sequence. In particular, the bridging element or bridging layer is in direct contact with the first and second semiconductor regions. Furthermore, the bridging element or bridging layer advantageously extends from the first contact across a side face of the first and second semiconductor regions to the second contact. For example, the first contact can be arranged on the second main surface. The second contact can be provided on a portion of the second semiconductor region that projects beyond the first semiconductor region.In this configuration, the distance between the two contacts is smaller than when the second contact is positioned on the first main surface, resulting in a shorter length for the bridging element extending from the first to the second contact. Advantageously, the resistance of the bridging element can be influenced, among other things, by its length.

[0028] In a preferred embodiment, the pn junction is covered by an electrically insulating coating, which is arranged between the semiconductor layer sequence and the bridging element or bridging layer, so that the active zone is electrically isolated from the bridging element or bridging layer.

[0029] In a further embodiment, the bridging element can be provided on an inner surface of the semiconductor layer sequence. For example, the semiconductor layer sequence can have a depression bounded by the inner surface. Preferably, the depression extends from the first main surface, through the first semiconductor region and the active zone, towards the second main surface and into the second semiconductor region. In particular, the bridging layer is arranged on the inner surface. Furthermore, the bridging layer can be in direct contact with the first and second semiconductor regions. Advantageously, the bridging layer can also extend from the first contact, which is preferably located on the first main surface, across the inner surface to the second contact, which is preferably located within the depression.

[0030] According to at least one embodiment, a large portion of the generated radiation is coupled out of the semiconductor chip through the second main surface. Preferably, the second main surface is uncovered by the first and second contacts. In other words, the second main surface can be free of the first and second contacts in a top view. Advantageously, this reduces absorption losses caused by the contacts.

[0031] In a preferred embodiment, the semiconductor layer sequence is energized on the carrier side. This means that both contacts are provided on the carrier.

[0032] According to at least one embodiment, at least one of the two contacts has a contact element. For example, the second contact can have a contact element arranged in the recess of the semiconductor layer sequence. In particular, the contact element is surrounded circumferentially by the bridging element. The bridging element can be applied as a coating to the inner surface of the semiconductor layer sequence that defines the recess. The bridging element can replace an insulating layer during normal operation.

[0033] In a preferred embodiment, the first contact has a contact layer interrupted by an opening. Preferably, the contact element of the second contact extends through the opening in the contact layer of the first contact. Particularly preferably, the contact layer and the contact element are connected to each other by the bridging element.

[0034] In a preferred embodiment, the first contact and the second contact each have a contact layer that is connected to each other by the bridging element. In particular, the contact layer of the first contact is arranged between the support and the first semiconductor region. Furthermore, the contact layer of the second contact can also be arranged between the support and the first semiconductor region.

[0035] Under normal operating conditions, i.e., below the breakdown voltage of the semiconductor chip, the bridging element is electrically non-conductive, thus acting as an insulator and advantageously replacing an insulating layer. Upon reaching the breakdown voltage, the bridging element advantageously becomes electrically conductive, allowing electrical charge to be dissipated via the bridging element. This protects the pn junction from damaging discharge pulses.

[0036] In an advantageous embodiment, the surface of the semiconductor layer sequence is pretreated at the locations where the bridging element is to be formed. For example, partial passivation, plasma treatment, or partial etching of the semiconductor layer sequence can be carried out, in particular to influence the electrical conductivity at the interface between the semiconductor layer sequence and the bridging element.

[0037] Overall, the current-voltage behavior of the bridging element can be adjusted as desired by selecting a suitable material for the bridging element and / or a suitable pretreatment of the semiconductor layer sequence and / or a suitable geometry.

[0038] According to at least one embodiment, the bridging element is provided on the support.

[0039] The carrier comprises a base body. Furthermore, the carrier includes at least one connection element that is electrically connected to the first or second contact. In other words, at least one of the contacts is electrically connected by means of the carrier or the connection element. The connection element is at least partially embedded in the base body and / or arranged on the base body.

[0040] The carrier has a first and a second terminal element, which are connected to each other by the bridging element. This connection can be, in particular, a mechanical one. It is also possible that the first and second terminal elements are directly adjacent to the bridging element. The first terminal element is electrically connected to the first contact, and the second terminal element is electrically connected to the second contact. The first and second terminal elements are electrically isolated from each other by the bridging element when the semiconductor chip is operated in the forward direction. The bridging element can be positioned between the first and second terminal elements and cover all outer surfaces of the first and / or second terminal elements that face the other terminal element.Furthermore, when a breakdown voltage is reached in the reverse direction, the bridging element advantageously becomes electrically conductive, so that electrical charges can be dissipated from the semiconductor chip via the carrier.

[0041] According to at least one embodiment, the first terminal element has a first via extending from a front to a rear surface of the base body and electrically connected to the first contact. Furthermore, the second terminal element can have a second via extending from the front to the rear surface and electrically connected to the second contact.

[0042] Furthermore, the first connection element can have a first connection layer arranged on the base body, which is electrically connected to the first contact. The second connection element can have a second connection layer arranged on the base body, which is electrically connected to the second contact.

[0043] According to at least one embodiment, the base body is formed by the bridging element. Alternatively, the bridging element can be arranged on the front or rear surface of the base body.

[0044] In all described arrangement options, the bridging element, regardless of whether it is provided on the semiconductor layer sequence or on the carrier, is integrated into the semiconductor chip, so that the semiconductor chip is advantageously designed to save space.

[0045] Furthermore, in the optoelectronic semiconductor chip described here, the bridging element can withstand several overvoltage pulses without significant changes to its electrical behavior. This increases the semiconductor chip's stability against electrostatic discharges and / or electrical overload. Additionally, eliminating the need for external protection elements can reduce manufacturing costs.

[0046] Further advantages, advantageous embodiments and further developments result from the following in conjunction with the Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17 to Fig. 18 described embodiments.

[0047] They show: Fig. Figures 1, 2 and 6 to 14 are schematic cross-sectional views of various embodiments of an optoelectronic semiconductor chip described here. Fig. 3 and Fig. 15 schematic cross-sectional views of sections of various embodiments of an optoelectronic semiconductor chip described here, Fig. 4 a schematic cross-sectional view of a section of an optoelectronic semiconductor chip described herein according to an exemplary embodiment and Fig. 5A a possible equivalent circuit diagram for this, and Fig. 5B another possible equivalent circuit diagram, Fig. 16 and Fig. 17 schematic cross-sectional views of sections of various embodiments of a multi-layered bridging element, Fig. Figure 18 shows a schematic cross-sectional view of an arrangement with multiple semiconductor layer stacks.

[0048] In Fig. Figure 1 shows an embodiment of an optoelectronic semiconductor chip 1, which has a semiconductor layer sequence 2 with a first semiconductor region 3 of a first conductivity type and a second semiconductor region 4 of a second conductivity type. In particular, the first semiconductor region 3 is a p-type region and the second semiconductor region 4 is an n-type region. An active zone 5 with a pn junction is formed between the first semiconductor region 3 and the second semiconductor region 4. In particular, the active zone 5 is provided for radiation generation. The semiconductor layer sequence 2 is preferably made of a nitride compound semiconductor.

[0049] Furthermore, the optoelectronic semiconductor chip 1 comprises a substrate 6 on which the semiconductor layer sequence 2 is arranged. For example, the substrate 6 can contain sapphire or consist of sapphire. Such a substrate 6 is particularly suitable for growing a semiconductor layer sequence 2 made of a nitride compound semiconductor. Furthermore, such a substrate 6 is advantageously transparent to the radiation generated by the active zone 5, so that the radiation can couple out of the semiconductor chip 1 through the substrate 6.

[0050] The semiconductor layer sequence 2 has a first main surface 2A, which is arranged on a side of the active zone 5 facing the support 6. Furthermore, the semiconductor layer sequence 2 has a second main surface 2B, which is arranged on a side of the active zone 5 facing away from the support 6. The semiconductor layer sequence 2 also has several side surfaces 2C, which are arranged transversely to the main surfaces 2A and 2B. The optoelectronic semiconductor chip 1 comprises a first contact 7, which is provided for electrically connecting the first semiconductor region 3 and is in particular a p-contact, and a second contact 8, which is provided for electrically connecting the second semiconductor region 4 and is in particular an n-contact. The first contact 7 is arranged on the second main surface 2B. The second contact 8 is arranged on a partial area 4A of the second semiconductor region 4 that projects beyond the first semiconductor region 3.

[0051] The optoelectronic semiconductor chip 1 comprises a bridging element 9, which is arranged on a side face 2C of the semiconductor layer sequence 2. The bridging element 9 has a bridging layer 9A, which is located outside the semiconductor layer sequence 2. The bridging layer 9A covers the pn junction of the active region 5. Furthermore, the bridging layer 9A extends from the first contact 7 to the second contact 8.

[0052] The current-voltage behavior of the bridging element 9 can be determined, in particular, by the interaction of the semiconductor layer sequence 2 and the bridging layer 9A. The bridging layer 9A can, for example, form a contact with the second semiconductor region 4 with ohmic resistance and a contact with the first semiconductor region 3 with non-linear resistance. The bridging element 9 exhibits, in particular, the characteristics of a Schottky diode. For example, the bridging layer 9A can contain or consist of a metal or a metallic compound. Suitable materials include, for example, Ti, Ag, Pt, Au, or Cu. Specifically, the bridging element 9 has a breakdown voltage that is higher in the forward direction than the operating voltage of the semiconductor layer sequence 2 and lower in the reverse direction than the breakdown voltage of the semiconductor layer sequence 2.When the breakdown voltage in reverse bias is reached, electrical charge is advantageously dissipated via the bridging element 9 and not via the active zone 5.

[0053] Furthermore, the bridging element 9 can exhibit the characteristics of a varistor. Advantageously, the breakdown voltage of the varistor is lower than the breakdown voltage of the semiconductor layer sequence 2 in both the forward and reverse directions, so that when the breakdown voltage is reached, the electrical charge is advantageously dissipated via the bridging element 9 and not via the active zone 5.

[0054] The bridging element 9, or bridging layer 9A, contains, in particular, a polycrystalline electroceramic material. Suitable electroceramic materials include, for example, sintered semiconductor materials. Materials such as zinc oxide, strontium oxide, strontium titanate, titanium oxide, and silicon carbide are particularly suitable for the bridging element 9. Furthermore, the bridging element can contain material additives, such as oxides of bismuth, antimony, cobalt, manganese, nickel, chromium, or silicon oxides. Advantageously, the nonlinear resistance behavior of the bridging element 9 can be specifically adjusted by means of one or more of these material additives.

[0055] The side surface 2C of the semiconductor layer sequence 2 can be pretreated before the bridging layer 9A is applied. For example, passivation, plasma treatment, or etching of the semiconductor layer sequence can be performed to selectively adjust the electrical resistance of the bridging element 9. Furthermore, the electrical resistance of the bridging element 9 can be selectively influenced by the length L of the bridging layer 9A.

[0056] The in Fig. The optoelectronic semiconductor chip 1 shown in Figure 2, according to a further embodiment, has a semiconductor layer sequence 2 with a recess 10. The recess 10 is bounded circumferentially by an inner surface 2D of the semiconductor layer sequence 2 and further by a bottom surface 2E of the semiconductor layer sequence 2. The recess 10 extends from the first main surface 2A, through the first semiconductor region 3 and the active zone 5, into the second semiconductor region 4. In particular, the recess 10 is arranged centrally. Furthermore, the recess 10 can be frustoconical in shape. The bridging element 9 is arranged on the inner surface 2D. The bridging element 9 has a bridging layer 9A which covers the active zone 5.

[0057] The first contact 7 is arranged on the first main surface 2A. The first contact 7 is applied to the first main surface 2A as a coating. Furthermore, the second contact 8 is arranged on the bottom surface 2E of the semiconductor layer sequence 2 and is applied to it, in particular, as a coating. The bridging layer 9A extends from the first contact 7 across the inner surface 2D to the second contact 8. The bridging layer 9A can advantageously be the one already described in connection with the exemplary embodiment of the Fig. The materials mentioned in section 1 and the described current-voltage behavior are present. In normal operation, the current flows predominantly through the active zone 5, while in the event of overvoltages, the current is diverted via the bridging element 9, thereby protecting the active zone 5.

[0058] The semiconductor layer sequence 2 is arranged on a support 6, which differs in particular from a growth substrate used for the growth of the semiconductor layer sequence 2. Preferably, the support 6 is formed from a metal or a metal compound. For example, the support 6 can be produced by galvanic reinforcement of a metallic starting layer. The support 6 is advantageously electrically conductive and serves for the electrical contacting of the second contact 8. The support 6 can extend into the recess 10.

[0059] The semiconductor chip 1 has an insulating layer 11 which covers the substrate 6 on surfaces facing the first main surface 7 and the inner surface 2D. The insulating layer 11 prevents an electrical connection between the first contact 7 and the substrate 6.

[0060] In this embodiment, the radiation generated in the active zone 5 is largely coupled out of the semiconductor chip 1 through the second main surface 2B. Advantageously, the semiconductor layer sequence 2 on the second main surface 2B has a structure, in particular a roughening. This improves the coupling efficiency.

[0061] In the Fig. 1 and Fig. In the two illustrated embodiments, the bridging element 9 or the bridging layer 9A is arranged on the semiconductor layer sequence 2.

[0062] In Fig. 3 is one possible variation of the one in the Fig. 1 and Fig. The embodiments shown in Figure 2 are illustrated. Here, the active zone 5 can be laterally covered with an electrically insulating coating 12, which is arranged between the semiconductor layer sequence 2 and the bridging element 9, so that the active zone 5 is electrically isolated from the bridging element 9.

[0063] Fig. Figure 4 shows a section of a semiconductor chip, for example according to one of the in Fig. 1 and Fig. In the embodiments shown in Figure 2, the bridging element 9 can exhibit both a nonlinear and an ohmic resistance in the region of the active zone 5. This is achieved through the interaction of bridging layer 9A and semiconductor layer sequence 2. For example, the nonlinear resistance can exhibit the characteristics of a Schottky diode. In the equivalent circuit diagram, the current-voltage behavior of the bridging element 9 can be represented by an ohmic resistor and a diode connected in series with the ohmic resistor. Furthermore, the current-voltage behavior of the active zone 5 can be represented by a diode. This results in a circuit arrangement for the semiconductor chip 1 in which the diode is connected antiparallel to the Schottky diode and in parallel to the ohmic resistor (see Figure 2). Fig. 5A).

[0064] Furthermore, the bridging element 9 can have the characteristics of a varistor, resulting in a circuit arrangement in which the diode is connected in parallel to the varistor (see Fig. 5B).

[0065] In Fig. Figure 6 shows a further embodiment of an optoelectronic semiconductor chip 1. Here, the semiconductor layer sequence 2 is energized from the carrier side. In particular, the carrier 6 is electrically conductive and serves for electrical contacting one of the two semiconductor regions 3, 4, preferably for electrical contacting the second semiconductor region 4. For this purpose, the carrier 6 is electrically connected to the second contact 8. The second contact 8 comprises a contact layer 8A, which is electrically and mechanically connected to the carrier 6 and covers it on a front surface facing the semiconductor layer sequence 2. Furthermore, the second contact 8 comprises several contact elements 8B, which are connected to the contact layer 8A and arranged transversely, in particular perpendicularly, to it.

[0066] The semiconductor layer sequence 2 has several depressions 10 extending from the first main surface 2A, through the first semiconductor region 3 and the active zone 5, to the second semiconductor region 4. Preferably, a contact element 8B is arranged in each depression 10.

[0067] Furthermore, the semiconductor chip 1 has a first contact 7, which comprises a contact layer 7A and a contact pad 7B. The contact layer 7A is arranged between the contact layer 8A of the second contact 8 and the semiconductor layer sequence 2. In particular, the contact layer 7A of the first contact 7 is in direct contact with the first semiconductor region 3. Advantageously, the contact layer 7A serves for the electrical contacting of the first semiconductor region 3.

[0068] The contact layer 7A has several openings 13, wherein in particular one opening 13 is arranged in the region of a recess 10. Preferably, a contact element 8B of the second contact 8 extends through an opening 13 of the contact layer 7A.

[0069] The semiconductor chip 1 has a bridging element 9 comprising a bridging layer 9A, which is arranged between the contact layer 7A of the first contact 7 and the contact layer 8A of the second contact 8. The bridging element 9 and / or the bridging layer 9A can be formed with an electroceramic material and / or a metal oxide. In normal operation, the two contact layers 7A and 8A are thus electrically isolated from each other by the bridging layer 9A.

[0070] The bridging element 9 comprises further bridging layers 9A, which are arranged in the recesses 10 and openings 13. In particular, each contact element 8B is circumferentially surrounded by a bridging layer 9A. This allows each contact element 8B to be electrically isolated circumferentially from the contact layer 7A and the semiconductor layer sequence 2 during normal operation.

[0071] The contact pad 7B is located on a portion of the contact layer 7A that extends beyond the semiconductor layer sequence 2. The contact pad 7B can be connected to an electrical conductor 14.

[0072] In Fig. Figure 7 shows another embodiment of an optoelectronic semiconductor chip 1. Here, the semiconductor layer sequence 2 is as in the one shown in Fig. In the embodiment shown in Figure 6, the current is supplied from the carrier side. However, the carrier 6 is electrically insulating. The first and second contacts 7, 8 each have a contact layer 7A, 8A, which is arranged on the carrier 6 and projects beyond the semiconductor layer sequence 2. On the free areas of the contact layers 7A, 8A not covered by the semiconductor layer sequence 2, these can each be connected to an electrical conductor 14.

[0073] In this embodiment, the bridging element 9 forms an almost complete encapsulation for the second contact 8. Only the ends of the contact elements 8B and the free area of ​​the contact layer 8A, to which the electrical conductor 14 is connected, are uncovered by the bridging element 9, so that in normal operation current can be impressed into the second semiconductor region 4 via the electrical conductor 14 and the second contact 8.

[0074] Another embodiment of an optoelectronic semiconductor chip 1, in which the semiconductor layer sequence 2 is energized on the carrier side, is described in Fig. Figure 8 illustrates this. The carrier 6 comprises a base body 15, a first terminal element 16 for electrically contacting the first contact 7, and a second terminal element 17 for electrically contacting the second contact 8. Each of the two terminal elements 16, 17 comprises a terminal layer 16A, 17A and several vias 16B, 17B. The terminal layers 16A, 17A are arranged on a rear surface of the base body 15 facing away from the semiconductor layer sequence 2. The vias 16B, 17B extend from a front surface of the base body 15 facing the semiconductor layer sequence 2 to the rear surface of the base body 15. Current can be supplied to the semiconductor layer sequence 2 via the terminal elements 16, 17. Preferably, the base body 15 contains an electrically insulating material.

[0075] The bridging element 9 is arranged between the second contact 8 and the first contact 7, as well as between the second contact 8 and the semiconductor layer sequence 2, and acts as an insulator during normal operation. In the event of overvoltages, the bridging element 9 becomes electrically conductive, allowing electrical charge to be dissipated from the semiconductor chip 1 via the bridging element 9 and the carrier 6.

[0076] The in Fig. Figure 9 illustrates an embodiment of an optoelectronic semiconductor chip 1, showing a variation of the bridging element 9, which is also used in the [reference to be added] Fig. 6, Fig. 7 to Fig. The 8 illustrated embodiments are conceivable.

[0077] Here, the bridging layers 9A, which surround the contact elements 8B on their circumference, are replaced by passivation layers 18. In particular, the passivation layers 18 are not electrically conductive both during normal operation and in the event of overvoltages, so that the electrical charge in the event of overvoltages can only be dissipated via the bridging element 9 arranged between the two contact layers 7, 8.

[0078] Alternatively, the bridging layer 9A arranged between the two contact layers 7A, 8A can be replaced by a passivation layer 18, as is the case in the Fig. 10 is shown as an embodiment of an optoelectronic semiconductor chip 1.

[0079] In the Fig. 11, Fig. 12 to Fig. Figure 13 shows further embodiments of optoelectronic semiconductor chips 1 that are energized on the carrier side. Furthermore, the bridging elements 9 are shown according to the [reference to be added]. Fig. 11, Fig. 12 to Fig. The bridging elements 9 are structured in the exemplary embodiments shown in Figure 13. In particular, the bridging elements 9 have several bridging regions 9B, which are separated from one another by gaps 19. In the illustrated embodiments, the bridging regions 9B are arranged on the first main surface 2A, so that the first main surface 2A is partially covered by the bridging regions 9B. For example, one of the two contacts 7, 8, preferably the first contact 7, extends into the gaps 19. To reduce the contact resistance, an electrically conductive layer 20 can be arranged between the semiconductor layer sequence 2 and the contact 7, 8 located in the gaps 19. Preferably, the electrically conductive layer 20 is formed from a transparent conductive oxide. During normal operation, current is injected into the semiconductor layer sequence 2 via the gaps 19.When the breakdown voltage is reached, discharge pulses are dissipated, among other things, via the bridging areas 9B, so that the active zone 5 can be protected.

[0080] At the in Fig. In the embodiment shown in Figure 11, a recess 10 is arranged at a central location in the semiconductor layer sequence 2, in which part of the second contact 8 is provided. Furthermore, the first contact 7 has a contact layer 7A with an opening 13, in which another part of the second contact 8 is arranged. The second contact 8 extends to a connection layer 17A arranged on the carrier 6 and is mechanically and electrically connected to it. In particular, the connection layer 17A also serves to fasten the semiconductor layer sequence 2 to the carrier 6. In particular, the carrier 6 is electrically conductive.

[0081] A bridging layer 9A of the bridging element 9 is arranged between the first contact 7 and the carrier 6, so that the first contact 7 is electrically isolated from the carrier 6 during normal operation. A contact area 7B is provided on a region of the contact layer 7A that is not covered by the semiconductor layer sequence 2. In this embodiment, the first contact has, in addition to the contact layer 7A, further layers 22, which are particularly reflective. A reflective layer 22 can also be arranged between the second contact 8 and a bridging layer 9A surrounding the second contact 8. Overall, the reflective layers 22 can improve the extraction efficiency of the radiation emitted via the second main surface 2B.

[0082] At the in Fig. In the embodiment shown in Figure 12, the contact areas 7B, 8C of the two contacts are arranged laterally to the semiconductor layer sequence 2 on opposite sides. The carrier 6 can be designed to be electrically insulating.

[0083] At the in Fig. In the embodiment shown in Figure 13, the first contact 7 is electrically connected to the carrier 6. Furthermore, the carrier 6 is electrically conductive, so that the semiconductor layer sequence 2 can be electrically connected via the carrier 6 and the first contact 7.

[0084] In Fig. Figure 14 shows a further embodiment of an optoelectronic semiconductor chip 1 in which the bridging element 9 is provided on the carrier side. In particular, the bridging element 9 has a bridging layer 9A, which forms the base body 15 of the carrier 6. The vias of the terminal elements 16, 17 are embedded in the base body 15.

[0085] At the in Fig. In the exemplary embodiment of a carrier 6 shown in Figure 15, the bridging element 9 is arranged on the carrier side. The bridging element 9 is part of the carrier 6 and is provided on a front surface of the base body 15. A sequence of semiconductor layers can be arranged on the bridging element 9. Alternatively, the bridging element 9 can be arranged on a rear surface of the base body 15, which faces away from the semiconductor layer sequence in the finished semiconductor chip. The vias 16B, 17B of the terminal elements are embedded in the bridging element 9. For example, the carrier 6 can be made of a semiconductor material, preferably silicon.

[0086] In Fig. Figure 16 shows an embodiment of a bridging element 9 that connects a contact area 7B of a first contact with a contact element 8B of a second contact or two vias 16B, 17B. The bridging element 9 has several bridging layers 9A, each separated from the others by an interface 9C. In particular, the concentration of material additives at the interface 9C is higher than in the adjacent bridging layers 9A. Upon reaching the breakdown voltage, the breakdown occurs, in particular, transversely, preferably perpendicularly, to the interface 9C (see arrow). In this embodiment, the breakdown occurs in a horizontal direction. The horizontal direction is, in particular, parallel to a plane in which the carrier extends.

[0087] In Fig. Figure 17 shows an embodiment of a bridging element 9 in which the breakthrough is in the vertical direction (see arrow). The vertical direction is perpendicular to a plane in which the support extends. The bridging element 9 connects a contact layer 7A of a first contact to a contact layer 8A of a second contact, or a connection layer 16A of a first connection element to a connection layer 17A of a second connection element. The bridging element 9 has several bridging layers 9A, each separated from the others by an interface 9C. In particular, the concentration of material additives at the interface 9C is higher than in the adjacent bridging layers 9A.

[0088] In Fig.Figure 18 shows an embodiment of an arrangement with several semiconductor layer stacks 200 arranged on a common substrate 6. The individual semiconductor layer stacks 200 have a similar structure to the semiconductor chips already described. An electrically conductive interconnect layer 21 is arranged between the semiconductor layer stacks 200 and the substrate 6. This connects the first contact 7 of one semiconductor layer stack 200 to the second contact 8 of the adjacent semiconductor layer stack 200. The semiconductor layer stacks 200 are thus connected in series. In particular, the bridging element 9 is arranged between the interconnect layer 21 and the respective contacts 7, 8 that adjoin the interconnect layer 21.

Claims

Optoelectronic semiconductor chip (1) comprising: - a semiconductor layer sequence (2) containing semiconductor material, comprising a first semiconductor region (3) of a first conductivity type and a second semiconductor region (4) of a second conductivity type and an active zone (5) with a pn junction formed between the first and the second semiconductor region (3, 4); - a substrate (6) on which the semiconductor layer sequence (2) is arranged; - a first contact (7) provided for electrically connecting the first semiconductor region (3); - a second contact (8) different from the first contact (7) provided for electrically connecting the second semiconductor region (4); - a bridging element (9) connected in parallel or antiparallel to the semiconductor layer sequence (2) and having a nonlinear electrical resistance.which, at an operating voltage of the optoelectronic semiconductor chip (1) in the forward direction, is higher than an electrical resistance of the semiconductor layer sequence (2) and, at overvoltages in the reverse direction, is lower than the electrical resistance of the semiconductor layer sequence (2), so that electrical charge is dissipated via the bridging element (9) in the event of overvoltages, wherein the bridging element (9) has at least one bridging layer (9A) which is arranged outside the semiconductor material of the semiconductor layer sequence (2), wherein the bridging element (9) is provided on the semiconductor layer sequence (2) and the bridging element (9) is in direct physical contact with the semiconductor layer sequence (2), and the bridging element (9) is directly adjacent to the first semiconductor region (3), the active zone (5) and / or the second semiconductor region (4), and wherein the bridging element (9) is provided on the support (6).and wherein the carrier (6) has a base body (15) and at least one first connection element (16) and a second connection element (17) which are at least partially embedded in and / or arranged on the base body (15), - the first connection element (16) is electrically connected to the first contact (7), - the second connection element (17) is electrically connected to the second contact (8), and wherein the first and second connection elements (16, 17) are connected to each other by the bridging element (9). Optoelectronic semiconductor chip according to the preceding claim, wherein the bridging layer (9A) is not an epitaxial layer. Optoelectronic semiconductor chip according to one of the preceding claims, wherein the bridging element (9) and / or the bridging layer (9A) comprises a polycrystalline electroceramic material. Optoelectronic semiconductor chip (1) according to one of the preceding claims, wherein the bridging element (9) connects the first and second semiconductor area (3, 4) together and / or connects a semiconductor area (3, 4) to the respective contact (7, 8). Optoelectronic semiconductor chip (1) according to one of the preceding claims, wherein the bridging element (9) connects the first and second contacts (7, 8) together. Optoelectronic semiconductor chip (1) according to one of the preceding claims, wherein the semiconductor layer sequence (2) has a first main surface (2A) facing the support (6) and a second main surface (2B) facing away from the support (6) and a side surface (2C) which extends obliquely to the first and second main surfaces (2A, 2B), and wherein the bridging layer (9A) is arranged on the side surface (2C). Optoelectronic semiconductor chip (1) according to one of the preceding claims, wherein the semiconductor layer sequence (2) has a recess (10) which is bounded by an inner surface (2D) of the semiconductor layer sequence (2), and wherein the bridging layer (9A) is arranged on the inner surface (2D). Optoelectronic semiconductor chip (1) according to one of the preceding claims, wherein the second contact (8) has a contact element (8B) which is arranged in a recess (10). Optoelectronic semiconductor chip (1) according to claim 8, wherein the contact element (8B) is circumferentially surrounded by the bridging element (9). Optoelectronic semiconductor chip (1) according to one of the two preceding claims, wherein the first contact (7) has a contact layer (7A) which is interrupted by an opening (13) through which the contact element (8B) extends. Optoelectronic semiconductor chip (1) according to one of the preceding claims, wherein the first contact (7) has a contact layer (7A) and the second contact (8) has a contact layer (8A) which are connected to each other by the bridging element (9). Optoelectronic semiconductor chip (1) according to one of the preceding claims, wherein the bridging element (9) comprises at least one of the following materials: zinc oxide, strontium oxide, strontium titanate, titanium oxide, silicon carbide. Optoelectronic semiconductor chip (1) according to one of the preceding claims, wherein the bridging element (9) contains at least one of the following material additives: bismuth, antimony, cobalt, manganese, nickel, chromium and silicon oxide. Optoelectronic semiconductor chip (1) according to one of the preceding claims, wherein the bridging element (9) is a varistor, a Schottky diode or a Zener diode.

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