METHOD FOR CONSTRUCTING A THREE-DIMENSIONAL STORAGE DEVICE FROM MULTIPLE DECKS OF STORAGE CELLS

Abstract

Method for constructing a three-dimensional storage device from multiple decks of memory cells (232), the method comprising: Generating a first deck (120) of memory cells (232, 272), wherein the first deck (120) has multiple tiers of memory cells (232) stacked above a source ladder (112); Creating a first highly doped hollow channel in the first deck (120) for electrical coupling with the source conductor (112), wherein the creation of the first hollow channel comprises: Creating a hollow column through the first deck (120) to the source conductor (112), Deposition of a highly doped polycrystalline material along the sides of the hollow column, and Filling the hollow column with an insulator; Creating a conductive stop layer (254) in the first hollow channel of the first deck (120), wherein the stop layer (254) is electrically coupled to the source conductor (112) via the first hollow channel; Forming an inter-tier insulator (264), wherein the inter-tier insulator (264) is a buffer oxide, is formed at least partially above and directly adjacent to the conductive stop layer (254) and is significantly thicker than other layers of the insulator; performing an ion implantation into the stop layer (254); Generating a second deck (140) of memory cells (272), wherein the second deck (140) has multiple tiers of memory cells (272) stacked above the source conductor (112); and Creating a second highly doped hollow channel in the second deck (140) for electrical coupling with the stop layer (254) by two-stage stamping etching.

Description

AREA

[0001] Embodiments of the invention generally relate to stacked circuit devices and, in particular, to the creation of stacked hollow channels for a three-dimensional circuit device. BACKGROUND

[0002] Computing and electronic devices continue to shrink in size, even as they are expected to deliver higher performance and storage capacity. Furthermore, the more components are used and the larger the usable surface area, the more power the devices consume. Size and power consumption are critical factors in electronic devices, especially handheld and mobile devices. Recent advances in electronic device manufacturing offer opportunities to produce devices with higher densities. However, practical limitations in certain manufacturing techniques restrict the possibility of achieving further density increases.

[0003] US 2010 / 0109065 A1 discloses a three-dimensional non-volatile storage device and a method for its manufacture. A substrate contains alternating conductive and non-conductive layers. Furthermore, the storage device includes hollow channels that pass through the layers.

[0004] US 2013 / 0 044 531 A1 discloses a semiconductor storage device comprising: A substrate with a cell region between a first and a second interconnection region, and multiple stacking structures.

[0005] US 2014 / 0024189A1 discloses a method for manufacturing a vertical storage device.

[0006] US patent 2012 / 0104484A1 discloses a non-volatile memory. The memory comprises a stacked structure and waveguides. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The invention is specified in the independent claim. Advantageous embodiments are described in the dependent claims.

[0008] The following description includes a discussion of figures with illustrations that represent exemplary implementations of embodiments of the invention. The drawings are exemplary. As used herein, references to one or more "embodiments" are to be understood as descriptions of a particular feature, structure, and / or property that are included in at least one implementation of the invention. Thus, phrases such as "in one embodiment" or "in an alternative embodiment" appearing herein describe different embodiments and implementations of the invention and do not necessarily all refer to the same embodiment. However, they are also not necessarily mutually exclusive. Fig. Figure 1 is a block diagram of an embodiment of a stacked circuit with a hollow channel. Fig. 2A-2I are block diagrams of an embodiment of a stacked circuit. Fig. Figure 3 is a flowchart of an embodiment of a process for generating a stacked hollow channel circuit. Fig. Figure 4 is a block diagram of an embodiment of a computing system in which stacked hollow channel circuits can be implemented. Fig. Figure 5 is a block diagram of an embodiment of a mobile device in which stacked hollow channel circuits can be implemented.

[0009] Descriptions of certain details and implementations follow, including a description of the figures which may represent some or all of the embodiments described below, as well as a discussion of other possible embodiments or implementations of the inventive concepts presented herein. DETAILED DESCRIPTION

[0010] As described herein, increased density for circuit components can be achieved through three-dimensional stacking. Specifically, a three-dimensional stacked circuit device comprises multiple decks of circuit elements electrically connected by a highly doped hollow channel and a conductive stop layer. The hollow channel and stop layer enable stacking of multiple decks. Each deck comprises multiple tiers of circuit elements, thus allowing stacking of circuit elements (e.g., vertical stacking). The first deck is directly adjacent to a source conductor and includes a highly doped hollow channel that is electrically coupled to the source conductor, thereby driving the activity of the circuit elements. The highly doped hollow channel of each deck extends from one end of the deck to the other (e.g., top to bottom in a vertical stack or side by side in a horizontal stack).(a horizontal row). Between each deck is a conductive stop layer, which connects the hollow channel of one deck to the hollow channel of the adjacent deck. Thus, all hollow channels of all decks are electrically coupled to the source conductor.

[0011] In one embodiment, the circuit elements are NAND flash memory cells. Thus, the circuit device is a three-dimensional (3D) memory device. In one embodiment, the hollow channels are constructed by generating straight columns through the multiple tiers of each deck. The chemistry conventionally used to generate straight columns has limitations regarding the column depth (e.g., how many tiers can be etched through) that can be achieved with straight column profiles and uniform etching stop (i.e., all columns have the same depth). For example, in the case of many tiers of stacked word lines (e.g., 36 tiers), an extremely high aspect ratio is presented, limiting the ability of current techniques to achieve the desired processing. As described herein, multiple decks can be generated separately with separate columns, each generated at a time point in each deck.Thus, the number of required tiers that need to be etched at any one time is limited, but the total number of tiers can be greater than with conventional techniques, since multiple decks can be stacked.

[0012] It is understood that the circuit requires a conductive stop layer to stack multiple tiers of circuit elements. The conductive stop layer provides the necessary conductivity to electrically couple the upper tier(s) to the source conductor below the first tier. To be conductive, the stop layer can be a metal alloy or a highly doped material. However, it is understood that using a highly conductive stop layer can lead to the diffusion of carriers into the hollow channels. The diffusion of electrical carriers into conventional hollow channels would lead to increased irregularity in the hollow channel's performance profile. Due to the heavy doping of the hollow channel, the diffusion of carriers from the conductive stop layer will not have a negative effect on the hollow channel's performance profile.

[0013] A high doping concentration in the hollow channel will significantly increase the string current and minimize the source-drain gradient difference. Thus, high doping can minimize the difference in performance or operation of the various circuit elements. However, high doping can limit the control of the turn-off behavior in the circuit elements, especially if the deck has many circuit elements. In one embodiment, the highly doped hollow channel is kept thin. Minimizing the channel thickness can allow for more controlled turn-off behavior of the circuit elements. For example, the channel thickness can be limited by the space charge region width of a fully depleted layer for the circuit architecture of the respective circuit element. In one embodiment, the channel thickness is limited to be significantly smaller than the radius or width of the column.For example, the channel thickness can be one-fifth of the column width or the width of the entire channel, or less (where the width is a measurement across the channel as seen from a cross-section of the hollow channel). A thinner channel can improve device-to-device uniformity. In one embodiment, the use of oxidation can adjust the channel thickness and further improve the turn-off current performance of the circuit elements.

[0014] The following descriptions refer to the accompanying drawings. It is understood that the drawings do not necessarily depict elements or components to scale. Certain elements are intentionally drawn out of proportion for illustrative and explanatory purposes. It is also understood that the specific examples refer to a vertical stacking of decks, one on top of the other. In one embodiment, the circuits could be arranged horizontally.

[0015] Fig. Figure 1 is a block diagram of an embodiment of a stacked circuit with a hollow channel. A System 100 represents an electronic circuit device that uses multiple decks of circuit elements. Instead of processing all circuit elements in a single stack and attempting to create a channel to operate all circuit elements, the System 100 is processed in layers with multiple decks of circuit elements.

[0016] A substrate 110 represents a substrate or semiconductor platform on which the electronic circuit is processed. The system 100 represents a cross-section of the electronic circuit, and it is understood that typically many such circuits would be processed simultaneously on a semiconductor wafer. The processing creates (e.g., by deposition) the source conductor 112 in the substrate 110. The source conductor 112 can activate or control the circuit operation of the circuit elements of the system 100. The source conductor 112 is a highly conductive material, such as a metallic material (e.g., tungsten silicide (WSix)) or another material with many highly mobile carriers. It is understood that not all circuit elements for a functional circuit are illustrated in the system 100.

[0017] An insulator 114 (elements 114-A and 114-B) can provide a barrier between the source 112 and the first deck, deck 120. Deck 120 comprises circuit elements 122 (elements 122-A and 122-B). The circuit elements 122 are generated in tiers within deck 120. Thus, several circuit elements 122 are stacked vertically adjacent to each other within deck 120. Deck 120 can contain from a few circuit elements 122 up to more than 30 circuit elements (e.g., 36 or 38 memory cells). A hollow channel 124 extends the entire height / length from deck 120 to the source 112, thus providing electrical connectivity from the source 112 to the circuit elements 122.

[0018] Deck 140 is the second deck of system 100 and is built or processed adjacent to deck 120. Deck 140 comprises circuit elements 142 (elements 142-A and 142-B). It is understood that the multiple tiers of circuit elements, 122 and 142, can be processed in steps or layers. Thus, the desired number of tiers can determine how many layers of processing are performed. In one embodiment, the circuit elements 122 and 142 are each stacked vertically as tiers of circuit elements within their respective decks. In another embodiment, the processing that produces the circuit elements 142 is the same as the processing that produces the circuit elements 122, but is performed in a different deck separated by specific deck processing operations.

[0019] In one embodiment, the processing creates an insulator 126 (elements 126-A and 126-B) on deck 120 to provide a separator on which deck 140 can be processed. The stop layer 130 is processed at the end of the hollow channel 124 and enables electrical connectivity from the hollow channel 144 of deck 140 to the hollow channel 124 of deck 120, and thus to the source 112. It is understood that the insulator 126 can be a single insulating layer surrounding the stop layer 130. Similarly, the hollow channels 124 and 144 can each be surrounded by circuit elements 122 and 142, respectively. Thus, the designation of "A" and "B" elements is merely for illustrative purposes to demonstrate the different sides of the circuit as seen from a cross-section through the hollow channels.

[0020] In one embodiment, the hollow channels 124 and 144 are produced as deep, narrow holes or pillars in the material. It is understood that if the source 112 is a metal layer, the processing can include etching processes which will produce a good pillar with uniform properties to be able to generate the hollow channel 124. To build the deck 140 on top of the deck 120, the stop layer can also be a highly conductive or metallic material, which would allow deterministic stopping during an etching process. Thus, a hollow channel can also be produced deterministically with a uniform depth and properties like other pillars (not specifically shown) that are also produced in the deck 140. In one embodiment, the insulator 126 is relatively thick compared to the thickness required to separate tiers of circuit elements.The thickness of the insulator 126 can allow the use of a two-stage etching process (see . Fig. 2G regarding further details), to provide more uniform hollow channel characteristics for Deck 140.

[0021] The hollow channels 124 and 144 are heavily doped and thus exhibit relatively high carrier mobility. The heavily doped nature of the hollow channels eliminates concerns regarding carrier diffusion from the stop layer 130. In one embodiment, the hollow channels 124 and 144 comprise a thin conductor region surrounding an insulator (see Fig. 2A-2I regarding specific details). A thin hollow channel conductor can limit the grain size of the heavily doped support, which can further reduce the effects of support diffusion.

[0022] System 100 explicitly illustrates two decks, Deck 120 and Deck 140. It is understood that the separation of the elements in the different decks, as well as the high conductivity of the hollow channels and stop layer connecting the decks, theoretically allows for any number of decks to be stacked in System 100. In one embodiment, the number of vertical stacks is theoretically unlimited, enabling significantly more efficient use of usable semiconductor die area. Thus, the total number of circuit elements in System 100 can be doubled, tripled, or more than what the usable area would conventionally allow based on stacking. Referring to the example above, conventional circuit design can allow the use of 36 tiers of memory cells on the usable area utilized by System 100.However, System 100 can allow the use of 72, 108, or even more tiers within the same usable area. The limitation on the number of tiers of circuit elements could therefore be the cost of processing the additional decks, rather than the traditional limitations on the processing itself.

[0023] Thus, the processing could generate another insulating layer (similar to insulator 126) and another stop layer (similar to stop layer 130) directly adjacent to deck 140. The second stop layer would be adjacent to the hollow channel 144 and would allow a hollow channel of a third deck to couple electrically with the source 112. Therefore, in one embodiment, the system 100 can comprise a third deck of circuit elements that are coupled to the source 112 via the stop layers and hollow channels vertically below.

[0024] Fig. Figures 2A-2I are block diagrams of an embodiment of a stacked circuit. For the purposes of this example, they illustrate Fig. 2A to 2I represent a three-dimensionally stacked storage device, with each deck having multiple tiers of storage cells. In particular, the example in Fig. References 2A-2I provide an exemplary embodiment of a vertically stacked memory device, with one deck processed on top of another deck, each deck comprising multiple vertical tiers of memory cells. In one embodiment, such processing can be performed in a “horizontal” manner, but for a device that is stacked out of a semiconductor substrate or wafer. Thus, “vertical” stacking in one embodiment can refer to any processing that extends circuit elements out of or upward and away from the semiconductor substrate on which the devices are processed and / or arranged for operation. Such processing enables a reduced area in a plane of the semiconductor substrate to which the devices are connected, while increasing the number of devices that are stacked out of the semiconductor substrate.

[0025] Fig. Figure 2A illustrates a circuit state 202 in which multiple tiers or cells 232 have been processed above a source 222. An insulator 224 is an inter-tier insulator that isolates one tier of cells 232 from another tier. The insulator 224 can, for example, be an oxide-based insulating material. In one embodiment, the circuit includes the selection gate 226, which is processed above a layer of the insulator 224 and below the tiers of cells 232. The selection gate 226 can be used to activate the cells 232. The insulator 234 can be a masking insulator or other insulator that allows further processing above the cells 232. Each cell 232 and the selection gate 226 can be created by one or more processing operations for each tier or layer that occur prior to state 202.

[0026] In one embodiment, the column 240 is produced by a stamping etch, which removes the liner of the insulator 124 and exposes the source 222. The source 222 is a source conductor layer on a semiconductor substrate. In another embodiment, the column 240 is produced by etching and creating a liner along the walls or sides of the column 240 (the liner is not specifically illustrated). The liner can be removed before further processing of the hollow channel column.

[0027] Fig. Figure 2B illustrates a circuit state 204 in which the processing creates the hollow channel conductor. In one embodiment, the processing deposits Poly 250 over the circuit. In another embodiment, the Poly 250 is kept thin with a high concentration of in-situ doping. Poly 250 is a polycrystalline material, such as polysilicon. Poly-Si tends to result in a large number of grains, which can cause many defects. The grain size conventionally causes a significant amount of variability in the performance of the cells 232. By reducing the thickness of the highly doped Poly 250, the processing can limit the grain size relative to the channel length.

[0028] It is understood that limiting the thickness of the poly channel can restrict the grain size, as it cannot grow beyond the channel thickness. By keeping Poly 250 thin, a smaller grain size can be produced, resulting in a more uniform material and improved performance. It is understood that Poly 250 also forms on the circuit, as illustrated by the layer of poly over the circuit.

[0029] Fig. Figure 2C illustrates a circuit state 206 in which the processing fills the hollow channel with an insulator. In one embodiment, the processing grows oxide 252 onto poly 250, including within the hollow channel. Oxide 252 can contribute to the performance characteristics of the hollow channel. It is understood that, in addition to the formation of oxide within the hollow channel on poly 250, oxide is also formed on the poly, which is then deposited onto the circuit. After the channel is filled, the processing can include operations to remove the oxide and poly layers, for example, by CMP (chemical-mechanical polishing). Thus, state 206 illustrates a completed channel in column 240 with an insulator 234 (e.g., a layer of nitride) over the circuit.

[0030] The channel, as described herein, is referred to as a "hollow channel." In one embodiment, the processing fills the hollow channel with oxide 252 or another insulator. The column can still be considered a hollow channel after such processing. The channel itself is the thin layer of conductive material, poly 250. The oxide is not technically part of the channel, as it is non-conductive. Thus, a column with a thin layer of poly-conductor on the walls surrounding a layer of oxide is considered a "hollow channel."

[0031] The hollow channel can encompass the highly doped poly material surrounding the channel insulator, with the channel conductor (Poly 250) being adjacent to the cells 232. Thus, a signal passed through Poly 250 can induce a charge in the cells 232. The hollow channel Poly 250 extends through the entire circuit to the source 222.

[0032] Fig. Figure 2D illustrates a circuit state 208 in which the processing prepares the circuit for a stop layer. In one embodiment, the processing causes the conductive channel to be deepened and rounded. In one embodiment, the processing comprises a combination of wet and dry etching to deepen a portion of the channel and round a corresponding corner (e.g., an upper corner) of the insulator 234 to allow the stop layer to be filled. In another embodiment, the deepening and rounding are further customized by additional processing. For example, the processing can deposit oxynitride at a gradient concentration to adjust the deepening width and rounding profile. The gradient concentration can lead to a reduction of ions (e.g., N+ ions) in the insulator 234.

[0033] Fig. Figure 2E illustrates a circuit state 210 in which the processing generates the stop layer. The stop layer 254 can be a metallic material or another highly conductive material. In one embodiment, the stop layer 254 has a chemical property to enable good stopping in a stamping etching process. For example, the stop layer 254 can be a material that does not react with an etching chemical used to increase the column depth, which ensures that the column exposes the stop layer 254 so that another channel can connect to it. The stop layer 254 is generated between adjacent decks, and in particular between the hollow channels of two adjacent decks. It is understood that in one embodiment, each deck can have a number of cells that are horizontally separated from one another, as well as vertical stacks of cells.In one embodiment, processing the stop layer 254 includes depositing WSix and polishing the circuit (it is understood that the polishing will probably remove some of the insulator 234).

[0034] Fig. Figure 2F illustrates a circuit state 212 in which the processing performs ion implantation into the stop layer 254. In one embodiment, the stop layer 254 should be implanted with positive ions to form an ohmic contact with the channels to provide electrical continuity. As shown, N+ implantation can be used as a dopant in the stop layer. It is understood that the insulator 234 may have a gradient, as shown in Fig. 2E is introduced, which could then be reversed by ion implantation. Thus, the amount of gradient generated in state 210 can correspond to the inverse amount of dopant implantation expected in state 212. In one embodiment, the metallic nature of the stop layer 254 might necessitate a thin oxide layer on the stop layer to prevent the metal from being exposed to an implant chamber. Therefore, the cover layer 262 (which may be the same as or similar to the inter-tier insulator 224) is shown covering the insulator 234 and the stop layer 254 for state 212.

[0035] Fig. Figure 2G illustrates a circuit state 214 in which another deck is built on top of the first deck (which may be a bottom deck in a vertical implementation). The circuit, as illustrated in state 212, represents the layer or deck of the circuit closest to the source conductor 222. Similar or identical processing operations can be performed to create an inter-tier insulator 264, tiers of cells 272, an insulator 274, and columns 242 and 244. In one embodiment, the insulator 264 between the decks is a buffer oxide and is significantly thicker than other layers of the insulator. A thicker buffer oxide insulator may facilitate better processing of the columns.

[0036] It can be observed that column 242 is illustrated as extending downwards to the stop layer 254, while column 244 stops at a shallower depth, resulting in a difference 246 between column depths. The thickness of the insulator 264 can be chosen to ensure that all columns should exhibit some etching into the insulator, even if others might extend all the way in to expose the stop layer of the deck below. In one embodiment, the processing performs a two-stage punch etching to achieve columns of uniform depth. Condition 214 can represent non-selective etching by tiers of cells 272.

[0037] Fig. Figure 2H illustrates a circuit state 216 in which the processing provides uniform columns. State 216 can represent selective etching (e.g., highly selective oxide etching) to produce uniform columns 248. In one embodiment, the processing uses an endpoint to detect a signal at the stop layer 254 and stops the etching of state 214. The processing can then change the chemistry to stop very cleanly at the stop layer 254, allowing columns that have not yet been etched to the stop layer to reach it.

[0038] Fig. Figure 2I illustrates a circuit state 218 in which the processing creates the hollow channel of the upper deck. It is understood that, although labelled as cells 272 in the second deck, cells 272 are essentially the same as cells 232. They can be formed by the same processing and thus, when completed, exhibit the same characteristic behavior. They are labelled differently solely for the purpose of identifying which components are formed on which deck. The same could be said for insulators 264 and 224 and insulators 274 and 234.

[0039] In one embodiment, the processing also forms a hollow channel with poly 280 as the channel conductor and oxide 282 to insulate the hollow channel. The hollow channel of the second deck is effectively the same as the hollow channel of the first deck, but the second hollow channel is directly coupled to the stop layer 254 at one end, and the first hollow channel is directly coupled to the stop layer 254 at one end and the source 222 at the other end. It is understood that, since poly 280 is highly doped, making the insulator 264 thicker has no effect on the ability of the second hollow channel to establish an electrical connection between the source 222 and the cells 272.

[0040] It is understood that, although two decks are shown, the same techniques could be applied to create more decks on the two illustrated decks. In one embodiment, the selection gate 226 is a selection gate for all tiers of cells (both cells 232 and 272) stacked vertically above the gate. In one embodiment, the selection gate 226 is considered part of the first deck, but could also be considered as being "below" the first deck. In the case that the selection gate is considered to be below the first deck, it is understood that the first hollow channel would extend through the entire first deck to below the first deck until electrical contact is made with the source conductor.

[0041] In one embodiment, part of the circuit processing involves heating or annealing layers of the device against one another to improve contact. For example, the processing may include annealing operations after the deposition of Poly 280, which can create a lower resistance in the contact between Poly 280 and the stop layer 254. With conventional methods, the channel conductor would not be highly doped, and annealing the stop layer on the channel would create a conductive gradient, resulting in non-uniform performance in the circuit device. Because Poly 280 is highly doped, diffusion from the stop layer 254 into the hollow channel has no negative effect on the device's performance.

[0042] Fig. Figure 3 is a flowchart of an embodiment of a process for generating a stacked hollow channel circuit. Process 300 can be an example of a process for generating the circuit and circuit states from Fig. To produce 2A-2I. Process 300 can be carried out by processing equipment of a manufacturing unit.

[0043] The manufacturer configures the processing equipment and performs a series of processing steps or operations on a semiconductor wafer to create the electronic circuits. The processing equipment may include tools to perform any type of material processing operation (deposition, CMP, etching, ion implantation, annealing, others). Such processing equipment includes computer equipment and mechanical and electrical tools that perform the processing. The processing equipment is controlled by one or more processing operation controllers, which may include hardware logic and / or software / firmware logic to control the processing. The equipment may be programmed or designed to perform specific operations in a particular sequence. Collectively, the equipment and processing or configuration may be referred to as a processing system.For the purposes of process 300, the operations are described as being carried out by “the processing”, which indirectly refers to the manufacturer and the processing system used by the manufacturer.

[0044] The processing creates a source region on a semiconductor substrate, such as a silicon wafer, 302. The electronic circuit is fabricated on the source. The source is a conductor that can be activated to generate electrical activity in the circuit elements. In one embodiment, the processing deposits a buffer oxide over the source, 304. The buffer oxide is an insulator. The processing creates a selection gate for the electronic circuit, 306. In one embodiment, the selection gate is the gate for all circuit elements that are stacked vertically above it.

[0045] The processing produces a deck of tiers of circuit elements, 308. In one embodiment, the processing deposits layers or tiers of cells or other circuit elements, 310. The tiers of circuit elements are produced vertically stacked and can be processed in multiple cycles of operations, where material can be selectively deposited and removed to produce the desired circuit elements, such as memory cells. The tiers of circuit elements can be separated by an oxide material as an inter-tier insulator. The processing can also deposit an insulator, such as a nitride material, on the deck as a hard-masking insulator. In one embodiment, the processing performs a stamping etch to produce a column for a channel, the column exposing the conductor layer below the deck of cells, 312. In the first deck, the exposed conductor is the source conductor.For additional decks, the source conductor can be considered the stop layer of the deck directly below. In one embodiment, the stamping etch is performed as a two-part etching process, with a first etch to remove some material and a second etch to create a clean stop on the conductor.

[0046] The processing system deposits a thin, highly doped polycrystalline material to create a highly doped hollow conductive channel, 314. The poly material can be deposited in the column with a thin layer of oxide acting as a tunnel oxide between the highly doped channel and the circuit elements. In one embodiment, the processing system fills the hollow channel with oxide as an insulator, 316. The processing system can remove an oxide and poly layer, for example, by CMP, 318. In one embodiment, the processing system determines whether the deck of just-processed cell layers is the last layer, 320. For example, the processing system can be designed to produce a certain number of decks, and the processing system tracks how many decks have been produced.In one embodiment, the processing system allows input to control whether or not additional processing should be performed on the same wafer(s) to create an additional deck. If the deck just completed is the top deck, 322 JA branch, the processing completes the electronic devices with the finishing processing, 336.

[0047] If the deck just processed is not the last deck, 322 NO branch, the processing creates another deck on top of the deck just processed. The decks are connected to each other by a conductive stop layer. In one embodiment, the processing creates a stop layer depression, such as by etching or processing the portion of the hollow channel created in the previously completed deck, 324. In another embodiment, the processing adjusts the depression depth and / or width and / or the rounding profile for the stop layer, 326. Such adjustments can refine the depression to prepare it for the processing to be used to create the stop layer and obtain a desired stop layer profile.

[0048] The processing can deposit a conductive stop layer into the recess, 328. The deposited material could be provided with an improved performance profile by implanting the stop layer material with N+ dopants. Thus, in one embodiment, the processing creates a thin oxide layer to prevent the stop layer material directed toward an implant chamber from being exposed, 330, and then implants N+ dopants into the stop layer, 332. Such an implantation is also naturally implanted into the insulator (e.g., an insulator covering the deck), and thus the processing could additionally create a gradient profile in the insulator to compensate for the ion implant. The ion implant can also create a gradient in the stop layer, which can be normalized by the stop layer during a annealing operation.In one embodiment, the processing deposits a thick buffer oxide onto the insulator and the stop layer to prepare for the tiers of cells or circuit elements, 334. The thick buffer oxide can be deposited as an etch buffer insulator. The processing can then proceed by depositing tiers of cells, 308, and performing a similar processing procedure to produce the other deck.

[0049] Fig. Figure 4 is a block diagram of an embodiment of a computing system in which stacked hollow channel circuits can be implemented. The System 400 represents a computing device according to any embodiment described herein and can be a laptop computer, a desktop computer, a server, a gaming or entertainment control system, a scanner, a copier, a printer, a routing or switching device, or any other electronic device. The System 400 includes a Processor 420, which provides the processing, operational management, and instruction execution for the System 400. The Processor 420 can comprise any type of microprocessor, central processing unit (CPU), processing core, or other processing hardware to provide processing for the System 400.The processor 420 controls the overall operation of the system 400 and may be or include one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or the like, or a combination of such devices.

[0050] A memory subsystem 430 represents the main memory of the system 400 and provides temporary storage for code to be executed by the processor 420 or data values ​​to be used in the execution of a routine. The memory subsystem 430 can include one or more memory devices, such as read-only memory (ROM), flash memory, one or more types of random access memory (RAM), or other memory devices, or a combination thereof. The memory subsystem 430 stores and hosts, among other things, an operating system (OS) 436 to provide a software platform for executing instructions in the system 400. Additionally, further instructions 438 are stored and executed by the memory subsystem 430 to provide the logic and processing for the system 400. The OS 436 and the instructions 438 are executed by the processor 420.The memory subsystem 430 comprises a memory device 432 where data, instructions, programs, or other elements are stored. In one embodiment, the memory subsystem includes a memory controller 434, which is a memory controller for generating instructions and outputting them to the memory device 432. It is understood that the memory controller 434 could be a physical part of the processor 420.

[0051] The processor 420 and the memory subsystem 430 are coupled to the bus / bus system 410. The bus 410 is an abstraction representing any one or more separate physical buses, communication lines / interfaces, and / or point-to-point connections linked by appropriate bridges, adapters, and / or controllers. Therefore, the bus 410 can, for example, include one or more of a system bus, a Peripheral Component Interconnect (PCI) bus, a HyperTransport or Industry Standard Architecture (ISA) bus, a Small Computer System Interface (SCSI) bus, a Universal Serial Bus (USB), or an Institute of Electrical and Electronics Engineers (IEEE) Standard 1394 bus (commonly referred to as "FireWire"). The buses of bus 410 can also correspond to interfaces in a network interface 450.

[0052] The System 400 also includes one or more input / output (I / O) interfaces 440, a network interface 450, one or more internal mass storage devices 460, and a peripheral interface 470, all coupled to the bus 410. The I / O interface 440 can include one or more interface components through which a user interacts with the System 400 (e.g., video, audio, and / or alphanumeric interfacing). The network interface 450 provides the System 400 with the ability to communicate with remote devices (e.g., servers, other computing devices) over one or more networks. The network interface 450 can include an Ethernet adapter, wireless interconnection components, USB (Universal Serial Bus), or other wired or wireless standards-based or proprietary interfaces.

[0053] The storage device 460 can be or include any conventional medium for storing large amounts of data in a non-volatile manner, such as one or more magnetic, solid-state, or optical disks, or a combination thereof. The storage device 460 holds code or instructions and data 462 in a persistent state (i.e., the value is retained even if the power supply to the system 400 is interrupted). The storage device 460 can be considered generically as a "memory," although the memory 430 is the execution or operational memory for providing instructions to the processor 420. While the storage device 460 is non-volatile, the memory 430 can include volatile memory (i.e., the value or state of the data is indeterminate if the power supply to the system 400 is interrupted).

[0054] The 470 peripheral interface can include any hardware interface not specifically mentioned above. Peripherals generally refer to devices that connect dependently to the System 400. A dependent connection is one in which the System 400 provides the software and / or hardware platform on which the operation is performed and with which a user interacts.

[0055] In one embodiment, the storage subsystem 430 (e.g., storage devices 432) and / or other components of the system 400 comprise elements that are generated as stacked hollow channel circuits. By generating the circuit elements in vertical tiers, the hardware components of the system 400 can be implemented in a smaller usable area than is conventionally possible. To generate the vertical tiers, the components can be generated with multiple decks of circuit elements. The decks are interconnected by highly doped hollow channels coupled by conductive stop layers. The stacked circuit devices can be generated with two or more decks.

[0056] Fig.Figure 5 is a block diagram of an embodiment of a mobile device in which stacked hollow channel circuits can be implemented. A device 500 represents a mobile computing device, such as a computing tablet, a mobile phone or smartphone, a wireless-enabled e-reader, a portable computing device, or another mobile device. It is understood that certain components are shown generally and not all components of such a device are shown in device 500.

[0057] The device 500 comprises a processor 510, which performs the primary processing operations of the device 500. The processor 510 may comprise one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by the processor 510 include running an operating platform or operating system on which applications and / or device functions are executed. The processing operations include operations related to input / output (I / O) with a human user or with other devices, operations related to power management, and / or operations related to connecting the device 500 to another device. The processing operations may also include operations related to audio I / O and / or display I / O.

[0058] In one embodiment, the device 500 comprises an audio subsystem 520, which represents hardware components (e.g., audio hardware and audio circuits) and software components (e.g., drivers, codecs) associated with providing audio functions to the computing device. Audio functions may include speaker and / or headphone output as well as microphone input. Devices for such functions may be integrated into or connected to the device 500. In one embodiment, a user interacts with the device 500 by providing audio commands, which are received and processed by the processor 510.

[0059] A display subsystem 530 represents hardware components (e.g., display devices) and software components (e.g., drivers) that provide a visual and / or tactile display for a user to interact with the computing device. The display subsystem 530 includes a display interface 532, which comprises the respective screen or hardware device used to provide a display to a user. In one embodiment, the display interface 532 includes logic separate from the processor 510 to perform at least some processing related to the display. In one embodiment, the display subsystem 530 includes a touchscreen display that provides both output and input to a user.

[0060] An I / O controller 540 represents hardware devices and software components related to user interaction. The I / O controller 540 can operate to manage hardware that is part of the audio subsystem 520 and / or display subsystem 530. Additionally, the I / O controller 540 illustrates a connection point for additional devices that can connect to the device 500, through which a user could interact with the system. For example, devices that can connect to the device 500 could include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I / O devices for use with specific applications, such as card readers or other devices.

[0061] As mentioned above, the I / O controller 540 can interact with the audio subsystem 520 and / or display subsystem 530. For example, input via a microphone or other audio device can provide input or commands for one or more applications or functions of the device 500. Additionally, audio output can be provided instead of, or in addition to, display output. In another example, if the display subsystem includes a touchscreen, the display device also functions as an input device that can be controlled, at least partially, by the I / O controller 540. Additional buttons or switches may also be present on the device 500 to provide I / O functions that are managed by the I / O controller 540.

[0062] In one embodiment, the I / O controller 540 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, gyroscopes, a global positioning system (GPS), or other hardware that may be enclosed in the device 500. Input can be part of direct user interaction as well as providing environment-specific input to the system to influence operations (such as filtering with respect to noise, adjusting displays with respect to brightness detection, applying a flash to a camera, or other features). In one embodiment, the device 500 includes a power management system 550, which manages battery power consumption, battery charging, and features related to power-saving operations.

[0063] A memory subsystem 560 comprises memory device(s) 562 for storing information in the device 500. The memory subsystem 560 may include non-volatile (state does not change if the power supply to the memory device is interrupted) and / or volatile (state is indeterminate if the power supply to the memory device is interrupted) memory devices. The memory 560 may store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the system 500. In one embodiment, the memory subsystem 560 includes a memory controller 564 (which could also be considered part of the control system 500 and possibly part of the processor 510).The memory controller 564 includes a scheduler to generate instructions and output them to the memory device 562.

[0064] Connectivity 570 comprises hardware devices (e.g., wireless and / or wired connectors and communication hardware) and software components (e.g., drivers, protocol stack) to enable the device 500 to communicate with external devices. The external devices could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripheral devices, such as headsets, printers, or other devices.

[0065] Connectivity 570 can encompass several different types of connectivity. In general terms, the device 500 is illustrated with cellular connectivity 572 and wireless connectivity 574. Cellular connectivity 572 generally refers to cellular network connectivity provided by wireless carriers, such as GSM (Global System for Mobile Communications) or variants or derivatives, CDMA (Code Division Multiple Access) or variants or derivatives, TDM (Time Division Multiplexing) or variations or derivatives, LTE (Long Term Evolution – also known as “4G”), or other cellular service standards.Wireless connectivity (574) refers to non-cellular wireless connectivity and can include personal area networks (such as Bluetooth), local area networks (such as Wi-Fi), and / or wide area networks (such as WiMAX), or other wireless communication methods. Wireless communication refers to the transmission of data through a non-fixed medium using modulated electromagnetic radiation. Wired communication uses a fixed communication medium.

[0066] Peripheral device connections 580 comprise hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) for establishing peripheral device connections. It is understood that the device 500 can be both a peripheral device (“to” 582) to other computing devices and can have peripheral devices (“from” 584) connected to it. The device 500 typically has a “docking” connector for connecting to other computing devices for purposes such as managing (e.g., downloading and / or uploading, modifying, synchronizing) content on the device 500. Additionally, a docking connector of the device 500 may enable connection to certain peripheral devices, which allows the device 500 to control content output to, for example, audiovisual or other systems.

[0067] In addition to a proprietary docking connector or other proprietary connection hardware, the device can establish 500 peripheral connections via common or standards-based connectors. Common types may include a Universal Serial Bus (USB) connector (which may encompass any of a number of different hardware interfaces), DisplayPort including Mini DisplayPort (MDP), High Definition Multimedia Interface (HDMI), FireWire, or another type.

[0068] In one embodiment, the storage subsystem 560 (such as storage devices 562) and / or other components of the system 500 comprise elements that are generated as stacked hollow channel circuits. By generating the circuit elements in vertical tiers, the hardware components of the system 400 can be implemented in a smaller usable area than is conventionally possible. To generate the vertical tiers, the components can be generated with multiple decks of circuit elements. The decks are interconnected by highly doped hollow channels coupled by conductive stop layers. The stacked circuit devices can be generated with two or more decks.

[0069] In one aspect, a circuit device comprises: a source conductor layer on a semiconductor substrate; several decks of memory cells, the decks being stacked on top of each other, each deck comprising several tiers of stacked memory cells, each tier comprising one memory cell; and at least one hollow channel extending through the deck, the hollow channel comprising a channel insulator, and a highly doped polycrystalline material surrounding the channel insulator and arranged adjacent to the several tiers of memory cells; and a conductive stop layer between each pair of adjacent decks, the stop layer connecting a hollow channel from one deck to the hollow channel of the other deck; the hollow channel of a first deck extending from the source conductor to the stop layer between the first deck and an adjacent deck, and the hollow channel of each other deck extending from the stop layer through the deck.

[0070] In one embodiment, the multiple decks comprise more than two decks of memory cells. In one embodiment, each deck comprises more than 30 tiers of memory cells. In one embodiment, the highly doped polycrystalline material comprises highly doped polysilicon. In one embodiment, the highly doped polycrystalline material comprises a thin channel of polycrystalline material having a thickness of about one-fifth the width of the hollow channel or less. In one embodiment, the conductive stop layer comprises a highly conductive material. In one embodiment, the highly conductive material comprises a metal alloy. In one embodiment, the circuitry further comprises a select gate in the first deck, wherein the select gate is the select gate for all memory cells of the multiple decks.

[0071] In one aspect, an electronic device comprises: a three-dimensional stacked storage device for storing data, the storage device comprising: a source conductive layer on a semiconductor substrate; multiple decks of memory cells, the decks being stacked on top of each other, each deck comprising multiple tiers of stacked memory cells, each tier comprising one memory cell; and at least one hollow channel extending through the deck, the hollow channel comprising a channel insulator, and a highly doped polycrystalline material surrounding the channel insulator and arranged adjacent to the multiple tiers of memory cells; and a conductive stop layer between each pair of adjacent decks, the stop layer connecting a hollow channel from one deck to the hollow channel of the other deck;wherein the hollow channel of a first deck extends from the source conductor to the stop layer between the first deck and an adjacent deck, and the hollow channel of each other deck extends from the stop layer through the deck; and a touchscreen display coupled to generate a display based on data accessed by the storage device.

[0072] In one embodiment, the multiple decks comprise more than two decks of memory cells. In one embodiment, the highly doped polycrystalline material comprises highly doped polysilicon. In one embodiment, the highly doped polycrystalline material comprises a thin channel of polycrystalline material having a thickness of about one-fifth of the width of the hollow channel or less. In one embodiment, the conductive stop layer comprises a highly conductive material. In one embodiment, the highly conductive material comprises a metal alloy. In one embodiment, the electronic device further comprises a selection gate in the first deck, wherein the selection gate is the selection gate for all memory cells of the multiple decks.

[0073] In one aspect, a method comprises: generating a first deck of circuit elements, wherein the first deck has several tiers of circuit elements stacked above a source conductor; generating a first highly doped hollow channel in the first deck for electrical coupling with the source conductor; generating a conductive stop layer in the first hollow channel of the first deck, wherein the stop layer is electrically coupled to the source conductor via the first hollow channel; generating a second deck of circuit elements, wherein the second deck has several tiers of circuit elements stacked above the source conductor; and generating a second highly doped hollow channel in the second deck for electrical coupling with the stop layer.

[0074] In one embodiment, generating the first hollow channel further comprises: generating a hollow column through the first deck to the source conductor; and depositing a highly doped polycrystalline material along the sides of the hollow column. In another embodiment, generating the first hollow channel further comprises: depositing a highly doped polycrystalline material along the sides of the hollow column, wherein the thickness of the polycrystalline material is much smaller than the width of the hollow column; and filling the hollow column with an insulator. In another embodiment, generating the hollow column further comprises: etching the hollow column with a non-selective etching material to generate an initial depth of the hollow column; and etching the hollow column with a selective etching material to generate a clean stop of the hollow column at the source conductor. In another embodiment, generating the conductive stop layer further comprises: depositing a metal alloy.In one embodiment, generating the conductive stop layer further comprises: annealing the stop layer at the first hollow channel. In one embodiment, the conductive stop layer comprises a first conductive stop layer, the method further comprising: generating a second conductive stop layer in the second hollow channel of the second deck, wherein the second stop layer is electrically coupled to the first stop layer via the second hollow channel; generating a third deck of circuit elements, wherein the third deck has multiple tiers of circuit elements stacked above the source conductor; and generating a third highly doped hollow channel in the third deck for electrical coupling to the second stop layer. In one embodiment, the method further comprises: generating a select gate between the source conductor and the multiple tiers of the first deck, wherein the select gate is the select gate for all memory cells of the multiple decks.

[0075] In one aspect, a manufacturing article comprising a computer-readable storage medium with content stored thereon, which, when executed, performs operations, comprising: generating a first deck of circuit elements, wherein the first deck has several tiers of circuit elements stacked above a source conductor; generating a first highly doped hollow channel in the first deck for electrical coupling with the source conductor; generating a conductive stop layer in the first hollow channel of the first deck, wherein the stop layer is electrically coupled to the source conductor via the first hollow channel; generating a second deck of circuit elements, wherein the second deck has several tiers of circuit elements stacked above the source conductor; and generating a second highly doped hollow channel in the second deck for electrical coupling with the stop layer.

[0076] In one embodiment, the content for generating the first hollow channel further comprises content for generating a hollow column through the first deck to the source conductor; and depositing a highly doped polycrystalline material along the sides of the hollow column. In another embodiment, the content for generating the first hollow channel further comprises content for depositing a highly doped polycrystalline material along the sides of the hollow column, wherein the thickness of the polycrystalline material is much smaller than the width of the hollow column; and filling the hollow column with an insulator. In another embodiment, the content for generating the hollow column further comprises content for etching the hollow column with a non-selective etching material to generate an initial depth of the hollow column; and etching the hollow column with a selective etching material to generate a clean stop of the hollow column at the source conductor.In one embodiment, the content for generating the conductive stop layer further comprises content for depositing a metal alloy. In another embodiment, the content for generating the conductive stop layer further comprises content for annealing the stop layer at the first hollow channel. In another embodiment, the conductive stop layer comprises a first conductive stop layer, and further comprises content for generating a second conductive stop layer in the second hollow channel of the second deck, wherein the second stop layer is electrically coupled to the first stop layer via the second hollow channel; generating a third deck of circuit elements, wherein the third deck has several tiers of circuit elements stacked above the source conductor; and generating a third highly doped hollow channel in the third deck for electrical coupling with the second stop layer.In one embodiment, the manufactured article further comprises content for generating a selection gate between the source conductor and the multiple tiers of the first deck, wherein the selection gate is the selection gate for all memory cells of the multiple decks.

[0077] In one aspect, a device comprises: means for generating a first deck of circuit elements, wherein the first deck has several tiers of circuit elements stacked above a source conductor; means for generating a first highly doped hollow channel in the first deck for electrical coupling with the source conductor; means for generating a conductive stop layer in the first hollow channel of the first deck, wherein the stop layer is electrically coupled to the source conductor via the first hollow channel; means for generating a second deck of circuit elements, wherein the second deck has several tiers of circuit elements stacked above the source conductor; and means for generating a second highly doped hollow channel in the second deck for electrical coupling with the stop layer.

[0078] In one embodiment, the means for generating the first hollow channel further comprise means for generating a hollow column through the first deck to the source conductor; and depositing a highly doped polycrystalline material along the sides of the hollow column. In another embodiment, the means for generating the first hollow channel further comprise means for depositing a highly doped polycrystalline material along the sides of the hollow column, wherein the thickness of the polycrystalline material is much smaller than the width of the hollow column; and filling the hollow column with an insulator. In another embodiment, the means for generating the hollow column further comprise means for etching the hollow column with a non-selective etching material to generate an initial depth of the hollow column; and etching the hollow column with a selective etching material to generate a clean stop of the hollow column at the source conductor.In one embodiment, the means for generating the conductive stop layer further comprise means for depositing a metal alloy.

[0079] In one embodiment, the means for generating the conductive stop layer further comprise means for annealing the stop layer at the first hollow channel. In one embodiment, the conductive stop layer comprises a first conductive stop layer, and further comprises means for generating a second conductive stop layer in the second hollow channel of the second deck, wherein the second stop layer is electrically coupled to the first stop layer via the second hollow channel; generating a third deck of circuit elements, wherein the third deck has several tiers of circuit elements stacked above the source conductor; and generating a third highly doped hollow channel in the third deck for electrical coupling with the second stop layer.In one embodiment, the device further comprises means for generating a selection gate between the source conductor and the multiple tiers of the first deck, wherein the selection gate is the selection gate for all memory cells of the multiple decks.

[0080] In one aspect, a circuit device comprises: a source conductive layer on a semiconductor substrate; multiple decks of memory cells, the decks being vertically stacked, each deck comprising multiple tiers of vertically stacked memory cells, each tier comprising one memory cell; and at least one hollow channel extending vertically through the deck, the hollow channel comprising a channel insulator, and a highly doped polycrystalline material surrounding the channel insulator and arranged adjacent to the multiple tiers of memory cells; and a conductive stop layer between each pair of vertically adjacent decks, the stop layer connecting a hollow channel from one deck to the hollow channel of the other deck;wherein the hollow channel of a bottommost deck extends from the source conductor to the stop layer between the bottommost deck and a vertically adjacent deck, and the hollow channel of each other deck extends from the stop layer to a top surface of the deck.

[0081] In one embodiment, the multiple decks comprise more than two decks of memory cells. In one embodiment, each deck comprises more than 30 tiers of memory cells. In one embodiment, the highly doped polycrystalline material comprises highly doped polysilicon. In one embodiment, the highly doped polycrystalline material comprises a thin channel of polycrystalline material with a thickness of about one-fifth of the width of the hollow channel or less. In one embodiment, the conductive stop layer comprises a highly conductive material. In one embodiment, the highly conductive material comprises a metal alloy. In one embodiment, the circuitry further comprises a select gate in the bottommost deck, wherein the select gate is the select gate for all memory cells of the multiple decks.

[0082] In one aspect, an electronic device comprises: a three-dimensional stacked storage device for storing data, the storage device comprising: a source conductive layer on a semiconductor substrate; multiple decks of memory cells, the decks being vertically stacked, each deck comprising multiple tiers of vertically stacked memory cells, each tier comprising one memory cell; and at least one hollow channel extending vertically through the deck, the hollow channel comprising a channel insulator, and a highly doped polycrystalline material surrounding the channel insulator and arranged adjacent to the multiple tiers of memory cells; and a conductive stop layer between each pair of vertically adjacent decks, the stop layer connecting a hollow channel from one deck to the hollow channel of the other deck;wherein the hollow channel of a bottom deck extends from the source conductor to the stop layer between the bottom deck and a vertically adjacent deck, and the hollow channel of each other deck extends from the stop layer to a top surface of the deck; and a touchscreen display coupled to generate a display based on data accessed by the storage device.

[0083] In one embodiment, the multiple decks comprise more than two decks of memory cells. In one embodiment, the highly doped polycrystalline material comprises highly doped polysilicon. In one embodiment, the highly doped polycrystalline material comprises a thin channel of polycrystalline material having a thickness of about one-fifth of the width of the hollow channel or less. In one embodiment, the conductive stop layer comprises a highly conductive material. In one embodiment, the highly conductive material comprises a metal alloy. In one embodiment, the electronic device further comprises a selection gate in the bottommost deck, wherein the selection gate is the selection gate for all memory cells of the multiple decks.

[0084] In one aspect, a method comprises: generating a first deck of circuit elements, wherein the first deck has several tiers of circuit elements stacked vertically above a source conductor; generating a first highly doped hollow channel in the first deck for electrical coupling with the source conductor; generating a conductive stop layer on the top side of the first hollow channel of the first deck, wherein the stop layer is electrically coupled to the source conductor via the first hollow channel; generating a second deck of circuit elements, wherein the second deck has several tiers of circuit elements stacked vertically above the source conductor; and generating a second highly doped hollow channel in the second deck for electrical coupling with the stop layer.

[0085] In one embodiment, generating the first hollow channel further comprises: generating a hollow column from a top surface of the first deck to the source conductor; depositing a highly doped polycrystalline material along sides of the hollow column, wherein the thickness of the polycrystalline material is much smaller than the width of the hollow column; and filling the hollow column with an insulator. In one embodiment, generating the hollow column further comprises: etching the hollow column with a non-selective etching material to generate an initial depth of the hollow column; and etching the hollow column with a selective etching material to generate a clean stop of the hollow column at the source conductor. In one embodiment, generating the conductive stop layer further comprises: annealing the stop layer at the first hollow channel.In one embodiment, the conductive stop layer comprises a first conductive stop layer, and further comprising: generating a second conductive stop layer on a top side of the second hollow channel of the second deck, wherein the second stop layer is electrically coupled to the first stop layer via the second hollow channel; generating a third deck of circuit elements, wherein the third deck has several tiers of circuit elements stacked vertically above the source conductor; and generating a third highly doped hollow channel in the third deck for electrical coupling to the second stop layer.

[0086] Flowcharts, as illustrated herein, provide examples of sequences of various process actions. The flowcharts can show operations to be performed by a software or firmware routine, as well as physical operations. In one embodiment, a flowchart can illustrate the state of a finite state machine (FSM), which can be implemented in hardware and / or software. Although shown in a particular sequence or order, the order of actions can be modified unless otherwise specified. Thus, the illustrated embodiments should be understood as examples only, and the process may be carried out in a different order, and some actions may be performed in parallel. Additionally, one or more actions may be omitted in different embodiments; thus, not all actions are required in every embodiment.Other process flows are possible.

[0087] Where various operations or functions are described herein, they may be described or defined as software code, instructions, configuration, and / or data. The content may be directly executable (“object” or “executable” form), source code, or differential code (“delta” or “patch” code). The software content of the embodiments described herein may be provided via a manufactured article with the content stored thereon, or via a method for operating a communication interface to transmit data over the communication interface. A machine-readable storage medium that can cause a machine to perform the described functions or operations includes any mechanism that stores information in a form accessible to a machine (e.g., computing device, electronic system, etc.), such as recordable / unrecordable media (e.g.,Examples of storage media include read-only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc. A communication interface comprises any mechanism that is connected via an interface to any hardwired, wireless, optical, etc., medium to communicate with another device, such as a memory bus interface, a processor bus interface, an internet connection, a disk controller, etc. The communication interface can be configured by providing configuration parameters and / or sending signals to prepare the communication interface to provide a data signal describing the software content. The communication interface can be accessed by one or more commands or signals sent to it.

[0088] Various components described herein can be a means of performing the described operations or functions. Each component described herein comprises software, hardware, or a combination thereof. The components can be implemented as software modules, hardware modules, special-purpose hardware (e.g., application-specific hardware, application-specific integrated circuits (ASICs), digital signal processors (DSPs), etc.), embedded controllers, hard-wired circuits, etc.

Claims

[1] A method of constructing a three-dimensional memory device from multiple decks of memory cells (232), the method comprising: Generating a first deck (120) of memory cells (232, 272), the first deck (120) comprising multiple tiers of memory cells (232) stacked above a source conductor (112); Creating a first highly doped hollow channel in the first deck (120) for electrically coupling to the source conductor (112), wherein creating the first hollow channel comprises: Creating a hollow column through the first deck (120) to the source conductor (112), Depositing a highly doped polycrystalline material along sides of the hollow column, and Filling the hollow column with an insulator; Creating a conductive stop layer (254) in the first hollow channel of the first deck (120), wherein the stop layer (254) is electrically coupled to the source conductor (112) via the first hollow channel; Forming an inter-tier insulator (264), wherein the inter-tier insulator (264) is a buffer oxide, is formed at least partially above and directly adjacent to the conductive stop layer (254), and is substantially thicker than other layers of the insulator; performing an ion implantation into the stop layer (254); Generating a second deck (140) of memory cells (272), the second deck (140) comprising multiple tiers of memory cells (272) stacked above the source conductor (112); and Creating a second highly doped hollow channel in the second deck (140) for electrical coupling to the stop layer (254) by two-stage punch etching. [2] The method of claim 1, wherein creating the hollow column further comprises: Etching the hollow column with a non-selective etching material to create an initial depth of the hollow column; and Etching the hollow column with a selective etching material to create a clean stop of the hollow column at the source conductor (112). [3] The method of claim 1, wherein creating the conductive stop layer (254) further comprises: Deposition of a metal alloy. [4] The method of claim 1, wherein creating the conductive stop layer (254) further comprises: Annealing the stop layer (254) on the first hollow channel. [5] The method of claim 1, wherein the conductive stop layer (254) comprises a first conductive stop layer, and further comprising: Creating a second conductive stop layer in the second hollow channel of the second deck (140), wherein the second stop layer is electrically coupled to the first stop layer via the second hollow channel; generating a third deck of memory cells, the third deck comprising multiple tiers of memory cells stacked above the source conductor (112); and Creating a third highly doped hollow channel in the third deck for electrical coupling with the second stop layer. [6] The method of claim 1, further comprising: Creating a select gate between the source conductor and the plurality of tiers of the first deck, the select gate being the select gate for all memory cells of the plurality of decks.

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