Power semiconductor device

Abstract

Power semiconductor device comprising: - a silicon carbide semiconductor layer (2) of a first conductivity type; - a switching device formed on the silicon carbide semiconductor layer (2) of the first conductivity type; - a contamination area (16) of a second conductivity type for relaxing an electric field, which is formed in a terminal area of ​​a training area of ​​the switching device, and which relaxes an electric field of the terminal area; and - an added area (7, 7A, 7B) of the first conductivity type, which is provided between trough areas (3) of the second conductivity type of a plurality of unit cells forming the switching device and at least on an outer side of the impurity area (16) for the relief of an electric field, and which has an impurity concentration that is higher than an impurity concentration in the silicon carbide semiconductor layer (2), wherein: - the added area (7, 7A, 7B) is designed to be deeper than any of the tub areas (3) and - wherein the added region (7, 7A, 7B) is designed to be flatter than the impurity region (16) for relaxing an electric field.

Description

Technical area

[0001] The present invention relates to a power semiconductor device such as a silicon carbide semiconductor device. State of the art

[0002] Various efforts are being made to reduce the ON resistance of a power switching device using a wide bandgap semiconductor such as silicon carbide (SiC), where the ON resistance is one of the performance characteristics of the power switching device. For example, as described in Fig. 2A of Patent Document 1, in order to reduce an ON resistance of the switching device, an n-type region having a higher concentration than that in a drift region is formed between p-wells, or an n-type JFET confinement region having a higher concentration than that in the drift region is formed on the lower side of the p-well.

[0003] As described, a device is known in which an n-type region is formed between p-wells to reduce an ON-resistance of a switching device, and examples of the performance characteristics of a power switching device include a breakdown voltage withstand capability in addition to the ON-resistance.

[0004] In a case where relaxation of an electric field due to a structure (terminal structure) of a terminal portion of a switching device is insufficient, a breakdown voltage and reliability of the switching device are deteriorated; however, conventionally, a configuration that not only reduces an ON-resistance of a switching device but also improves the breakdown voltage withstand capability of the switching device is not disclosed. State of the art documentPatent document

[0005] Patent Document 1: Unexamined Japanese Patent Application JP 2006- 511 961 A

[0006] JP 2011-258 640 A describes a silicon carbide semiconductor device with low feedback capacitance and low switching loss.This semiconductor device includes a semiconductor substrate, a drift layer formed on a surface of the semiconductor substrate, first recess regions selectively formed on the drift layer, source regions selectively formed in regions on surfaces of the first recess regions and defining the surfaces of the first recess regions disposed between the regions and the drift layer as channel regions, a gate electrode formed from the channel regions to the drift layer via a gate insulating layer, second recess regions of a second conductive type formed in a non-contacting state with the first recess regions in at least a part of the regions except for the first recess regions in a plan view of cell placement regions in the drift layer, source electrodes in contact with the first and second well regions.

[0007] US 2013 / 0 285 071 A1 relates to a semiconductor device in which an n-type semiconductor region having a dopant concentration higher than a dopant concentration of an n-type semiconductor region is formed on a front side of a region in a silicon carbide semiconductor element in which a junction termination extension is formed. - -Drift layer. The edge of the junction termination extension is covered from the bottom to the front by an n-type semiconductor region on the side facing away from the active region. This makes it possible to obtain a device with low resistance and high dielectric strength, or, if the device's resistance is reduced, a device with low power loss.

[0008] JP 2007-184434 A discloses a semiconductor device that can improve process reproducibility and reduce the on-resistance and field value in a gate insulating film while maintaining a withstand voltage. The semiconductor device includes an n-type SiC drift layer, p-type SiC base regions selectively formed on the n-type SiC drift layer, an n-type recess region formed on the n-type SiC drift layer, n-type SiC well regions formed on the surface layer of the p-type SiC base regions, and a gate insulating film and a gate electrode formed over upper portions of the n-type SiC well regions, the p-type SiC base regions, and the n-type recess region.In this case, the n-type recess region is formed to have a higher doping density than the n-type SiC drift layer, while the recess region is formed to have a uniform density with respect to the longitudinal direction, and the lower layer side is formed to have a higher density with respect to the up-and-down direction than the side of the upper layers. Summary of the inventionProblems to be solved by the invention

[0009] As explained above, conventionally, a structure which not only reduces an ON resistance of a switching device but also improves a breakdown voltage withstand capability is not disclosed, and it is difficult to improve the yield rate of switching devices while ensuring the breakdown voltage and the reliability of the switching devices.

[0010] The present invention is intended to solve the above problem, and an object of the present invention is to provide a power semiconductor device in which an ON resistance of a switching device is reduced and a breakdown voltage withstand capability is improved. Means to solve the problems

[0011] The object underlying the invention is achieved in a power semiconductor device according to the invention with the features of claim 1 and alternatively with the features of claim 3. Advantageous further developments are the subject of the respective dependent claims.

[0012] A power semiconductor device according to the present invention comprises: a silicon carbide semiconductor layer of a first conductivity type; a switching device formed on the silicon carbide semiconductor layer; an impurity region of a second conductivity type for relaxing an electric field, which is formed in a terminal region of a switching device formation region and relaxes an electric field of the terminal region; and an added region of the first conductivity type, which is provided between well regions of the second conductivity type of a plurality of unit cells constituting the switching element and at least on an outer side of the impurity region for relaxing an electric field, and which has an impurity concentration higher than that in the silicon carbide semiconductor layer.

[0013] According to the invention, the added region is formed to be deeper than each of the well regions, and the added region is formed to be shallower than the impurity region for relaxing an electric field.

[0014] Alternatively, according to the invention, the added region comprises a first added region formed to be deeper than each of the well regions and a second added region formed to be shallower than each of the well regions, wherein the first added region has an impurity concentration of the first conductivity type higher than an impurity concentration of the first conductivity type in the second added region, and wherein the first added region is formed to be shallower than the impurity region for relaxing an electric field. Effects of the invention

[0015] According to the power semiconductor device according to the present invention, the resistance of a JFET region between the well regions is reduced, thus reducing the ON resistance of the switching device. Expansion of a depletion layer in the terminal region is suppressed, and thus a reduction in breakdown voltage withstand capacity can be prevented. Furthermore, since the depletion layer is less likely to expand, the size of the area to which an electric field is applied is reduced.Therefore, even in a case where there is a defect on a surface of the terminal portion or adhesion of foreign matter to the surface of the terminal portion, the possibility that the above defect or adhesion occurs at a portion to which an electric field is applied is reduced, the manufacturing yield rate of switching devices is improved, and reliability of the switching devices is improved. Short description of the drawings Fig. 1 is a plan view illustrating a top view arrangement of a field effect transistor having a general MOS structure. Fig. Figure 2 is a partial cross-sectional view of the field effect transistor having the general MOS structure. Fig. 3 is a partial cross-sectional view of a silicon carbide MOS transistor according to a first embodiment for explaining the technical background of the present invention. Fig. 4 is a schematic view for explaining an extension of a depletion layer in a terminal region of the field effect transistor having the general MOS structure. Fig. 5 is a schematic view for explaining an extension of a depletion layer in a terminal region of the silicon carbide MOS transistor according to the first embodiment for explaining the technical background of the present invention. Fig. 6 is a diagram illustrating an impurity profile of the silicon carbide MOS transistor according to the first embodiment for explaining the technical background of the present invention. Fig. 7 is a diagram illustrating an impurity profile of the silicon carbide MOS transistor according to the first embodiment for explaining the technical background of the present invention. Fig. 8 is a cross-sectional view for explaining a manufacturing process of the silicon carbide MOS transistor according to the first embodiment for explaining the technical background of the present invention. Fig. 9 is a cross-sectional view for explaining a manufacturing process of the silicon carbide MOS transistor according to the first embodiment for explaining the technical background of the present invention. Fig. 10 is a cross-sectional view for explaining a manufacturing process of the silicon carbide MOS transistor according to the first embodiment for explaining the technical background of the present invention. Fig. 11 is a cross-sectional view for explaining a manufacturing process of the silicon carbide MOS transistor according to the first embodiment for explaining the technical background of the present invention. Fig. 12 is a cross-sectional view for explaining a manufacturing process of the silicon carbide MOS transistor according to the first embodiment for explaining the technical background of the present invention. Fig. 13 is a cross-sectional view for explaining a manufacturing process of the silicon carbide MOS transistor according to the first embodiment for explaining the technical background of the present invention. Fig. 14 is a partial cross-sectional view of a silicon carbide MOS transistor according to a second embodiment for explaining the technical background of the present invention. Fig. 15 is a diagram illustrating an impurity profile of the silicon carbide MOS transistor according to the second embodiment for explaining the technical background of the present invention. Fig. 16 is a diagram illustrating an impurity profile of the silicon carbide MOS transistor according to the second embodiment for explaining the technical background of the present invention. Fig. 17 is a partial cross-sectional view of a silicon carbide MOS transistor according to a third embodiment for explaining the technical background of the present invention. Fig. 18 is a diagram illustrating an impurity profile of the silicon carbide MOS transistor according to the third embodiment for explaining the technical background of the present invention. Fig. 19 is a diagram illustrating an impurity profile of the silicon carbide MOS transistor according to the third embodiment for explaining the technical background of the present invention. Fig. 20 is a partial cross-sectional view of a silicon carbide MOS transistor according to a fourth embodiment of the present invention. Fig. 21 is a diagram illustrating an impurity profile of the silicon carbide MOS transistor according to the fourth embodiment of the present invention. Fig. 22 is a diagram illustrating an impurity profile of the silicon carbide MOS transistor according to the fourth embodiment of the present invention. Fig. 23 is a partial cross-sectional view of a silicon carbide MOS transistor according to a fifth embodiment of the present invention. Fig. 24 is a diagram illustrating an impurity profile of the silicon carbide MOS transistor according to the fifth embodiment of the present invention. Fig. 25 is a diagram illustrating an impurity profile of the silicon carbide MOS transistor according to the fifth embodiment of the present invention. Description of the embodiments<Einführung>

[0016] The term "MOS" was previously used to refer to a metal / oxide / semiconductor junction structure and is an abbreviation for metal-oxide-semiconductor. However, especially in a field-effect transistor with a MOS structure (hereinafter referred to simply as a "MOS structure"), materials for a gate insulation layer and a gate electrode have been improved in recent years from the perspectives of integration, improvement in a manufacturing process, and the like.

[0017] For example, in MOS transistors, it is more likely that polycrystalline silicon is used as a gate electrode material than a metal, primarily from the perspective of forming a source and drain in a self-aligned manner. Furthermore, from the perspective of improving electrical characteristics, a high-dielectric material is used as a gate insulating layer material; however, this material is not necessarily limited to an oxide.

[0018] Therefore, the term "MOS" is not necessarily used to limit the term to a metal / oxide / semiconductor lamination structure. Furthermore, such a limitation is not required in the present description. That is, given a general technical understanding, "MOS" here not only has a meaning as an abbreviation derived from its word origin, but also has a meaning that includes a conductor / insulator / semiconductor lamination structure in a broad sense. <Erste Ausführungsform zur Erläuterung des technischen Hintergrunds der vorliegenden Erfindung> <vorrichtungsanordnung>

[0019] Fig. 1 is a plan view illustrating a top view arrangement of a field effect transistor (silicon carbide MOS transistor) 90 having a general MOS structure formed on a silicon carbide (SiC) substrate.

[0020] As in Fig. 1, the silicon carbide MOS transistor 90 is provided with a source pad SE located at a central portion of a main surface of a chip having a rectangular outer shape. The shape of the source pad SE in a plan view is a shape in which a central portion of one side of the rectangle is recessed inward, and a gate pad GE is provided to enter the inwardly recessed portion of the source pad SE. Note that in an area "X" in Fig. 1 For the sake of simplicity, a portion of the source contact point SE is omitted to represent unit cells UC provided below the source contact point SE.

[0021] The gate pad GE is a portion to which a gate voltage is applied from an external control circuit (not shown), and the gate voltage applied here is supplied through a gate wiring (not shown) to a gate electrode (not shown) of the unit cell UC, which is a smallest unit structure of the MOS transistor.

[0022] The source pad SE is provided on an active region AR where the plurality of unit cells UC are arranged, and has an arrangement such that source electrodes (not shown) of the respective unit cells UC are connected in parallel.

[0023] The outer side of the active region AR where the unit cells are formed is a terminal region TP, and the terminal region TP is provided with a JTE (junction termination extension) region (not shown) or the like as a structure for relaxing an electric field. Furthermore, a channel stop region 17 is provided on an outer side of the terminal region TP. Note that although the channel stop region 17 cannot be seen from a top side because it is formed in a substrate surface, for the sake of simplicity, the channel stop region 17 is illustrated as if it could be seen.

[0024] It should be noted that, with respect to the position and number of gate pads GE and the shape and number of source pads SE and the like, there may be various types and different cases depending on the MOS transistor; however, since these remotely depend on the arrangements and effects of the present invention, explanation and illustration thereof will be omitted.

[0025] Fig. Figure 2 shows the layout of the cross section of a cell area defined by a line AA in Fig. 1 and the arrangement of the cross-section of the connection area, which is indicated by a line BB.

[0026] As in Fig. 2, the silicon carbide MOS transistor 90 includes an n-type drift layer 2 formed on a main surface of a silicon carbide substrate 1 having an n-type impurity, and a drain electrode 14 formed on a back surface side (side opposite to the main surface side where the source pad SE is provided) of the silicon carbide substrate 1.

[0027] In addition, in an upper layer region of the drift layer 2, a plurality of selectively formed p-type well regions 3, a p-type JTE region 16 defining an outer edge of the active region AR, and the channel stop region 17 provided separately from the JTE region 16 are provided.

[0028] An n-type source region 4 and a p-type contact region 5 connected to an inner end surface of the source region 4 are provided in a surface of the well region 3. Note that a contact region 5 is also provided in the terminal region TP; however, in the terminal region TP, the contact region 5 is provided so as to be connected to an end surface of the source region 4 on the side facing the JTE region 16.

[0029] On a main surface of the drift layer 2, a gate insulating layer 8 is formed to cover the portion between the adjacent well regions 3 and edge regions of the well regions 3 and edge regions of the source regions 4, and a gate electrode 9 is formed on the gate insulating layer 8.

[0030] The gate insulating layer 8 and the gate electrode 9 are covered with an interlayer insulating layer 10, and the interlayer insulating layer 10 is provided to also cover the drift layer 2 in the terminal region TP.

[0031] An ohmic electrode 11 made of nickel (Ni), for example, is formed on upper portions of the source region 4 and the contact region 5 that are not covered with the interlayer insulation layer 10. A source electrode 12 is formed on the ohmic electrodes 11 and the interlayer insulation layer 10. This source electrode 12 forms the source contact pad SE.

[0032] In contrast to the general silicon carbide MOS transistor 90 explained above, a cross-sectional arrangement of a silicon carbide MOS transistor 100 according to a first embodiment for explaining the technical background of the present invention is shown in Fig. 3. It should be noted that in Fig. For simplicity, FIG. 3 shows a state in which an ohmic electrode 11 is just formed, and the arrangement of the layer higher than the ohmic electrode 11 is omitted. Furthermore, a drain electrode 14 is also omitted. The same applies to the subsequent cross-sectional views.

[0033] Fig. Figure 3 shows the arrangement of the cross section of a cell area indicated by a line AA of the Fig. 1 and the arrangement of the cross section of a terminal portion indicated by a line BB. Note that the top view arrangement is identical between the silicon carbide MOS transistor 90 and the silicon carbide MOS transistor 100.

[0034] The Fig. The silicon carbide MOS transistor 100 shown in Fig. 3 has n-type impurity regions (added regions) 7 having a relatively high concentration provided on an upper layer region of a drift layer 2 between adjacent well regions 3 and an upper layer region of the drift layer 2 in the entire area of ​​a terminal region.

[0035] By forming the n-type impurity region having a relatively high concentration between adjacent well regions 3, that is, in a so-called JFET region, the resistance value of a current path formed within the drift layer 2 from a channel region toward a silicon carbide substrate 1 in a case of an ON state can be reduced, and the ON resistance of the silicon carbide MOS transistor 100 can be reduced.

[0036] Furthermore, by forming the added region 7 also on the upper layer portion of the drift layer 2 on an outer side of the JTE region 16 in the terminal region, a decrease in breakdown voltage withstand capacity can be suppressed. That is, theoretically, the ON resistance of a silicon carbide MOS transistor can be designed to be about one two-hundredth of that of a silicon MOS transistor; however, the ON resistance is not as low. This is because the channel mobility of the silicon carbide MOS transistor is extremely small. The reason for this is that the transition state density of SiO2 / SiC is approximately one digit higher than the transition state density of SiO2 / Si. It is considered that the channel mobility decreases due to Coulomb scattering caused by electrons trapped in this transition state.

[0037] As described, the junction state density at the SiO2 / SiC junction is high, and electrons are likely to be trapped. In the terminal region, since there is a region where an interlayer insulation layer 10 and the drift layer 2 are in contact with each other, and electrons are trapped in the region, a depletion layer is likely to be expanded. This state is schematically shown in Fig. 4 shown.

[0038] As in Fig. 4, a depletion layer VC extending from an edge portion of the JTE region 16 reaches a channel stop region 17. Note that in a case where the channel stop region 17 is not provided, the depletion layer VC reaches a chip end. Since the chip end is not provided with a protective layer because dicing is performed at the chip end, and damage caused by the dicing remains at the chip end, application of an electric field to the chip end causes an increase in the amount of electric discharge and leakage current. The channel stop region 17 prevents this, and providing the channel stop region 17 prevents the depletion layer from reaching the chip end. Note that electrons EL trapped at the junction between the interlayer insulating layer 10 and the drift layer 2 in Fig. 4 represent electrons trapped in the SiO2 / SiC junction.

[0039] In contrast, by forming the added region 7 on the upper layer region of the drift layer 2 on the outer side of the JTE region 16, expansion of the depletion layer VC can be suppressed. This state is schematically shown in Fig. 5 shown.

[0040] As in Fig. As shown in Figure 5, the depletion layer VC extending from the edge portion of the JTE region 16 does not reach the channel stop region 17, so expansion of the depletion layer VC is suppressed, a decrease in the breakdown voltage withstand capacity can be suppressed, and further, leakage current can be suppressed. It is generally understood that expanding a depletion layer can relax an electric field concentration and increase a breakdown voltage of a semiconductor device.This is because breakdown is likely to occur at a portion where the depletion layer is narrow, or at a portion where the curvature of a boundary line of a terminal portion of the depletion layer is large and electrical concentration is likely to occur. Breakdown is suppressed by expanding the depletion layer and designing the curvature of the boundary line of the terminal portion of the depletion layer to be small. However, if the depletion layer is designed too wide so that it reaches the chip end, it becomes a cause of an increase in the amount of electrical discharge and leakage current, as described above.

[0041] In addition, the channel stop region is formed by implanting an impurity at a high concentration through ion implantation, resulting in numerous crystal defects. When the depletion layer reaches such a channel stop region, an electric field is applied to the region where there are many crystal defects, causing an increase in leakage current.

[0042] Furthermore, since the depletion layer VC is less likely to expand, the area to which an electric field is applied becomes small. Therefore, even if there is a defect on a surface of the terminal region or adhesion of foreign matter to the surface of the terminal region, the possibility of the protruding defect or adhesion occurring at a portion to which an electric field is applied is reduced, the manufacturing yield of a SiC MOSFET is improved, and reliability is also improved. <verunreinigungsprofil>

[0043] Next, using Fig. 6 and Fig. 7 Impurity profiles of added region 7 and JTE region 16 explained. Fig. 6 is a diagram describing the impurity profile of the added region 7 as a box-like impurity profile and showing a relationship to the impurity profile of the JTE region 16.

[0044] The Fig. The impurity profile of the JTE region 16 shown in Figure 6 is a profile in a case where Al (aluminum) is implanted at an implantation energy of 500 keV and a doping amount of 1.39 × 10 13 / cm 2 implanted by ion implantation.

[0045] As in Fig. 6, the maximum concentration of the added area is 7 5 × 10 10 / cm 3 , wherein the maximum concentration is set so that it is not greater than one-tenth of the maximum concentration in the JTE region 16 which has a maximum value before the depth of 600 nm, wherein the maximum concentration is 7.5 × 10 17 / cm 3 By using such an arrangement, a desired breakdown voltage can be achieved without dry etching a substrate surface after implantation.

[0046] It is considered that this is because, since the amount of impurities introduced into a surface portion is small, damage on the surface portion (crystal defects formed by ion implantation) is small.

[0047] In addition, in forming the JTE region 16, since an implantation energy of the ion implantation is set high and the position of the highest impurity concentration is at a depth as deep as 600 nm, the tolerance of an etching performed for removing a damaged layer on the surface of the JTE region 16, that is, the etching amount enabling a desired breakdown voltage value to be obtained, can be made wide.

[0048] Fig. 7 shows an impurity profile in a case where the added region 7 is formed by ion implantation, and here, an example of a case where the added region 7 is formed by ion implantation in three stages is shown.

[0049] As in Fig. As shown in Figure 7, the added region 7 is formed by ion implantation in three stages, that is, an ion implantation in a first stage in which N (nitrogen) is implanted at an implantation energy of 350 keV and a doping amount of 3.00 × 10 11 / cm 2 by ion implantation, an ion implantation in a second stage in which N is implanted at an implantation energy of 180 keV and a doping amount of 2.40 × 10 11 / cm 2 by ion implantation, and an ion implantation in a third stage, in which N is implanted at an implantation energy of 75 keV and a doping amount of 2.00 × 10 11 / cm 2 implanted by ion implantation.

[0050] By performing ion implantation in three stages, the added region 7 has an impurity profile close to a box-like impurity profile. Note that increasing the number of implantations results in an impurity profile that approaches the box-like impurity profile. Furthermore, in a case where the added region 7 is formed not by ion implantation but by epitaxial growth, the impurity profile further approaches the box-like impurity profile.

[0051] Note that in a case where the added region 7 is formed by epitaxial growth, no implantation defect occurs, and the added region 7 becomes an impurity region with excellent crystal quality. However, it is difficult to make a thickness uniform, and a thickness distribution occurs, and there is a variation in an impurity concentration. In contrast, in a case where the added region 7 is formed by ion implantation, although there is a possibility of an implantation defect occurring, a thickness distribution and a variation in an impurity concentration do not occur.

[0052] In addition, in the above, the arrangement in which the JTE region 16 is provided in the terminal region is illustrated; however, the terminal structure is not limited to this, and the effects are also apparent in a case where one of an arrangement in which an FLR (Field Limiting Ring) region is provided, an arrangement in which the JTE region and the FLR region are combined, or the like is used, as long as the arrangement is provided with an impurity region for relaxing an electric field that relaxes an electric field at the terminal region. <fertigungsverfahren>

[0053] Next, a manufacturing method of the silicon carbide MOS transistor 100 using Fig. 8 to 13 explained.

[0054] First, a silicon carbide substrate having an n-type impurity and a resistivity of 0.015 to 0.028 Ω cm is prepared as the silicon carbide substrate 1. Silicon carbide is a wide bandgap semiconductor having a larger bandgap than that of silicon, and since a switching device and a diode configured to have a wide bandgap semiconductor as a substrate material have a high breakdown voltage characteristic and a high allowable current density, the switching device and the diode can be made smaller than a silicon semiconductor device, and by using this small switching device and diode, it is possible to reduce the size of a semiconductor device module including these devices.

[0055] In addition, since the switching device and the diode have a high thermal resistance property, a size reduction of a radiation fin of a heat sink and cooling by air cooling instead of water cooling are enabled, and a further size reduction of the semiconductor device module is enabled.

[0056] Then, an n-type silicon carbide epitaxial layer is formed on an upper portion of the silicon carbide substrate 1 by epitaxial crystal growth to form the drift layer 2. Here, the impurity concentration in the drift layer 2 falls, for example, in the range of 1 × 10 15 up to 5 × 10 16 cm -3 , and the thickness is 5 to 50 µm.

[0057] Next, in a Fig. 8, an ion implantation of an n-type impurity such as nitride (N) or phosphorus (P) is performed from the upper portion of the drift layer 2, and the added region 7 extending over the entire surface of the upper layer portion of the drift layer 2 is formed. Here, the added region 7 is formed such that the depth is 0.3 to 1.2 µm, and the impurity concentration is in the range of 5 × 10 15 up to 5 × 10 17 cm -3 falls and the concentration is higher than that in drift layer 2.

[0058] Next, a resist material is applied on the drift layer 2 after the added region 7 has been formed, designing is carried out by photolithography, and as shown in Fig. As shown in Figure 9, a resist mask RM1 is formed in which a portion corresponding to the JTE region 16 is an opening. Next, using the resist mask RM1, ion implantation of a p-type impurity such as aluminum (A), boron (B), or the like is performed, and the JTE region 16 is formed. Here, the depth of the JTE region 16 is 0.5 to 1.0 µm, and the impurity concentration falls within the range of 5 × 10 16 up to 1 × 10 18 cm -3 .

[0059] Next, after the resist mask RM1 has been removed, a resist material is applied on the drift layer 2, designing is carried out by photolithography and, as shown in Fig. 10, a resist mask RM2 is formed, in which portions corresponding to the well regions 3 are opening portions. Next, using the resist mask RM2, ion implantation of a p-type impurity such as Al, B, or the like is performed, and the well regions 3 are formed. Here, the depth of the well regions 3 is 0.5 to 1.0 µm, and the impurity concentration falls within the range of 1 × 10 18 up to 5 × 10 18 cm -3 .

[0060] Next, after the resist mask RM2 has been removed, a resist material is applied on the drift layer 2, designing is carried out by photolithography and, as shown in Fig. 11, a resist mask RM3 is formed in which portions corresponding to the source regions 4 and the channel stop region 17 are opening portions. Next, using the resist mask RM3, ion implantation of an n-type impurity such as N, P, or the like is performed, and the source regions 4 and the channel stop region 17 are formed. Here, the depth of each of the source regions 4 and the channel stop region 17 is 0.2 to 0.5 μm, and the impurity concentration falls within the range of 1 × 10 19 up to 5 × 10 20 cm -3 Note that the channel stop region 17 is not an essential structure for the present invention, and the channel stop region 17 need not be provided. Furthermore, the source region 4 and the channel stop region 17 are formed separately.

[0061] Next, after the resist mask RM3 has been removed, a resist material is applied on the drift layer 2, designing is carried out by photolithography and, as shown in Fig. 12, a resist mask RM4 is formed, in which portions corresponding to the contact regions 5 are opening portions. Next, using the resist mask RM4, ion implantation of a p-type impurity such as Al, B, or the like is performed, and the contact regions 5 are formed. Here, the depth of the contact region 5 is 0.2 to 0.5 µm, and the impurity concentration falls within the range of 1 × 10 20 up to 5 × 10 20 cm -3 Note that in the above explanation, an example was presented in which a resist is used as a mask each time ion implantation is performed. However, ion implantation can be performed by using a hard mask made of SiO2 or the like and heating the substrate to a high temperature. In this case, there is an advantage in reducing crystal defects generated by implantation.

[0062] Thereafter, after the resist mask RM4 has been removed, the gate insulating layer 8 and the gate electrode 9 are formed on a main surface of the drift layer 2 in the manner shown in Fig. 13, the gate insulating film 8 and the gate electrode 9 are covered with the interlayer insulating film 10, and further, the drift layer 2 in the terminal region is also covered with the interlayer insulating film 10.

[0063] Then, a contact hole is provided so that it passes through the interlayer insulation layer 10 and reaches the source region 4 and the contact region 5, and the ohmic electrode 11, made of Ni, for example, is formed on the lower surface of the contact hole. Thus, the device can be Fig. 3 can be obtained.

[0064] Then the source electrode 12 ( Fig. 2) is formed on the ohmic electrode 11 and the interlayer insulation layer 10. In addition, the drain electrode 14 ( Fig. 2) on the back surface side (side opposite to the main surface where a source pad electrode is provided) of the silicon carbide substrate 1, and thus the silicon carbide MOS transistor 100 is obtained.

[0065] As explained above, since the added region 7 is provided to extend over the entire surface of the upper layer portion of the drift layer 2, it is not necessary to perform selective ion implantation when forming the added region 7, and manufacturing processes can be simplified. Furthermore, by forming the added region 7 by ion implantation, compared with a case of forming by epitaxial growth, the uniformity of the impurity concentration in the substrate surface and the film thickness become more excellent, and not only the ON-resistance of the SiC MOSFET but also the breakdown voltage of the terminal structure are more stabilized, and the effect of improving the manufacturing yield rate of SiC MOSFETs is achieved.

[0066] Note that first, an example of forming the added region 7 has been described above; however, in a case of using ion implantation, a formation order of the added region 7 is not limited. <Zweite Ausführungsform zur Erläuterung des technischen Hintergrunds> <vorrichtungsanordnung>

[0067] Fig. Fig. 14 is a cross-sectional view illustrating cross-sectional arrangements of a cell region and a terminal region of a silicon carbide MOS transistor 200 according to a second embodiment for explaining the technical background of the present invention. Note that identical reference numerals are assigned to arrangements identical to those of the Fig. 3 are identical, and overlapping explanations are omitted.

[0068] The Fig. The silicon carbide MOS transistor 200 shown in Fig. 14 has an added region 7A formed to be deeper than a well region 3.

[0069] By forming the added region 7A to be deeper than the well region 3, a resistance of a JFET region can be further reduced, and in addition, since a current is injected into a drift layer 2 via the added region 7A below the bottom surface of the well region 3, a current flow is widened, and an ON-resistance of the SiC MOSFET can be further reduced.

[0070] Further, since the added region 7A is also formed on the upper layer portion of the drift layer 2 in the entire area of ​​the terminal portion, a decrease in a breakdown voltage withstand capability can be suppressed. <verunreinigungsprofil>

[0071] Next, using Fig. 15 and Fig. 16 Contamination profiles of the added area 7A and the well area 3 explained. Fig. 15 is a diagram describing the impurity profile of the added region 7A as a box-like impurity profile and showing a relationship to the impurity profile of the well region 3.

[0072] The Fig. The impurity profile of the well region 3 shown in Figure 15 represents a profile in a case where Al is implanted at an implantation energy of 500 keV with a doping amount of 5.20 × 10 13 / cm 2 by ion implantation, a profile in a case of ion implantation at an implantation energy of 450 keV and a doping amount of 3.00 × 10 13 / cm 2 and an overall profile of both.

[0073] As in Fig. 15, the maximum concentration of the added area 7A is 5 × 10 10 / cm 3 , wherein the maximum concentration is set so that it is not greater than one-tenth of the maximum concentration in the well region 3, which has a maximum value before the depth of 600 nm, wherein the maximum concentration is 5 × 10 18 / cm 3 is.

[0074] By providing the added region 7A and thus reducing the Al concentration in the surface of the well region 3, the channel mobility of the MOS transistor is improved, and thus the ON resistance is reduced. Furthermore, the threshold value of the MOS transistor can be adjusted by adjusting the Al concentration in the surface and the N concentration in the added region 7.

[0075] In addition, the added region 7A is formed to be deeper than the well region 3, wherein the depth to the deepest portion of the well region 3 is about 800 nm, while the depth to the deepest portion of the added region 7A is about 900 nm.

[0076] Fig. Fig. 16 shows an impurity profile in a case where the added region 7A is formed by ion implantation, and here, an example of a case where the added region 7A is formed by ion implantation in four stages is shown. Note that the impurity profile shown in Fig. 15 is shown as the contamination profile of the tub area 3.

[0077] As in Fig. As shown in Fig. 16, the added region 7A is formed by ion implantation in four stages, that is, an ion implantation in a first stage in which N is implanted at an implantation energy of 665 keV and a doping amount of 5.00 × 10 11 / cm 2 by ion implantation, an ion implantation in a second stage in which N is implanted at an implantation energy of 350 keV and a doping amount of 3.00 × 10 11 / cm 2 by ion implantation, an ion implantation in a third stage, in which N at an implantation energy of 180 keV and a doping amount of 2.40 × 10 11 / cm 2 by ion implantation, and an ion implantation in a fourth stage, in which N is implanted at an implantation energy of 75 keV and a doping amount of 2.00 × 10 11 / cm 2 implanted by ion implantation.

[0078] By performing ion implantation in such four stages, the added region 7A has an impurity profile close to a box-like impurity profile. Note that increasing the number of implantations makes the impurity profile closer to the box-like impurity profile. Furthermore, in a case where the added region 7A is formed not by ion implantation but by epitaxial growth, the impurity profile further approaches the box-like impurity profile. <Dritte Ausführungsform zur Erläuterung des technischen Hintergrunds> <vorrichtungsanordnung>

[0079] Fig. Fig. 17 is a cross-sectional view illustrating cross-sectional arrangements of a cell region and a terminal region of a silicon carbide MOS transistor 300 according to a third embodiment for explaining the technical background of the present invention. Note that identical reference numerals are assigned to arrangements identical to those of the Fig. 3 are identical, and overlapping explanations are omitted.

[0080] The Fig. The silicon carbide MOS transistor 300 shown in FIG. 17 includes an added region 7B (first added region) formed to be deeper than a well region 3, and an added region 7B (second added region) formed to be shallower than the well region 3. Then, the added region 7B is formed such that the n-type impurity concentration is higher than that in the added region 7.

[0081] By forming the added region 7B having a high impurity concentration to be deeper than the well region 3, a resistance of a JFET region can be further reduced, and in addition, since a current is injected into a drift layer 2 via the added region 7B below the bottom surface of the well region 3, a current flow is widened, and an ON-resistance of the SiC MOSFET can be further reduced.

[0082] Further, since the added region 7 and the added region 7B are also formed on an upper layer portion of the drift layer 2 in the entire area of ​​the terminal portion, a decrease in a breakdown voltage withstand capability can be suppressed. <verunreinigungsprofil>

[0083] Next, using Fig. 18 and Fig. 19 Impurity profiles of added region 7, added region 7B, well region 3 and JTE region 16 explained. Fig. 18 is a diagram describing the impurity profiles of the added regions 7 and 7B as box-like impurity profiles and showing a relationship to the impurity profile of the well region 3.

[0084] The Fig. The impurity profile of the well region 3 shown in Figure 18 represents a profile in a case where Al is implanted at an implantation energy of 500 keV and a doping amount of 5.20 × 10 13 / cm 2 by ion implantation, a profile in a case in which ion implantation at an implantation energy of 450 keV and a doping amount of 3.00 × 10 13 / cm 2 and an overall profile of both.

[0085] As in Fig. 18, the maximum concentration of the added area is 7 5 × 10 10 / cm 3 , the maximum concentration being set so that it is not higher than one-tenth of the maximum concentration of the well region 3, which has a maximum value before the depth of 600 nm, the maximum concentration being 5 × 10 18 / cm 3 is.

[0086] By providing the added region 7 and thus reducing the Al concentration in the surface of the well region 3, the channel mobility of the MOS transistor is improved, and thus the ON resistance is reduced. Furthermore, the threshold value of the MOS transistor can be adjusted by adjusting the Al concentration in the surface and the N concentration in the added region 7.

[0087] In addition, the added region 7B is formed at a depth of more than 600 nm, which is deeper than the position of the concentration peak of the well region 3. Thus, formation of a pn junction by an n-type impurity region and a p-type impurity region, both of which have high concentrations, is prevented, and a region with a high electric field strength can be eliminated.

[0088] Fig. 19 is a diagram describing the impurity profiles of the added regions 7 and 7B as box-like impurity profiles and showing a relationship to the impurity profile of the JTE region 16.

[0089] The Fig. The impurity profile of the JTE region 16 shown in Figure 19 is a profile in a case where Al is implanted at an implantation energy of 500 keV and a doping amount of 1.39 × 10 13 / cm 2 implanted by ion implantation.

[0090] As in Fig. 19, the maximum concentration of the added area is 7 5 × 10 10 / cm 3 , wherein the maximum concentration is set so as not to be higher than one-tenth of the maximum concentration in the JTE region 16 having a maximum value before the depth of 600 nm, wherein the maximum concentration is 7.5 × 10 17 / cm 3 is.

[0091] In addition, in forming the JTE region 16, since an implantation energy is set high and the position of the peak value of the impurity concentration is at a depth as deep as about 600 nm, the tolerance of etching performed for removing a damaged layer on the surface of the JTE region 16, that is, the range of the etching scope which enables obtaining a desired breakdown voltage, can be made wide.

[0092] In addition, the added region 7B is formed at a depth of more than 600 nm, which is deeper than the concentration peak position of the JTE region 16. Thus, formation of a pn junction by an n-type impurity region and a p-type impurity region, both of which have high concentrations, is prevented, and a region with a high electric field strength can be eliminated. <Vierte und erfindungsgemäße Ausführungsform> <vorrichtungsanordnung>

[0093] Fig. Fig. 20 is a cross-sectional view illustrating cross-sectional arrangements of a cell region and a terminal region of a silicon carbide MOS transistor 400 according to a fourth embodiment of the present invention. Note that identical reference numerals are assigned to arrangements identical to those of the Fig. 3 are identical, and overlapping explanations are omitted.

[0094] The Fig. The silicon carbide MOS transistor 400 shown in Fig. 20 has an added region 7A formed to be deeper than a well region 3.

[0095] By forming the added region 7A to be deeper than the well region 3, a resistance of a JFET region can be further reduced, and in addition, since a current is injected into a drift layer 2 via the added region 7A below the bottom surface of the well region 3, a current flow can be widened, and an ON-resistance of the SiC MOSFET can be further reduced.

[0096] Further, since the added region 7A is also formed on an upper layer portion of the drift layer 2 in the entire area of ​​the terminal portion, a decrease in a breakdown voltage withstand capability can be suppressed.

[0097] Furthermore, in the silicon carbide MOS transistor 400, since the added region 7A is formed to be shallower than a JTE region 16 and deeper than the well region 3, the JTE region 16 forms a pn junction with the drift layer 2 with a low concentration, the electric field strength of the terminal region can be reduced, a breakdown voltage is stabilized, and a reliability of the SiC MOSFET can be improved. <verunreinigungsprofil>

[0098] Next, using Fig. 21 and Fig. 22 Impurity profiles of the added region 7A, the well region 3 and the JTE region 16 are explained.

[0099] Fig. 21 is a diagram describing the impurity profile of the added region 7A as a box-like impurity profile and showing a relationship to the impurity profile of the well region 3.

[0100] The Fig. The impurity profile of the well region 3 shown in Figure 21 represents a profile in a case where Al is implanted at an implantation energy of 335 keV and a doping amount of 8.20 × 10 13 / cm 2 implanted by ion implantation.

[0101] As in Fig. 21, the maximum concentration of the added area 7A is 5 × 10 10 / cm 3 , wherein the maximum concentration is set so as not to be higher than one tenth of the maximum concentration in the well region 3, which has a maximum value at the depth of about 400 nm, wherein the maximum concentration is 5 × 10 10 / cm 3 is.

[0102] By providing the added region 7A and thus reducing the Al concentration in the surface of the well region 3, the channel mobility of the MOS transistor is improved, and thus the ON resistance is reduced. Furthermore, the threshold value of the MOS transistor can be adjusted by adjusting the Al concentration in the surface and the N concentration in the added region 7A.

[0103] Fig. 22 is a diagram describing the impurity profile of the added region 7A as a box-like impurity profile and showing a relationship to the impurity profile of the JTE region 16.

[0104] The Fig. The impurity profile of the JTE region 16 shown in Figure 22 is a profile in a case where Al is implanted at an implantation energy of 500 keV and a doping amount of 1.39 × 10 13 / cm 2 implanted by ion implantation.

[0105] As in Fig. 22, the maximum concentration of the added area 7A is 5 × 10 10 / cm 3 , the maximum concentration being set so as not to be higher than one-tenth of the maximum concentration of the JTE region 16, which has a maximum value before the depth of 600 nm, the maximum concentration being 7.5 × 10 17 / cm 3 is.

[0106] In addition, since the added region 7A is formed to be not larger than one-tenth of the maximum concentration in the JTE region 16, a desired breakdown voltage can be obtained without dry etching a substrate surface after implantation.

[0107] In addition, in the formation of the JTE region 16, since the implantation energy of ion implantation is set high and the position of the peak value of the impurity concentration is at a depth as deep as about 600 nm, the tolerance of etching performed for removing a damaged layer on the surface of the JTE region 16, that is, the range of the etching scope which enables to obtain a desired breakdown voltage value, can be made wide. <Fünfte und erfindungsgemäße Ausführungsform> <vorrichtungsanordnung>

[0108] Fig. Fig. 23 is a cross-sectional view illustrating cross-sectional arrangements of a cell region and a terminal region of a silicon carbide MOS transistor 500 according to a fifth embodiment of the present invention. Note that identical reference numerals are assigned to arrangements identical to those of the Fig. 3 are identical, and overlapping explanations are omitted.

[0109] The Fig. The silicon carbide MOS transistor 500 shown in FIG. 23 includes an added region 7B formed to be deeper than a well region 3 and an added region 7 formed to be shallower than the well region 3. Furthermore, the added region 7B is formed such that an n-type impurity concentration is higher than that in the added region 7.

[0110] By forming the added region 7B having a high impurity concentration to be deeper than the well region 3, a resistance of a JFET region can be further reduced, and furthermore, since a current is injected into a drift layer 2 via the added region 7B under the bottom surface of the well region 3, a current flow is widened, and an ON-resistance of the SiC MOSFET can be further reduced.

[0111] Further, since the added regions 7 and 7B are also formed on an upper layer portion of the drift layer 2 in the entire area of ​​the terminal portion, a decrease in a breakdown voltage withstand capability can be suppressed.

[0112] Furthermore, in the silicon carbide MOS transistor 500, since the added region 7B is formed to be shallower than a JTE region 16 and deeper than the well region 3, the JTE region 16 forms a pn junction with the drift layer 2 with a low concentration, the electric field strength of the terminal region can be reduced, a breakdown voltage is stabilized, and reliability can be improved. <verunreinigungsprofil>

[0113] Next, using Fig. 24 and Fig. 25 Impurity profiles of added region 7, added region 7B, well region 3 and JTE region 16 are explained. Fig. 24 is a diagram describing the impurity profiles of the added regions 7 and 7B as box-like impurity profiles and showing a relationship to the impurity profile of the well region 3.

[0114] The Fig. The impurity profile of the well region 3 shown in Figure 24 represents a profile in a case where Al is implanted at an implantation energy of 335 keV and a doping amount of 8.20 × 10 13 / cm 2 implanted by ion implantation.

[0115] As in Fig. 24, the maximum concentration of the added area is 7 5 × 10 10 / cm 3 , wherein the maximum concentration is set so that it is not higher than one tenth of the maximum concentration in the well region 3, which has a maximum value at the depth of about 400 nm, wherein the maximum concentration is 5 × 10 10 / cm 3 is.

[0116] By providing the added region 7 and thus reducing the Al concentration in the surface of the well region 3, the channel mobility of the MOS transistor is improved, and thus the ON resistance is reduced. Furthermore, the threshold value of the MOS transistor can be adjusted by adjusting the Al concentration in the surface and the N concentration in the added region 7.

[0117] In addition, the added region 7B is formed at a depth of more than 400 nm, which is deeper than the position of the concentration peak of the well region 3. Thus, formation of a pn junction by an n-type impurity region and a p-type impurity region, both of which have high concentrations, is prevented, and a region with a high electric field strength can be eliminated.

[0118] Fig. 25 is a diagram describing the impurity profiles of the added regions 7 and 7B as box-like impurity profiles and showing a relationship to the impurity profile of the JTE region 16.

[0119] The Fig. The impurity profile of the JTE region 16 shown in Figure 25 is a profile in a case where Al is implanted at an implantation energy of 500 keV and a doping amount of 1.39 × 10 13 / cm 2 implanted by ion implantation.

[0120] As in Fig. 25, the maximum concentration of the added area is 7 5 × 10 10 / cm 3 , the maximum concentration being set so as not to be higher than one-tenth of the maximum concentration of the JTE region 16, which has a maximum value before the depth of 600 nm, the maximum concentration being 7.5 × 10 17 / cm 3 is.

[0121] In addition, since the added region 7 is formed to be not larger than one-tenth of the maximum concentration in the JTE region 16, a desired breakdown voltage can be obtained without dry etching a substrate surface after implantation.

[0122] In addition, in the formation of the JTE region 16, since the implantation energy of ion implantation is set high and the position of the peak value of the impurity concentration is at a depth as deep as about 600 nm, the tolerance of etching performed for removing a damaged layer on the surface of the JTE region 16, that is, the range of the etching scope which enables to obtain a desired breakdown voltage, can be made wide.

[0123] Furthermore, in the above explanation, an n-channel type MOSFET is used as an example; however, the present invention can be applied to a p-channel type MOSFET. In a case of a p-channel type, an added region is a p-type, and by using boron (B), which has a low mass, as an impurity in this case, an implantation energy can be set low.

[0124] Furthermore, the application of the present invention is not limited to a MOSFET, and the present invention can be applied to a switching device such as an IGBT (Insulated Gate Bipolar Transistor).< / verunreinigungsprofil> < / vorrichtungsanordnung> < / verunreinigungsprofil> < / vorrichtungsanordnung> < / verunreinigungsprofil> < / vorrichtungsanordnung> < / verunreinigungsprofil> < / vorrichtungsanordnung> < / fertigungsverfahren> < / verunreinigungsprofil> < / vorrichtungsanordnung>

Claims

[1] Power semiconductor device, comprising: - a silicon carbide semiconductor layer (2) of a first conductivity type; - a switching device formed on the silicon carbide semiconductor layer (2) of the first conductivity type; - an impurity region (16) of a second conductivity type for relaxing an electric field, which is formed in a terminal region of a formation region of the switching device and which relaxes an electric field of the terminal region; and - an added region (7, 7A, 7B) of the first conductivity type, which is provided between well regions (3) of the second conductivity type of a plurality of unit cells constituting the switching device and at least on an outer side of the impurity region (16) for relaxing an electric field, and which has an impurity concentration higher than an impurity concentration in the silicon carbide semiconductor layer (2), wherein: - the added area (7, 7A, 7B) is designed to be deeper than each of the tub areas (3) and - wherein the added region (7, 7A, 7B) is formed to be flatter than the impurity region (16) for relaxing an electric field. [2] The power semiconductor device according to claim 1, wherein the added region (7, 7A, 7B) has an impurity concentration of the first conductivity type that is not higher than one-tenth of an impurity concentration of a second conductivity type in the impurity region (16) for relaxing an electric field. [3] Power semiconductor device, comprising: - a silicon carbide semiconductor layer (2) of a first conductivity type; - a switching device formed on the silicon carbide semiconductor layer (2) of the first conductivity type; - an impurity region (16) of a second conductivity type for relaxing an electric field, which is formed in a terminal region of a formation region of the switching device and which relaxes an electric field of the terminal region; and - an added region (7, 7A, 7B) of the first conductivity type, which is provided between well regions (3) of the second conductivity type of a plurality of unit cells constituting the switching device and at least on an outer side of the impurity region (16) for relaxing an electric field, and which has an impurity concentration higher than an impurity concentration in the silicon carbide semiconductor layer (2), wherein: - the added portion comprises a first added portion (7B) which is formed to be deeper than each of the tub portions (3) and a second added portion (7) which is formed to be shallower than each of the tub portions (3), - the first added region (7B) has an impurity concentration of the first conductivity type that is higher than an impurity concentration of the first conductivity type in the second added region (7), and - the first added region (7B) is formed to be flatter than the impurity region (16) for relaxing an electric field. [4] The power semiconductor device according to claim 3, wherein the second added region (7) has an impurity concentration of the first conductivity type that is not higher than one-tenth of an impurity concentration of the second conductivity type in the impurity region (16) for relaxing an electric field. [5] The power semiconductor device according to claim 1 or 3, wherein the added region (7, 7A, 7B) is formed on an entire region of an upper layer portion of the silicon carbide semiconductor layer (2). [6] The power semiconductor device according to claim 1 or 3, wherein the impurity region (16) for relaxing an electric field comprises at least one of a JTE (Junction Termination Extension) region and an FLR (Field Limiting Ring) region.

Images