SEMICONDUCTOR DEVICE

Abstract

Semiconductor device comprising the following: - a drift layer (20) of a first conductivity type formed on a semiconductor substrate (10) of a first conductivity type; - a plurality of first trough areas (30) of a second conductivity type, which are located at a distance in a surface layer of the drift layer (20); - a second trough area (31, 31b, 31f) of the second conductivity type, which is formed in plan view on both sides of the totality of the majority of first trough areas (30) in the surface layer of the drift layer (20), wherein the second trough area (31, 31b, 31f) has a formation area that is larger than that of the first trough areas (30); - a first separation zone (22) of the first conductivity type, which is designed to penetrate each of the first trough areas (30) starting from a surface layer of each of the first trough areas (30) in a depth direction; - a source area (40) of the first conductivity type, which is formed in the plan view on both sides of the first separation area (22) in the surface layer of each of the first trough areas (30); - a first Schottky electrode (75) located on the first separation region (22); - a first ohmic electrode (70) located above each of the first trough areas (30) and arranged on the source area (40), while in contact with each of the first trough areas (30) and the source area (40); - a second separation area (21) of the first conductivity type, which forms an area for separating the first tub areas (30) from each other; - a second ohmic electrode (70) located above the second basin area (31, 31b, 31f); - a third separation area (23, 23b, 23c) of the first conductivity type, which is designed to penetrate the second trough area (31, 31b, 31f) from a surface layer of the second trough area (31, 31b, 31f) in the depth direction, so that it surrounds the first trough areas (30) by extending in a direction which intersects a direction from the second trough area (31, 31b, 31f) to the first trough areas (30) in the top view; - a second Schottky electrode (75) located on the third separation region (23, 23b, 23c); - a gate electrode (60) which extends through a first insulating layer (50) over part of the first and second trough areas (30, 31, 31b, 31f), except for positions where the first and second Schottky electrodes (75) and the first and second ohmic electrodes (70) are located; - a second insulating layer (55) designed to cover the gate electrode (60); and - a source electrode (80) arranged to cover the first and second Schottky electrodes (75), the first and second ohmic electrodes (70) and the second insulating layer (55).

Description

Technical field

[0001] The present invention relates to a semiconductor device. State of the art

[0002] In semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), built-in diodes can be used as reverse-flow diodes. For example, patent document JP 2003-017701A proposes a method for using Schottky junction diodes (SBDs) as reverse-flow diodes built into unit cells of MOSFETs.

[0003] DE 103 93 777 T5 describes a semiconductor device that uses a silicon carbide semiconductor substrate with p-type and n-type impurity semiconductor regions formed by ion implantation. These regions can improve the electrical properties of the final semiconductor device by reducing the surface roughness of the silicon carbide semiconductor substrate. The semiconductor device is a Schottky barrier diode or a pn diode comprising at least one p-type semiconductor region and one n-type semiconductor region selectively embedded in a silicon carbide semiconductor region with an outermost surface layer that is a (000-1) surface or a surface inclined at an angle to the (000-1) surface, and a metal electrode formed on the outermost surface layer that controls the direction in which electric current flows perpendicular to the outermost surface layer when a voltage is applied to the metal electrode.

[0004] US 2011 / 0024802A1 describes a miniaturization of a semiconductor device comprising a power transistor and an SBD, and includes a semiconductor device having a first region and a second region formed on a principal area of ​​a semiconductor substrate; multiple first conductors and multiple second conductors formed in the first and second regions, respectively; a first semiconductor region and a second semiconductor region formed between adjacent first conductors in the first region, the second semiconductor region being located within the first semiconductor region and having a conductivity type opposite to that of the first semiconductor region;a third semiconductor region formed between adjacent second conductors in the second region, wherein the third semiconductor region has the same conductivity type as the second semiconductor region and a lower density than the second semiconductor region; a metal formed on the semiconductor substrate in the second region, wherein the third semiconductor region has a metal contact region for contacting the metal, the metal being electrically connected to the second semiconductor region, and wherein the center-to-center distance between adjacent first conductors in the first region is smaller than the distance between adjacent second conductors in the second region. Summary of the invention Problems to be solved with the invention

[0005] A pn diode is integrated into a semiconductor device, such as a MOSFET. When the pn diode operates while a forward voltage is applied to it, minority charge carriers are consequently implanted or introduced into a drift layer.

[0006] The minority charge carriers that have been implanted then recombine with majority charge carriers in the drift layer, generating energy (recombination energy). This energy is known to disrupt the periodic structure of the semiconductor, causing crystal defects. Silicon carbide, in particular, has a high recombination energy due to its large band gap, and it possesses various stable crystal structures, making them easily altered. Therefore, the operation of the pn diode leads to the formation of crystal defects.

[0007] The disturbed crystal structure has a high electrical resistance, so this phenomenon, which occurs particularly in an active region (namely in a region that has unit cells including a channel) of the MOSFET, increases the turn-on resistance, namely an element resistance against a forward current between source and drain, and increases the conduction losses when current of the same density is passed through.

[0008] Conduction losses are one type of predominant loss in the MOSFET, so the occurrence of crystal defects in the MOSFET, caused by the operation of the pn diode in the active region, increases the heat generation of the MOSFET and makes long-term stable operation difficult.

[0009] For the MOSFET with the integrated Schottky junction diode, the diffusion potential of the Schottky junction diode is designed to be lower than that of a pn junction. Consequently, a unipolar current flows through the integrated Schottky junction diode during reverse current operation until the pn diode is active. Therefore, a fixed value of the reverse current is allowed to pass while the pn diode is not operating, and the increase in the turn-on resistance can be avoided.

[0010] However, in a terminal layout described in patent document JP 2003 - 017 701 A, the increasing reverse current flowing through the MOSFET at a low voltage between source and drain causes the pn diode to operate in a unit cell located in a region near the termination, rather than the pn diode operating in a unit cell located in the middle of the active region under a unit cell group in the MOSFET.

[0011] If a semiconductor device is used for a long time under operating conditions in which such a voltage is exceeded, then the turn-on resistance in the unit cells in the peripheral area and in the unit cells in the central area increases in the specified order, so that the turn-on resistance in the entire chip also increases.

[0012] To limit the rise in the turn-on resistance across the entire chip to an acceptable value or lower, the reverse current flowing through the entire element must be limited to restrict the current flowing through the pn diode in the unit cell located near the termination. This demonstrates that the chip required to conduct a desired current must be larger, and consequently, the chip's cost increases.

[0013] The present invention was conceived in consideration of the problems mentioned above. It is therefore an object of the invention to increase the value of the current flowing through the entire chip until a pn diode in a unit cell operates near a termination, and to reduce the size of the chip and the associated cost of the chip. Ways to solve the problem

[0014] The problem underlying the invention is solved by a semiconductor device having the features of independent claim 1. Advantageous embodiments of the invention are specified in dependent claims 2 to 5. Effects of the invention

[0015] According to the aspects of the present invention, the third separation region of the first conductivity type, which is designed to penetrate the second trough region starting from the surface layer of the second trough region in the depth direction, and the second Schottky electrode, which is located on the third separation region, are provided in order to cause a voltage drop in the drift layer around the second Schottky electrode in a backflow state.

[0016] This reduces the voltage across the pn diode in the first two regions located in the active area. Consequently, the pn diode can be prevented from operating, and a larger current can flow back through the Schottky junction diode. As a result, a larger return current than the unipolar current flows through the entire chip, allowing for a smaller chip size.

[0017] These and other tasks, features, aspects and advantages of the present technology will become even more apparent from the following detailed description of the present technology when viewed together with the accompanying drawings. Brief description of the drawings Fig. Figure 1 is a schematic cross-sectional view of a unit cell of a MOSFET with a built-in Schottky junction diode according to one embodiment. Fig.Figure 2 is a schematic top view of the unit cell of the MOSFET with the built-in Schottky junction diode according to the embodiment. Fig. Figure 3 is a schematic top view of the unit cell of the MOSFET with the built-in Schottky junction diode according to the embodiment. Fig. Figure 4 is a schematic top view showing the entire semiconductor device according to the embodiment. Fig. Figure 5 shows a schematic cross-sectional view and a schematic top view of the semiconductor device according to the embodiment, as well as a schematic cross-sectional view without the use of the present invention. Fig. Figure 6 shows a schematic cross-sectional view and a schematic top view of the semiconductor device according to the embodiment, as well as a schematic cross-sectional view without the use of the present invention. Fig.Figure 7 is a diagram showing results of current and voltage characteristics calculated using device simulation in a reverse flow state in the unit cell of the MOSFET with the built-in Schottky junction diode. Fig. Figure 8 is a schematic cross-sectional view of a unit cell of a MOSFET without a built-in Schottky junction diode. Fig. Figure 9 is a diagram showing the results of a simulation that verifies the effects of the design. Fig. Figure 10 is a diagram showing the results of a simulation that verifies the effects of the embodiment. Fig. Figure 11 shows a diagram indicating equipotential lines when a voltage is applied between the source and the drain in the MOSFET. Fig.Figure 12 shows a diagram that presents results of current and voltage characteristics calculated by means of a device simulation in a reverse flow state in the unit cell of the MOSFET with the built-in Schottky junction diode. Fig. Figure 13 is a schematic top view of a semiconductor device according to the embodiment. Fig. Figure 14 is a schematic top view of the semiconductor device according to the embodiment. Fig. Figure 15 is a schematic top view of the semiconductor device according to the embodiment. Fig. Figure 16 is a schematic top view of the semiconductor device according to the embodiment. Fig. Figure 17 is a schematic top view of the semiconductor device according to the embodiment. Fig. Figure 18 shows a schematic cross-sectional view and a top view of the semiconductor device according to the embodiment. Fig.Figure 19 shows a schematic cross-sectional view and a top view of the semiconductor device according to the embodiment. Fig. Figure 20 is a schematic top view showing the entire semiconductor device with a built-in current sensor according to the embodiment. Fig. Figure 21 is a schematic cross-sectional view of the semiconductor device according to the embodiment. Fig. Figure 22 is a schematic cross-sectional view of the semiconductor device without using the present invention. Fig. Figure 23 is a schematic cross-sectional view of the semiconductor device according to the embodiment. Fig. Figure 24 is a schematic cross-sectional view of the unit cell of the MOSFET with the built-in Schottky junction diode according to the embodiment. Description of the embodiments

[0018] The following descriptions illustrate embodiments with reference to the accompanying drawings. Furthermore, the diagrams are shown schematically, and any relationship between the size and position of an image shown in each diagram is not necessarily exact and may be modified accordingly. In the following description, identical components have the same reference numerals. Their designations and functions are also the same. Consequently, their detailed description is omitted in some cases.

[0019] If terms relating to specific positions and directions, such as "upwards", "downwards", "side", "bottom", "front" and "back", are used in the following description, the terms are used for the sake of simplicity to facilitate understanding of the embodiment and do not relate to the actual directions in the embodiment.

[0020] In the embodiments described below, a silicon carbide semiconductor device (SiC) is used as an example of semiconductor devices, and in particular an n-channel silicon carbide MOSFET, wherein the first conductivity type is an n-type and the second conductivity type is a p-type, is described as an example. First embodiment configuration

[0021] First, the configuration of a semiconductor device according to a first embodiment is described. Fig.Figure 1 is a schematic cross-sectional view of a unit cell of a MOSFET with a built-in Schottky junction diode located in an active region. Fig. Figure 2 is a diagram of the unit cell of the MOSFET with the built-in Schottky junction diode when viewed from above. Fig. Figure 2 shows only an area (a semiconductor region) in which a semiconductor layer is formed, without an electrode, an insulating layer, and the like, as in Fig. 1, to show.

[0022] As in Fig. As shown in Figure 1, the semiconductor device has a drift layer 20 of n-type (first conductivity type) silicon carbide formed on a first main surface of a substrate 10 which has a polytype of 4H and is formed from low-resistance n-type (first conductivity type) silicon carbide.

[0023] In the Fig. 1 and Fig.2 the substrate 10 made of silicon carbide has the first principal surface in the plane direction of a (0001) plane, and the first principal surface is inclined by 4° in the direction of the c-axis.

[0024] The drift layer 20 is an n-type semiconductor layer (of the first conductivity type) with a first impurity concentration. A plurality of p-type (of the second conductivity type) well regions 30, containing aluminum (Al), which is a p-type (of the second conductivity type) impurity, are formed at intervals within a planar layer of the drift layer 20. The p-type (of the second conductivity type) impurity concentration in the well regions 30 is a second impurity concentration.

[0025] The bathtub areas 30, which are in Fig.The separation zones shown in Figure 1 are formed at two locations at a distance from each other in the cross-sectional view of the interior of the unit cell. The area for separating the trough regions 30 from each other is an n-type region (of the first conductivity type), which is designated as a second separation zone 21. The second separation zone 21 is a region formed in the surface layer portion of the drift layer 20 and has the same depth as the depth of the trough regions 30, measured from the surface of the drift layer 20 in the depth direction.

[0026] A first separation region 22 of the first conductivity type is configured such that it penetrates each of the trough regions 30 from a surface layer of each of the trough regions 30 in the depth direction. The first separation region 22 is a region located directly below a Schottky electrode 75, which is described below.

[0027] A source region 40 of n-type (of the first conductivity type), containing nitrogen (N), which is an n-type (of the first conductivity type) defect, is partially formed on the surface layer of the trough regions 30. The source region 40 is narrower than the depth of the trough regions 30. Viewed from above, the source region 40 is present on both sides of the first separation region 22.

[0028] A first p-type (second conductivity type) trough contact area 35 containing aluminium (Al) that is the p-type (second conductivity type) defect is preferably formed on the trough area 30, sandwiched between the source area 40 and the first separation area 22 on the side of the surface layer of the drift layer 20.

[0029] A gate insulating layer 50 made of silicon oxide is formed over the area of ​​the second separation region 21, the area of ​​the trough region 30 and part of the area of ​​the source region 40.

[0030] Furthermore, a gate electrode 60 is formed on a surface of the gate insulating layer 50 such that it corresponds to the second separation region 21, the well regions 30, and an end region of the source region 40. A region of the well region 30, sandwiched between the second separation region 21 and the source region 40, which corresponds to the gate electrode 60 through the gate insulating layer 50, and which has an inversion layer formed during the turn-on operating states, is called the channel region.

[0031] An intermediate layer insulating layer 55 made of silicon oxide is formed on the gate insulating layer 50 such that it covers the gate electrode 60. An ohmic electrode 70 on the source side, for reducing the contact resistance to the silicon carbide, is formed on an area of ​​the source region 40 that is not covered by the gate insulating layer 50, and on a portion of an area of ​​the first well contact region 35 on a side that is in contact with the source region 40. The well regions 30 can readily donate electrons to and receive them from the ohmic electrode 70 on the source side through the first well contact region 35, which has a low resistance.

[0032] The Schottky electrode 75 is formed on the surface of the first separation region 22 and is Schottky-bonded to the silicon carbide of the first separation region 22. The Schottky electrode 75 preferably has at least the surface of the first separation region 22, but it may also not include it. The Schottky electrode 75 can be arranged such that, when viewed from above, the ohmic electrode 70 extends across the trough regions 30 on both sides of the Schottky electrode 75. The Schottky electrode 75 can extend further to the surface of the interlayer insulating layer 55, as shown in Fig. 24 shown.

[0033] A source electrode 80 is formed on the ohmic electrode 70 on the source side, the Schottky electrode 75, and the intermediate insulating layer 55. The source electrode 80 electrically short-circuits the ohmic electrode 70 on the source side and the Schottky electrode 75. In other words, the ohmic electrode 70 on the source side is electrically connected to the Schottky electrode 75.

[0034] A drain electrode 85 is formed on a second main surface of the substrate 10 opposite its first main surface, namely on the back surface of the substrate 10 by means of a resistive electrode 71 on the back side. Although not shown specifically, the gate electrode 60 is electrically short-circuited with a gate terminal and gate wiring through a gate contact hole that penetrates the interlayer insulating layer 55 in a portion of an area excluding the unit cell in the semiconductor device.

[0035] The second separation region 21 is a path through which an on-state current flows when the MOSFET is switched on, and the first separation region 22 is a region through which a unipolar current flows as a return current of the Schottky junction diode, which is described in detail below.

[0036] The unit cell can have a pattern, such as a pattern in Fig. 3. The striped pattern shown is different from the one in Fig. 2 patterns shown. Fig. Figure 3 is a diagram of the unit cell of the MOSFET with the built-in Schottky junction diode viewed from above.

[0037] Fig. Figure 4 is a diagram of the semiconductor device viewed from above or from the sides of the first main surface. Fig.Figure 4 shows the top-view position of the active region with dashed lines. The source electrode 80 is configured to have the top-view position of the active region. The gate electrode 82, which is electrically isolated from the source electrode 80, is formed on the first main surface. In this description, any region of the entire semiconductor device, excluding the active region in which the unit cells are periodically arranged, is referred to as an inactive region.

[0038] The Fig. 5A is a diagram describing the structure of a part adjacent to the gate electrode 82, namely a termination of the active region, and is a schematic cross-sectional view corresponding to position aa' in Fig. 3 corresponds to the Fig. 5B is a schematic top view of the area according to Fig.5A, and it only shows the semiconductor area, without showing the electrode, the insulating layer, and the like.

[0039] The Fig. Figure 5C is a schematic cross-sectional view of the same area without the use of the present invention.

[0040] The Fig. Figure 6A is a diagram illustrating the structure of an area adjacent to the termination of the chip, namely the termination of the active area, and is a schematic cross-sectional view corresponding to position bb' in Fig. 4 corresponds to the Fig. 6B is a schematic top view of the area according to Fig. 6A, and it only shows the semiconductor area, without showing the electrode, the insulating layer, and the like. Fig. Figure 6C is a schematic cross-sectional view of the same area without the use of the present invention.

[0041] In Fig.5 The gate electrode 82 is formed on the interlayer insulating layer 55 and is electrically connected to the gate electrode 60 through a gate contact hole 95 that penetrates part of the interlayer insulating layer 55. A wide basin 31 is formed around the active area, and the wide basin 31 and the basin 30 in the outermost peripheral unit cell sandwich the n-type area, which has the same width as that of the second separation area 21, with the wide basin 31 having a formation area that is larger than that of the basin 30.

[0042] The top-view position of the wide well region 31 corresponds to the top-view position of the gate electrode 82. The wide well region 31 is connected to the source electrode 80 at a position near the active region via a well contact hole 91, which penetrates part of the interlayer insulating layer 55 located on one side adjacent to the well regions 30. The first well contact region 35 and the resistive electrode 70 (the second resistive electrode) are formed in a surface layer region of the wide well region 31 that contacts the well contact hole 91.

[0043] A field insulating layer 52 with a thickness greater than that of the gate insulating layer 50 is partially formed in a layer above the drift layer 20 and below the gate electrode 60 and is located further away from the active region than the top-view positions of the trough contact hole 91 and a Schottky junction diode contact hole 92.

[0044] In Fig.6 The wide trough region 31 is formed around the active region, and the wide trough region 31 and the trough region 30 in the outermost peripheral unit cell sandwich the n-type region, which has the same width as that of the second separation region 21, with the wide trough region 31 having a region larger than that of the trough region 30. A p-type transition-termination expansion (JTE) region 37 with a defect concentration lower than that of the wide trough region 31 is formed closer to the peripheral side of the element than the wide trough region 31. The JTE region 37 is connected to the wide trough region 31.

[0045] The wide basin area 31 is connected to the source electrode 80 through the basin contact hole 91, which penetrates part of the intermediate insulating layer 55 located on the side adjacent to the basin areas 30. The first basin contact area 35 and the ohmic electrode 70 are formed in the area of ​​the wide basin area 31 that contacts the basin contact hole 91.

[0046] In the two positions according to aa' (see Fig. 4) and bb' (see Fig. 4) are only possible using the present invention ( Fig. 5A, Fig. 5B, Fig. 6A and Fig.6B) a part of the interlayer insulating layer 55 and a part of the gate insulating layer 50 is removed to form the Schottky junction diode contact hole 92 between the well area 30 in the outermost peripheral unit cell and the well contact hole 91, and the source electrode 80 is in contact with the Schottky electrode 75 deposited on the silicon carbide through the Schottky junction diode contact hole 92.

[0047] A third separation region 23, in which the wide trough region 31 is not formed, is located below the Schottky electrode 75. In other words, the third separation region 23 is surrounded by the wide trough region 31, and it is the n-type region due to the absence of a p-type implantation to form the wide trough region 31. In other words, the third separation region 23 is configured such that it penetrates the wide trough region 31 from the surface layer of the wide trough region 31 in the depth direction. Consequently, the Schottky junction diode surrounded by the wide trough region 31 is formed in the ineffective region.

[0048] Both Schottky junction diodes, formed in the active region and the inactive region, have a diffusion potential that is lower than the diffusion potential of the pn junction formed in silicon carbide. Manufacturing process

[0049] The following describes a method for manufacturing the MOSFET with the built-in Schottky junction diode, which is the semiconductor device, in this embodiment.

[0050] First, the drift layer 20 made of silicon carbide with a thickness of 5 µm to 200 µm is epitaxially formed with an n-type defect concentration of 1 × 10 14 cm -3 up to 1 × 10 17 cm -3 grown by chemical vapor deposition (CVD) on the surface of substrate 10, which has a first principal surface in the plane direction of the (0001) plane, has the polytype of 4H and is formed from n-type silicon which has a low resistance.

[0051] Subsequently, an implantation mask is formed on the surface of the drift layer 20 using a photoresist or similar material, and Al, which is a p-type defect, is ion-implanted. At this stage, the depth of ion implantation of Al is approximately 0.5 µm to 3 µm, which does not exceed the thickness of the drift layer 20. The defect concentration of the ion-implanted Al is in the range of 1 × 10⁻⁶ 17 cm -3 up to 1 × 10 19 cm -3 , and it is higher than the first impurity concentration in the drift layer 20. The implantation mask is then removed. The areas implanted with aluminum ions in this step are the basin areas 30 and the wide basin area 31.

[0052] Subsequently, an implantation mask is formed on the surface of the drift layer 20 using a photoresist or similar material, and Al, which is a p-type defect, is ion-implanted. At this stage, the depth of ion implantation of Al is approximately 0.5 µm to 3 µm, which does not exceed the thickness of the drift layer 20. The defect concentration of the ion-implanted Al is in the range of 1 × 10⁻⁶ 16 cm -3 up to 1 × 10 18 cm -3 It is higher than the first defect concentration in the drift layer 20, and it is lower than the concentration of Al in the trough areas 30. Subsequently, the implantation mask is removed. The area implanted with Al ions in this step is the JTE area 37.

[0053] Subsequently, an implantation mask is formed on the surface of the drift layer 20 with the photoresist or the like, and N, which is an n-type defect, is ion-implanted. The depth of ion implantation of N is shallower than the thickness of the trough areas 30. The defect concentration of the ion-implanted N is in the range of 1 × 10 18 cm -3 up to 1 × 10 21 cm -3 , and it exceeds the second p-type defect concentration in the basin areas 30. The n-type area among the areas implanted with N in this step is the source area 40.

[0054] Subsequently, an implantation mask is formed on the surface of the drift layer 20 with the photoresist or the like, and Al, which is a p-type defect, is ion-implanted, and the implantation mask is removed. The area ion-implanted with Al in this step is the first well contact area 35. The first well contact area 35 is provided to maintain sufficient electrical contact between the well areas 30 and the ohmic electrode 70 on the source side, and the p-type defect concentration in the first well contact area 35 is preferably adjusted to a concentration that is higher than the second p-type defect concentration in the well areas 30.For the ion implantation of the p-type defects in this step, the substrate 10 or the drift layer 20 is preferably heated to 150 °C or higher for ion implantation in order to reduce the resistance in the first trough contact area 35.

[0055] A heat treatment unit then performs annealing for 30 seconds to one hour in an atmosphere containing an inert gas, such as argon (Ar) (at 1300 °C to 1900 °C). This annealing process electrically activates the ion-implanted nitrogen and aluminum.

[0056] Then, the field insulating layer 52, which has a thickness of approximately 0.5 µm to 2 µm and is formed from a silicon dioxide layer, is formed using the CVD process, photolithography, or similar techniques, in an area excluding the position that corresponds almost exactly to the aforementioned active area. At this time, the field insulating layer 52 can be removed at the position that corresponds almost exactly to the cell area using photolithography or etching, after it has been formed, for example, over the entire surface.

[0057] Then, an area of ​​silicon carbide not covered by the field insulating layer 52 is thermally oxidized to form silicon oxide, which is the gate insulating layer 50, having a desired thickness. Next, a polycrystalline silicon conductivity layer is formed on the gate insulating layer 50 using a low-pressure CVD process and patterned to form the gate electrode 60. Then, the intermediate insulating layer 55 is formed using the same low-pressure CVD process. Finally, a contact hole penetrating the intermediate insulating layer 55 and the gate insulating layer 50, reaching the first well contact area 35 and the source area 40 in the unit cell, is formed simultaneously with the well contact hole 91.

[0058] After a metal layer containing Ni as the main component has been formed by sputtering or the like, a heat treatment is subsequently carried out at temperatures of 600 °C to 1100 °C to cause a reaction to occur between the metal layer containing Ni as the main component and the silicon carbide layer in the contact hole, in order to form a silicide between the silicon carbide layer and the metal layer.

[0059] Then the metal layer on the intermediate insulating layer 55, with the exception of the silicide formed by the reaction, is removed by wet etching with any solution of sulfuric acid, nitric acid, hydrochloric acid, or a mixed solution of all three and aqueous hydrogen peroxide. This forms the ohmic electrode 70 on the source side.

[0060] Subsequently, metal containing Ni as the main component is formed on the back surface (the second main surface) of the substrate 10 and heat-treated to form the ohmic electrode 71 on the back side of the substrate 10.

[0061] Subsequently, the interlayer insulating layer 55 on the first separation region 22 and the interlayer insulating layer 55 and the gate insulating layer 50 at the positions of the Schottky junction diode contact hole 92 and the gate contact hole 95 are removed by applying a patterned photoresist or the like. Wet setting, which does not damage the silicon carbide surface acting as an interface of the Schottky junction diode, is a preferred removal method.

[0062] The Schottky electrode 75 is then deposited by sputtering or similar processes. Ti, Mo, Ni, or similar materials are preferably deposited as the Schottky electrode 75.

[0063] Subsequently, a wiring metal of Al or the like is formed by sputtering or vapor deposition on the surface of the substrate 10 that has been processed so far, and it is brought into a predetermined shape by means of photolithography to form the source electrode 80, which forms the ohmic electrode 70 on the source-source side and the Schottky electrode 75, and to form the gate electrode 82, which is in contact with the gate electrode 60.

[0064] Furthermore, the drain electrode 85, which represents the metal layer, is formed on the surface of the ohmic electrode 71 on the back side, which is formed on the back side of the substrate 10, and the semiconductor device, which is in Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5 to Fig. The version shown in section 6 is complete. Operation

[0065] The operation of the MOSFET with the built-in Schottky junction diode, which is the semiconductor device, is described below in a simple way in three states in this embodiment.

[0066] The first state is hereinafter referred to as a “switch-on state”, wherein a high voltage is applied to the drain electrode 85 with respect to the source electrode 80, and wherein a positive voltage greater than or equal to a threshold value is applied to the gate electrode 82.

[0067] In the switched-on state, an inversion channel is formed in the channel region, and a path through which electrons, acting as charge carriers, flow is formed between the n-type source region 40 and the second n-type separation region 21. On the other hand, an electric field (a reverse bias) is applied to the integrated Schottky junction diode in a direction in which current hardly flows through the Schottky junction, namely in a reverse direction, so that no current flows.

[0068] The electrons flowing from the source electrode 80 to the drain electrode 85 reach the drain electrode 85 from the source electrode 80 through the ohmic electrode 70, the source electrode 40, the channel region, the second separation region 21, the drift layer 20 and then the substrate 10, according to the electric field formed by the positive voltage applied to the drain electrode 85.

[0069] Therefore, a positive voltage is applied to the gate electrode 60, causing a turn-on current to flow from the drain electrode 85 to the source electrode 80. At this point, the voltage between the source electrode 80 and the drain electrode 85 is called the turn-on voltage, and a value at which the turn-on voltage is divided by the density of the turn-on current is called the turn-on resistance.

[0070] The turn-on resistance is equal to the total resistance in the path through which the electrons flow. The product of the turn-on resistance and the square of the turn-on current is equal to the conduction losses consumed when the MOSFET is energized, so the turn-on resistance is preferably low. The turn-on current flows only through the active region, including the channel, and does not flow through the inactive region.

[0071] The second state is hereinafter referred to as a “switch-off state”, wherein a high voltage is applied to the drain electrode 85 with respect to the source electrode 80, and wherein a voltage less than or equal to the threshold is applied to the gate electrode 60.

[0072] In the off state, the inversion channel is not formed in the channel region, so the on-state current does not flow, and the high voltage in the on state is present between the source electrode 80 and the drain electrode 85 of the MOSFET. At this point, the voltage of the gate electrodes 82 is almost equal to the voltage of the source electrode 80, so the high voltage is also present between the gate electrode 82 and the drain electrode 85.

[0073] In the active region, the reverse bias is applied to a pn junction formed between the trough region 30 and the drift layer 20, and a thick depletion layer spreads to the drift layer 20, the concentration of which is relatively low, so that the application of the voltage to the gate insulating layer 50 can be prevented.

[0074] The gate insulating layer 50 on the second separation region 21 does not have a p-type region directly beneath it, and it is therefore subject to an electric field strength that is relatively higher than that applied to the gate insulating layer 50 at the trough regions 30, but if the width of the second separation region 21 is suitably limited, a depletion layer extending from the trough regions 30 to the second separation region 21 can limit the electric field applied to the gate insulating layer 50 to a desired value or lower.

[0075] A thin depletion layer spreads not only in the drift layer 20 and the second separation region 21, but also to the p-type well regions 30, whose concentration is relatively high. This allows holes created by the depletion layer forming in the well regions 30 to be discharged into the source electrode 80 through the first well contact region 35 during a process of switching to the off state. In other words, the electrical contact between the well regions 30 and the source electrode 80 can prevent the high electric field strength from being applied to the gate insulating layer 50 at the well regions 30 during the off state.

[0076] The area of ​​ineffective region in which the gate electrode 82 is arranged, which is in Fig.Figure 5 shows the following: The wide basin 31, which is formed in the area containing most of the top-view positions of the gate insulating layer 50 and the field insulating layer 52, which are located in the ineffective region; and the basin contact hole 91 for enabling electrical contact between the wide basin 31 and the source electrode 80 in a portion of the basin contact hole 91. Similarly, this can prevent the high electric field strength from being applied to the gate insulating layer 50 and the field insulating layer 52, which are located in the ineffective region.

[0077] In the end area of ​​the chip, which is in Fig.As shown in Figure 6, in the ineffective area, a portion of the wide well region 31 and the JTE region 37 is depleted in addition to the drift layer 20, in order to reduce the concentration of electric fields generated at the termination of the element and to prevent a decrease in the withstanding voltage. At this point, holes generated in the depletion layer of the wide well region 31 and the JTE region 37 are discharged into the source electrode 80 through the nearest well contact hole 91.

[0078] On the other hand, an electric field in the same direction as the electric field in the "switch-on state" is applied to the built-in Schottky junction diode, so ideally no current flows. However, the applied electric field is much stronger than in the "switch-on state," and consequently, a leakage current can occur.

[0079] The large leakage current increases the heat generation of the MOSFET, and the MOSFET and any module containing the MOSFET can be thermally destroyed. Consequently, the electric field applied to the Schottky junction is preferably suppressed to reduce the leakage current.

[0080] The third state is a state in which a reverse current flows from the source electrode 80 towards the drain electrode 85 while a low voltage is applied to the drain electrode 85 with respect to the source electrode 80, i.e., while an electromotive force is applied to the MOSFET. This state is subsequently referred to as a "reverse current state".

[0081] In the reverse flow state, an electric field (forward bias) is applied in the forward direction to the integrated Schottky junction diode, and a unipolar current, consisting of an electron current, flows from the Schottky electrode 75 towards the silicon carbide layer. If the voltage of the source electrode 80 with respect to the drain electrode 85 (the voltage between source and drain) is low, the entire reverse flow current passes through the integrated Schottky junction diode, preventing the implantation of minority charge carriers into the drift layer 20. Consequently, no crystal defects occur, which also prevents an increase in the on-state resistance.

[0082] However, the voltage between source and drain continues to increase, and the pn diode formed between the trough region 30 and the drift layer 20 in the active region operates under special conditions, which causes the implantation of minority charge carriers into the drift layer 20 in the active region. As a result, crystal defects can occur.

[0083] The inventors discovered that the conditions that cause the pn diode to operate in its active region are influenced by the environment of the unit cells. Taking this into account, the inventors devised a technique to make it more difficult for the pn diode to operate in its active region.

[0084] For the sake of simplicity, a periodic arrangement of the unit cells, continuing indefinitely, is assumed before further explanation. In this case, a device simulation can be performed assuming that only the unit cells are truncated from the periodicity and that one unit cell is the mirror image of another if the reflection occurs at a boundary between adjacent unit cells. Hereinafter, the MOSFET with the built-in Schottky junction diode, which exhibits the unit cells only in the periodic arrangement, is referred to as an ideal MOSFET with a built-in Schottky junction diode.

[0085] Fig.Figure 7 is a diagram showing the results of the current and voltage characteristics calculated using device simulation in the reverse-flow state in the unit cell of the MOSFET with the built-in Schottky junction diode and the unit cell of the MOSFET without the built-in Schottky junction diode.

[0086] The vertical axis gives a current [A / cm²]. 2 ] the current flowing through the drain electrode, and the horizontal axis indicates a voltage between source and drain [V]. Fig. Figure 7 shows the characteristic curves of the MOSFET with the built-in Schottky junction diode with triangular markings and the characteristic curves of the MOSFET without the built-in Schottky junction diode with round markings. Fig. Figure 8 shows a cross-sectional view of the MOSFET without the built-in Schottky junction diode, whose characteristic curves are shown for comparison purposes.

[0087] It's out Fig.Figure 7 clearly shows that the current increases abruptly when the voltage between source and drain exceeds approximately 7 V in the MOSFET with the integrated Schottky junction diode (triangular markings). It is conceivable that the pn diode described above is operating and transitioning from unipolar to bipolar operation, causing conductivity modulation in the drift layer.

[0088] It is worth noting that the voltage between source and drain, which drives the pn diode, is higher in the MOSFET with the integrated Schottky junction diode than in the MOSFET without the integrated Schottky junction diode. This can be described as follows. Before a more detailed description, it must be mentioned that the voltage applied to the pn junction is a potential difference between the well region 30 and a contact area of ​​the drift layer 20 with the well region 30.

[0089] Initially, the following applies to the MOSFET without the built-in Schottky junction diode: If the voltage between source and drain is less than or equal to the diffusion potential of the pn diode or less than or equal to the voltage operating the pn diode, then no current flows between source and drain, so that the potential of the drain electrode 85 is equal to the potential of the contact area of ​​the drift layer 20 with the well region 30.

[0090] In other words, the entire voltage between source and drain is applied to the pn diode. Therefore, when the voltage between source and drain, which has been gradually increased, exceeds the operating voltage of the pn diode, the pn diode begins to operate; that is, the minority charge carriers begin to be implanted into the drift layer 20.

[0091] For the MOSFET with the built-in Schottky junction diode, the following applies: If the voltage between source and drain is higher than the operating voltage of the Schottky junction diode and less than or equal to the operating voltage of the pn diode, then the unipolar current between source and drain flows through the Schottky junction diode, resulting in a voltage drop in the conduction path according to the product of the resistivity and the current density.

[0092] In other words, the voltage drop also occurs in the drift layer 20 and the substrate 10. By the value of the voltage, which is equal to the voltage drop, the potential of the contact area of ​​the drift layer 20 with the well region 30 is lower than the voltage between source and drain. As a result of this effect, the MOSFET with the integrated Schottky junction diode has a high voltage between source and drain, which drives the Schottky junction diode and allows a larger unipolar current than the reverse current to pass through until the pn diode operates.

[0093] Furthermore, the proximity of the active region termination in the MOSFET with the integrated Schottky junction diode is taken into account. The unit cells at the active region termination are adjacent to the wide well region 31, as described above.

[0094] In structures without the use of the present invention, as in Fig.5C and Fig. As shown in Figure 6C, no unipolar current can flow through the wide well region 31, so that most of the voltage between source and drain is applied to the pn diode, which is the transition between the wide well region 31 and the drift layer 20.

[0095] Therefore, the voltage between source and drain exceeds the operating voltage of the pn diode, leading to the implantation of minority charge carriers from the wide well region 31 into the drift layer 20. At this point, the holes that have diffused into the drift layer 20 recombine with electrons at this location, causing the crystal defects in the drift layer in the active region to increase the resistance of the drift layer 20.

[0096] However, since the path of the turn-on current is mainly in the active region, the expanded defects that occur in the drift layer 20, which is located immediately below the wide trough region 31, rarely increase the resistance when the turn-on current flows through the active region, i.e., the turn-on resistance.

[0097] The problem here arises when the voltage between the source and drain of the pn diode in the unit cells near the termination of the active region, which is lower than the voltage across the pn diode in the unit cells of the ideal MOSFET with the integrated Schottky junction diode, exceeds the operating voltage of the pn diode. This causes minority charge carriers to be implanted from the well regions 30 into the drift layer 20. At this point, the holes that have diffused into the drift layer 20 recombine with electrons at this location, resulting in crystal defects in the drift layer in the active region increasing the turn-on resistance.

[0098] The operating voltage of the pn diode in the unit cells near the termination is reduced by the mechanism described below.

[0099] The unipolar current from the Schottky junction diode diffuses into the drift layer 20, which is located directly below the wide well region 31 in the outermost peripheral unit cells. The voltage drop in the drift layer 20, located directly below the well regions 30 in the outermost peripheral unit cells, is smaller than the voltage drop in the drift layer 20 of the ideal MOSFET with the integrated Schottky junction diode. As a result, the voltage applied to the pn diode increases in the outermost peripheral unit cells, and bipolar operation begins at a source-drain voltage that is lower than that of the ideal MOSFET with the integrated Schottky junction diode.

[0100] The unipolar current from the Schottky junction diode can diffuse into the drift layer 20, which is located immediately below the wide basin 31, not only in the outermost peripheral cells in the active region, but also in the cells near the outermost peripheral cells, especially if the drift layer 20 has a high thickness. As a result, the outermost peripheral cells have the lowest source-drain voltage, causing each of these cells to begin bipolar operation, while the cells closer to the inside exhibit characteristics more similar to those of an ideal MOSFET with the integrated Schottky junction diode.

[0101] In a case where the charge carriers remain in the drift layer 20 for a long time, the minority charge carriers, when implanted from the wide well region 31, can also diffuse into the drift layer 20, which is located immediately below the well regions 30 in the adjacent active region. To satisfy the charge neutrality conditions, the electrons, as the majority charge carriers, are implanted from the substrate 10 in this case to increase the electron density, leading to a decrease in the resistivity of the drift layer 20. The reduced resistivity of the drift layer 20 decreases the voltage drop that occurs in the drift layer 20, thus increasing the voltage applied to the pn junction.

[0102] Therefore, in the outermost peripheral unit cells, the voltage applied to the pn diode increases, and bipolar operation begins at an even lower source-drain voltage. Furthermore, the bipolar operation in the outermost peripheral unit cells begins to cause the diffusion of minority charge carriers into the unit cells located closer to the inside. In this way, the bipolar operation of the pn diode in the wide well region 31 causes bipolar operation in each of the unit cells, starting from the unit cell located closer to the inside of the active region.

[0103] The effect gradually decreases as it propagates to the unit cells located closer to the inside. Consequently, the outermost peripheral cells have the lowest source-drain voltage required to induce bipolar operation in each cell, while the cells closer to the inside exhibit properties more similar to those described above, assuming the periodic arrangement of unit cells continues indefinitely.

[0104] As described above, the following applies: When applying the voltage between source and drain that exceeds the operating voltage of the pn diode in the well region 30 in the outermost peripheral cells in the active region, the bipolar operation can cause the crystal defects in some of the unit cells near the outermost peripheral cells in the active region to increase the turn-on resistance across the entire chip.

[0105] The larger value of the return current flowing through the entire chip between source and drain at high drive voltages expands the region in which bipolar operation occurs. The return current density must therefore be set to a fixed value or less to limit the area where crystal defects can occur. However, this increases the chip area, leading to a higher chip cost.

[0106] In other words, the decrease in the operating voltage of the pn diode in the unit cells in the active region can be prevented by preventing the operation of the pn diode in the well regions 30 in the outermost peripheral cells. To achieve this, it is likely to be effective to reduce the potential difference between the well region 30 and the contact surface of the drift layer 20 with the well region 30 by ensuring a sufficient unipolar current from the Schottky junction diode immediately below the well regions 30 in the outermost peripheral cells, thus increasing the voltage drop in the drift layer 20.

[0107] The semiconductor device in this embodiment, which is located in the Fig. 5A, the Fig. 5B, the Fig. 6A and the Fig.As shown in Figure 6B, the Schottky junction diode has a contact hole 91 in the partially missing part of the wide well area 31. If the voltage between source and drain is greater than the diffusion potential of the Schottky junction diode, then the current flows from the Schottky junction diode near the Schottky junction diode contact hole 92 towards the silicon carbide layer.

[0108] The current is diffused horizontally into the drift layer 20, causing the voltage drop not only in the area immediately below the Schottky junction diode contact hole 92, but also in the drift layer 20, which is located immediately below the well areas 30 in the active area, the substrate 10, as well as the drift layer 20 and the substrate 10 near the well contact hole 91, which is adjacent to the Schottky junction diode contact hole 92.

[0109] As a result, the voltage applied to the pn junction near the area with the Schottky junction diode contact hole 92 is reduced by the value of the voltage drop. Consequently, bipolar operation in the peripheral unit cells can be suppressed up to the higher voltage between source and drain.

[0110] Fig. Figure 9 shows results calculated by a device simulation of current characteristics and voltage characteristics in the reverse state in the MOSFET with the built-in Schottky junction diode including ten unit cells of the MOSFET with the built-in Schottky junction diode, the wide well region 31 and the Schottky junction diode which is located closer to the unit cell region than the first well contact region 35 in the wide well region 31 and which is formed in the partially missing part of the wide well region 31.

[0111] The vertical axis indicates the current (A) flowing through the drain electrode, and the horizontal axis indicates the voltage between source and drain (V). The distance between the end region of the outermost peripheral unit cell and the Schottky junction diode formed in the partially missing part of the wide well region 31 is 5 µm, and the distance between the end region of the outermost peripheral unit cell and the first well contact region 35 in the wide well region 31 is 20 µm.

[0112] In Fig.Figure 9 shows thick dashed lines in the graph indicating the results of the current and voltage characteristics calculated by device simulation in the reverse flow state only in the unit cells of the MOSFET with the built-in Schottky junction diode, where one dashed line indicates the Schottky junction diode in the cell region where the current starts to flow with a source-drain voltage of approximately 1 V, and where another dashed line indicates the pn diode in the cell region where the current starts to flow with a source-drain voltage of approximately 8 V.

[0113] The currents flowing through the Schottky junction diodes in the ten cells located at different positions are given collectively around the current flowing through the Schottky junction diodes in the unit cells only. The currents flowing through the pn diodes in the ten cells located at different positions are given collectively around the current flowing through the pn diodes in the unit cells only.

[0114] Fig. Figure 10 shows the results obtained using the same calculation for the MOSFET with the built-in Schottky junction diode, which does not have the Schottky junction diode that is formed in the partially missing part of the wide well region 31. Fig.10. Thick dashed lines in the graph indicate the results of the current and voltage characteristics calculated by device simulation in the reverse flow state only in the unit cells of the MOSFET with the built-in Schottky junction diode, where one dashed line indicates the Schottky junction diode in the cell region where the current starts to flow with a source-drain voltage of approximately 1V, and where another dashed line indicates the pn diode in the cell region where the current starts to flow with a source-drain voltage of approximately 8V.

[0115] The currents flowing through the Schottky junction diodes in the ten cells located at different positions are given collectively around the current flowing through the Schottky junction diodes in the unit cells only. The currents flowing through the pn diodes in the ten cells located at different positions are given collectively around the current flowing through the pn diodes in the unit cells only.

[0116] In the simulation, the current flowing through the Schottky junction diode in the cell region diffuses towards the drift layer 20, which is located directly below the wide trough region 31. Consequently, the voltage drop in the drift layer 20 is lower than in the case where only the unit cells of the MOSFET with the integrated Schottky junction diode are simulated, thus increasing the voltage applied to the Schottky junction diode and the pn diode.

[0117] This effect is more pronounced in cells located closer to the outer periphery. In the Fig. 9 and Fig.10. The currents flowing through the Schottky junction diodes in the ten cells located at different positions increase in the cell closer to the outer periphery, while the rising voltage of the pn diodes in the ten cells located at different positions decreases in the cell closer to the outer periphery.

[0118] The rise voltage of the pn diode in the outermost peripheral cells decreases to approximately 6 V compared to the case where only one of the unit cells in Fig. 10 is calculated (with the thick dashed line indicating that the current starts to flow at approximately 8 V), while the rise voltage of the pn diode in the outermost peripheral cells in Fig. 9 is held high at approximately 8 V.

[0119] The Fig.Figure 11A shows equipotential lines when a voltage of 6 V is applied between source and drain in the MOSFET with the built-in Schottky junction diode, including the ten unit cells of the MOSFET with the built-in Schottky junction diode, the wide well region 31, the Schottky junction diode which is located closer to the unit cell region than the first well contact region 35 in the wide well region 31 and which is formed in the partially missing part of the wide well region 31.

[0120] The Fig. Figure 11B shows equipotential lines when a voltage of 6 V is applied between source and drain in the MOSFET with the built-in Schottky junction diode, which does not have a Schottky junction diode formed in the partially missing part of the wide well region 31.

[0121] According to Fig.In 11A, a current propagates from the Schottky junction diode formed in the partially missing part of the wide well region 31 to the drift layer 20, which comprises the lower parts of the well regions 30 in the outermost peripheral unit cells. This causes the voltage drop in the lower regions of the well regions 30 in the outermost peripheral unit cells. Consequently, the voltage applied to the pn junction in the well regions 30 in the unit cells is smaller than that in the case according to Fig. 11B.

[0122] This allows for a smaller degree of voltage drop in the rise time of the pn diode in the well regions 30 in the unit cells. More precisely: The MOSFET with the built-in Schottky junction diode has the wide well region 31 and the Schottky junction diode, which is located closer to the unit cell region than the first well contact region 35 in the wide well region 31 and which is formed in the partially missing part of the wide well region 31, and consequently bipolar operation in the well regions 30 in the unit cells can be prevented.

[0123] Fig.Figure 12 shows results of current characteristics and voltage characteristics in the reverse flow state in the pn diode calculated with the device simulation in the well areas 30 in the outermost peripheral unit cells of the MOSFET with the built-in Schottky junction diode, including the ten unit cells of the MOSFET with the built-in Schottky junction diode, the wide well area 31 and the Schottky junction diode which is located closer to the unit cell area than the first well contact area 35 in the wide well area 31 and which is formed in the partially missing part of the wide well area 31. Fig. Figure 12 shows the results for the cases in which the distance between the end region of the outermost peripheral unit cell and the Schottky junction diode formed in the partially missing part of the wide trough region 31 is set in a range of 1.5 µm to 5 µm.

[0124] In Fig.12 Rhombus-shaped markers indicate the case in which the distance between the end region of the outermost peripheral unit cell and the Schottky junction diode, which is formed in the partially missing part of the wide well region 31, is 1.5 µm; square markers indicate the case in which the distance is 2 µm; triangular markers indicate the case in which the distance is 3 µm; circular markers indicate the case in which the distance is 4 µm; and crosses indicate the case in which the distance is 5 µm. The dashed lines in the graph indicate the results of the current and voltage characteristics in the reverse-flow state only in the unit cells of the MOSFET without the integrated Schottky junction diode.

[0125] As in Fig.As shown in Figure 12, if the distance between the end region of the outermost peripheral unit cell and the Schottky junction diode formed in the partially missing part of the wide well region 31, or the distance between each of the well regions 30 and the Schottky electrode 75 formed in the wide well region 31, is less than or equal to 3 µm, the rise voltage of the pn diode in the well regions 30 in the outermost peripheral unit cells is greater than the rise voltage of the pn diode in the well regions 30 when only the unit cells are considered. In other words, the drop in the rise voltage of the pn diode in the well regions 30 can be suppressed in all unit cells in the active region.

[0126] In this way, it is preferable if the distance between the end region of the outermost peripheral unit cell and the Schottky junction diode formed in the partially missing part of the wide well region 31 is as short as possible, and preferably less than or equal to 3 µm, which can prevent the drop in the rise voltage of the pn diode in the well regions 30 in the outermost peripheral unit cells. As already described, the decrease in the operating voltage of the pn diode in the well regions 30 in all unit cells in the active region can be prevented by disabling the operation of the pn diode in the well regions 30 in the outermost peripheral cells. Effects

[0127] The effects of this embodiment are described below.

[0128] According to this embodiment, the semiconductor device comprises the following: the drift layer 20 of the first conductivity type; the well regions 30, which serve as first well regions of the second conductivity type; the wide well region 31, which serves as a second well region of the second conductivity type; the first separation region 22 of the first conductivity type; the source region 40 of the first conductivity type; the Schottky electrode 75, which serves as a first Schottky electrode located on the first separation region 22; the ohmic electrode 70, which serves as a first ohmic electrode located above each of the well regions 30 and on the source region 40, while contacting each of the well regions 30 and the source region 40; the second separation region 21 of the first conductivity type; the ohmic electrode 70, which serves as a second ohmic electrode located above the wide well region 31;the third separation region 23 of the first conductivity type; the Schottky electrode 75, which serves as a second Schottky electrode located on the third separation region 23; the gate electrode 60; the interlayer insulating layer 55, which serves as a second insulating layer; and the source electrode 80.;

[0129] The drift layer 20 is formed on the substrate 10, which serves as a semiconductor substrate of the first conductivity type. The majority of the trough regions 30 are located at a distance within the surface layer of the drift layer 20.

[0130] The wide trough area 31, when viewed from above, is formed on both sides of the majority of trough areas 30 in the surface layer of the drift layer 20. The wide trough area 31 has a formation area that is larger than that of each of the trough areas 30.

[0131] The first separation zone 22 is designed such that it penetrates each of the basin areas 30 from the surface layer of each basin area 30 in the depth direction. The source zone 40, when viewed from above, is formed on both sides of the first separation zone 22 in the surface layer of each basin area 30.

[0132] The second separation area 21 is an area for separating the trough areas 30 from each other. The third separation area 23 is arranged closer to the trough areas 30 than the ohmic electrode 70, which serves as the second ohmic electrode in the wide trough area 31, and it is designed such that it penetrates the wide trough area 31 from the surface layer of the wide trough area 31 in the depth direction.

[0133] The gate electrode 60 is located, through the gate insulating layer 50, which serves as the first insulating layer, over part of the basin areas 30 and the wide basin area 31, except for positions where the Schottky electrode 75 and the ohmic electrode 70 are located.

[0134] The interlayer insulating layer 55 is configured to cover the gate electrode 60. The source electrode 80 is arranged to cover the Schottky electrode 75, the ohmic electrode 70, and the interlayer insulating layer 55.

[0135] Such a configuration allows the MOSFET with the integrated Schottky junction diode to have the wide well region 31 and the Schottky junction diode, which is located closer to the unit cell region than the first well contact region 35 in the wide well region 31 and which is formed in the partially missing part of the wide well region 31. This can prevent the voltage drop of the pn diode in the well regions 30 in the unit cells in the active region (especially the pn diode in the outermost peripheral unit cells in the active region).

[0136] For this reason, a larger current value can be made to flow back into the Schottky junction diode in order to increase the return current, which flows as a unipolar current through the entire chip, allowing for a reduced size of the chip, as well as reduced chip costs resulting from the reduced size.

[0137] Configurations other than those above may be omitted in a suitable manner, and the same effects may be obtained even if any configuration in this description is added in a suitable manner.

[0138] In this embodiment, the distance between the Schottky electrode 75, which serves as the second Schottky electrode, and each of the trough areas 30 is less than or equal to 3 µm.

[0139] Such a configuration can increase the current flowing from the Schottky junction diode, located in the wide basin 31, to the drift layer 20 immediately below the outer peripheral cells in the reverse-flow state, and consequently the voltage drop can be further increased. This can prevent the pn diode in the outer peripheral cells from operating. Second embodiment configuration

[0140] Fig.Figure 13 is a schematic top view to describe the structure of a part adjacent to the gate electrode 82, the termination of the active region, and Fig. 13 corresponds to position aa' in Fig. 4. Fig. Figure 13 shows only the semiconductor area, without showing the electrode, insulating layer, or the like. Fig. Figure 14 is a schematic top view to describe the structure of a part that does not contain the gate electrode 82 and is adjacent to the termination of the chip, the termination of the active area, and Fig. 14 corresponds to position bb' in Fig. 4. Fig. Figure 14 shows only the semiconductor area, without showing the electrode, insulating layer, or the like.

[0141] In Fig. 13 and Fig.14 is a third separation region 23b, a partially missing area of ​​the wide well region 31b between each of the well regions 30 in the outermost peripheral unit cells and the first well contact region 35 in the wide well region 31b, and it is configured to surround the active region. Although not shown specifically, the Schottky electrode 75 is formed on the surface of the third separation region 23b to allow the passage of the unipolar current during reverse flow operation.

[0142] In this way, the Schottky junction diode region is formed continuously in the wide well region 31b, so that it surrounds the active region, or it is formed in a direction that intersects the direction from the wide well region 31b towards the well regions 30 in the top view, thereby enabling the unipolar current to flow uniformly from the Schottky junction diode in the wide well region 31b to the drift layer 20 below the well regions 30 in the unit cells. Consequently, the unipolar current does not vary according to the top-view positions, and the decrease in the operating voltage of the pn diode in the outer peripheral unit cells can be prevented.

[0143] An excessive increase in the area of ​​the Schottky junction diode region in the MOSFET with the integrated Schottky junction diode increases the leakage current in the off-state. Therefore, to reduce the Schottky junction diode region in the MOSFET with the integrated Schottky junction diode, a plurality of third separation regions 23c, which are partially missing regions of a wide well region 31c designed to surround the active region, can be discretely formed, as shown in Fig. 15 and Fig. 16 shown (which are described in detail in a third embodiment). Effects

[0144] The effects of this embodiment are described below.

[0145] According to this embodiment, the third separation area 23b is formed continuously in the direction that intersects the direction towards the trough areas 30, which serve as the first trough areas in the top view.

[0146] Such a configuration allows the unipolar current to flow uniformly from the Schottky junction diode in the wide well region 31b to the drift layer 20 below the well regions 30 in the unit cells. Consequently, the unipolar current does not vary according to the top-view positions, and the decrease in the operating voltage of the pn diode in the well regions 30 in the unit cells in the active region (especially the pn diode in the outermost peripheral unit cells in the active region) can be prevented.

[0147] For this reason, a larger current value can be made to flow back into the Schottky junction diode in order to increase the return current, which flows as a unipolar current through the entire chip, allowing for a reduced size of the chip, as well as reduced chip costs resulting from the reduced size.

[0148] In this embodiment, the differences between the first embodiment and this embodiment are described, while the description of the same or corresponding components is omitted. Third embodiment configuration

[0149] Fig. Figure 15 is a schematic top view to describe the structure of a part adjacent to the gate electrode 82, the termination of the active region, and Fig. 15 corresponds to position aa' in Fig. 4. Fig.Figure 15 shows only the semiconductor area, without showing the electrode, insulating layer, or the like. Fig. Figure 16 is a schematic top view to describe the structure of a part that does not contain the gate electrode 82 and is adjacent to the termination of the chip, the termination of the active area, and Fig. 16 corresponds to position bb' in Fig. 4. Fig. Figure 16 shows only the semiconductor area, without showing the electrode, insulating layer, or the like.

[0150] In Fig. 15 and Fig.16 The third separation region 23c is the partially missing portion of the wide basin region 31c, located in a region around the first basin contact region 35 within the wide basin region 31c, the region comprising an area between each of the basin regions 30 in the outermost peripheral unit cells and the first basin contact region 35 within the wide basin region 31c. The third separation region 23c does not completely surround the first basin contact region 35. Although not shown specifically, the Schottky electrode 75 is formed on the surface of the third separation region 23c to allow the passage of the unipolar current during reverse flow operation.

[0151] Consequently, during reverse flow, the unipolar current flows through the drift layer 20 around the first well contact area 35 in the wide well area 31c, causing the voltage drop. This leads to the reduced voltage applied to the pn junction around the first well contact area 35 in the wide well area 31c, and consequently, the decrease in the operating voltage of the pn diode can be prevented.

[0152] The third separation area 23c does not completely surround the first basin contact area 35 in the wide basin area 31c, so that a path can be maintained through which a displacement current flows even in the case where a high dV / dt is applied, for example during a switching operation.

[0153] As long as the third separation area 23c does not completely surround the first trough contact area 35 in the wide trough area 31c, a plurality of third separation areas 23d can be discretely formed, or the third separation areas 23d that are adjacent to each other can be connected to each other, as in Fig. 17 shown. Effects

[0154] The effects of this embodiment are described below.

[0155] According to this embodiment, the third separation area 23c surrounds the ohmic electrode 70, which serves as the second ohmic electrode in the top view, and at least part of the area surrounding the ohmic electrode 70 is missing.

[0156] Such a configuration allows the unipolar current to flow through the drift layer 20 around the first well contact area 35 in the wide well area 31c (located below the ohmic electrode 70) during reverse flow operation, causing the voltage drop. This results in the reduced voltage applied to the pn junction around the first well contact area 35 in the wide well area 31c, and consequently, the decrease in the operating voltage of the pn diode can be prevented.

[0157] As a result, conductivity modulation due to the bipolar current flowing from the pn diode in the wide well region 31c to the drift layer 20 immediately below the well regions 30 in the unit cells is prevented, and the voltage drop occurring in the drift layer 20 immediately below the well regions 30 in the unit cells can be sufficiently maintained to prevent the decrease in the operating voltage of the pn diode in the well regions 30 in the unit cells.

[0158] For this reason, a larger current value can be made to flow back into the Schottky junction diode in order to increase the return current, which flows as a unipolar current through the entire chip, allowing for a reduced size of the chip.

[0159] The third separation area 23c does not completely surround the first basin contact area 35 in the wide basin area 31c, so that a path can be maintained through which a displacement current flows even in the case where a high dV / dt is applied, for example, during the switching process.

[0160] In this embodiment, the differences between the first embodiment and this embodiment are described, while the description of the same or corresponding components is omitted. Fourth embodiment configuration

[0161] The Fig. Figure 18A is a schematic cross-sectional view to describe the structure of a part adjacent to the gate electrode 82, namely the termination of the active region, and the Fig. 18A corresponds to position aa' in Fig. 4. The Fig. 18B is a schematic top view of the area according to Fig.18A, and it only shows the semiconductor area, without showing the electrode, the insulating layer, and the like.

[0162] The Fig. Figure 19A is a schematic cross-sectional view to describe the structure of a region that does not contain the gate electrode 82 and is adjacent to the termination of the chip, namely the termination of the active region, and Fig. 19A corresponds to position bb' in Fig. 4. The Fig. Figure 19B is a schematic top view of the area according to Fig. 19A, and it only shows the semiconductor area, without showing the electrode, the insulating layer, and the like.

[0163] In Fig. 18 and Fig.19 The third separation region 23 is a partially missing part of a wide trough region 31f, which is formed between each of the trough regions 30 in the outermost peripheral unit cells and a first contact trough region 35f in the wide trough region 31f. The Schottky electrode 75 is formed on the surface of the third separation region 23 to allow the passage of the unipolar current during reverse flow operation.

[0164] A fourth separation region 24 is formed in the first trough contact region 35f within the wide trough region 31f. Furthermore, the Schottky electrode 75, which contacts at least part of the area of ​​the fourth separation region 24, and the ohmic electrode 70, which is in contact with at least part of the area of ​​the first trough contact region 35f, are formed. The Schottky electrode 75 and the ohmic electrode 70 contact the source electrode 80 through the trough contact hole 91.

[0165] In the manufacturing process, which is almost the same as in the first embodiment, only the implantation positions of the wide basin area 31f and the first basin contact area 35f need to be modified, and the mask layout for arranging the ohmic electrode 70 and the Schottky electrode 75 at the desired positions needs to be modified. Effects

[0166] The effects of this embodiment are described below.

[0167] According to this embodiment, the semiconductor device has the fourth separation area 24 and the Schottky electrode 75, which serves as a third Schottky electrode.

[0168] The fourth separation region 24 is a first-type conductivity region configured to penetrate the wide trough region 31f, which serves as a second trough region, from the surface layer of the wide trough region 31f in the depth direction. The Schottky electrode 75 is an electrode located on the fourth separation region 24.

[0169] The ohmic electrode 70, which serves as a second ohmic electrode, is located above the wide basin area 31f.

[0170] Such a configuration allows the MOSFET with the built-in Schottky junction diode to contain the wide well region 31f and the Schottky junction diode, which is located closer to the unit cell region than the first well contact region 35f in the wide well region 31f, and which is positioned in the partially missing part of the wide well region 31f such that it surrounds the active region.

[0171] Such a configuration allows the MOSFET with the integrated Schottky junction diode to have the Schottky junction diode located in the first well contact area 35f within the wide well area 31f. The unipolar current therefore flows through the Schottky junction diode located in the first well contact area 35f within the wide well area 31f until the pn diode in the wide well area 31f is operational.

[0172] Therefore, during reverse flow, the unipolar current flows through the drift layer 20 immediately below the first cup contact region 35f in the wide cup region 31f, causing the voltage drop. This leads to the reduced voltage applied to the pn junction around the first cup contact region 35f in the wide cup region 31f, and consequently, the decrease in the operating voltage of the pn diode in the wide cup region 31f can be prevented.

[0173] As a result, conductivity modulation due to the bipolar current flowing from the pn diode in the wide well region 31f to the drift layer 20 immediately below the well regions 30 in the unit cells is prevented, and the voltage drop occurring in the drift layer 20 immediately below the well regions 30 in the unit cells can be sufficiently maintained to prevent the decrease in the operating voltage of the pn diode in the well regions 30 in the unit cells.

[0174] For this reason, a larger current value can be made to flow back into the Schottky junction diode in order to increase the return current, which flows as a unipolar current through the entire chip, allowing for a reduced size of the chip.

[0175] In this embodiment, the differences between the first embodiment and this embodiment are described, while the description of the same or corresponding components is omitted. Fifth embodiment configuration

[0176] In this embodiment, a MOSFET with a built-in Schottky junction diode, which has a built-in current sensor, is described as an example.

[0177] First, the structure and functions of the current sensor are described. Fig. Figure 20 is a diagram viewed from above the MOSFET with the integrated Schottky junction diode on which the integrated current sensor is mounted, or viewed from the side of the first main surface. Fig. Figure 20 shows the top-view position of the active area with dashed lines.

[0178] In the MOSFET with the integrated Schottky junction diode, which includes the current sensor, a sensor electrode 81, separated from a source electrode 80a in the top view, is formed on the first main surface. The active region, which includes the unit cells arranged in the same layout as those in the part of the source electrode 80a, is formed in the part of the sensor electrode 81.

[0179] It is assumed that the source electrode 80 is replaced by the sensor electrode 81 in the cross-sectional view of the unit cell, which is the same as the unit cell located below the source electrode 80, which is in Fig. Figure 2 shows the sensor electrode 81 covering the Schottky electrode 75, which is formed on the first separation region 22, and the ohmic electrode 70, which is formed in the wide trough region and the source region.

[0180] The unit cells located in the active region below the source electrode 80a are referred to as main cells, while the unit cells located in the active region below the sensor electrode 81 are referred to as sensor cells. The gate electrode 60 and the drain electrode 85 in the main cell are electrically short-circuited with a corresponding electrode in the sensor cell and are at the same potential. The sensor electrode 81 also operates at essentially 0 volts, which is nearly the same voltage that operates the source electrode 80a.

[0181] It is therefore conceivable that the same current always flows through the one master cell and the one sensor cell. The number of sensor cells is significantly lower than the number of master cells, for example, one ten-thousandth. The current flowing through the small number of unit cells is measured by a shunt resistor or similar device, and the current value is multiplied by the ratio of the number of cells so that the current flowing through the source electrode can be estimated.

[0182] In particular, if an excessive current flows through the element when it is switched on, a switch-off signal is provided for the gate electrode 82 upon detection of the overcurrent, in order to prevent thermal damage to the element. This is the advantage of incorporating the current sensor.

[0183] Fig.Figure 21 is a schematic cross-sectional view of an area from one end area of ​​the main cell arrangement to one end area of ​​the sensor cell arrangement. Fig. Figure 22 is a schematic cross-sectional view of the area without the use of the present invention. Both are schematic cross-sectional views relating to the area cc' in Fig. 20 corresponds.

[0184] A sandwich-like area between the two active areas has a gate electrode that connects the two active areas to the gate insulating layer 50 or the field insulating layer 52 below the gate electrode. As described above, the structure according to this embodiment prevents the application of a high electric field to the gate insulating layer 50 and the field insulating layer 52 in the off state.

[0185] In this embodiment, the main cells and the sensor cells are separated by the wide basin area 31, and the third separation area 23 is formed as the partially missing part of the wide basin area 31 near the sensor cells. Viewed from above, the wide basin area 31 is formed on both sides of the entirety of sensor cells, which correspond to some of the majority of basin areas 30, in the surface layer of the drift layer 20.

[0186] The wide basin area 31 is formed on both sides of the entire array of sensor cells when viewed from above, in order to separate the sensor cells from the other basin areas 30. The third separation area 23 is formed closer to the sensor cells than the ohmic electrode 70 in the wide basin area 31. The Schottky electrode 75 is configured such that at least a portion of the Schottky electrode 75 contacts the third separation area 23.

[0187] The Schottky electrode 75 is connected to the sensor electrode 81 through the Schottky junction diode contact hole 92, which penetrates the intermediate insulating layer 55 and the gate insulating layer 50. In the Fig. In the structure shown in Figure 22, the wide basin area 31a has no missing part and no Schottky junction diode contact hole 92, so that an intermediate insulating layer 55a and a gate electrode 60a are formed in the areas described above.

[0188] In the manufacturing process, which is almost identical to that of the first embodiment, only each mask layout needs to be modified. The sensor electrode 81 can be formed simultaneously with the source electrode 80a and the gate electrode 82; that is, the sensor electrode 81 can be formed by first depositing a metal material, then applying a pattern using a photoresist, and finally etching it.

[0189] In the case where the distance between the well area 30 and the Schottky electrode 75, which is formed in the wide well area 31, is less than or equal to 3 µm, a similar procedure can be used as in the one described in Fig. In the case shown in Figure 12, the drop in the rising voltage of the pn diode in the trough area 30 is prevented.

[0190] Similar to the one in Fig. 13 and Fig.In the case shown in Figure 14, the third separation area can be formed continuously in the direction that intersects the direction from the wide tub area towards the sensor area in the top view. Effects

[0191] The effects of this embodiment are described below.

[0192] According to this embodiment, the semiconductor device has the sensor area (the sensor cell) and the sensor electrode 81.

[0193] The sensor cell is an area that has at least one basin area 30 of the majority of basin areas 30 and that is separated from another basin area 30 of the basin areas 30 by means of the wide basin area that is formed on both sides of the sensor cell when viewed from above.

[0194] The sensor electrode 81 is arranged such that it covers the Schottky electrode 75, which serves as a first Schottky electrode formed on the first separation region 22 in the sensor cell, and that it covers the ohmic electrode 70, which serves as a first ohmic electrode formed on the sensor cell and the source region 40. The sensor electrode 81 is a separate electrode from the source electrode 80.

[0195] Such a configuration allows the Schottky junction diode, located between the sensor cell and the ohmic electrode in the wide basin area, to cause the voltage drop even in the drift layer immediately below the sensor cell, and consequently the operation of the pn diode in the sensor cell can be prevented.

[0196] This effect is achieved by forming the Schottky junction diode in the partially missing part of the wide trough area 31 near the sensor cell and by connecting the Schottky electrode 75 to the sensor electrode 81 instead of the source electrode 80 in order to position the Schottky junction diode closer to the sensor cell.

[0197] It can be stated that it is effective to arrange the Schottky junction diode at the position closer to the sensor cell, which follows from the mechanism by which the forward voltage applied to the pn diode near the Schottky junction diode is reduced by the unipolar current caused by the Schottky junction diode, which is located in part of the wide trough area 31, and which causes the voltage drop immediately below the Schottky junction diode in the drift layer 20 and the substrate 10 near the part immediately below the Schottky junction diode, as described above.

[0198] The occurrence of crystal defects in the sensor cell is particularly damaging compared to the occurrence of crystal defects in the main cell. This is because the number of cells for the current sensor is significantly lower than the number of main cells, and the resistance changes more dramatically across the entire active area of ​​the current sensor, even when crystal defects occur in the same area. The current flowing through the source electrode 80 cannot be accurately measured due to the change in resistance within the current sensor, and an excessive current flow prevents a correct turn-off signal from being transmitted to the gate electrode 60. This increases the risk of element failure.

[0199] This embodiment can specify the semiconductor device with higher reliability, which prevents a change in the on-state resistance in the sensor cell.

[0200] The above explanations describe the reduced occurrence of crystal defects in the sensor cell. Furthermore, the reduced occurrence of crystal defects is also important for the main cell.

[0201] Fig. 23 is a schematic cross-sectional view corresponding to the area of ​​cc' in the Fig. 20 corresponds to. As in Fig. As shown in Figure 23, it is also effective that the Schottky junction diodes, which are formed in the wide basin area 31 near the main cell and the sensor cell, are each connected to the source electrode 80 and the sensor electrode 81, respectively.

[0202] The current flowing through the sensor cells is typically small and has a low capacitance, so the sensor cells are more likely to be destroyed than the main cells, due to electrostatic effects or similar causes. For this reason, the structure can incorporate a larger number of unit cells for higher capacitance, and it can include the trough region 30 instead of the second separation region 21 in at least one of the sensor cells to reduce the current to a desired value, or it can omit the source region 40 in at least one of the sensor cells. Even in these cases, the unit cell can incorporate the Schottky junction diode in the third separation region 23.

[0203] In this embodiment, the differences between the first embodiment and this embodiment are explained, while the re-description of the same or corresponding components is omitted. Modifications

[0204] The embodiments described above use nitrogen as an n-type (first conductivity type) impurity, which can be a phosphorus compound or an arsenic compound.

[0205] The embodiments described above use aluminum as a p-type (second conductivity type) defect, which can be a boron compound or gallium.

[0206] In the embodiments described above, the description is given with specific examples of, for example, the crystal structure, the plane direction of the main surface, the angle of deviation and the respective implantation condition, but the applicability is not limited to a range of these numerical values.

[0207] The embodiments described above illustrate that the silicon carbide semiconductor element is particularly effective, but the other large bandgap semiconductor elements are also effective, and silicon semiconductor elements also have a certain degree of efficiency.

[0208] In the embodiments described above, the first tub contact area 35 is formed in the area that is in contact with the ohmic electrode 70 in the wide tub area 31, but the first tub contact area 35 can also not be formed in that area.

[0209] The embodiments described above describe the case in which the n-channel MOSFET is used, but a p-channel MOSFET can also be used, in which the first conductivity type is the p-type and the second conductivity type is the n-type.

[0210] The present invention is also applicable to MOSFETs with a superjunction structure.

[0211] The embodiments described above use silicon carbide for the gate insulating layer, which can be a deposition layer using a CVD process.

[0212] The embodiments described above illustrate a so-called vertical MOSFET which includes the drain electrode 85 formed on the back surface of the substrate 10, but the embodiments are also applicable to a so-called lateral MOSFET, such as a RESURF MOSFET which has a drain electrode 85 formed on the front surface of the drift layer 20.

[0213] The embodiments described above illustrate a MOSFET having a gate insulating layer 50, but the present invention is also applicable to a unipolar device, such as a junction field-effect transistor (JFET) and a metal-semiconductor field-effect transistor (MESFET), which do not include such a gate insulating layer 50.

[0214] In the embodiments described above, the ohmic electrode 70 on the source side and the Schottky electrode 75 are manufactured separately, but they can also be formed entirely from the same material or from different materials.

[0215] The embodiments described above refer to the example of a unit structure that has the shape of a square cell, as in e.g. Fig.2 described, but the unit structure can also have a hexagonal shape, and it can also have a striped shape, so that the sectional structure according to Fig. 1 continues, for example, in the direction of depth.

[0216] The semiconductor device described in the above embodiments can be used, for example, for electrical power, electric railways, automobiles, household electrical applications, solar cells and communication.

[0217] The materials, dimensions, sizes, and relative positions of the respective structural components and the execution conditions described in the embodiments described above are intended to be illustrative and non-limiting in every respect. It is therefore understood that numerous modifications and variations can be conceived without deviating from the scope of the invention. For example, a freely chosen structural component can be modified, added, or omitted, and furthermore, at least one structural component can be extracted from at least one embodiment and combined with a structural component from another embodiment.

[0218] A structural component, referred to as "a" structural component in the respective embodiment described above, may also comprise "one or more" structural components, as long as this is not inconsistent with the concept according to the invention. Furthermore, the structural components that constitute the invention are conceptual units, such that a structural component may have a plurality of structures and may correspond to a part of a structure. The respective structural component of the present invention may have a structure that has another structure or shape, as long as the same functions are achieved.

[0219] Based on the entirety of the explanations, which are references for all purposes of the present invention, it is expressly denied in the present application that the present invention is a conventional technology.

[0220] The preferred aspects of the present invention can be summarized as follows: Aspect 1. Semiconductor device comprising: a drift layer (20) of a first conductivity type formed on a semiconductor substrate (10) of the first conductivity type; a plurality of first well regions (30) of a second conductivity type located at a distance in an area layer of the drift layer (20); a second well region (31, 31b, 31f) of the second conductivity type formed in plan view on both sides of the entirety of the plurality of first well regions (30) in the area layer of the drift layer (20), wherein the second well region (31, 31b, 31f) has a formation area larger than that of the first well regions (30); a first separation region (22) of the first conductivity type formed such that it separates each of the first well regions (30) from an area layer of each of the first well regions. (30) penetrates in a depth direction;a source region (40) of the first conductivity type, which in plan view is formed on both sides of the first separation region (22) in the surface layer of each of the first trough regions (30); a first Schottky electrode (75) located on the first separation region (22); a first ohmic electrode (70) located above each of the first trough regions (30) and located on the source region (40), while in contact with each of the first trough regions (30) and the source region (40); a second separation region (21) of the first conductivity type, which is a region for separating the first trough regions (30); from each other; a second ohmic electrode (70) located above the second well region (31, 31b, 31f); a third separation region (23, 23b, 23c) of the first conductivity type, which is arranged closer to the first well regions (30) than the second ohmic electrode (70) in the second well region (31, 31b, 31f) and which is configured to penetrate the second well region (31, 31b, 31f) in the depth direction starting from a surface layer of the second well region (31, 31b, 31f); a second Schottky electrode (75) located on the third separation region (23, 23b, 23c); a gate electrode (60) extending through a first insulating layer (50) over a part of the first and second tub areas (30, 31, 31b, 31f), with the exception of positions where the first and second Schottky electrodes (75) and the first and second ohmic electrodes (70) are located;a second insulating layer (55) configured to cover the gate electrode (60); and a source electrode (80) configured to cover the first and second Schottky electrodes (75), the first and second ohmic electrodes (70) and the second insulating layer (55). Aspect 2. Semiconductor device according to aspect 1, wherein the distance between the second Schottky electrode (75) and each of the first well areas (30) is less than or equal to 3 µm. Aspect 3. Semiconductor device according to aspect 1 or 2, wherein the third separation region (23b) is continuous in a The direction is formed which intersects the direction starting from the second tub area (31b) in the direction of the first tub areas (30) in the top view. Aspect 4. Semiconductor device according to aspect 1 or 2, wherein the third separation region (23c) surrounds the second ohmic electrode (70) in the top view, and wherein at least part of the region surrounding the ohmic electrode (70) is missing. Aspect 5. Semiconductor device according to aspect 1 or 2, further comprising: a fourth separation region (24) of the first conductivity type, configured to penetrate the second well region (31f) from a surface layer of the second well region (31f) in the depth direction; and a third Schottky electrode (75) located on the fourth separation region (24), wherein the second ohmic electrode (70) is located above the second well region (31f). Aspect 6. Semiconductor device according to aspect 1 or 2, wherein the drift layer (20) comprises silicon carbide. Aspect 7. Semiconductor device comprising: a drift layer (20) of a first conductivity type formed on a semiconductor substrate (10) of the first conductivity type; a plurality of first trough regions (30) of a second conductivity type located at a distance in an area layer of the drift layer (20); a second trough region (31, 31b) of the second Conductivity type formed in plan view on both sides of some of the majority of first trough areas (30) in the surface layer of the drift layer (20), wherein the second trough area (31, 31b) has a formation area larger than that of the first trough areas (30); a sensor area comprising at least one first trough area (30) of the majority of first trough areas (30) and separated from another first trough area (30) of the first trough areas (30) by means of the second trough area (31, 31b) formed in plan view on both sides of the sensor area; a first separation area (22) of the first conductivity type formed such that it penetrates each of the first trough areas (30) at least in the sensor area starting from a surface layer of each of the first trough areas (30) in a depth direction;a source region (40) of the first conductivity type, which in plan view is formed on both sides of the first separation region (22) in the surface layer of each of the first trough regions (30), at least in the sensor region; a first Schottky electrode (75) located on the first separation region (22); a first ohmic electrode (70) located above each of the first trough regions (30) and located on the source region (40), at least in the sensor region; a second separation region (21) of the first conductivity type, which is a region for separating the first trough regions (30) from each other; a second ohmic electrode (70) located above the second trough region (31, 31b); a third separation region (23, 23b) from the first; a conductivity type that is arranged closer to the sensor area than the second ohmic electrode (70) in the second well area (31, 31b) and that is configured to penetrate the second well area (31, 31b) in the depth direction starting from a surface layer of the second well area (31, 31b); a second Schottky electrode (75) located on the third separation area (23, 23b); a gate electrode (60) that extends through a first insulating layer (50) over a portion of the first and second well areas (30, 31, 31b), except for positions where the first and second Schottky electrodes (75) and the first and second ohmic electrodes (70) are located; a second insulating layer (55) configured to cover the gate electrode (60); and a sensor electrode (81) arranged so that it covers the first Schottky electrode (75) and the first ohmic electrode (70). Aspect 8. Semiconductor device according to aspect 7, wherein the distance between the second Schottky electrode (75) and each of the first well areas (30) is less than or equal to 3 µm. Aspect 9. Semiconductor device according to aspect 7 or 8, wherein the third separation area (23b) is formed continuously in the direction which intersects a direction starting from the second trough area (31b) in the direction of the sensor area in the top view. Aspect 10. Semiconductor device according to aspect 7 or 8, wherein the sensor area has the majority of first basin areas (30), and wherein the source area (40) is not formed in at least one first basin area (30) of the first basin areas (30) in the sensor area. Aspect 11. Semiconductor device according to aspect 7 or 8, wherein the sensor area has the majority of first basin areas (30), and the second separation area (21) is not formed between a part of the sensor area and another first basin area (30) of the first basin areas (30). Aspect 12. Semiconductor device according to aspect 7 or 8, wherein the drift layer (20) comprises silicon carbide. Description of reference symbols 10 substrate 20 Drift layer 21 second separation area 22 first separation area 23, 23b third separation area 23c, 23d third separation area 24 fourth separation area 30 Bathtub area 31, 31a, 31b third separation area 31c, 31f wide tub area 35, 35f first tub contact area 37 JTE range 40 Source area 50 Gate insulating layer 52-field insulating layer 55, 55a Intermediate layer insulating layer 60, 60a, 82 Gate electrode 70 ohmic electrode 71 ohmic electrode on the back 75 Schottky electrode 80, 80a Source electrode 81 Sensor electrode 85 Drain electrode 91 Tub contact hole 92 Schottky junction diode contact holes 95 Gate contact hole

Claims

Semiconductor device comprising: - a drift layer (20) of a first conductivity type formed on a semiconductor substrate (10) of the first conductivity type; - a plurality of first well regions (30) of a second conductivity type, spaced apart in an area layer of the drift layer (20); - a second well region (31, 31b, 31f) of the second conductivity type, formed in plan view on both sides of the entirety of the plurality of first well regions (30) in the area layer of the drift layer (20), wherein the second well region (31, 31b, 31f) has a formation area larger than that of the first well regions (30); - a first separation region (22) of the first conductivity type, formed such that it separates each of the first well regions (30) from an area layer of each of the first well regions (30) in a depth direction penetrates;- a first conductivity type source region (40) formed in plan view on both sides of the first separation region (22) in the surface layer of each of the first trough regions (30); - a first Schottky electrode (75) located on the first separation region (22); - a first ohmic electrode (70) located above each of the first trough regions (30) and arranged on the source region (40), while in contact with each of the first trough regions (30) and the source region (40); - a second conductivity type first separation region (21) forming a region for separating the first trough regions (30) from each other; - a second ohmic electrode (70) located above the second trough region (31, 31b, 31f);- a third separation region (23, 23b, 23c) of the first conductivity type, configured to penetrate the second trough region (31, 31b, 31f) from a surface layer of the second trough region (31, 31b, 31f) in the depth direction, so that it surrounds the first trough regions (30) by extending in a direction that intersects a direction from the second trough region (31, 31b, 31f) to the first trough regions (30) in plan view; - a second Schottky electrode (75) located on the third separation region (23, 23b, 23c); - a gate electrode (60) located through a first insulating layer (50) over a portion of the first and second trough regions (30, 31, 31b, 31f), except at positions where the first and the second Schottky electrode (75) and the first and second ohmic electrodes (70); - a second insulating layer (55) designed to cover the gate electrode (60);and a source electrode (80) arranged to cover the first and second Schottky electrodes (75), the first and second ohmic electrodes (70) and the second insulating layer (55). Semiconductor device according to claim 1, wherein in the third separation area (23c) at least one area surrounding the first trough areas (30) is missing in the top view. Semiconductor device according to claim 1 or 2, wherein a current flowing through the second Schottky electrode (75) during a reverse flow operation is greater than a current flowing through the first Schottky electrode (75). Semiconductor device according to one of claims 1 to 3, further comprising: - a fourth separation region (24) of the first conductivity type, which is configured to penetrate the second well region (31f) from a surface layer of the second well region (31f) in the depth direction; and - a third Schottky electrode (75) located on the fourth separation region (24), - wherein the second ohmic electrode (70) is located on the second well region (31f). Semiconductor device according to one of claims 1 to 4, wherein the drift layer (20) comprises silicon carbide.

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