USE OF A SILICON CARBIDE IN CRYSTAL WAFER FOR THE CONSTRUCTION OF AN ELECTRONIC DEVICE

Abstract

Use of a silicon carbide crystal wafer (101) for the fabrication of an electronic device, wherein the silicon carbide crystal wafer (101) comprises thread dislocations (20), each of which has a dislocation line (21) extending through a C-plane, and a Burgers vector (bv) that contains at least one component in a C-axis direction, characterized by the fact that After producing silicon carbide crystal wafers, a silicon carbide crystal wafer (101) is selectively selected and used, in which the density of thread dislocations with angles (θ1), each of which is formed by an orientation of the Burgers vector and an orientation of the dislocation line that are greater than 0° and within 40°, to 300 dislocations / cm 2 or less fixed, and The density of thread dislocations where the angles are greater than 40° is reduced to 30 dislocations / cm². 2 or is less fixed.

Description

CROSS-REFERENCE TO RELATED REGISTRATION

[0001] This application is based on the Japanese patent application JP 2015 - 170 814 A, filed on August 31, 2015. TECHNICAL AREA

[0002] The present disclosure relates to the use of a silicon carbide crystal wafer for the manufacture of an electronic device (silicon carbide hereinafter referred to as SiC). STATE OF THE ART

[0003] JP 2014-159 351 A describes a high-quality SiC single crystal. For the SiC single crystal in JP 2014-159 351 A, it is required that spiral dislocations be classified into large-distortion and small-distortion dislocations based solely on a Burgers vector, and that it exhibits a low density of large-distortion dislocations.

[0004] In DE 10 2010 001 720 A1, a single-crystal SiC substrate, a SiC wafer and a SiC semiconductor device are described with a penetration dislocation having a dislocation line that penetrates a c-surface of a (0001) plane, wherein the angle between the dislocation line and the c-axis of the (0001) orientation is less than or equal to 22.5 degrees. SUMMARY OF THE INVENTION

[0005] According to an investigation by the inventors of the present invention into the relationship between the properties of devices or components and threading dislocations, threading dislocations present in a SiC single crystal include dislocations with a large angle between the orientation of a Burgers vector and the orientation of a dislocation line. The inventors of the present invention found that the existence of a large number of dislocations with such a large angle in the SiC single crystal would lead to a significant deterioration of the device's properties.

[0006] One objective of the present disclosure is to provide a method for manufacturing an electronic device with improved device characteristics.

[0007] The problem was solved by using a silicon carbide crystal wafer to manufacture an electronic device according to claim 1.

[0008] The silicon carbide crystal wafer used according to the present invention comprises thread dislocations, each of which has a dislocation line extending through a C-plane and a Burgers vector containing at least one component in a C-axis direction. Additionally, the density of thread dislocations with angles, each formed by an orientation of the Burgers vector and an orientation of the dislocation line greater than 0° and within 40°, is 300 dislocations / cm². 2 or less specified. Furthermore, the density of thread dislocations where the angles are greater than 40° is 30 dislocations / cm². 2 or less fixed.

[0009] The device properties can be improved by fabricating an electronic device using a silicon carbide crystal wafer with a low density of threaded dislocations exhibiting large distortion. Accordingly, a high-quality silicon carbide crystal wafer can be provided.

[0010] According to a preferred embodiment of the present invention, the silicon carbide crystal wafer is a silicon carbide crystal epitaxial wafer comprising: a silicon carbide crystal substrate and an epitaxial growth layer arranged on the silicon carbide crystal substrate. Additionally, both the silicon carbide crystal substrate and the epitaxial growth layer comprise thread dislocations, and each of the thread dislocations has a dislocation line extending through a C-plane and a Burgers vector containing at least one component in a C-axis direction. Furthermore, the density of thread dislocations with angles, each formed by an orientation of the Burgers vector and an orientation of the dislocation line greater than 0° and within 40°, is 300 dislocations / cm². 2or less specified, and the density of thread dislocations where the angles are greater than 40° is 30 dislocations / cm². 2 or less fixed.

[0011] The device properties can be improved by fabricating an electronic device using a silicon carbideine crystal epiaxial wafer with a low density of threaded dislocations exhibiting large distortion. Accordingly, a high-quality silicon carbideine crystal epiaxial wafer can be provided.

[0012] In the invention, the use of a silicon carbide crystal wafer for the fabrication of an electronic device comprises a silicon carbide crystal substrate with dislocations. Each of the thread dislocations has a dislocation line extending through a C-plane and a Burgers vector containing at least one component in a C-axis direction. The method is characterized in that a silicon carbide crystal substrate is used in which the density of thread dislocations of the silicon carbide crystal substrate with angles, each formed by an orientation of the Burgers vector and an orientation of the dislocation line greater than 0° and within 40°, is 300 dislocations / cm². 2 or less is specified, and the density of thread dislocations of the silicon carbide crystal substrate, where the angles are greater than 40°, is set to 30 dislocations / cm². 2or is less fixed.

[0013] According to a preferred embodiment, an epitaxial growth layer is arranged on the silicon carbide crystal substrate. Additionally, both the silicon carbide crystal substrate and the epitaxial growth layer comprise thread dislocations, and each thread dislocation has a dislocation line extending through a C-plane and a Burgers vector containing at least one component in a C-axis direction. Furthermore, the density of thread dislocations with angles, each formed by an orientation of the Burgers vector and an orientation of the dislocation line greater than 0° and within 40°, is 300 dislocations / cm². 2 or less specified, and the density of thread dislocations where the angles are greater than 40° is 30 dislocations / cm². 2 or less fixed.

[0014] Since the electronic device obtained by the use according to the invention contains the silicon carbide crystal substrate or each of the silicon carbide crystal substrate and the epitaxial growth layer with a low density of thread dislocations with large distortion, the device properties can be improved compared to a case with a high density of thread dislocations with large distortion. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and other tasks, features, and advantages of the present disclosure will become clearer from the following detailed description with reference to the accompanying drawings. The drawings show: Fig. 1 a cross-sectional view of a SiC single crystal epiaxial wafer in a first embodiment; Fig. 2 a cross-sectional view of a MOS capacitor in the first embodiment; Fig. 3 a schematic view illustrating a thread offset; Fig. 4 a graph showing a relationship between an angle between a Burgers vector and a dislocation line of a thread dislocation and the lifetime of a MOS capacitor; and Fig. 5 a cross-sectional view of a SiC single crystal wafer in another embodiment. EXECUTIONAL FORMS FOR IMPLEMENTING THE INVENTION

[0016] The following describes embodiments of the present disclosure with reference to the drawings. In the following embodiments, identical or related elements may be designated by the same reference numerals. Originally, a dash (-) was to be placed above a desired number to indicate the crystal orientation; however, since the representation is limited by electronic applications, the dash is placed before the desired number in the present description. First embodiment

[0017] The present embodiment describes a SiC single-crystal epiaxial wafer and a MOS capacitor manufactured using the SiC single-crystal epiaxial wafer.

[0018] As in Fig. As shown in Figure 1, a SiC single-crystal epitaxial wafer 1 comprises a SiC single-crystal substrate 2 and a SiC epitaxial growth layer 3 formed by epitaxial growth on a surface of the SiC single-crystal substrate 2. Hereinafter, the SiC single-crystal epitaxial wafer 1 can also be referred to as a wafer 1, the SiC single-crystal substrate 2 can also be referred to as a single-crystal substrate 2, and the SiC epitaxial growth layer 3 can also be referred to as an epilayer 3. The SiC single crystal forming the single-crystal substrate 2 and the epilayer 3 exhibits a polymorphism of 4H. An off-angle on a surface 1a of the wafer 1 (i.e., a surface 3a of the epilayer 3) is approximately 4° in a <11-20> direction with respect to a {0001} plane. Epilayer 3 exhibits n-type conductivity. The SiC single crystal may exhibit a different polymorphism such as 6H or 3C.The offset angle on surface 1a of wafer 1 can be set within 10° in the <11-20> direction with respect to the {0001} plane.

[0019] The wafer 1 to be used can have a diameter of 100 mm or more, or approximately 150 mm or more. The wafer 1 preferably has a micropipe density of less than 1 / cm². 2 , a threading edge dislocation density of less than 3000 / cm² 2 , a stacking defect density of less than 0.1 / cm² 2 and an inclusion density of less than 1 / cm³ 3 on.

[0020] As in Fig. Figure 2 shows a MOS capacitor 10 formed from an electronic device having a MOS structure. The MOS capacitor 10 comprises a single-crystal substrate 2, an n-type drift layer epilayer 3 formed on a front side of the SiC single-crystal substrate 2, an oxide film 4 formed on a surface 3a of the epilayer 3, a first electrode 5 formed on a surface of the oxide film 4, and a second electrode 6 formed on a back side of the SiC single-crystal substrate 2.

[0021] The MOS capacitor 10 is produced by forming the oxide film 4 on the surface 1a of the in Fig. The wafer 1 shown in Figure 1 is used to form the first electrode 5 on the surface of the oxide film 4, the second electrode 6 is formed on the back side of the single-crystal substrate 2, and the wafer 1 is cut into a desired size. The single-crystal substrate 2 and the epilayer 3 of the wafer 1 correspond to the single-crystal substrate 2 and the epilayer 3 of the MOS capacitor 10. Thus, the "substrate" in this description can refer to its state before and after the wafer is cut. The single-crystal substrate 2 and the epilayer 3 of the wafer 1, as well as the single-crystal substrate 2 and the epilayer 3 of the MOS capacitor 10 in this embodiment, each correspond to the specifications of the present invention for the thread dislocations.

[0022] As in the Fig. 1 and Fig. As shown in Figure 2, a threaded dislocation 20 exists in the single-crystal substrates 2 and the epilayers 3 of the wafer 1 and the MOS capacitor 10. The threaded dislocation 20 is a crystal defect in which atomic planes are arranged helically around a dislocation line 21. The threaded dislocation 20 has a dislocation line 21 that extends through a C-plane of the SiC single crystal and a Burgers vector that contains at least one component in a C-axis direction.

[0023] Here, the C-plane is a {0001}-plane, and the C-axis is a <0001> -axis. The Burgers vector containing at least one component in a C-axis direction represents a case where the Burgers vector contains only the component in the C-axis direction, and a case where the Burgers vector contains the component in the C-axis direction and components in other axis directions. Examples of the case where the Burgers vector contains the component in the C-axis direction and components in other axis directions include bv = a + c, bv = m + c, and bv = 2a + c. In these equations, "bv" represents a Burgers vector, "a" represents a vector in a 1 / 3 <11-20> direction, and "c" represents a vector in a <0001> -direction and represents “m” as a vector in a <1-100> direction.

[0024] As in Fig. As shown in Figure 3, the orientation of the Burgers vector bv is also shifted relative to the orientation of the dislocation line 21 in the thread dislocation 20. A larger angle θ1 between the orientation of the Burgers vector bv and the orientation of the dislocation line 21 causes a greater distortion. The angle θ1 can be greater than 0° and less than 90° (0° < θ1 < 90°).

[0025] In the present embodiment, the single-crystal substrate 2 and the epilayer 3 have a density of thread dislocations 20, the angles θ1 of which lie between the orientation of the Burgers vector bv and the orientation of the dislocation line are greater than 0° and within 40° (0° < θ1 ≤ 40°), wherein the density is 300 dislocations / cm². 2 or less defined, and exhibit a density of thread dislocations 20 whose angles θ1 are greater than 40° (θ1 > 40°), where the density is 30 dislocations / cm 2or less defined. Preferably, the single-crystal substrate 2 and the epilayer 3 have a density of thread dislocations 20 whose angles θ1 lie within 20° (0° < θ1 ≤ 20°), wherein the density is based on 300 dislocations / cm³. 2 or less specified, and exhibit a density of thread dislocations 20 whose angles θ1 are greater than 20° (θ1 > 20°), where the density is 30 dislocations / cm 2 or less defined. Furthermore preferably, the single-crystal substrate 2 and the epilayer 3 have a density of thread dislocations 20 whose angles θ1 lie within 7° (0° < θ1 ≤ 7°), wherein the density is based on 300 dislocations / cm³. 2 or less defined, and exhibit a density of thread dislocations 20 whose angles θ1 are greater than 7° (θ1 > 7°), where the density is 30 dislocations / cm 2or less precisely defined. The angle θ1 greater than 0° and within 40° refers to angles that meet the requirement for angle θ1 being greater than 0° and within 40°. The angles θ1 need not necessarily be equal, but can be different. The same applies to angles θ1 within 20° or 7°.

[0026] The Burgers vector bv can be determined by large-angle convergent-beam electron diffraction (LACBED). For example, when a defocused electron beam is projected onto a sample, distortion around a dislocation splits a line of the higher-order Laue zone (HOLZ). The split HOLZ lines are then indexed by simulation. The Burgers vector bv of the thread dislocation 20 can be determined by analyzing the indices of the HOLZ lines and the number of split HOLZ lines.

[0027] The orientation of dislocation line 21 is determined by a three-dimensional (3D) observation method using a transmission electron microscope (TEM). While the inclination of a dislocation in a direction perpendicular to an electron beam incidence direction can be evaluated in a normal TEM observation, the inclination in a parallel direction cannot. That is, the inclination of a dislocation within a plane parallel to the electron beam incidence direction cannot be evaluated. Therefore, either the electron beam incidence direction or the sample is tilted to evaluate the inclination in a direction parallel to a predetermined incidence direction.

[0028] For example, observing an electron beam diffraction pattern with an incidence direction aligned to a [1-100] direction allows the determination of an inclination angle from a <0001> axis in a [11-20] direction. The <0001> axis direction is determined from the electron beam diffraction pattern. The electron beam projection direction is then rotated by 180° around the <0001> The axis is rotated. This changes the inclination of the observed dislocation. The inclination in the [1-100] direction is calculated from the magnitude of this change.

[0029] The orientation of dislocation line 21 can also be determined using a confocal photoluminescence device (3DPL) or a confocal Raman spectrometer (3D-Raman).

[0030] The angle between the Burgers vector bv and the dislocation line 21 is determined by a calculation method for calculating an angle between two vectors in a spatial figure.

[0031] The density of the thread dislocations 20 can be determined by counting the number of thread dislocations 20 per area of ​​1 cm². 2in a predetermined plane of the SiC single crystal. For example, the epilayer 3 is etched using molten salt containing KOH, and the number of thread dislocations 20, where substantially hexagonal etch pits are observed, is counted using a TEM or optical microscope. The plane to be observed is one inclined at an angle of no more than 10° from the C-plane. The area to be considered has a size of 1 cm × 1 cm. The area to be considered can be 1 cm × 1 cm or larger, or less than 1 cm × 1 cm. If the area to be considered is not large enough, the dislocation density cannot be correctly assessed. Therefore, the area to be considered preferably has a size of 1 cm × 1 cm or larger.

[0032] Fig. Figure 4 shows the results of the experiments carried out by the inventors of the present invention on the relationship between the lifetime of the above-mentioned MOS capacitor 10 and the angle θ1 between the Burgers vector bv and the dislocation line 21 of the thread dislocations 20 that exist in the single crystal substrate 2 and the epilayer 3.

[0033] As described in points P1 to P6 in Fig. As shown in Figure 4, this experiment used wafer 1 with predetermined densities of thread dislocations 20, whose angles θ1 were a predetermined angle or less. The wafers 1 used in the experiment, represented by points P1, P2, and P3, each had a density of thread dislocations whose angles exceeded the angle of each point, with a density of 30 dislocations / cm². 2or less. For example, wafer 1, represented by point P3, had a density of thread dislocations 20, whose angles are larger than the angle at point P3, where the density is 30 dislocations / cm². 2 or less. An approximate curve TL1 of points P1, P2 and P3 in Fig. 4 was determined by exponential approximation using a least squares method.

[0034] The point P1, P2, P4, P5 and P6 in Fig. The Burgers vector bv of the thread dislocations 20 in wafer 1, shown in Figure 4, was a + c. The Burgers vector bv of the thread dislocations 20 in wafer 1, represented by point P3, was m + c. The wafers 1 used here were produced according to a process described in Japanese patent JP 3 745 668 B2. The wafers 1 used here each had a surface 1a with an offset angle that was set to approximately 4° in a <11-20> direction with respect to a {0001} plane. The thread dislocations 20 whose density was measured were those that had reached the surface 1a.

[0035] To measure the lifetime of the MOS capacitors 10, a constant voltage was applied in reverse to the MOS capacitors 10 and the time was measured until the leakage current rises to a predetermined level.

[0036] The in Fig. The four experimental results shown demonstrated that, for the production of high-quality devices with a lifetime of 2000 seconds or more, the density of thread dislocations 20, whose angles θ1 are greater than 0° and lie within 40°, must be increased to 300 dislocations / cm². 2 or less reduced, and the density of thread dislocations 20, whose angles θ1 are greater than 40°, to 30 dislocations / cm 2 or less reduced. The results of the in Fig. The experiments shown in the 4 also demonstrated that, in order to produce high-quality devices with a lifetime of 5000 seconds or more, the density of thread dislocations 20, whose angles θ1 are greater than 0° and lie within 20°, must be increased to 300 dislocations / cm². 2 or less is reduced, and the density of thread dislocations 20, whose angles θ1 are greater than 20°, is reduced to 30 dislocations / cm² 2or less. The results of the experiment shown in 4 also showed that, for the production of high-quality devices with a lifetime of 10,000 seconds or more, the density of thread dislocations 20, whose angles θ1 are greater than 0° and lie within 7°, must be reduced to 300 dislocations / cm². 2 or less reduced, and the density of thread dislocations 20, whose angles 1 are greater than 7°, to 30 dislocations / cm 2 or is less reduced.

[0037] Fig. Figure 4 shows the results of the experiment on the thread dislocations present in wafers 1, whose angles θ1 lie within specified values. Based on the results of this experiment, it can be assumed that even if the angles θ1 are unequal, it is possible to produce high-quality devices with a lifetime of 2000 seconds or more, as long as the angle θ1 is less than 40°.

[0038] As described above, the wafer 1 of the present embodiment has a density of thread dislocations 20 present in the single crystal substrate 2 and the epilayer 3, the angles θ1 of which are formed between the orientation of the Burgers vector bv and the orientation of the dislocation line 21 are greater than 0° and lie within 40°, with the density being 300 dislocations / cm². 2 or less specified, and has a density of thread dislocations 20 whose angles θ1 are greater than 40°, with the density being 30 dislocations / cm 2 or less defined. Preferably, the wafer 1 of the present embodiment has a density of thread dislocations 20 whose angles θ1 are within 20°, wherein the density is 300 dislocations / cm². 2or less is specified, and has a density of thread dislocations 20 whose angles θ1 are greater than 20°, with the density being 30 dislocations / cm 2 or less defined. More preferably, the wafer 1 of the present embodiment has a density of thread dislocations 20 whose angles θ1 are within 7°, wherein the density is 300 dislocations / cm². 2 or less specified, and has a density of thread dislocations 20 whose angles θ1 are greater than 7°, with the density being 30 dislocations / cm 2 or is less fixed.

[0039] As described above, the wafer 1 of the present embodiment has a low density of thread dislocations with high distortion. Therefore, by manufacturing MOS capacitors 10 using the wafer 1 of the present embodiment, the lifetime of the MOS capacitors 10 can be extended.

[0040] The MOS capacitor 10 of the present embodiment has a density of thread dislocations 20 occurring in the single-crystal substrate 2 and the epilayer 3, the angles θ1 of which are formed between the orientation of the Burgers vector bv and the orientation of the dislocation line 21 are greater than 0° and lie within 40°, with the density being 300 dislocations / cm². 2 or less is specified, and exhibit a density of thread dislocations 20 whose angles θ1 are greater than 40°, with the density being 30 dislocations / cm² 2 or less specified. Preferably, the MOS capacitor 10 has a density of thread dislocations 20 whose angles θ1 are within 20°, wherein the density is 300 dislocations / cm². 2 or less is specified, and has a density of thread dislocations 20 whose angles θ1 are greater than 20°, with the density being 30 dislocations / cm 2or less defined. Furthermore preferably, the MOS capacitor 10 has a density of thread dislocations 20 whose angles θ1 are within 7°, with the density being 300 dislocations / cm². 2 or less specified, and has a density of thread dislocations 20 whose angles θ1 are greater than 7°, with the density being 30 dislocations / cm 2 or is less fixed.

[0041] As described above, the single-crystal substrate 2 and the epilayer 3 forming the MOS capacitor 10 exhibit a low density of threaded dislocations with large distortion. Therefore, the lifetime of the MOS capacitor 10 can be extended compared to a MOS capacitor with a high density of threaded dislocations with large distortion. This means that the device characteristics of the electronic device can be improved.

[0042] In the present embodiment, the surface 3a of the epilayer 3 in the wafer 1 and the MOS capacitor 10 has an offset angle that is defined within 10° in the <11-20> direction with respect to the {0001} plane. The angle θ1 and the density of the thread dislocations 20 reaching this surface 3a are specified. This is because the influence of thread dislocations 20 with large distortion on device properties is considered to be particularly significant when the thread dislocations 20 exist near the surface 3a of the epilayer 3. However, it is assumed that the thread dislocations 20 with large distortion adversely affect the device properties not only when the thread dislocations 20 exist near the surface 3a of the epilayer 3, but also when they exist in regions other than near the surface 3a of the epilayer 3.Therefore, the thread dislocations 20, whose angle θ1 and density are to be specified, are not limited to those that exist in the epilayer 3 such that they reach the surface 3a.

[0043] While the wafers 1 of the present embodiment are manufactured according to the method described in Japanese patent JP 3 745 668 B2, the wafers can be manufactured according to other methods. Other embodiments

[0044] The present disclosure is not limited to the embodiments described above and may be modified as necessary within the scope of the claims, as is described below by way of example. (1) In the first embodiment, the MOS capacitors 10 are an example of an electronic device fabricated using the SiC single crystal, and the lifetime of the MOS capacitors 10 is investigated. It is assumed that the results regarding the lifetime of other electronic devices will be similar to those in Fig. 4. Other electronic devices include those having a MOS structure other than MOS capacitors and electronic devices having diodes. An electronic device having a MOS structure, similar to the MOS capacitor 10, encloses a first electrode 5 on a SiC single crystal via an oxide film 4. A MOSFET with a first electrode 5 as a gate electrode is an example of an electronic device having the MOS structure. Examples of electronic devices with diodes include Schottky diodes and PN diodes. A Schottky diode can be formed, for example, by removing the oxide film 4 from the in Fig. The structure shown in Figure 2 is omitted, i.e., the first electrode 5 is formed on the surface 3a of the epilayer 3, so that the first electrode 5 establishes a Schottky contact with the epilayer 3. Fig. 2. A PN diode can be formed if a p-type layer is formed as a surface layer on the epilayer 3, so that the first electrode 5 makes ohmic contact with the p-type layer. (2) In the first embodiment, the electronic device is fabricated using the SiC single-crystal epitaxial wafer 1. Alternatively, the electronic device can be fabricated using a Fig. The SiC single-crystal wafer 101 shown in Figure 5 is produced. This SiC single-crystal wafer 101 is produced from a SiC single crystal in a substrate form and does not contain an epitaxial growth layer. That is, the SiC single-crystal wafer 101 is formed only from the single-crystal substrate 2 and the epilayer 3 of the wafer 1 of the first embodiment.

[0045] The SiC single-crystal wafer 101, similar to the single-crystal substrate 2 of wafer 1 in the first embodiment, exhibits a low density of thread dislocations with large distortion. Therefore, by fabricating an electronic device using the SiC single-crystal wafer 101, the lifetime of the electronic device can be extended similarly to the first embodiment.

[0046] Preferably, a surface 101a of this SiC single-crystal wafer 101 has an offset angle that is specified within 10° in the <11-20> direction with respect to the {0001} plane, wherein the angle and density are specified similarly to the first embodiment with respect to the thread dislocations 20 that reach this surface 101a.

[0047] The electronic device to be manufactured can have a structure that includes the SiC single-crystal substrate and the SiC epitaxial growth layer, or it can have a structure that includes the SiC single-crystal substrate but not the epitaxial growth layer. Examples of an electronic device with a structure that does not include an epitaxial growth layer include the one described in Fig. Figure 2 shows the MOS capacitor 10 without the epilayer 3 and instead with a single-crystal substrate 2 that forms the part corresponding to the epilayer 3. In this case, the surface of the single-crystal substrate 2 corresponds to the surface 101a of the SiC single-crystal wafer 101.

[0048] (3) The embodiments described above are not irrelevant to each other and may be combined as necessary, unless the combination is obviously impossible. It is understood that the elements constituting the embodiments described above are not necessarily essential, except where they are explicitly specified as essential and where they are theoretically clearly considered to be essential.

Claims

[1] Use of a silicon carbide crystal wafer (101) for the manufacture of an electronic device, wherein the silicon carbide crystal wafer (101) comprises thread dislocations (20), each of which has a dislocation line (21) extending through a C-plane, and a Burgers vector (bv) that contains at least one component in a C-axis direction, characterized by , that After producing silicon carbide crystal wafers, a silicon carbide crystal wafer (101) is selectively selected and used, in which the density of thread dislocations with angles (θ1), each of which is formed by an orientation of the Burgers vector and an orientation of the dislocation line that are greater than 0° and within 40°, to 300 dislocations / cm 2 or less fixed, and The density of thread dislocations where the angles are greater than 40° is reduced to 30 dislocations / cm². 2 or is less fixed. [2] Use according to claim 1, wherein the silicon carbideine crystal wafer (101) is a silicon carbideine crystal epitaxial wafer, comprising: a silicon carbide crystal substrate (2); and an epitaxial growth layer (3) arranged on the silicon carbidein crystal substrate, wherein both the silicon carbide crystal substrate and the epitaxial growth layer enclose thread dislocations (20) and each of the thread dislocations has a dislocation line (21) extending through a C-plane and a Burgers vector (bv) containing at least one component in a C-axis direction, where the density of thread dislocations with angles (θ1), each of which is formed by an orientation of the Burgers vector and an orientation of the dislocation line that are greater than 0° and within 40°, is 300 dislocations / cm 2 or less fixed, and where the density of thread dislocations, where the angles are greater than 40°, is 30 dislocations / cm² 2 or is less fixed. [3] Use according to claim 1 or 2, where the density of thread dislocations, where the angles are within 20°, is 300 dislocations / cm² 2 or less determined and where the density of thread dislocations, where the angles are greater than 20°, is 30 dislocations / cm² 2 or is less fixed. [4] Use according to claim 1 or 2, where the density of thread dislocations, where the angles are within 7°, is 300 dislocations / cm² 2 or less determined where the density of thread dislocations, where the angles are greater than 7°, is 30 dislocations / cm² 2 or is less fixed.

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