Semiconductor device and its manufacturing process

Abstract

Semiconductor device, comprising: a substrate (SUB, EP) with a main surface provided with an off-angle inclined in a reference crystal direction of a <11-20> direction or a <1-100> direction with respect to a main crystal surface of a (0001) surface or a (000-1) surface; a plurality of trenches (DT) provided in the substrate (SUB, EP) such that they extend in a first direction along the main surface of the substrate (SUB, EP) and are spaced apart from each other in a second direction orthogonally to the first direction along the main surface of the substrate (SUB, EP); a first columnar region (PC) provided in the trench (DT) and consisting of a crystal layer with the same crystal structure as the substrate (SUB, EP); and a second column area (NC) consisting of a part of the substrate (SUB, EP) between the trenches (DT) adjacent to each other in the second direction, where an angular error between the reference crystal direction and the first direction lies within ± θ, if the depth of the trench (DT) is h, the width of the trench (DT) is w, and k is a coefficient greater than 0 and less than 2, which determines θ by θ = {arctan {k × (w / h)}} / 13 a first peak area (B1) at one end of the trench (DT) has a first tapered shape in the first direction, the width of which becomes narrower in plan view towards its tip end, a second peak area (B2) at the other end of the trench (DT) in the first direction has a second tapered shape, the width of which becomes narrower in plan view towards its tip end, and The angle of inclination of the first tapered shape with respect to the first direction is smaller than the angle of inclination of the second tapered shape with respect to the first direction.

Description

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and is accordingly applicable to a semiconductor device including a power semiconductor element embodied by, for example, a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and a manufacturing method thereof. STATE OF THE ART

[0002] Prior art in this technical field includes, for example, Japanese Patent Application Laid-Open No. JP 2013-138171 A (Patent Document 1) and Ryoji Kosugi et al., "Development of SiC super-junction (SJ) device by deep trench-filling epitaxial growth," Materials Science Forum, Vol. 740-742 (2013), pp. 785-788 (Non-Patent Document 1).

[0003] Patent Document 1 describes a semiconductor device in which an n-type charge amount and a p-type charge amount are balanced in an n-type column region and a p-type column region forming a superjunction structure in a cell region, and a charge balance change region is provided in a peripheral region in which the n-type charge amount in the superjunction structure is gradually made larger than the p-type charge amount as one moves toward an outer circumferential direction of the cell region. Other semiconductor devices having a superjunction structure are described in Patent Documents 2 and 3.

[0004] In addition, Non-Patent Document 1 discloses an example in which a trench having a width of 2.7 µm and a depth of 7 µm formed in a 4H-SiC substrate is filled with a SiC layer without forming a cavity under the premise of forming the superjunction structure. RELATED TECHNICAL PATENT DOCUMENTS Patent Document 1: Japanese Patent Application Laid-Open No. JP 2013-138171 A Patent Document 2: US Patent Application Laid-Open No. US 2014 / 0151785 A1 Patent Document 3: US Patent Application Laid-Open No. US 2016 / 0087032 A1 Non-Patent Document 1: Ryoji Kosugi et. al., Development of SiC super-junction (SJ) device by deep trench-filling epitaxial growth, Materials Science Forum Vol. 740-742 (2013) pp. 785-788 SUMMARY OF THE INVENTION PROBLEMS TO BE SOLVED BY THE INVENTION

[0005] The power semiconductor element with the superjunction structure has an advantage that it can reduce the on-resistance while ensuring a high withstand voltage.

[0006] The trench filling method (hereinafter also referred to as the trench filling method) is known as one of the methods for forming a superjunction structure. The trench filling method is considered effective for reducing the on-resistance over a wide range of withstand voltage because it allows the superjunction structure to be formed with a deep trench. However, although a high-aspect-ratio trench is required to realize a high-withstand voltage power semiconductor device, it is not easy to fill the high-aspect-ratio trench with a satisfactory yield using the epitaxial growth filling method, and there is a problem of low production yield of the manufacturing apparatus including the power semiconductor device.

[0007] Note that even in Non-Patent Document 1, the reproducibility of successful filling is low and the reason for this is unknown. MEANS TO SOLVE THE PROBLEMS

[0008] The problem described above is solved by a semiconductor device having the features of claim 1 and by the manufacturing methods described in claims 9 and 10.

[0009] In particular, a semiconductor device is preferably configured to include: a single-crystal substrate having a main crystal surface inclined with respect to a reference crystal direction, which is a predetermined crystal direction; a plurality of trenches provided in the substrate so as to extend in a first direction along the main crystal surface of the substrate and spaced apart from each other in a second direction orthogonal to the first direction along the main crystal surface of the substrate; a first pillar region provided within the trench and composed of a crystal layer having the same crystal structure as that of the substrate;and a second pillar region consisting of a part of the substrate between the trenches adjacent to each other in the second direction, wherein an angular error between the reference crystal direction and the first direction is within ± θ and the θ is defined by θ = {arctan {k × (w / h)}} / 13, when a depth of the trench is h, a width of the trench is w, and k is a coefficient less than 2; EFFECTS OF THE INVENTION

[0010] According to the present invention, it is possible to improve the production yield and the reliability of the semiconductor device including the power semiconductor element.

[0011] The aspects, configurations and effects different from those described above will be clarified by the following descriptions of the embodiments. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view showing a first example of a layout of a plurality of semiconductor chips formed on a SiC single crystal wafer according to a first embodiment; Fig. 2 is a plan view showing a second example of the layout of the plurality of semiconductor chips formed on the SiC single crystal wafer according to the first embodiment; Fig. 3 is a schematic diagram for describing an example of filling a plurality of trenches formed in the semiconductor device according to the first embodiment; Fig. 4 is a plan view showing a configuration of the semiconductor device according to the first embodiment; Fig. 5 is a cross-sectional view (cross-sectional view taken along a line AA' in Fig. 4) showing the configuration of the semiconductor device according to the first embodiment; Fig. 6 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the first embodiment; Fig. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device of Fig. 6 from continued shows; Fig. 8 is a cross-sectional view showing the manufacturing process of the semiconductor device of Fig. 7 from continued shows; Fig. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device of Fig. 8 from continued shows; Fig. 10 is a cross-sectional view showing the manufacturing process of the semiconductor device of Fig. 9 from continued shows; Fig. 11 is a cross-sectional view showing the manufacturing process of the semiconductor device of Fig. 10 from continued shows; Fig. 12 is a cross-sectional view showing the manufacturing process of the semiconductor device of Fig. 11 from continued shows; Fig. 13 is a cross-sectional view showing the manufacturing process of the semiconductor device of Fig. 12 from continued shows; Fig. 14 is a cross-sectional view showing the manufacturing process of the semiconductor device of Fig. 13 from continued shows; Fig. 15 is a plan view showing a plurality of trenches formed in a substrate according to a second embodiment; Fig. 16 is an enlarged cross-sectional view showing one end of the trench formed in the substrate according to the second embodiment; Fig. 17 is a plan view showing a plurality of trenches formed in a substrate according to a modification of the second embodiment; Fig. 18 is a plan view showing a first comparative example of a layout of a plurality of semiconductor chips formed on a SiC single crystal wafer, which was studied by the inventors of the present invention prior to the present invention; Fig. 19 is a plan view showing a second comparative example of a layout of a plurality of semiconductor chips formed on a SiC single crystal wafer, which was studied by the inventors of the present invention prior to the present invention; Fig. 20 is a schematic diagram for describing an example of filling a plurality of trenches formed in a semiconductor device studied by the inventors of the present invention prior to the present invention; Fig. 21 is a diagram showing an example of backfilling in cases where an HCl / SiH4 flow ratio in the epitaxial growth filling method is 33.3, 50, and 66.7; Fig. 22 is a diagram showing an example of backfilling in the case where a pressure in a growth furnace during epitaxial growth in the epitaxial growth filling method is 10 kPa; Fig. 23(a) to 23(i) are cross-sectional SEM images of a plurality of trenches formed in a substrate with different inclination angles of an extending direction with respect to a <11-20> direction and then filled with a crystal layer; Fig. 24 is a graph showing a relationship between an inclination angle θ trench of a pattern on a photomask with respect to the <11-20> direction and an inclination angle θ mesa of the SiC layer formed by epitaxial growth on a side surface of an upper portion of the trench, which SiC layer is composed of Fig. 23 is obtained; Fig. 25(a), Fig. 25(b) and Fig. 25(c) are schematic diagrams each showing a model for considering a relationship between trench dimensions and a state in which the crystal layer closes the trench when the crystal layer grows obliquely from the side surface of the upper portion of the trench; Fig. Figure 26 is a graphical representation showing an allowable angular error between the trench direction and the <11-20> direction obtained from the Fig. 25 models shown and insight C is calculated; Fig. 27 is a graph showing a relationship between an inclination angle θ trench of a pattern on a photomask with respect to the <11-20> direction and each of a crystal growth rate at a trench bottom (upper plots in the graph) and a crystal growth rate at a mesa top (lower plots in the graph); Fig. 28 is a table showing an angular error θ between the trench direction and the <11-20> direction obtained from a fitting curve of the crystal growth rate at the trench bottom shown in Fig. 27, and an adjustment margin coefficient k calculated from the angular error θ; and Fig. 29(a), Fig. 29(b) and Fig. 29(c) are plan views showing modifications of the tip shape of the trench in the second embodiment and the modification of the second embodiment. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0012] When simply “substrate” is mentioned, unless otherwise specified, the “substrate” includes not only a substrate made of single-crystal silicon carbide (SiC) and a substrate made of single-crystal silicon (Si), but also a substrate having an epitaxial layer formed on a main surface of a substrate made of single-crystal silicon carbide (SiC) or a substrate made of single-crystal silicon (Si).

[0013] Furthermore, unless otherwise specified, a numerical sequence (orientation index) enclosed by parentheses <> indicates a crystal orientation and is described, for example, by four orientation indices such as the <11-20> direction in a hexagonal single crystal. Herein, a minus sign indicates that the orientation index immediately following the sign is an orientation with a minus component, and <11-20> means that the orientation index 2 is in the minus direction. Furthermore, a numerical sequence (surface index) enclosed by parentheses () indicates a crystal surface and is described, for example, by four surface indices such as the (0001) surface in a hexagonal single crystal.

[0014] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. (Advantages of a superjunction structure)

[0015] The power MOSFET according to the present embodiment has a superjunction structure. The power MOSFET with a superjunction structure like this can achieve the advantages described below.

[0016] In power MOSFETs, the withstand voltage is ensured by reducing the impurity concentration of the substrate and expanding the depletion layer formed in the substrate in the off-state. Therefore, to achieve a high withstand voltage, it is necessary to increase the thickness of the substrate with a low impurity concentration. On the other hand, if the thickness of the substrate with a low impurity concentration is increased, the on-resistance of the power MOSFET becomes high. In power MOSFETs, there is a trade-off between improving the withstand voltage and reducing the on-resistance.

[0017] In the power MOSFET of the present embodiment, a superjunction structure including a p-type column region and an n-type column region arranged cyclically and periodically is formed in a substrate. The superjunction structure is generally composed of a plurality of p-type column regions arranged at regular intervals in an n-type substrate and a plurality of n-type column regions each composed of the n-type substrate between adjacent p-type column regions.

[0018] In this power MOSFET with the superjunction structure, in an off-state, the depletion layer also extends in a lateral direction from a pn junction formed in a boundary region between the p-type pillar region and the n-type pillar region. Therefore, even if the impurity concentration of the n-type pillar region serving as a current path is increased, the depletion layers extending in an internal direction of the n-type pillar region sandwiched between the two boundary regions are connected, so that the entire n-type pillar region is expected to be depleted. Accordingly, the entire n-type pillar region is depleted in an off-state, and thus the withstand voltage can be ensured.In other words, in the power MOSFET with the superjunction structure, the impurity concentration of the n-type column region serving as the current path can be increased, and the entire n-type column region can be depleted. As a result, the on-resistance of the power MOSFET with the superjunction structure can be reduced while maintaining a high withstand voltage. (Advantage of a trench filling method)

[0019] For example, in the superjunction structure, from the standpoint of reducing the on-resistance of the power MOSFET, it is effective to narrow the interval between adjacent p-type pillar regions to reduce the width of the n-type pillar region. This is because, from the standpoint of reducing the on-resistance, it is desirable to increase the n-type impurity concentration of the n-type pillar region serving as the current path. Namely, if the n-type impurity concentration of the n-type pillar region is increased to reduce the on-resistance, the extension of the depletion layer to the n-type pillar region is reduced, and thus, it is necessary to reduce the width of the n-type pillar region for depletion of the entire n-type pillar region.

[0020] Therefore, in consideration of ensuring the withstand voltage while increasing the n-type impurity concentration of the n-type pillar region to reduce the on-resistance, it is necessary that the interval between the adjacent p-type pillar regions is decreased to reduce the width of the n-type pillar region.

[0021] A typical method for forming a superjunction structure is known as the "trench filling method." In the trench filling method, the p-type pillar region is formed in the trench formed in the substrate using the epitaxial growth method. Therefore, the formation accuracy of the p-type pillar region is determined by the formation accuracy of the trench. Since the trench is generally formed using photolithography and dry etching techniques, the p-type pillar regions can be formed with high precision, and the interval between adjacent p-type pillar regions can be reduced in the trench filling method.

[0022] Another method for forming the superjunction structure is the "multi-epitaxy method." However, in the multi-epitaxy method, the p-type pillar region is formed by the ion implantation method. Therefore, multi-stage ion implantation is required to form the deep p-type pillar region in the substrate, and there is a problem of increasing the number of ion implantations.

[0023] Therefore, the trench filling method is adopted in the present embodiment. The power MOSFET with the superjunction structure formed by the trench filling method will be described below. (Detailed description of defects accompanying an epitaxial growth filling process)

[0024] The semiconductor device including the power MOSFET with the superjunction structure according to the present embodiment is fabricated on a substrate made of single-crystal silicon carbide (SiC) in wafer form (hereinafter referred to as a SiC single-crystal substrate). Specifically, the p-type pillar region and the n-type pillar region constituting the superjunction structure are alternately arranged in an epitaxial layer formed on a main surface of a SiC single-crystal substrate. The SiC single-crystal substrate generally has a main surface in which a (0001) surface is tilted by 4° in a <11-20> direction, and the SiC single-crystal substrate is fabricated such that the orientation flat and the <11-20> direction are approximately parallel to each other.Therefore, the epitaxial layer formed on the main surface of the SiC single crystal substrate by the epitaxial growth method has the same crystal structure as the SiC single crystal substrate.

[0025] For example in Fig. However, as shown in Figure 18, due to variations in process conditions during the manufacturing of a SiC single-crystal substrate SW, the direction of an orientation flat OF is not parallel to the <11-20> direction, and an angular error between the direction of the orientation flat OF and the <11-20> direction becomes larger than ±1° in some cases. In such cases, if a plurality of trenches (also referred to as recesses) DT constituting the superjunction structure in each of the semiconductor chips SC are formed to be approximately parallel to the direction of the orientation flat OF, an angular error between the extending direction (also referred to as the longitudinal direction) of the trench DT and the <11-20> direction becomes larger than ±1°.

[0026] For example in Fig. As shown in Figure 19, even if an angular error between the direction of the orientation flat OF and the <11-20> direction is less than ±1°, the extending direction of the plurality of trenches DT formed in each of the semiconductor chips SC also deviates from the direction of the orientation flat OF in some cases due to variations in process conditions during their manufacturing. In such a case, an angular error between the extending direction of the trench DT and the <11-20> direction becomes greater than ±1° in some cases.

[0027] The investigation by the inventors of the present invention has revealed that when the angular error between the extending direction of the trench DT and the <11-20> direction becomes larger than ± 1°, it becomes difficult to fill the inside of the trench DT with a semiconductor layer by the epitaxial growth filling method.

[0028] Fig. 20 is a schematic diagram for describing an example of filling using the epitaxial growth filling method in the case where the angular error between the trench extension direction DT and the <11-20> direction is greater than ±1°. The epitaxial layer EP is formed on the main surface of the SiC single-crystal substrate SW, and the plurality of trenches DT are formed in the epitaxial layer EP so as to extend in one direction. The angular error between the trench extension direction DT and the <11-20> direction is, for example, about ±5°.

[0029] In an initial stage of epitaxial growth, a semiconductor layer SM, such as a SiC layer, grows from a bottom of the trench DT and an upper surface of a convex portion of the epitaxial layer EP, and the interior of the trench DT is gradually filled. However, since the growth direction of the semiconductor layer SM is gradually tilted as the epitaxial growth progresses, the top portion of the trench DT and both end portions in the extension direction are closed, and vacancies (also referred to as voids) VO are formed in the trench DT. When the depth of the trench DT is 5 μm or more, especially 10 μm or more, defects such as these accompanying the filling process by epitaxial growth are conspicuously encountered. (Findings that led to the present invention)

[0030] The findings that led to the present invention are described in detail below.

[0031] (1) Experimental results on crystal growth of a SiC layer filling the interior of a trench

[0032] Fig. 23(a) to 23(i) are cross-sectional SEM images of a plurality of trenches formed in a substrate with different inclination angles of a direction with respect to the <11-20> direction and then filled with a crystal layer. The plurality of trenches are formed in the substrate to have intentional inclination deviations with respect to the <11-20> direction by using a photomask in which a plurality of patterns with different inclination angles with respect to the <11-20> direction are formed. Fig. 23(a) to 23(i) each show the state of trench filling in the case where the inclination angle of the pattern with respect to the <11-20> direction is changed in increments of 0.5° in the range of -2.0° to +2.0° on the photomask.

[0033] Fig. 23(a) to 23(i) each show an inclination angle θ trench of the structure or pattern on the photomask with respect to the <11-20> direction, and Fig. For example, Figure 23(a) shows “-2.0°”. Note that an angle “(-1.5°)”, in Fig. 23(a) is written in parentheses, is an "estimated actual angle" described later. The pattern inclined toward the <-1100> direction orthogonal to the <11-20> direction is also referred to as the plus-side inclined pattern, and the pattern inclined toward the direction opposite to the <-1100> direction (i.e., <1-100>) is referred to as the minus-side inclined pattern.

[0034] As experimental conditions, after the plurality of trenches are formed in the 4H-SiC substrate with an off-angle of 4 degrees with respect to the <11-20> direction, the interior of the trenches is filled by crystal growth of a SiC layer. The photomask for forming the trench is aligned or adjusted by an exposure device so that the orientation flat of the substrate used for the experiment and the pattern with θ trench = 0° are parallel to each other.

[0035] The substrate used in the experiment is manufactured so that the orientation flat corresponds to the <11-20> direction, but an angular error between the orientation flat of the substrate in specifications and the <11-20> direction is within ± 5°. The trench is formed by the ICP (inductively coupled plasma) etching method, the depth of the trench is 22 µm to 25 µm, and its width is 2.25 µm to 2.5 µm. The size of the convex portion of the substrate, which corresponds to the space separating the adjacent trenches, is also 2.25 µm to 2.5 µm. In addition, the other experimental conditions not mentioned here, such as crystal growth for filling the SiC layer, are similar to those described later in <<Herstellungsverfahren einer Halbleitervorrichtung> > the first embodiment will be described.

[0036] In the experimental results, the best result is obtained in the pattern with θ trench = -0.5°, which is in Fig. 23(d), and the SiC layer is embedded in the trench in a preferred state while the trench maintains verticality. On the other hand, in the cases of Fig. 23(c), Fig. 23(b) and Fig. 23(a), that is, in the cases where θ trench is tilted to the minus side, the SiC layer tilted to the left side starts from the lateral surface of the trench and covers the upper part of the trench as the angle increases. In the cases of Fig. 23(e), Fig. 23(f), Fig. 23(g), Fig. 23(h) and Fig. 23(i), that is, in cases where θ of the trench is tilted toward the plus side, the right-side tilted SiC layer also grows from the lateral surface of the trench and covers the upper part of the trench as the angle increases. According to the results described above, the following conclusions can be drawn. (Insight A)

[0037] When θ trench increases and the upper portion of the trench is covered with the SiC layer formed by crystal growth, the source gas can hardly be supplied to the inside of the trench, so that the crystal growth to fill the SiC layer inside the trench is inhibited. (Insight B)

[0038] The approximately vertical crystal growth of the SiC layer can be obtained in the pattern of θ trench = -0.5°, and the orientation flat of the substrate used in the experiment is designed to deviate from the precise <11-20> direction by about 0.5°. Therefore, it is possible to assign the “estimated actual angle between the trench extension direction and the <11-20> direction specific to the crystal,” which is shown in the parentheses in Fig. 23(a) to 23(i). In this experiment, Fig. 23(d) close to the estimated actual angle of 0°.

[0039] (2) Relationship between tilt angle θ trench of a pattern on a photomask with respect to a <11-20> direction and tilt angle θ mesa of a SiC layer grown on a side surface of an upper region of a trench

[0040] Fig. Fig. 24 is a graph showing a relationship between an inclination angle θ trench of the pattern on the photomask with respect to the <11-20> direction and an inclination angle θ mesa of the SiC layer grown on the side surface of the upper portion of the trench, which consists of Fig. 23. It can be seen that θ trench and θ mesa have a proportional relationship, which is approximated by a straight line. From this diagram, the following conclusion is drawn. (Insight C)

[0041] θ Graben and θ Mesa have a proportional relationship approximated by a straight line, and its slope is 13.

[0042] (3) Model for investigating a relationship between trench shape and growth inhibition of a crystal layer in the trench Fig. 25(a), Fig. 25(b) and Fig. 25(c) are schematic diagrams each showing a model for considering a relationship between trench dimensions and a state in which the crystal layer closes the trench if the crystal layer grows in an obliquely inclined manner from the lateral surface of the upper portion of the trench.

[0043] Fig. Figure 25(a) shows a first model in which crystal growth with an inclination angle Q1 starts from the upper region h / 2 of the lateral surface of the trench with the height h and the width w, and the trench is closed. This corresponds to the case in which the SiC layer grows in an inclined manner from the upper half of the lateral surface of the trench, in which Fig. 23. Therefore, the experimental result shown in Fig. 25(a) represents the minimum condition required to avoid growth inhibition of the crystal layer inside the trench. The maximum tilt angle Q1, which is obtained in the model shown in Fig. 25(a) is permissible, is represented by the following (Expression 1). Q1=arctan(2w / h)

[0044] Fig. Figure 25(b) shows a second model to effectively reduce the growth inhibition of the crystal layer inside the trench. The crystal layer with a tilt angle Q2 grows from the upper region h / 2 of the lateral surface of the trench as a standard in this model, and crystal growth is inhibited to half w / 2 of the trench width, so that the entrance of the trench is not closed. The maximum tilt angle Q2, which is used in the Fig. 25(b) is permissible is represented by the following (Expression 2). Q2=arctan(w / h)

[0045] Fig. Figure 25(c) shows a more desirable third model. As a standard, in this model, the crystal layer grows with an inclination angle Q3 from the upper region h / 2 of the lateral surface of the trench, and crystal growth is restricted to a quarter w / 4 of the trench width with a further margin, so that it does not close the trench entrance. The maximum inclination angle Q3, which is present in the Fig. 25(c) is permissible, is represented by the following (Expression 3). Q3=arctan(w / 2h)

[0046] Namely, in order to avoid the growth inhibition of the crystal layer inside the trench, the growth angle of the crystal layer must be at least smaller than the angle Q1 of (Expression 1), it is preferably smaller than the angle Q2 of (Expression 2), and is more preferably smaller than the angle Q3 of (Expression 3). (4) Allowable angular error θ of a trench direction with respect to a <11-20> direction, calculated from models shown in FIG. 25

[0047] Fig. Figure 26 is a graphical representation showing an allowable angular error between the trench direction and the <11-20> direction obtained from the Fig. 25 and the above (Finding C). Since Q1 of (Expression 1), Q2 of (Expression 2), and Q3 of (Expression 3) correspond to a θ Mesa of (Finding C), the allowable angular error θ of the trench extension direction with respect to the <11-20> direction can be obtained as the value corresponding to the θ trench if the value obtained from the experimental result of Fig. 24 obtained slope 13 is used. Thus, the following conclusion can be obtained. (Insight D)

[0048] In order to avoid the growth inhibition of the crystal layer inside the trench, the angle error θ between the trench extension direction and the <11-20> direction must be at least smaller than the angle of the following (Expression 4). θ=Q1 / 13={arctan(2w / h)} / 13

[0049] The angle error θ between the trench direction and the <11-20> direction is preferably smaller than the angle of the following (Expression 5). θ=Q2 / 13={arctan(w / h)} / 13

[0050] The angle error θ between the trench direction and the <11-20> direction is preferably smaller than the angle of the following (Expression 6). θ=Q3 / 13={arctan(w / 2h)} / 13

[0051] Since the angle error θ between the trench extending direction and the <11-20> direction has values ​​on both the plus side and the minus side as the allowable angle error, the angle error within ± θ, represented by (Expression 4), (Expression 5) and (Expression 6) above, is the finding to effectively reduce the growth inhibition of the crystal layer inside the trench.

[0052] Fig. Figure 26 shows the calculation results of (Expression 4), (Expression 5) and (Expression 6) above. The vertical axis of Fig. 26 represents the angular error θ of the trench direction with respect to the <11-20> direction, which is calculated for the Fig. 25(a), Fig. 25(b) and Fig. 25(c) is permissible. The first horizontal axis represents the height h when the trench width w is set to 2 µm, and shows the range from 0 µm to 40 µm. The second horizontal axis represents the aspect ratio (ratio = h / w), which is a dimensionless value, and shows the range from 0 to 20.

[0053] In Fig. 26, when the aspect ratio is less than 5, the allowable value of the angular error θ of the direction of travel with respect to the <11-20> direction increases significantly due to the characteristics of the function. Therefore, in the region with a relatively small aspect ratio (0 to 5), the range of the angular error θ is relatively large.

[0054] On the other hand, when the aspect ratio is greater than or equal to 5, the allowable value of the angular error θ does not change much and gradually decreases as the aspect ratio increases. Therefore, the management of the angular error θ is important in the range of the aspect ratio of 5 or more. Furthermore, when the aspect ratio becomes greater than or equal to 10, since the characteristics that gradually decrease and are approximated by a curved line and a nearly straight line also appear and the value of the angular error θ itself becomes small, the management of the angular error θ becomes more important. In other words, as the applicable range of the present invention, the remarkable effect can be expected in the range of the aspect ratio of 5 or more. Further, the more remarkable effect can be expected in the range of the aspect ratio of 10 or more.

[0055] (5) Relationship between tilt angle θ trench of a pattern on the photomask with respect to the <11-20> direction and crystal growth rate at the trench bottom

[0056] Fig. 27 summarizes the Fig. 23 and is a graph showing a relationship between the tilt angle θ trench of the pattern on the photomask with respect to the <11-20> direction and a crystal growth rate at a trench bottom (upper plots in the graph). In addition, Fig. 27 shows a crystal growth rate at a mesa top (upper surface of a convex portion of a substrate) (lower plots in the graph). The mesa structure herein refers to a convex portion. When a plurality of trenches are formed in the substrate, convex portions of the substrate, each serving as a spacer to separate adjacent trenches, are formed, and the convex portion is referred to as a mesa structure. The curved line representing the points of the experimental results shown in Fig. 27 is a Gaussian fitting or regression curve.

[0057] Out of Fig. From Figure 27, it can be seen that the crystal growth rate at the trench bottom is sensitively affected by the θ trench. It is assumed that the mechanism in which the entrance at the top of the trench is narrowed due to the crystal layer grown in an inclined manner, so that the source gas of the crystal growth is hardly supplied to the trench bottom, is at work.

[0058] Note that since crystal growth at the mesa top occurs near the top surface of the substrate and is less likely to be affected by the restriction of source gas supply, the crystal growth rate at the mesa top changes relatively smoothly with respect to the θ trench. However, even in this case, the crystal growth rate at the mesa top decreases in the pattern of θ trench = -0.5°, and this supports the fact that the source gas is efficiently supplied to the trench bottom from the opposite perspective.

[0059] Incidentally, if (Expression 4), (Expression 5) and (Expression 6) are more generalized and elaborated, the following (Expression 7) is obtained. θ={arctan{k×(w / h)}} / 13

[0060] k is defined herein as “adjustment margin coefficient” for convenience, and k is a coefficient smaller than 2. (Expression 4), (Expression 5), and (Expression 6) are specific cases corresponding to k = 2, k = 1, and k = 1 / 2, respectively. When k becomes smaller than 2, the inclined growth of the crystal layer shown in Fig. 23, suppresses the filling of the crystal layer inside the trench, and improves the degree of completion. Note that the theoretical minimum value of k is 0, but at this time, θ = 0. Since it is difficult to realize k = 0 in an actual production process, the cost of the semiconductor device can be optimized by selecting k in consideration of the balance between production yield and production cost (production margin).

[0061] If (Expression 7) is solved inversely for k, the following (Expression 8) is obtained. k=(h / w)×tan(13×θ) (6) Calculation result of an adjustment margin coefficient k

[0062] Fig. Figure 28 shows the adjustment margin coefficient k, which is calculated by subtracting the angle error θ from the width of θ trench at a predetermined height in the best fit curve of the crystal growth rate at the trench bottom shown in Fig. 27, and the angular error θ is substituted into (Expression 8). The height equivalent to the change in the crystal growth rate at the trench bottom is referred to as the "height position (level)" and is defined as a value from 0% to 100%, while the tail (θ trench = -2.0° or +1.0°) of the Gaussian curve is fixed to 0% (crystal growth rate: GR = 2.38 µm / h) and the peak (θ trench = -0.46°) of the Gaussian curve is fixed to 100%.

[0063] In Fig. 28, the angular error θ is obtained by reading the width (L-width) of θ trench of the Gaussian curve at the height position (level) of 50%, 80% and 90% and halving the width (L-width). Fig. 23, since the depth h of the trench is 22 µm to 25 µm and the width w is 2.25 µm to 2.5 µm, the average values ​​of h = 23.5 µm and w = 2.385 µm are used when k is calculated using (Expression 8).

[0064] The following examines the importance of "height position (level)" in the crystal growth of the trench fill before the trench entrance is completely closed. A simplified model assumes that the source gas supplied for trench fill is divided into the following three components. (a) Fraction contributing to crystal growth occurring at the trench bottom: A1 + A2(θ) (b) Fraction contributing to crystal growth occurring at the mesa top: B1 + B2(θ) (c) Fraction contributing to crystal growth occurring on the lateral surface of the trench: C1 + C2(θ)

[0065] This is because the Fig. 23 and Fig. 27, the experimental results presented suggest the presence of the constant part that is independent of θ ditch of A1, B1 and C1 and the presence of the variable part that depends on θ ditch of A2(θ), B2(θ) and C2(θ).

[0066] The above (a) is a proportion that is the objective of the present invention, and it is desirable to maximize the contribution of the source gas to this proportion. Since the above (b) is crystal growth that occurs vertically upward from the mesa top, it is not directly detrimental to the backfill of the trench bottom; however, it is desirable to reduce it as much as possible. The above (c) is a proportion that complicates the objective of the present invention, and it is desirable to minimize the contribution of the source gas to this proportion.

[0067] Assuming that the supply of source gas is constant and the sum total of the above (a), (b) and (c) is always constant, the following expression is obtained: A1+A2(θ)+B1+B2(θ)+C1+C2(θ)=Const

[0068] Since A1, B1 and C1 are constants, they are transferred to the right-hand side and combined as a new constant Konst', so that the following expression is obtained. A2(θ)+B2(θ)+C2(θ)=Const'

[0069] When the contribution of the source gas to A2(θ) in (Expression 10) is 100%, the remaining B2(θ) and C2(θ) become 0%. This corresponds approximately to θ trench = 0.5°, shown in Fig. 27, and corresponds to 100% as the height position (level). Furthermore, this is a state in which the above (a) can be maximized and the above (b) and (c) can be minimized.

[0070] In contrast, when the contribution to A2(θ) in (Expression 10) is 0%, the remaining B2(θ) + C2(θ) becomes 100%. This corresponds approximately to θ trench = -2.0° or θ trench = + 1.0°, shown in Fig. 27, and corresponds to 0% as the height position (level). This is also a condition in which (a) above is minimized and (b) and (c) above are maximized. From the foregoing, the height position (level) can be understood as a parameter that approximately expresses the efficiency of crystal growth toward the trench bottom. From the above results, the following insight is obtained. (Insight E)

[0071] The angle error θ between the trench extension direction and the crystal orientation (for example, <11-20> direction) in order to reduce the growth inhibition of the crystal layer inside the trench with the height h and the width w is generally represented by at least the following expression ((Expression 7), shown again). θ={arctan{k×(w / h)}} / 13

[0072] k is defined herein as the adjustment margin coefficient and must be a value less than 2. Compared with the case where the crystal growth rate at the trench bottom is saturated (0%), the crystal growth rate that is 50% or more efficient is ensured when k = 0.9 or less. Furthermore, the crystal growth rate that is 80% or more efficient is ensured when k = 0.5 or less. More preferably, the crystal growth rate that is 90% or more efficient is ensured when k is 0.3 or less.

[0073] The present embodiment provides a new technical thought that can improve a production yield and reliability of a semiconductor device by securely filling an inside of a trench with the crystal layer by the epitaxial growth filling method in a semiconductor device including a power MOSFET having the superjunction structure, based on the above-described findings leading to the present invention. (First Embodiment)< <Merkmale und Effekte einer Halbleitervorrichtung)

[0074] Features and effects of the semiconductor device according to the first embodiment will be described with reference to Fig. 1, Fig. 2 and Fig. 3 described. Fig. 1 is a plan view showing a first example of a layout of a plurality of semiconductor chips formed on a SiC single crystal wafer according to the first embodiment. Fig. 2 is a plan view showing a second example of the layout of the plurality of semiconductor chips formed on the SiC single crystal wafer according to the first embodiment. Fig. 3 is a schematic diagram for describing an example of filling a plurality of trenches formed in the semiconductor device according to the first embodiment.

[0075] First, with reference to Fig. 1, the first example of the semiconductor device according to the first embodiment will be described.

[0076] As in Fig. As shown in Figure 1, the semiconductor device including the power MOSFET with the superjunction structure according to the first embodiment is fabricated on a SiC single-crystal substrate SW in wafer form for each semiconductor chip SC. Specifically, an epitaxial layer having the same crystal structure as the SiC single-crystal substrate SW is formed on a main surface of the SiC single-crystal substrate SW, and the superjunction structure, in which p-type pillar regions PC and n-type pillar regions NC extending in an x-direction (first direction) are alternately arranged in a y-direction (second direction) orthogonal to the x-direction along the main surface of the SiC single-crystal substrate SW, is provided in the epitaxial layer. The SiC single-crystal substrate SW is made of, for example, a hexagonal 4H polytype SiC single crystal (abbreviated as "4H-SiC").

[0077] The p-type pillar regions PC are formed by the epitaxial growth method, a semiconductor layer (SiC layer) embedded in a plurality of trenches DT formed in the epitaxial layer extending in the x-direction and spaced apart from each other in the y-direction. Each of the n-type pillar regions NC formed by the epitaxial layer is formed between the p-type pillar regions PC adjacent to each other in the y-direction. The semiconductor layer is a crystal layer having the same crystal structure as that of the epitaxial layer, i.e., the SiC single-crystal substrate SW.

[0078] For example, the trench DT has a depth of 5 µm or more, and the trench DT with an aspect ratio of about 10 and a depth of about 20 µm can be exemplified. Furthermore, the trench DT has a tapered shape that becomes narrower as it goes deeper, and the taper angle formed by the bottom surface and the side surface of the trench DT is, for example, about 88° to 90°. The taper angle may be 80° to 90° (80° or more to 90° or less), more preferably 85° to 90°, and most preferably 88° to 90°.

[0079] In the first example of the semiconductor device, the SiC single-crystal substrate SW has the main surface whose (0001) surface is tilted by 4° in the <11-20> direction, and the angular error between the orientation flat OF and the <11-20> direction is within ±θ. As described above in (Finding E), θ is determined by {arctan {k × (w / h)} / 13 for the trench having the height h and the width w. Herein, k is at least less than 2, preferably 0.9 or less, more preferably 0.5 or less, and even more preferably 0.3 or less. As an example of the value within ±θ, a value within ±1° (-1° or more and 1° or less) can be cited as a typical value.

[0080] Furthermore, the plurality of trenches DT are formed such that the extending direction (x-direction) of the plurality of trenches DT formed in the epitaxial layer and the direction of the orientation flat OF of the SiC single-crystal substrate SW are the same. Therefore, the angular error between the extending direction (x-direction) of the trench DT and the <11-20> direction is within ±θ. Note that the "same direction" mentioned here does not mean entirely the same direction, but essentially the same direction or approximately the same direction, and includes a certain range that takes variations into account.

[0081] Next, with reference to Fig. 2, the second example of the semiconductor device according to the first embodiment is described.

[0082] As in Fig. As shown in Figure 2, in the second example of the semiconductor device, the SiC single-crystal substrate SW has a main surface whose (0001) surface is tilted by 4° in the <11-20> direction, and the angular error between the orientation flat OF and the <11-20> direction is larger than the above-mentioned ±θ. Further, the plurality of trenches DT are formed such that the extending direction (x-direction) of the plurality of trenches DT formed in the epitaxial layer and the <11-20> direction are the same. Therefore, the angular error between the extending direction (x-direction) of the trench DT and the <11-20> direction is within ±θ.

[0083] Fig. 3 is a schematic diagram to describe an example of filling by the epitaxial growth filling method in the first example and the second example of the semiconductor device according to the first embodiment, that is, in the case where the angular error between the extending direction (x direction) of the trench DT and the <11-20> direction is within ±θ.

[0084] At an initial stage of epitaxial growth, the semiconductor layer SM grows from the bottom of the trench DT and the upper surface of the convex portion of the epitaxial layer EP, and the interior of the trench DT is gradually filled. Furthermore, since the angular error between the extension direction (x direction) of the trench DT and the <11-20> direction is within ±θ, the inclination of the growth direction of the semiconductor layer SM is small even as the epitaxial growth progresses, and the interior of the trench DT can be filled with the semiconductor layer SM before the top portion and both end portions in the extension direction of the trench DT are closed.

[0085] Since voids are less likely to form in the trench DT, the reduction in production yield due to backfill failure can be prevented. The reliability of the semiconductor device can also be improved. <<Ausgestaltung einer Halbleitervorrichtung> >

[0086] The semiconductor device according to the first embodiment will be described with reference to Fig. 4 and Fig. 5 described. Fig. 4 is a plan view showing the configuration of the semiconductor device according to the first embodiment. Fig. 5 is a line AA' in Fig. 4 taken cross-sectional view.

[0087] As in Fig. As shown in Figure 4, the semiconductor chip SC according to the first embodiment has a rectangular shape and includes a cell region (also referred to as an active region) CR, a transition region TR, and a peripheral region (also referred to as a peripheral region) PER. The transition region TR is arranged to surround the exterior of the cell region CR, and the peripheral region PER is arranged to surround the transition region TR. In other words, the cell region CR is arranged in an inner region surrounded by the peripheral region PER via the transition region TR.

[0088] For example, in the cell region CR, a plurality of power MOSFETs with a superjunction structure are formed, which serve as switching elements. On the other hand, in the peripheral region PER, a peripheral structure is formed, embodied by a chamfer structure, a diffusion ring structure, a field ring structure, or a field plate structure that diagonally etches the periphery. These peripheral structures are fundamentally formed based on a design concept that reduces the likelihood of avalanche breakdown phenomena due to electric field concentration.

[0089] As described above, in the semiconductor chip SC according to the first embodiment, the plurality of power MOSFETs having the superjunction structure are formed in the inner region including the central region, and the peripheral structure, which is the electric field relaxation structure, is formed in the outer region surrounding the inner region.

[0090] The structure of each of the cell area CR, the transition area TR and the peripheral area PER is described below. (1) Structure of the cell area CR

[0091] As in Fig. As shown in Figure 5, the cell region CR has the superjunction structure in which the p-type pillar regions PC and the n-type pillar regions NC extending in the x-direction are alternately arranged in the y-direction orthogonal to the x-direction along the main surface of the substrate SUB in the epitaxial layer on the main surface of the substrate SUB. Further, as described above, the angular error between the extending direction (x-direction) of the plurality of trenches DT in which the plurality of p-type pillar regions PC are formed and the <11-20> direction is within ±θ. θ is determined as described above in (Finding E).

[0092] In the first embodiment, the cell region CR is exemplified in which the ratio between the width of the p-type pillar region PC in the y-direction and the width of the n-type pillar region NC in the y-direction is 1:1; but the cell region CR is not limited to this, and the width of the p-type pillar region PC in the y-direction and the width of the n-type pillar region NC in the y-direction may be different from each other.

[0093] The specific description is given below. The epitaxial layer EP is formed on the main surface of the substrate SUB, which is made of silicon carbide (SiC) containing an impurity or an n-type impurity such as nitrogen (N), phosphorus (P), or arsenic (As). The epitaxial layer EP is composed of a semiconductor layer (S layer) containing silicon carbide (SiC) in which an n-type impurity such as nitrogen (N), phosphorus (P), or arsenic (As) is introduced as a main component, and has the same crystal structure as that of the substrate SUB. The n-type impurity concentration of the epitaxial layer EP is lower than that of the substrate SUB, and is, for example, 3.0 × 10 16 / cm 3 .

[0094] In addition, the plurality of p-type pillar regions PC are formed in the epitaxial layer EP such that they are spaced apart from each other in the y-direction. Each of the p-type pillar regions PC is composed of a semiconductor layer (SiC layer) into which a p-type impurity such as aluminum (Al) or boron (B) is introduced. The semiconductor layer is a crystal layer having the same crystal structure as the epitaxial layer EP, and the p-type impurity concentration of the p-type pillar region PC is, for example, 3.0 × 10 16 / cm 3 A portion of the epitaxial layer EP located between the adjacent p-type column regions PC serves as the n-type column region NC. A drain region of the power MOSFET consists of the epitaxial layer EP containing the plurality of n-type column regions NC and the substrate SUB.

[0095] An element region is further formed on the upper surface of the epitaxial layer EP in which the superjunction structure is formed.

[0096] In the element region, a channel region CH is formed in contact with the p-type pillar region PC on the upper surface of the epitaxial layer EP, and a source region SR is formed to be enclosed in the channel region CH. At this time, the channel region CH is composed of a semiconductor region into which a p-type impurity such as aluminum (Al) or boron (B) is introduced, and the source region SR is composed of a semiconductor region into which an n-type impurity such as nitrogen (N), phosphorus (P), or arsenic (As) is introduced. In addition, a body contact region BC, which reaches the channel region CH from the upper surface of the epitaxial layer EP, is formed in the central part of the source region SR.The body contact region BC is composed of a semiconductor region into which a p-type impurity such as aluminum (Al) or boron (B) is introduced, and the impurity concentration of the body contact region BC is higher than the impurity concentration of the channel region CH.

[0097] Furthermore, a gate insulating film GI is formed on the region sandwiched between the adjacent channel regions CH, and a gate electrode GE is formed on the gate insulating film GI. The gate insulating film GI is formed of, for example, a silicon oxide film; but the gate insulating film GI is not limited to this and may be formed of, for example, a high-dielectric-constant film having a higher dielectric constant than a silicon oxide film. Further, the gate electrode GE is formed of, for example, a polycrystalline silicon film. This gate electrode GE is formed to be aligned with the source region SR. An interlayer insulating film IL made of, for example, silicon oxide is formed to cover a top surface and a sidewall of the gate electrode GE.

[0098] A source electrode SE is formed over the interlayer insulating film IL, which covers the plurality of gate electrodes GE. The source electrode SE is formed from a stacked film of a barrier conductor film, such as titanium tungsten (TiW) and an aluminum (Al) film. Accordingly, the source electrode SE is electrically connected to the source region SR and is also electrically connected to the channel region CH via the body contact region BC.

[0099] At this time, the body contact region BC has a function to ensure the ohmic contact with the source electrode SE, and the source region SR and the channel region CH are electrically connected at the same potential due to the presence of the body contact region BC.

[0100] Therefore, it is possible to suppress the ON operation of the parasitic NPN bipolar transistor, which has the source region SR as the emitter region, the channel region CH as the base region, and the n-type column region NC as the collector region. The electrical connection between the source region SR and the channel region CH at the same potential means that no potential difference is generated between the emitter region and the base region of the parasitic NPN bipolar transistor, and thus it is possible to suppress the ON operation of the parasitic NPN bipolar transistor.

[0101] A surface protection film PAS, made of silicon oxide, for example, is formed to partially cover the source electrode SE, and a portion of the source electrode SE is exposed by the surface protection film PAS. A drain electrode DE made of metal is also formed on a back surface (the surface opposite the main surface on which the epitaxial layer EP is formed) of the semiconductor substrate SUB.

[0102] In the manner described above, the plurality of power MOSFETs having the superjunction structure are formed in the cell region CR. (2) Structure of the transition area TR

[0103] As in Fig. As shown in Figure 5, the junction region TR also has the superjunction structure in which the plurality of p-type pillar regions PC and the plurality of n-type pillar regions NC composed of the epitaxial layer EP are alternately arranged in the y-direction. Furthermore, as described above, the angular error between the extension direction (x-direction) of the plurality of trenches DT in which the plurality of p-type pillar regions PC are formed and the <11-20> direction is within ±θ. θ is determined herein as described above in (Finding E).

[0104] The concrete description is given below. As with the cell region CR, the plurality of p-type pillar regions PC and the plurality of n-type pillar regions NC are also similarly formed in the junction region TR. Further, on the channel region CH, via the gate insulating film GI, a gate lead-out region GPU composed of the polycrystalline silicon film is formed in the same layer as the gate electrode GE of the cell region CR. Further, the interlayer insulating film IL is formed to cover an upper surface and a sidewall of the gate lead-out region GPU, and an opening exposing a part of the upper surface of the gate lead-out region GPU is formed in a part of the interlayer insulating film IL.

[0105] A gate lead-out electrode GPE, composed of the stacked film, in the same layer as the source electrode SE of the cell region CR is also formed on the interlayer insulating film IL enclosing the interior of the opening. Here, the gate lead-out region GPU is electrically connected to the plurality of gate electrodes GE, and the gate voltage applied to the gate lead-out electrode GPE is applied to each of the plurality of gate electrodes GE through the gate lead-out region GPU.

[0106] Further, on the upper surface of the epitaxial layer EP, the channel region CH is formed, extending from the cell region CR, and a source lead-out region SPR is formed to be enclosed within the channel region CH. Furthermore, on the upper surface of the epitaxial layer EP, the interlayer insulating film IL is formed to cover the channel region CH, and an opening is formed in the interlayer insulating film IL to expose the source lead-out region SPR. A source lead-out electrode SPE, composed of the stacked film in the same layer as the gate lead-out electrode GPE, is formed on the interlayer insulating film IL, enclosing the interior of the opening.

[0107] Also in the transition region TR, the surface protection film PAS, which is made of, for example, silicon oxide, is formed to partially cover the gate lead-out electrode GPE and the source lead-out electrode SPE, and a partial area of ​​the gate lead-out electrode GPE and a partial area of ​​the source lead-out electrode SPE are exposed from the surface protection film PAS.

[0108] The transition structure is formed in the transition region TR in the manner described above. (3) Structure of the peripheral area PER

[0109] As in Fig. As shown in Figure 5, the peripheral region PER also has the superjunction structure in which the plurality of p-type pillar regions PC and the plurality of n-type pillar regions NC composed of the epitaxial layer EP are alternately arranged in the y-direction. Furthermore, as described above, the angular error between the extension direction (x-direction) of the plurality of trenches DT in which the plurality of p-type pillar regions PC are formed and the <11-20> direction is within ±θ. Here, θ is determined as described above in (Finding E).

[0110] The concrete description is given below. As in the cell region CR, the plurality of p-type pillar regions PC and the plurality of n-type pillar regions NC are also similarly formed in the peripheral region PER. Further, a plurality of dummy electrodes FE formed of the polycrystalline silicon film are formed in the same layer as the gate electrode GE of the cell region CR on the upper surface of the epitaxial layer EP via the silicon oxide film in the same plane as the gate insulating film GI of the cell region CR. In addition, the interlayer insulating film IL is formed on the upper surface of the epitaxial layer EP so as to cover an upper surface and a sidewall of the plurality of dummy electrodes FE.

[0111] The surface protection film PAS, which consists of silicon oxide, for example, is also formed in the peripheral area PER.

[0112] In the manner described above, the peripheral structure is formed in the peripheral area PER. <<Herstellungsverfahren einer Halbleitervorrichtung> >

[0113] An example of a manufacturing method of a semiconductor device according to the first embodiment will be described with reference to Fig. 6 to 14 described. Fig. 6 to 14 are cross-sectional views illustrating a manufacturing process of the semiconductor device according to the first embodiment.

[0114] First, as in Fig. As shown in Figure 6, the substrate (thin plate having an approximately circular shape in plan view, referred to as a wafer) SUB is prepared with a main surface (front surface, upper surface) on which a low-concentration epitaxial layer EP composed of an n-type semiconductor layer is formed. The substrate SUB is made of, for example, a hexagonal SiC single crystal of 4H polytype or 6H polytype and has the main surface whose (0001) surface is tilted by 4° in the <11-20> direction. Therefore, the epitaxial layer EP is also made of a SiC single crystal and has the same crystal structure as the substrate SUB.

[0115] An n-type impurity such as nitrogen (N), phosphorus (P), or arsenic (As) is introduced into the epitaxial layer EP. The n-type impurity concentration of the epitaxial layer EP is, for example, approximately 3.0 × 10 16 / cm3 , and the thickness of the epitaxial layer EP is, for example, about 20 µm to 30 µm.

[0116] As in Fig. Next, as shown in Fig. 7, the plurality of trenches DT extending in the x-direction and spaced apart from each other in the y-direction are formed in the epitaxial layer EP in the cell region CR, the junction region TR, and the peripheral region PER by, for example, the selective etching method using a pattern made of an insulating material as a hard mask.

[0117] The depth of the trench DT from the top surface of the epitaxial layer EP is, for example, 5 µm or more, and a trench DT with an aspect ratio of about 10 and a depth of about 20 µm from the top surface of the epitaxial layer EP can be exemplified. Furthermore, by setting the taper angle of the trench DT to, for example, about 88° to 90°, the concentration distribution of the semiconductor layer in the filling region can be improved.

[0118] The direction of extension (x-direction) of the trench DT also exhibits an angular error within ± θ with respect to the <11-20> direction. θ is determined here as described above in (Finding E).

[0119] The method for forming the trench DT differs depending on the specification of the previously prepared substrate SUB, and the following first method (the first example described with reference to Fig. 1) and second method (the second example described with reference to Fig. 2) can be cited as examples.

[0120] First method: When preparing the substrate SUB, the substrate SUB is prepared in which the angular error between the orientation flat direction and the <11-20> direction is within ±θ1 (θ1: first angular error). The standard specification of the angular error of the SiC substrate currently available is up to ±5°. On the other hand, when filling the deep trench DT with a depth greater than 10 µm, for example, a specially designed substrate SUB in which the angular error is within ±0.5° must be prepared in the first method.

[0121] Next, in the exposure apparatus, exposure is performed to form an etching pattern of the trench DT using a photomask (reticle). Here, it is assumed that the angular error (θ2: second angular error) due to the offset between the photomask and the substrate SUB caused by the exposure apparatus is sufficiently small relative to the first angular error or is corrected by preliminary measurement and adjustment of the exposure apparatus. Namely, in the exposure process, it is assumed that the second angular error is sufficiently smaller than the first angular error (θ2 << θ1).

[0122] As described above, in the first method, the angular error between the extending direction (x-direction) of the trench DT and the <11-20> direction is set within ± θ by preparing the substrate SUB in which the first angular error is within ± θ as described above in (Finding E).

[0123] Second method: In this case, when preparing the substrate SUB, the substrate SUB is prepared with a standard specification for the angular error between the orientation flat direction and the <11-20> direction. For example, the angular error of the SiC substrate with the currently available standard specification is within ± 5°.

[0124] Next, defect data is obtained by measuring the angular error (first angular error) between the orientation flat direction and the <11-20> direction using X-ray diffraction or the like. The angular error measurement can be performed by batch processing for each crystal ingot from which the substrate SUB is cut, or it can be performed for each individual piece of the substrate SUB. The former is more advantageous in terms of fewer measurements; but batch management of the substrate SUB is required. Since the latter performs measurements for individual pieces, an in-line measuring device or the like is necessary; but strict management is possible because the measurement is performed for each individual piece. The angular error measurement described above can be performed by a semiconductor device manufacturer.Alternatively, the substrate SUB may be prepared in such a way that a third party such as a substrate manufacturer measures the angular error and the substrate SUB, whose error data has been specified, is delivered to the manufacturer.

[0125] Furthermore, in the exposure process, an angle correction is performed on the orientation flat by the exposure apparatus using the error data obtained in advance described above. As described in the first method, θ2 << θ1 is satisfied as a prerequisite in the exposure apparatus to be used. In this way, the angle error between the extending direction (x direction) of the trench DT and the <11-20> direction is set within ±θ. However, it is assumed that the angle error between the direction of the orientation flat of the substrate SUB prepared in advance and the <11-20> direction is within a range that can be corrected in the exposure apparatus.

[0126] Combined Use of the First and Second Methods: The combined use of the first and second methods described above is effective depending on the required θ. In this case, the substrate SUB having the first angular error smaller than the standard specification is prepared, error data of the first angular error is measured, and angle correction is performed using the error data in the exposure device. According to this method, since θ can be made small, it is possible to manage the filling of the trench DT with an extremely high aspect ratio (for example, an aspect ratio of 10 or more), and it is possible to obtain an effect that the distribution of the impurity concentration in the filling crystal region inside the trench DT is uniform regardless of the aspect ratio.

[0127] To form the trench DT, an ICP etching system, for example, is used. Furthermore, it is desirable that the temperature of the lower electrode, on which the substrate SUB is mounted, be controlled at 50°C or more during etching, thus making it possible to form the trenches DT of a desired shape with satisfactory reproducibility and uniformity.

[0128] Next, as in Fig. As shown in FIG. 8, a p-type semiconductor layer, which is a crystal layer having the same crystal structure as the epitaxial layer EP, is formed within the plurality of trenches DT formed in the epitaxial layer EP in the cell region CR, the junction region TR, and the peripheral region PER, by, for example, the epitaxial growth filling method. Subsequently, the p-type semiconductor layer grown on the upper surface of the epitaxial layer EP (n-type pillar region NC) separating the adjacent trenches DT is ground and further polished by, for example, the CMP (chemical mechanical polishing) method, whereby the p-type pillar regions PC composed of the p-type semiconductor layer are formed only in the plurality of trenches DT.The part between the trenches DT, which are spaced apart in the y-direction, serves as the n-type pillar region NC, which consists of the epitaxial layer EP.

[0129] Since the angular error between the extending direction of the plurality of trenches DT and the <11-20> direction is within ± θ, even in the case that the trench DT has the aspect ratio of about 10, the upper portion and the two end portions of the trench DT are not closed, and the interior of the plurality of trenches DT can be filled with the p-type semiconductor layer without forming voids.

[0130] Furthermore, in the epitaxial growth method, it is possible to fill the interior of the plurality of trenches DT with the p-type semiconductor layer with satisfactory reproducibility by controlling the gas types, gas flow rate, temperature, pressure, and the like. For example, a silicon (Si) source gas, a carbon (C) source gas, hydrogen (H2) gas, hydrogen chloride (HCl) gas, and a dopant gas are used as the gas types. For example, monosilane (SiH4) gas or the like is used as the silicon (Si) source gas. For example, ethylene (C2H4), methylacetylene (C3H4), propane (C3H8), or the like is used as the carbon (C) source gas. When aluminum (Al) is selected as the p-type dopant, trimethylaluminum (TMA), triethylaluminum (TEA), or the like is also used as the dopant gas.

[0131] As the conditions of the epitaxial growth filling method, the HCl / SiH4 flow ratio is, for example, 30 or more and 65 or less, and the H2 / SiH4 flow ratio is, for example, 500 or more and 7,000 or less.

[0132] Fig. Figure 21 is a graph showing an example of filling in cases where the HCl / SiH4 flow ratio in the epitaxial growth filling method is 33.3, 50, and 66.7. The H2 / SiH4 flow ratio is 5000.

[0133] As in Fig. As shown in Figure 21, when the HCl / SiH4 flow ratio is 33.3, the interior of the trench DT is satisfactorily filled with the p-type semiconductor layer. However, when the HCl / SiH4 flow ratio is less than 30, the upper portion of the trench DT tends to close, and voids are generated. On the other hand, when the HCl / SiH4 flow ratio is greater than 65, the etching becomes excessive, and the shape of the initial trench DT collapses. When the H2 / SiH4 flow ratio is less than 500, surface bunching also becomes considerable. On the other hand, when the H2 / SiH4 flow ratio is greater than 7000, excessive etching occurs or voids are generated.

[0134] Furthermore, the pressure in the growth furnace during epitaxial growth is set to, for example, 30 kPa or more and 100 kPa or less.

[0135] Fig. 22 is a diagram showing an example of backfilling in the case where, in the epitaxial growth filling method, the pressure in the growth furnace during epitaxial growth is 10 kPa.

[0136] As in Fig. As shown in Figure 22, at pressures lower than 30 kPa, which is the lower limit pressure, the etching becomes excessively severe, particularly on the lateral surface of the trench DT, and the shape of the original trench DT collapses. On the other hand, although it is desirable for the upper limit pressure to be high, atmospheric pressure is the upper limit pressure for performing safe epitaxial growth in a quartz furnace.

[0137] Note that the epitaxial growth filling process conditions can be changed during epitaxial growth, and the dopant gas flow rate, SiH4 flow rate, and carbon / silicon (C / Si) ratio can be changed as needed. This makes it possible to uniformly distribute the concentration of the p-type semiconductor layer in the filling region.

[0138] The p-type impurity concentration, the width, and the pitch of the p-type column region PC in each of the cell region CR, the junction region TR, and the peripheral region PER are also adjusted to achieve charge balance. The semiconductor device according to the first embodiment exemplifies a case where the ratio of the width of the p-type column region PC in the y-direction to the width of the n-type column region NC in the y-direction is 1:1. In this case, the p-type impurity concentration of the p-type column region PC is adjusted so that the total charge amount of the p-type column region PC and the total charge amount of the n-type column region NC are the same.Therefore, the p-type impurity concentration of the p-type pillar region PC is the same as the n-type impurity concentration of the epitaxial layer EP forming the n-type pillar region NC, and is, for example, about 3.0 × 10. 16 / cm 3 .

[0139] In the manner described above, according to the first embodiment, the superjunction structure in which the p-type pillar region PC and the n-type pillar region NC are alternately formed is formed in the epitaxial layer EP by the “trench filling method”.

[0140] Next, a process for forming the element region on the upper surface of the epitaxial layer EP in which the superjunction structure has been formed will be described.

[0141] As in Fig. As shown in Figure 9, after the upper surface of the epitaxial layer EP is planarized, the channel region CH is formed in the cell region CR and the junction region TR by, for example, the selective ion implantation method using a pattern made of an insulating material as a hard mask. The channel region CH is a p-type semiconductor region formed by, for example, introducing a p-type impurity such as aluminum (Al) or boron (B) into the epitaxial layer EP.

[0142] Next, the plurality of source regions SR are formed in the cell region CR by, for example, the selective ion implantation method using a pattern made of an insulating material as a hard mask, and the source lead-out region SPR is formed in the junction region TR. The source region SR and the source lead-out region SPR are n-type semiconductor regions formed by introducing an n-type impurity such as nitrogen (N), phosphorus (P), or arsenic (As) into the epitaxial layer EP. The plurality of source regions SR formed in the cell region CR are electrically connected to the source lead-out region SPR formed in the junction region TR.

[0143] Next, the body contact region BC, whose bottom reaches the channel region CH, is formed in the central part of each of the plurality of source regions SR in the cell region CR by, for example, the selective ion implantation method using a pattern made of an insulating material as a hard mask. The body contact region BC is a p-type semiconductor region formed by, for example, introducing a p-type impurity such as aluminum (Al) or boron (B) into the epitaxial layer EP, and is formed such that the impurity concentration of the body contact region BC is higher than the impurity concentration of the channel region CH.

[0144] Note that in a sequence of the ion implantation processes described above, ion implantation can be performed while setting the temperature of the substrate SUB to 300°C or higher to suppress defects caused by ion implantation. Furthermore, although not described here, a termination structure can be formed by performing ion implantation to ensure a high withstand voltage.

[0145] Next, after a series of ion implantation processes, a capping layer to prevent surface roughness, such as a carbon film with a thickness of 1 µm or more, is deposited on the upper surface of the epitaxial layer EP by sputtering or the like, and a heat treatment is performed at a temperature of approximately 1600°C to 1800°C to activate the impurity. The capping layer is then removed.

[0146] Next, as in Fig. As shown in Figure 10, the gate insulating film GI is formed on the upper surface of the epitaxial layer EP, and a conductor film PF is formed on the gate insulating film GI. The gate insulating film GI is made of, for example, silicon oxide and is formed by, for example, the thermal oxidation method. However, the gate insulating film GI is not limited to a silicon oxide film and may be a high-dielectric-constant film having a higher dielectric constant than a silicon oxide film, typically embodied by a hafnium oxide film. On the other hand, the conductor film PF formed on the gate insulating film GI is made of, for example, polycrystalline silicon and is formed by, for example, the CVD (chemical vapor deposition) method.

[0147] Next, as in Fig. As shown in Figure 11, the conductive film PF is patterned by, for example, the selective etching method using a resist pattern as a mask. As a result, the plurality of gate electrodes GE are formed in the cell region CR, the gate lead-out region GPU is formed in the junction region TR, and the plurality of dummy electrodes FE are formed in the peripheral region PR. The gate lead-out region GPU is formed to be electrically connected to the plurality of gate electrodes GE.

[0148] Next, the interlayer insulating film IL, which covers the plurality of gate electrodes GE, the gate lead-out region GPU, and the plurality of dummy electrodes FE, is formed on the upper surface of the epitaxial layer EP. The interlayer insulating film IL is made of, for example, silicon oxide and is formed using, for example, the CVD method.

[0149] Next, by selective etching, for example, using a resist pattern as a mask, openings whose bottoms reach the source region SR and the body contact region BC are formed between the adjacent gate electrodes GE in the cell region CR in the interlayer insulating film IL, and an opening exposing a part of the gate lead-out region GPU is formed in the junction region TR. Furthermore, the source lead-out region SPR is exposed in the junction region TR by forming an opening in the interlayer insulating film IL.

[0150] As in Fig. As shown in Figure 12, a metal film is formed on the interlayer insulating film IL, including the openings exposing the source region SR and the body contact region BC, the opening exposing the gate lead-out region GPU, and the opening exposing the source lead-out region SPR. The metal film is formed from a stacked film of, for example, a titanium tungsten (TiW) film and an aluminum (Al) film, and is formed by, for example, the sputtering method.

[0151] The metal film is then patterned, for example, by selective etching using a resist pattern as a mask. As a result, the source electrode SE, which is electrically connected to the source region SR and the body contact region BC, is formed in the cell region CR, and the gate lead-out electrode GPE, which is electrically connected to the gate lead-out region GPU, and the source lead-out electrode SPE, which is electrically connected to the source lead-out region SPR, are formed in the junction region TR.

[0152] As in Fig. Next, as shown in Figure 13, a surface protection film PAS is formed to cover the source electrode SE, the gate lead-out electrode GPE, and the source lead-out electrode SPE. The surface protection film PAS is then patterned by, for example, the selective etching method using a resist pattern as a mask, thereby exposing a partial region of the source electrode SE, a partial region of the gate lead-out electrode GPE, and a partial region of the source lead-out electrode SPE. Thus, the regions exposed by the surface protection film PAS can serve as external connection regions.

[0153] As in Fig. Next, as shown in Figure 14, the substrate SUB is thinned by grinding the substrate SUB from the back surface on a side opposite the main surface of the substrate SUB. A metal film to form the drain electrode DE is then formed on the back surface of the substrate SUB using the sputtering method or the deposition method. Afterward, laser annealing, for example, is performed at approximately 1000°C, corresponding to the heat treatment, to obtain the low-resistance contact.

[0154] In the manner described above, the semiconductor device including the power MOSFET with the superjunction structure according to the first embodiment can be manufactured.

[0155] In the first embodiment, the SiC single-crystal substrate having the main surface (off angle) whose (0001) surface is tilted by 4° in the <11-20> direction is exemplified; however, the SiC substrate is not limited to this. For example, a SiC single-crystal substrate having the main surface whose (0001) surface is tilted by 1° or more and 5° or less in the <11-20> direction may be used. Alternatively, a SiC single-crystal substrate having an off angle in a main crystal surface of a (000-1) surface may be used instead of the (0001) surface.

[0156] Further, a hexagonal SiC single-crystal substrate having a main surface whose main crystal surface is tilted in the <11-20> direction is exemplified; however, the SiC substrate is not limited to this. For example, a hexagonal SiC single-crystal substrate having a main surface whose main crystal surface is tilted in the <1-100> direction orthogonal to the <11-20> direction may be used. If necessary, the crystal direction in which the off-angle is provided may be in any direction other than those described above. Therefore, a predetermined crystal direction in which the off-angle is provided, such as the <11-20> direction, is generally referred to as a reference crystal direction.

[0157] Further, as a hexagonal SiC single crystal substrate, a 4H polytype SiC substrate (4H-SiC) that is currently established or popular is exemplified; but the present invention can be applied even if a 6H polytype SiC substrate (6H-SiC) having an off angle is used.

[0158] There is also a possibility that the present invention can be similarly applied to other wide band-gap compound semiconductors such as nitrogen gallium or gallium nitride (GaN) as a hexagonal substrate. Furthermore, there is a possibility that the present invention can be applied to the similar problem even if a crystal structure is different, such as in 3C-SiC, gallium oxide (Ga2O3), or the like.

[0159] In addition, in the above-described <<Herstellungsverfahren einer Halbleitervorrichtung> > The orientation flat OF is used as a reference mark with respect to the <11-20> direction. Incidentally, in a 4-inch SiC substrate currently commercially available, a reference mark is provided, which is referred to as a primary flat or a secondary flat. Accordingly, the orientation flat is a generic term that includes the primary flat and the secondary flat. In a large-sized Si substrate, a notch is also used as the similar reference mark in some cases. Therefore, the orientation flat OF described in the first embodiment more generally means a reference mark for indicating a specific crystal orientation provided in the substrate.

[0160] As described above, the angular error between the trench DT extension direction and the <11-20> direction is set within ±θ. θ is determined as described above in (Finding E). Accordingly, when the power MOSFET having the superjunction structure in which the p-type source region PC and the n-type pillar region NC are alternately arranged is formed by the trench filling method, the interiors of the plurality of trenches DT can be advantageously filled without forming voids. As a result, the production yield and reliability of the semiconductor device can be improved.

[0161] In addition to the inventions described in the claims, the inventions described below in [Appendix A] and [Appendix B] can be understood from the above first embodiment. Furthermore, inventions corresponding to combinations of these inventions and the inventions described in the claims can also be understood. [Appendix A]

[0162] A semiconductor device comprising: a substrate having a main surface on which an off-angle is provided that is inclined in a predetermined reference crystal direction (for example, <11-20> direction or <1-100> direction) with respect to a predetermined main crystal surface (for example, (0001) surface or (000-1) surface); a plurality of trenches provided in the substrate so as to extend in a first direction along the main surface of the substrate and to be spaced apart from each other in a second direction orthogonal to the first direction along the main surface of the substrate; a first pillar region provided within each of the trenches and composed of a crystal layer having the same crystal structure as the substrate;and a second pillar region consisting of a part of the substrate between the trenches adjacent to each other in the second direction, wherein an angular error between the reference crystal direction and the first direction is within ± θ and, when a depth of the trench is h, a width of the trench is w, and k is a coefficient greater than 0 and less than 2, the θ is determined by θ = {arctan {k × (w / h)}} / 13.; [Appendix B]

[0163] The semiconductor device according to [Appendix A], wherein the trench has a tapered shape that becomes narrower as one goes deeper, and a taper angle formed by a bottom surface and a side surface of the trench is 88° to 90°. (Second embodiment)

[0164] A semiconductor device according to the second embodiment will be described with reference to Fig. 15 and Fig. 16 described. Fig. 15 is a plan view showing a plurality of trenches formed in a substrate according to the second embodiment. Fig. 16 is an enlarged cross-sectional view showing an end portion of the trench formed in the substrate according to the second embodiment. (1) First feature and its effect

[0165] As in Fig. As shown in Figure 15, the plurality of trenches DT forming the superjunction structure are formed in the epitaxial layer EP. The plurality of trenches DT extend in the x-direction and are spaced apart from each other in the y-direction, and the plurality of trenches DT are filled with a semiconductor layer by the epitaxial growth filling method.

[0166] Furthermore, in the central region A1 of the trench DT in the x-direction, the trench DT has a constant width in the y-direction in plan view; however, in a first tip region B1 and a second tip region B2 at both end regions of the trench DT in the x-direction, the lateral surfaces of the trench DT are inclined with respect to the x-direction in plan view, and the width in the y-direction gradually decreases as one approaches the outer periphery of the semiconductor device. The shape in which the lateral surfaces of the trench DT are inclined with respect to the x-direction in plan view is referred to as a "tapered shape."

[0167] As in the first embodiment described above, the angular error between the extending direction of the groove DT (x-direction) and the <11-20> direction is within ±θ. θ is determined herein as described above in (Finding E).

[0168] As in Fig. 16, at the first tip region B1 and the second tip region B2 of the trench DT, the bottom surface of the trench DT is also inclined with respect to the top surface of the epitaxial layer EP (horizontal surface formed by the x-direction and the y-direction), and the width in the z-direction gradually decreases as one approaches the outer periphery of the semiconductor device.

[0169] When the trench DT is filled with the semiconductor layer SM using the epitaxial growth filling method, silicon (Si) or carbon (C) contained in the source gas is more consumed at the first tip region B1 and the second tip region B2 of the trench, and the trench DT is less likely to be successfully filled with the semiconductor layer SM at the tip regions B1 and B2 compared with the central region A1 of the trench DT.However, in the second embodiment, since the side surfaces and the bottom surface of the trench DT are inclined at the first tip region B1 and the second tip region B2 of the trench DT, the volume of the trench DT gradually decreases as one approaches the outer periphery of the semiconductor device, so that the inside of the trench DT can be filled with the semiconductor layer SM even if the semiconductor layer SM is reduced for filling the trench DT by the epitaxial growth filling method. (2) Second feature and its effect

[0170] As in Fig. As shown in Figure 15, a length L1 of the first tip portion B1 of the trench DT in the x-direction and a length L2 of the second tip portion B2 of the trench DT in the x-direction are different from each other, and the length L1 of the first tip portion B1 located in the <11-20> direction is shorter than the length L2 of the second tip portion B2 located in the direction opposite to the <11-20> direction. In other words, an angle θ 11 formed between the lateral surface of the first tip region B1 located in the <11-20> direction and the x-direction is greater than an angle θ 12 formed between the lateral surface of the second tip region B2 located in the direction opposite to the <11-20> direction and the x-direction.

[0171] When the trench DT is filled with the semiconductor layer using the epitaxial growth filling method, the second peak region B2 located in the direction opposite to the <11-20> direction is less likely to be successfully filled with the semiconductor layer than the first peak region B1 located in the <11-20> direction. Accordingly, there is a concern that the first peak region B1 located in the <11-20> direction and the second peak region B2 located in the direction opposite to the <11-20> direction may not be successfully filled with the semiconductor layer in approximately the same time.

[0172] However, in the second embodiment, the first peak region B1 located in the <11-20> direction and the second peak region B2 located in the direction opposite to the <11-20> direction are formed to have different shapes. Furthermore, the second peak region B2 located in the direction opposite to the <11-20> direction is formed to have a shape that can be filled with the semiconductor layer more easily than the first peak region B1 located in the <11-20> direction, so that the first peak region B1 located in the <11-20> direction and the second peak region B2 located in the direction opposite to the <11-20> direction can be filled with the semiconductor layer at approximately the same time. (3) Third feature and its effect

[0173] As in Fig. As shown in Figure 15, a first dummy pattern DTR1 of a trench is formed between the first tip regions B1 of the trenches DT that are adjacent to each other in the y-direction, and a second dummy pattern DTR2 of a trench is formed between the second tip regions B2 of the trenches DT that are adjacent to each other in the y-direction. Furthermore, each of the first dummy patterns DTR1 and the second dummy patterns DTR2 is filled with the semiconductor layer by the epitaxial growth method.

[0174] The first dummy pattern DTR1 is arranged to be spaced from the first tip regions B1 of the trenches DT that are adjacent to each other in the y-direction, and the second dummy pattern DTR2 is arranged to be spaced from the second tip regions B2 of the trenches DT that are adjacent to each other in the y-direction.

[0175] The shapes of the first dummy pattern DTR1 and the second dummy pattern DTR2 are triangular in plan view. A side surface of the first dummy pattern DTR1, which is opposite to the side surface of the first tip region B1 of the trench DT, is formed to be parallel to the side surface of the first tip region B1, and a side surface of the second dummy pattern DTR2, which is opposite to the side surface of the second tip region B2 of the trench DT, is formed to be parallel to the side surface of the second tip region B2.

[0176] The inventors investigated, as a comparative example, the technology of forming a plurality of trenches in a substrate made of Si (silicon) single crystal (hereinafter referred to as a Si single crystal substrate) and filling the interior of the plurality of trenches with a semiconductor layer by the epitaxial growth filling method. In this case, with respect to the semiconductor layer filled in the trenches DT, the influence due to the presence or absence of the dummy pattern was not noticeably apparent. However, in the case of the SiC single crystal substrate, the influence due to the presence or absence of the dummy pattern was noticeably apparent with respect to the semiconductor layer filled in the trenches DT, and more preferential filling of the semiconductor layer was achieved when the first dummy pattern DTR1 and the second dummy pattern DTR2 were provided. (4) Modification

[0177] A semiconductor device according to a modification of the second embodiment will be described with reference to Fig. 17 described. Fig. 17 is a plan view showing a plurality of trenches formed in a substrate according to the modification of the second embodiment.

[0178] As in Fig. As shown in Figure 17, the shapes of the first dummy pattern DTR1 and the second dummy pattern DTR2 may be trapezoidal in plan view. Also in this case, the side surface of the first dummy pattern DTR1 opposite to the side surface of the first tip portion B1 of the trench DT is formed to be parallel to the side surface of the first tip portion B1, and the side surface of the second dummy pattern DTR2 opposite to the side surface of the second tip portion B2 of the trench DT is similarly formed to be parallel to the side surface of the second tip portion B2.

[0179] Fig. 29(a), Fig. 29(b) and Fig. 29(c) are plan views showing modifications of the tip shape of the trench in the second embodiment and the modification of the second embodiment. Fig. 29(a), Fig. 29(b) and Fig. 29(c) show the modifications of the tip shape of the trench DT in Fig. 15 and Fig. 17. It is assumed that the Fig. 15 has a shape in which the tip ends are cut off at the first and second tip regions (a shape with a finite width at the tip end).

[0180] Meanwhile, the trench DT in Fig. 29(a) has a pointed tip shape (ideally a shape with zero width at the tip end) and is otherwise the same as that in Fig. 15. Note that in the case where the trench is formed by an ordinary method using a photomask having a pattern with the pointed tip shape as in Fig. 29(a), the resulting trench DT has a blunt shape with a finite width at the tip end due to the dullness of the pattern that occurs in the photomask process and the inertia in the etching process, as shown in Fig. 15.

[0181] For this reason, the shape of the tip, which is as sharp as possible, is used in Fig. 29(a) using a technique such as optical proximity correction (OPC). Regarding the first tip region B1 of the trench DT and the second tip region B2 of the trench DT, which are shown in Fig. 29(a), it is assumed that the angles formed between their lateral surfaces and the x-direction (here angles from the center line) θ 11 or θ 12 By using the Fig. 29(a), the slope growth at the mesa top is determined according to the angle θ 11 and the angle θ 12 promoted, and it is possible to suppress the recess (recess) at the end portion of the trench on the wafer surface after planarization

[0182] Fig. Fig. 29(b) shows an example in which a tip portion has a recess with a pointed tip. This is a case in which the recess with a pointed tip is formed in a direction similar to that in Fig. 29(a). Regarding the Fig. 29(a), the tip shape of the trench is defined here to have a “positive curvature” when viewed from the center line of the trench, and with respect to the condition shown in Fig. As shown in Figure 29(b), the tip shape of the trench is defined to have a “negative curvature” when viewed from the centerline of the trench.

[0183] Regarding the first tip area B1 of the trench DT and the second tip area B2 of the trench DT, which are Fig. 29(b), it is assumed that the angles formed between their lateral surfaces and the center line are θ 11 or θ 12 By adopting the shape in which the tip area has a recess with a Fig. 29(b), the diffusion of the source gas from the tip portion of the trench to the center of the trench is promoted, and it is possible to suppress the recess (recess) at the end portion of the trench on the wafer surface after planarization.

[0184] Fig. Figure 29(c) shows an example in which each tip region has an asymmetric shape with respect to the center line of the trench. This shape can also be considered as having a right-angled triangle at the tip region. With respect to the first tip region B1 of the trench DT and the second tip region B2 of the trench DT, which are shown in Fig. 29(c), it is assumed that the angles of the tip regions (angles of the right-angled triangles not in contact with the central region A1) θ 21 or θ 22 Although the shape of the trench in Fig. 29(c) is essentially a rhombus, it can also be trapezoidal. By Fig. 29(c), the same effect as in the above-described case of Fig. 29(a).

[0185] The appropriate range for θ 11 , θ 12 , θ 21 and θ 22 in Fig.29(a) to 29(c) is greater than θ determined by expression (7) and less than 90 degrees. It is preferably 45° or less, and more preferably 30° or less. As described in the section "(2) Second Feature and Its Effect" in the above (second embodiment), it is more preferable that the relationships θ 11 > θ 12 and θ 21 > θ 22 are fulfilled. (5) Appendix

[0186] The second embodiment includes at least the following embodiments, and inventions without conditions of the angular error θ are also included. Note that the invention of combining these inventions and the invention encompassed by the first embodiment described above is not excluded. [Appendix 1]

[0187] A semiconductor device comprising: a single crystal substrate having a main surface provided with an off-angle inclined in a predetermined reference crystal direction (for example, <11-20> direction or <1-100> direction) with respect to a predetermined main crystal surface (for example, (0001) surface or (000-1) surface); a plurality of trenches provided in the substrate so as to extend in a first direction along the main surface of the substrate and to be spaced apart from one another in a second direction orthogonal to the first direction along the main surface of the substrate; a first pillar region provided in the trench and consisting of a crystal layer having the same crystal structure as the substrate; and a second pillar region consisting of a part of the substrate between the trenches adjacent to each other in the second direction; wherein a first tip portion and a second tip portion located at both end portions of the trench in the first direction have a first width and a second width in the second direction, respectively, a central region of the trench between the first tip region and the second tip region has a third width in the second direction, and the first width and the second width are narrower than the third width. [Appendix 2]

[0188] The semiconductor device according to Appendix 1, wherein the first width and the second width gradually decrease as one goes toward an outer circumferential direction of the substrate. [Appendix 3]

[0189] The semiconductor device according to Appendix 1, wherein a length of the first tip portion in the first direction and a length of the second tip portion in the first direction are different from each other. [Appendix 4]

[0190] The semiconductor device according to Appendix 1, wherein a first dummy pattern is arranged between the first tip portions of the trenches adjacent to each other in the second direction so as to be spaced from the trenches, and a second dummy pattern is arranged between the second tip portions of the trenches adjacent to each other in the second direction so as to be spaced from the trenches. [Appendix 5]

[0191] The semiconductor device according to Appendix 4, wherein the first dummy pattern and the second dummy pattern are triangular or trapezoidal in plan view. [Appendix 6]

[0192] The semiconductor device according to Appendix 1, wherein the first tip region and the second tip region located at the two end regions of the trench in the first direction have a first depth and a second depth, respectively, the central region of the trench between the first tip region and the second tip region has a third depth, and the first depth and the second depth are shallower than the third depth. [Appendix 7]

[0193] The semiconductor device according to Appendix 6, wherein the first depth and the second depth gradually decrease as one goes toward an outer circumferential direction of the substrate.

[0194] As described above, according to the second embodiment, in addition to considering the angular error between the extending direction of the trench DT and the <11-20> direction, the central region A1 of the trench DT and the first and second tip regions B1 and B2 are formed to have different shapes, and the first dummy pattern DTR1 and the second dummy pattern DTR2 are arranged so that the plurality of trenches DT can be advantageously filled with the semiconductor layer. As a result, the production yield and reliability of the semiconductor device can be improved.

[0195] For example, in the embodiments described above, the plurality of p-type pillar regions were formed by forming the plurality of trenches in the n-type epitaxial layer on the n-type substrate and then filling the plurality of trenches with the p-type semiconductor layer. In this way, the superjunction structure composed of the plurality of p-type pillar regions and the plurality of n-type pillar regions, each composed of the n-type epitaxial layer between the adjacent p-type pillar regions, was formed. However, the present invention is not limited to this. For example, a plurality of n-type pillar regions may be formed by forming a plurality of trenches in a p-type epitaxial layer on an n-type substrate and then filling the plurality of trenches with an n-type semiconductor layer.In this way, the superjunction structure is formed, which consists of the plurality of n-type pillar regions and the plurality of p-type pillar regions, each consisting of the p-type epitaxial layer between the n-type pillar regions.

[0196] Furthermore, the above-described embodiments are not limited to the fabrication of the superjunction structure and are a fundamental technology for filling the interior of a relatively deep trench using crystal growth. Therefore, the present invention can be applied as long as the substrate and the crystal layer filling the interior of the trench have the same crystal structure, even if the substrate and the filling crystal layer have the same conductivity type. For example, a MEMS (micro-electromechanical system) device can be considered as such an application. List of reference symbols A1 central area B1 first peak area B2 second peak area BC Body contact area CH Canal Region CR cell area DE Drainage area DT Graben DTR1 first dummy pattern DTR2 second dummy pattern EP epitaxial layer FE dummy electrode GE gate electrode GI Gate insulating film GPE gate lead-out electrode GPU Gate Lead-Out Area IL interlayer insulating film NC n-type columnar region OF orientation flat PAS surface protection film PC columnar region of p-type PER peripheral area PF conductor film SC semiconductor chip SE source electrode SM semiconductor layer SPE source lead-out electrode SPR Source Lead-Out Area SR source area SUB Substrat SW SiC single crystal substrate TR transition area VO cavity

Claims

[1] A semiconductor device comprising: a substrate (SUB, EP) having a main surface provided with an off-angle inclined in a reference crystal direction of a <11-20> direction or a <1-100> direction with respect to a main crystal surface of a (0001) surface or a (000-1) surface; a plurality of trenches (DT) provided in the substrate (SUB, EP) such that they extend in a first direction along the main surface of the substrate (SUB, EP) and are spaced apart from one another in a second direction orthogonal to the first direction along the main surface of the substrate (SUB, EP); a first pillar region (PC) provided in the trench (DT) and consisting of a crystal layer having the same crystal structure as the substrate (SUB, EP); and a second column region (NC) consisting of a part of the substrate (SUB, EP) between the trenches (DT) adjacent to each other in the second direction, where an angular error between the reference crystal direction and the first direction is within ± θ, if a depth of the trench (DT) is h, a width of the trench (DT) is w and k is a coefficient greater than 0 and less than 2, the θ is determined by θ = {arctan {k × (w / h)}} / 13 a first tip region (B1) at one end of the trench (DT) has a first tapered shape in the first direction, the width of which becomes narrower towards its tip end in plan view, a second tip region (B2) at the other end of the trench (DT) has a second tapered shape in the first direction, the width of which becomes narrower towards its tip end in plan view, and an inclination angle of the first tapered shape with respect to the first direction is smaller than an inclination angle of the second tapered shape with respect to the first direction. [2] The semiconductor device according to claim 1, wherein the k is any one of 0.9 or less, 0.5 or less, and 0.3 or less. [3] The semiconductor device according to claim 1 or 2, wherein the depth h of the trench is 5 µm or more or 10 µm or more. [4] A semiconductor device according to any one of claims 1 to 3, wherein an aspect ratio (h / w) of the trench (DT) is 5 or more or 10 or more. [5] A semiconductor device according to any one of claims 1 to 4, wherein the substrate (SUB, EP) comprises a hexagonal silicon carbide single crystal substrate (SW), the reference crystal direction is the <11-20> direction, the main crystal surface is the (0001) surface, and the crystal layer is a silicon carbide crystal layer. [6] A semiconductor device according to claim 5, wherein the substrate (SUB, EP) comprises a silicon carbide single crystal substrate (SW) of 4H polytype or 6H polytype having a first conductivity type and an epitaxial layer (EP) having the first conductivity type formed on the silicon carbide single crystal substrate (SW), the off-angle is 1° or greater and 5° or less, the silicon carbide crystal layer has a second conductivity type which is different from the first conductivity type, and the semiconductor device is a MOSFET having a superjunction structure formed from the first column region (PC) and the second column region (NC). [7] Semiconductor device according to one of claims 1 to 6, where the trench (DT) has a tapered shape that becomes narrower as you go deeper, and a taper angle formed by a bottom surface and a lateral surface of the trench is 88° to 90°. [8] Semiconductor device according to one of claims 1 to 7, wherein a first dummy pattern (DTR1) spaced from the trenches (DT) is formed between the first tip regions (B1) of the plurality of trenches (DT) adjacent to each other in the second direction, and a second dummy pattern (DTR2) spaced from the trenches (DT) is formed between the second tip portions of the plurality of trenches (DT) adjacent to each other in the second direction. [9] A method of manufacturing a semiconductor device, comprising the steps of: Preparing a substrate (SUB, EP) having a main surface provided with an off-angle inclined in a reference crystal direction of a <11-20> direction or a <1-100> direction with respect to a main crystal surface of a (0001) surface or a (000-1) surface, and having a reference mark (OF) provided to have a first angular error with respect to the reference crystal direction; Preparing a photomask for forming an etching pattern on the substrate (SUB, EP) to form a plurality of trenches (DT) in the substrate (SUB, EP) which extend in a first direction along the main surface of the substrate (SUB, EP) and are spaced apart from one another in a second direction orthogonal to the first direction along the main surface of the substrate (SUB, EP); Forming the etching pattern on the substrate (SUB, EP) using the photomask; Forming the plurality of trenches (DT) in the substrate (SUB, EP) using the etching pattern; and Filling the interior of the plurality of trenches (DT) with a crystal layer having the same crystal structure as the substrate (SUB, EP) by means of a crystal growth process, wherein, when preparing the substrate (SUB, EP), the substrate (SUB, EP) in which the first angular error is within ± θ is selected and prepared, and when a depth of the trench (DT) is h, a width of the trench (DT) is w and k is a coefficient greater than 0 and less than 2, the θ is determined by θ = {arctan {k × (w / h)}} / 13. [10] A method of manufacturing a semiconductor device, comprising the steps of: Preparing a substrate (SUB, EP) having a main surface provided with an off-angle inclined in a reference crystal direction of a <11-20> direction or a <1-100> direction with respect to a main crystal surface of a (0001) surface or a (000-1) surface, and having a reference mark (OF) provided to have a first angular error with respect to the reference crystal direction; Preparing a photomask for forming an etching pattern on the substrate (SUB, EP) to form a plurality of trenches (DT) in the substrate (SUB, EP) which extend in a first direction along the main surface of the substrate (SUB, EP) and are spaced apart from one another in a second direction orthogonal to the first direction along the main surface of the substrate (SUB, EP); Forming the etching pattern on the substrate (SUB, EP) using the photomask; Forming the plurality of trenches (DT) in the substrate (SUB, EP) using the etching pattern; and Filling the interior of the plurality of trenches (DT) with a crystal layer having the same crystal structure as the substrate (SUB, EP) by means of a crystal growth process, wherein, when the substrate (SUB, EP) is prepared, error data of the first angular error in the substrate (SUB, EP) are measured or the substrate (SUB, EP) whose error data of the first angular error are specified is prepared, when the etching pattern is formed using the photomask, an angle correction with respect to the reference mark (OF) is performed by the exposure device using the error data, an angular error between the reference crystal direction and the first direction is within ± θ, and when a depth of the trench (DT) is h, a width of the trench (DT) is w and k is a coefficient greater than 0 and less than 2, the θ is determined by θ = {arctan {k × (w / h)}} / 13. [11] The manufacturing method of the semiconductor device according to claim 10, wherein, when preparing the substrate (SUB, EP), the substrate (SUB, EP) in which the first angular error is within ± θ is selected and prepared. [12] The manufacturing method of the semiconductor device according to claim 10 or 11, wherein the measurement of the first angular error is performed by batch processing for each crystal ingot from which the substrate (SUB) is cut out, or for each individual piece of the substrate (SUB, EP). [13] A manufacturing method of the semiconductor device according to any one of claims 9 to 12, wherein k is any one of 0.9 or less, 0.5 or less, and 0.3 or less. [14] A manufacturing method of the semiconductor device according to any one of claims 9 to 13, wherein the depth h of the trench (DT) is 5 µm or more or 10 µm or more. [15] A manufacturing method of the semiconductor device according to any one of claims 9 to 14, wherein an aspect ratio (h / w) of the trench (DT) is 5 or more or 10 or more. [16] A method of manufacturing the semiconductor device according to any one of claims 9 to 15, wherein the substrate (SUB, EP) comprises a hexagonal silicon carbide single crystal substrate (SW), the reference crystal direction is the <11-20> direction, the main crystal surface is the (0001) surface, and the crystal layer is a silicon carbide crystal layer. [17] A manufacturing method of the semiconductor device according to claim 16, wherein the substrate (SUB, EP) comprises a silicon carbide single crystal substrate (SW) of 4H polytype or 6H polytype having a first conductivity type and an epitaxial layer (EP) having the first conductivity type formed on the silicon carbide single crystal substrate (SW), the off-angle is 1° or greater and 5° or less, the silicon carbide crystal layer has a second conductivity type which is different from the first conductivity type, the reference mark (OF) is an orientation flat (OF) or a notch of the substrate, and the semiconductor device is a MOSFET with a superjunction structure composed of trenches (DT) filled with the silicon carbide crystal layer. [18] The manufacturing method of the semiconductor device according to claim 16, wherein a gas used to grow the silicon carbide crystal layer to fill the plurality of trenches (DT) includes H2 gas, HCl gas, and SiH4 gas, and an HCl / SiH4 flow ratio is 30 or more and 65 or less, and an H2 / SiH4 flow ratio is 500 or more and 7,000 or less. [19] The manufacturing method of the semiconductor device according to claim 16, wherein a gas used to grow the silicon carbide crystal layer to fill the plurality of trenches includes H2 gas, HCl gas, and SiH4 gas, and a pressure in a growth furnace during the epitaxial growth is 30 kPa or more and 100 kPa or less.

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