Ultra-thin high-density semiconductor packages

DE112017008442B4Pending Publication Date: 2026-07-23INTEL CORP
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Patent Information

Authority / Receiving Office
DE · DE
Patent Type
Patents
Current Assignee / Owner
INTEL CORP
Filing Date
2017-12-30
Publication Date
2026-07-23

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Abstract

A semiconductor arrangement (100, 150) comprising: a package (128) comprising a first die (116a) spaced laterally from a second die (116b) by a first molding compound (104), and one or more metal layers and dielectric layers beneath the first die, the second die, and the first molding compound; an interposer (106) wherein the one or more metal layers and dielectric layers of the package are coupled to the interposer by first connections; a component (110) beneath the interposer; columns (114) adjacent to the component and beneath the interposer; a substrate (108) beneath the component and the columns, wherein the component is coupled to the substrate by second connections (126), the substrate having a thickness in the range of 66 micrometers to 70 micrometers; a second molding compound (122) in contact with sidewalls of the component and extending over an upper surface of the component;and solder balls (112) coupled to the substrate, wherein the first of the solder balls are vertically below the component and the second of the solder balls are vertically below the columns.;
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