Method for combining own and counter capacity recording

Abstract

A capacitance measurement method comprising: generating a first set of one or more currents (Irx) by precharging, for each transmitting (TX) electrode (Tx1, TxK) of a set of one or more TX electrodes, an intrinsic capacitance (Cstx) of the TX electrode and a counter-capacitance (Cm) between the TX electrode and a receiving (RX) electrode (RxM) of a set of one or more RX electrodes by applying a first excitation voltage (Vtx) corresponding to the TX electrode (Tx1, TxK) to the TX electrode (Tx1, TxK) to induce a first current of the first set of currents; generating a second set of one or more currents (Itx) by applying, for each TX electrode (Tx1, TxK) of the set of TX electrodes, a reference voltage (Vref) to the TX electrode to induce a second current of the second set of currents;and for each TX electrode (Tx1, TxK) of the set of TX electrodes, calculating a measure of the self-capacitance of the TX electrode based on the second set of currents, and calculating a measure of the counter-capacitance between the TX electrode and each RX electrode in the set of RX electrodes based on the first set of currents, characterized in that for each TX electrode of the set of TX electrodes, calculating the measure of the self-capacitance of the TX electrode includes: calculating a measure of a parasitic capacitance (Cp) for the TX electrode based on the reference voltage (Vref) applied to the TX electrode and the induced second current; calculating the measure of the counter-capacitance (Cm) between the TX electrode and each RX electrode of the set of RX electrodes by performing a deconvolution operation based on the first set of currents; and subtracting a sum of the counter-capacitance measures (Cms) from the measure of parasitic capacitance (Cs).;

Description

RELATED REGISTRATIONS

[0001] This application is an international application of US patent application number 15 / 850,119, filed on December 21, 2017, claiming priority over provisional US patent application number 62 / 535,402, filed on July 21, 2017, all of which are incorporated herein by reference in their entirety. AREA OF INVENTION

[0002] This disclosure concerns the field of capacity measurement and in particular methods for measuring self-capacity (SC) and mutual capacity (MC). STATE OF THE ART

[0003] Computing devices, such as notebook computers, personal data assistants (PDAs), kiosks, and mobile phones, feature user interface devices, also known as HIDs (Human Interface Devices). One type of user interface device is a touch-sensitive pad (also commonly called a touchpad), which can be used to emulate the function of a personal computer's (PC) mouse. A touch-sensitive pad replicates the X / Y movement of a mouse by using two defined axes containing a collection of sensor electrodes that detect the position of one or more objects, such as a finger or stylus. The touch-sensitive pad provides a user interface device for performing functions such as positioning a pointer or selecting an item on a display.Another type of user interface device is a touchscreen. Touchscreens, also known as touch windows, touch panels, or touch-sensitive panels, are transparent display overlays that allow a display to be used as an input device, thus eliminating the need for the keyboard and / or mouse as the primary input device for interacting with the display's content. Other user interface devices include buttons, sliders, and other elements that can be used to detect touches, taps, drags, and other gestures.

[0004] Capacitance sensing systems are increasingly used to implement these and other types of user interface devices. These systems operate by detecting electrical signals generated at electrodes that reflect changes in capacitance. Such changes in capacitance might indicate a touch event or the presence of a conductive object, such as a finger, near the electrodes. The capacitance changes of the sensing electrodes can then be measured by an electrical circuit that converts the capacitances measured at the capacitive sensing elements into digital values ​​for interpretation by a host device. However, the accuracy of existing capacitance sensing circuits can be degraded by noise and fluctuations affecting the drive voltages, current source outputs, switching frequencies, and other signals within the sensing circuit.Such measurement inaccuracies can result in inaccurate positioning or touch detection in a capacitance-based user interface device. List of characters

[0005] The present revelation is illustrated in the figures of the accompanying drawings in an exemplary and non-limiting manner. Fig. Figure 1 is a block diagram representing a capacity measurement system according to one embodiment. Fig. Figure 2 illustrates a capacity measurement system in a vehicle according to one embodiment. Fig. Figure 3 illustrates circuit diagrams for stages of a multiphase detection process according to one embodiment. Fig. Figures 4A-4D illustrate circuit diagrams according to one embodiment, representing stages in a multiphase process for the combined detection of self-capacitance and counter-capacitance. Fig. Figure 5 illustrates an embodiment of a system for the combined detection of own capacity and counter-capacity. Fig. Figure 6 is a timing diagram according to one embodiment, illustrating signals generated in a capacity measurement system. Fig. Figure 7 illustrates an embodiment of a system for the combined detection of own capacity and counter-capacity. Fig. Figure 8 is a timing diagram according to one embodiment, illustrating signals generated in a capacity measurement system. Fig. Figure 9 illustrates an embodiment of a system for the combined detection of own capacity and counter-capacity. Fig. Figures 10A-10D illustrate circuit diagrams according to an embodiment, representing stages in a multiphase process for the combined detection of self-capacitance and counter-capacitance. Fig. Figure 11 is a timing diagram according to an embodiment illustrating signals generated in a capacity measurement system. Fig. Figures 12A-12B illustrate circuit diagrams according to an embodiment, representing stages in a multiphase process for the combined detection of self-capacitance and counter-capacitance. Fig. Figure 13 is a timing diagram according to an embodiment illustrating signals generated in a capacity measurement system. Fig. Figures 14A-14B illustrate circuit diagrams according to an embodiment representing stages in a capacitance sensing process that compensates a baseline signal. Fig. Figure 15 illustrates circuit diagrams according to an embodiment, representing stages in a baseline compensation process. Fig. Figure 16 is a timing diagram according to one embodiment, illustrating signals generated during a baseline compensation process. Fig. Figures 17A-17B illustrate circuit diagrams according to an embodiment representing stages in a capacitance sensing process that compensates a baseline signal. Fig. Figure 18 illustrates a circuit diagram for a baseline compensation process according to one embodiment. Fig. Figure 19 is a timing diagram according to one embodiment, illustrating signals generated during a baseline compensation process. Fig. Figures 20A-20D illustrate circuit diagrams according to an embodiment that represent stages in a capacitance sensing process that compensates a baseline signal. Fig. Figure 21 illustrates a process for performing a combined measurement of own capacity and counter-capacity according to one embodiment. Fig. Figure 22 illustrates a process for calculating own capacity and counter-capacity. DETAILED DESCRIPTION

[0006] The following description sets forth numerous specific details, such as examples of specific systems, components, methods, and so forth, to provide a good understanding of various embodiments of the claimed subject matter. However, it will be clear to a person skilled in the art that at least some embodiments can be carried out without these specific details. In other cases, well-known components or methods are not described in detail or are presented in a simple block diagram format to avoid unnecessarily obscuring the claimed subject matter. The specific details set forth are therefore merely exemplary. Certain implementations may differ from these exemplary details and nevertheless be considered to be within the spirit and scope of the claimed subject matter.

[0007] Computing devices that accept input via a capacitive touch-sensing surface, such as a touchscreen or trackpad, benefit from the ability to distinguish between liquids on the sensing surface and actual finger or stylus touches intended as input to the device. One approach to discarding liquid-induced contacts is to measure the intrinsic capacitances of electrodes in the touch-sensing array. For example, water on the sensing surface affects the reverse capacitance between electrodes but does not affect an electrode's intrinsic capacitance, which is generally the capacitance between the electrode and ground. According to one approach, the intrinsic capacitance can be measured across the entire touch-sensing surface by applying an excitation signal in phase to a subset of the sensor electrodes in the array.For example, in a sensor arrangement comprising row electrodes intersecting column electrodes, an excitation signal can be applied to all of the row electrodes or to all of the column electrodes. Countercapacitance measurements are performed in separate scan cycles; for example, the device can alternate between self-capacitance and countercapacitance scans.

[0008] However, this approach leads to significant electromagnetic emissions due to the phase-coherent excitation of multiple electrodes for self-capacitance measurement, which can exceed the limits applicable to use in motor vehicles or other vehicles. Furthermore, self-capacitance measurements obtained in this way can be affected by back-capacitances between the excited sensor electrodes (e.g., row electrodes) and the unexcited sensor electrodes (e.g., column electrodes); accordingly, such implementations include an additional shielding driver to reduce the effect of back-capacitances, adding extra overhead. The separate self-capacitance and back-capacitance scans also result in a slower update rate for position values ​​derived from the back-capacitance measurements.

[0009] In one embodiment, a capacitance sensing device can solve these problems by using a multiphase sensing procedure to measure the countercapacitances simultaneously with the self-capacitances. Such a capacitance sensing device includes additional circuitry to allow voltage signals applied to the electrodes during the pre-charge and sensing stages of a multiphase self-capacitance sensing sequence to also be used to excite countercapacitances between electrodes. The sensitivity of the read self-capacitance values ​​to fluctuations in the countercapacitance is suppressed by data processing.

[0010] This combined self-capacitance and counter-capacitance measurement generates a low level of electromagnetic emissions, similar to a counter-capacitance scan alone, and is therefore suitable for applications where low emission characteristics are critical. Compared to self-capacitance measurement using in-phase excitation of electrodes, emissions can be reduced by a factor of 100 or more. Furthermore, the combined self-capacitance and counter-capacitance measurement solution eliminates the need for two separate procedures to measure the self-capacitances and counter-capacitances at the sensor array. Instead, the self-capacitance and counter-capacitance values ​​are obtained through a single scan procedure. This solution also operates without additional shielding to remove the effect of counter-capacitance variations on the self-capacitance readings.The measured self-capacitance and counter-capacitance values ​​are appropriately separated by data processing techniques, so that the sensor can distinguish between liquids on the detection surface and intentional touches.

[0011] Fig. Figure 1 illustrates a functional block diagram of a capacity measurement system. 100 , which performs combined self-capacitance and counter-capacitance measurements according to one embodiment. In the acquisition system 100 The processing device measures 110 Self-capacitances and counter-capacitances at electrodes in the capacitive sensor arrangement 130 The sensor arrangement 130 It comprises a set of one or more TX sensor electrodes and a set of one or more RX sensor electrodes. Each of the TX sensor electrodes is connected via one of the TX lines. 111 with the processing device 110connected, while each of the RX sensor electrodes is connected via one of the RX lines. 112 with the processing device 110 is connected. The processing device 110 performs processing of the measured capacitance values ​​to distinguish between intended and unintended contacts (e.g. liquid on the sensor surface) and to determine the locations of the intended contacts.

[0012] The processing device 110 reports the locations of intended touches to the host device 150 The host device 150 Based on the reported contact points, it performs one or more functions. In one embodiment, the processing device can 110 the measured own capacities and counter capacities to the host device 150 report and can initiate further processing of the measured values ​​in the host device 150 be performed.

[0013] The processing device 110 It includes a number of components to transmit excitation signals to the sensor array. 130 to deliver, measure the resulting signals (e.g., current or charge) at the sensor array, and calculate the self-capacitances and counter-capacitances based on the measurements. The multiplexer 113 It comprises switching circuits that selectively connect the different sensor electrodes to excitation signals or measurement channels. The TX generator 115 generates a TX signal as an excitation signal that is sent via the multiplexer 113 and the TX lines 111 selectively to the TX sensor electrodes in the arrangement 130 A VTX generator is being created. 114 generates a voltage Vtx , which can be selectively applied to the sensor electrodes when generating the TX excitation signal. The multiplexer 113It can also selectively apply a ground voltage to the sensor electrodes.

[0014] The multiplexer 113 can the electrodes in the sensor assembly 130 also selectively with the charge-to-code converters 116 connect so that the amounts of charge generated by the excitation of the electrodes can be measured. In one embodiment, the charge-to-code converters are integrated. 116 The current is measured over a set period and the resulting measured charge is converted into a digital code that can be used for further processing. This is the baseline compensation circuit. 117 provides a baseline compensation signal to the capacitance-to-code converters 116 , which reduces the effect of a baseline signal from the sensor array. Alternatively, the baseline compensation circuit can be used. 117 the compensation signal to a shielding electrode under the sensor assembly 130 invest.

[0015] The channel engine 118 It receives the digital codes representing the charge measured at each electrode and delivers the raw values ​​to the deconvolution module. 119 , which performs deconvolution operations on the values ​​to create a counter-capacity map 120 and an intrinsic capacity vector 121 to generate. The counter-capacity map 120 The intrinsic capacitance vector is represented as a matrix of values ​​with dimensions corresponding to the number of row and column electrodes in the sensor array, such that the countercapacitance of each intersection between a row electrode and a column electrode is represented by an element in the matrix. The intrinsic capacitance vector includes an element for each TX electrode (e.g., row electrode) representing the intrinsic capacitance of that TX electrode.

[0016] The counter-capacities 120 and own capacities 121are connected to the post-processing and communication block 122 transferred. The post-processing block 122 performs additional calculations to detect the presence of any intended contacts and to locate such contacts based on the capacities 120-121 to determine the points of contact. The contact points are determined by the block. 122 to the host device 150 transmitted.

[0017] Fig. Figure 2 illustrates a block diagram of a vehicle 200 , in which the capacity recording system 100 is implemented according to one embodiment. The detection system 100 includes the host 150 , the processing device 110 and the sensor arrangement 130 In one embodiment, the sensor arrangement 130 It is made from a transparent, conductive material such as indium tin oxide (ITO, indium tin oxide) and lies on a display. 202The host device 150 controls the display 202 and updates the display in response to the sensor array 130 measured own capacities and counter-capacities, so that the display 202 and the sensor arrangement 130 together they function like a touchscreen.

[0018] The host device 150 receives via the sensor array 130 Inputs that can be used to control one or more subsystems 201 of the vehicle 200 to control the vehicle subsystems. 201 based on the sensor arrangement 130 The vehicle subsystems are controlled by measured intrinsic and counter-capacitances, which represent user inputs. 201 This may include the vehicle's climate control, engine management, infotainment and / or other electronically controlled vehicle systems.

[0019] Fig. Figure 3 illustrates two stages of operation of a capacity measurement circuit. 300 , which performs a multi-phase self-capacitance measurement, according to one embodiment. The capacitance measurement circuit 300 measures intrinsic capacitances of two electrodes RX-1 and RX-N , which are the first RX electrode and the Nth RX electrode in the sensor assembly 130 represent. The capacities Cs1 and CsN represent the intrinsic capacitances of the electrodes RX-1 or RX-N dar.

[0020] During the pre-charging stage, the detection electrodes RX-1 and RX-N by opening the switches SW3-1 and SW3-N from the acquisition channel 301 Insulated. Accordingly, the detection electrodes are RX-1 and RX-N They are isolated from each other and can be pre-charged to different voltages. In the sensor arrangement 130 As a whole, some electrodes can be placed on Vtx Some are pre-charged, while others are pre-charged by mass. As illustrated, SW2-1 closed, while SW1-1 is open, so that the electrode RX-1 is connected to ground RX-N with Vtx is connected. The company's own capacities Cs1 and CsN are thus reduced to mass or to Vtx summoned.

[0021] During the detection stage, the switches SW2-1 and SW2-N opened to access the sensor electrodes RX-1 and RX-N to separate them from their respective pre-charge voltages. The sensor electrodes RX-1 and RX-N are achieved by closing the switches SW3-1 and SW3-N with the acquisition channel 301 connected. The voltage Vref is applied to each of the electrodes. RX-1 and RX-N maintained. A load Q1 flows into the company's own capacity Cs1 the electrode RX-1 , since RX-1 It was pre-charged to a lower voltage than Vref. A charge QN flows from its own capacitance. CsN , since RX-N to a higher voltage Vtx as Vref was pre-charged. If this process is used for all of the RX electrodes ( RX-1 , RX-2 ... RX-N ) in the sensor arrangement 130 The acquisition channel receives the data during the process. 301 a charge Qin according to equation 1 below: Q i n = Q 1 + Q 2 + … Q N ; In equation 1, the values ​​(Q1, Q2, ... QN) represent the charge that, after the pre-charging stage, is stored in the individual capacities ( Cs1 , Cs2 , ... CsN ) is stored. Equation 1 can be rewritten as shown in Equation 2 below: Qin = S1 ⋅ U t x ⋅ C s 1 + S 2 ⋅ U t x ⋅ C s 2 + … + S N ⋅ U t x ⋅ C s N = = U t x ⋅ [ S 1 S 2 … Sn ] ⋅ [ C s 1 C s 2 M C s N ] = u t x ⋅ S ⋅ Csx ;

[0022] In Equation 2, (S1-Sn) represents the excitation sequence for one measurement cycle, represented by the elements 1, -1, and 0. A value of 1 indicates excitation in a positive direction, a value of -1 indicates excitation in a negative direction, and a value of 0 indicates that no excitation voltage is applied to the sensor electrode. Accordingly, Utx represents the change in voltage applied to the electrode from the pre-charge stage to the sensing stage. As shown in Equation 2, Utx is the same for all electrodes; in alternative embodiments, Utx may differ from electrode to electrode.

[0023] If the sensor is successively excited with N different excitation sequences, the excitation procedure can be represented as an excitation matrix S with the values ​​S11-SNN, as shown in equation 3 below. Qin = U t x ⋅ [ S 11 S 21 L S N 1 S 12 S 22 L S N 2 M M O M S 1 N S 2 N O S N N ] ⋅ [ C s 1 C s 2 M C s N ] = U t x ⋅ S ⋅ C s x ;

[0024] In the excitation matrix S, elements in the same row (e.g., S11, S21, ... SN1) are applied to different electrodes at the same time, while elements in the same column (e.g., S11, S12, ... S1N) are applied to the same electrode at different times. If the excitation matrix S has an inverse form S -1 The recorded intrinsic capacities can be determined by performing a deconvolution of the measured charge values ​​Qin, as shown in equation 4 below, where D is the deconvolution matrix: C s x = [ D 11 D 21 L D N 1 D 12 D 22 L D N 2 M M O M D 1 N D 2 N L D N N ] ⋅ [ Q i n 1 Q i n 2 M Q i n N ] U t x = D ⋅ Qin U t x ; D = S − 1 ;

[0025] Exciting the sensor electrodes with a combination of out-of-phase signals reduces the sensor's emissions compared to in-phase excitation of all row or column sensor electrodes. The emission depends on the sum of the excitation sequence elements (e.g., S11-SNN). If the sum of the elements is equal to 1, for example, the emission observed over a distance is similar to the emission produced by exciting a single electrode. Additionally, the deconvolution calculation includes charge measurements for multiple sensor electrodes, which, after deconvolution, results in an averaging effect that makes the detection result less sensitive to noise introduced into the sensor.

[0026] In one embodiment, a sensor electrode can be excited in a positive direction during an initial pre-charging phase and in a negative direction during a subsequent pre-charging phase. Accordingly, the voltage applied to the sensor electrode fluctuates from Vtx to ground. Over the course of several cycles, the periodic voltage fluctuates between Vtx and ground and can be applied to a TX sensor electrode to be used as a counter-capacitance excitation signal to measure a counter-capacitance between the TX sensor electrode and one or more RX electrodes.

[0027] Fig. 4A, Fig. 4B, Fig. 4C and Fig. 4D illustrates each step A , B , C and D a multiphase measurement process that simultaneously measures self-capacitances and counter-capacitances, according to one embodiment. In the pre-charging stages A and C connect the switches SW1 and SW2 the TX sensor electrode alternately with ground and Vtx . Between each of the pre-charging stages A and C will the switches SW1 and SW2 opened and connects the switch SW3 the TX sensor electrode with the detection channel 401 , which maintains a reference voltage Vref at its inputs. As a result, the induced currents charge and discharge. Itx and Irx The intrinsic capacitance of the TX electrode and the counter-capacitance between the TX electrode and the RX electrode. The counter-capacitance Cm is measured over the entire excitation voltage range (from 0 V to Vtx ), which during the stages B , C (who the current Irx induce in one direction) and the stages D , A (who the current Irx (inducing in the opposite direction) is applied, charging and discharging. The intrinsic capacitance of the TX electrode is increased during the stages. B and D captured when the capture channel 401 via the switch SW3 is connected to the TX electrode. The capacitance measurement process repeats the steps. A , B , C and D sequentially and starts after the stage is completed D again with the level A to.

[0028] As in Fig. 4A illustrates, connects during the stage A the desk SW2 the TX electrode to ground to conduct a current Irx to induce an increase in charge in the opposing capacitance while simultaneously decreasing the charge in the self-capacitance. Relative to the previous stage D The voltage applied to the TX electrode changes from Vref to 0 V, so that the potential difference is across the counter-capacitance Cm is increased relative to the previous level. D The potential difference decreases via the own capacity Cstx away, since both sides of Cstx are now grounded.

[0029] In Fig. 4B are the switches SW1 and SW2 open to allow the TX electrode to remain open during the stage B from Vtx and to separate the ground. The switch SW3 is closed to connect the TX electrode to the detection channel 401 to connect. The acquisition channel 401 receives a voltage Vref upright at the TX electrode, thus inducing a current Itx , which stores the charge in its own capacity Cstx increased. The current Irx is part of Itx , which is in the counter capacity Cm Stored charge decreased. Relative to the previous stage AThe voltage at the TX electrode increases from 0 V to Vref and thus increases the potential difference via its own capacity Cstx across. The potential difference across the counter capacity Cm The distance is reduced because both sides of Cm now at Vref lay.

[0030] As in Fig. 4C illustrates, connects during the stage C the desk SW1 the TX electrode with Vtx , to generate a current Irx to increase the charge in both the own capacity Cstx as well as the counter capacity Cm to increase. Relative to the previous level B The voltage applied to the TX electrode increases from Vref on Vtx , so that the potential difference is greater than the counter-capacitance Cm is increased relative to the previous level. B The potential difference also increases with respect to the company's own capacity. Cstx away.

[0031] In Fig. 4D are the switches SW1 and SW2 open to allow the TX electrode to remain open during the stage D from Vtx and to separate the ground. The switch SW3 is closed to connect the TX electrode to the detection channel 401 to connect. The acquisition channel 401 receives a voltage Vref upright at the TX electrode, thus inducing a current Itx , which stores the charge in its own capacity Cstx reduced. The current Irx reduces the capacity in the opposite direction. Cm Stored charge. Relative to the previous stage C The voltage at the TX electrode decreases from Vtx on Vref and thus reduces the potential difference via the own capacity Cstx across. The potential difference across the counter capacity Cm The distance is also reduced, as both sides of Cm now at Vref lay.

[0032] Table 1 below presents the information for each of the levels. A , B , C and D The charge represents the load that is applied to the detection channels on both the TX and RX sides. 401 and 402 is transferred. Table 1 shows the charge that is transferred during the stages. A , B , C and D The data transferred to the TX acquisition node is represented as QtxA, QtxB, QtxC, and QtxD, respectively. This data is processed during the stages. A , B , C and D The charge transferred to the RX node is represented as QrxA, QrxB, QrxC and QrxD, respectively. TABLE 1: Charge transferred during the excitation stage Stufe An den TX-Knoten transferierte Ladung An den RX-Knoten transferierte Ladung A QtxA = 0 QrxA = Uref-Cm B QtxB = Uref-(Cstx + Cm) QrxB = -UrefiCm C QtxC = 0 QrxC = (Uref - Utx)·Cm D QtxD = (Uref - Utx)·(Cstx + Cm) QrxD = (Utx - Uref)·Cm

[0033] The charge in the TX node (which represents the TX electrode), which is connected to the input of the TX detection channel 401 is coupled, increases during the stage B and decreases during the stage D, since Uref is smaller than Utx. Accordingly, the total charge Qtx at the input of the TX detection channel is calculated. 401 The measurement for all stages is taken according to equation 5 below. Q t x = Q t x B − Q t x D = U t x ⋅ ( C s t x + C m )

[0034] The charge in the RX node (which represents the RX electrode), which is connected to the input of the RX sensing channel 402 is coupled, increases during the stages D and A and decreases during the stages B and C Accordingly, the total charge Qrx at the input of the TX detection channel is calculated as follows: 402 The measurement is taken according to equation 6 below. Q r x = ( Q r x D + Q r x A ) − ( Q r x B + Q r x C ) = { ( U t x − U r e f ) ⋅ C m + U r e f ⋅ C m } − { − U r e f ⋅ C m + ( U r e f − U t x ) ⋅ C m } = 2 ⋅ U t x ⋅ C m

[0035] The integration period of the self-capacity measurement channel 401 is half as long as the integration period of the counter-capacity measurement channel 402Accordingly, the effect of the counter-capacitance Cm on the charge Qtx passing through the TX detection channel can be 401 As shown in Equation 7, the measured values ​​are eliminated to obtain Qtx', which is due to the intrinsic capacitance. Cstx represents measured charge. Q t x ' = Q t x − 0,5 ⋅ Q r x = U t x ⋅ ( C s t x + C m ) − U t x ⋅ C m = U t x ⋅ C s t x

[0036] Fig. Figure 5 illustrates a part of the detection system according to one embodiment. 100 , which is configured to perform the above self-capacitance and counter-capacitance measurement procedure for multiple TX and RX sensor electrodes in a sensor array 130 to be carried out. The illustrated part of the data collection system 100 includes the sensor arrangement 130 and components of the processing device 110 The processing device 110 includes a set of TX connectors, with one TX connector corresponding to each TX sensor electrode in the sensor assembly. 130is connected. The set of TX connectors includes the TX connectors. 601-1 , 601-2 , 601-N , each connected to a corresponding first, second, and Nth TX sensor electrode. The processing device 110 includes additional TX connectors for the other TX electrodes that are in Fig. Number 5 has been omitted for clarity. Each of the RX sensor electrodes in the arrangement 130 is via an RX multiplexer 606 with one of a set of charge-to-code converter devices (i.e. charge ADC devices) (e.g. 605 ) tied together.

[0037] Each of the TX connectors 601-1-601-N It has a similar structure to the TX connector. 601-1 and works in a similar way. The TX connector 601-1 includes the switches SW1-1 , SW2-1 and SW3-1 , which work in a similar way to the respective switches SW1 , SW2 and SW3 , which are in the Fig. 4A-4D are illustrated. The timing of these switches is determined by the TX sequence generator. 115 based on a switching frequency Ftx controlled by the TX sequence generator. 115 The generated read enable signal (RdE signal, RdE = Read Enable) controls the switch. SW3-1 , which can be closed to access a TX pin 603-1 (which is connected to the first TX electrode) with a self-capacitance read bus 602 to connect. The corresponding SW3 switches in the other TX terminals are also closed by the RdE signal, so that all of the TX electrodes are connected to the bus at the same time. 602 be connected. The bus 602 is connected to the input of a charge-to-analog-to-digital converter (charge ADC, ADC = Analog-to-Digital Converter) 604 , or charge-to-code converter, of the TX detection channel connected to the intrinsic capacitance of the TX electrode in a similar manner to the TX detection channel 401to be seen in figures C1-C4. The charge ADC 604 The self-capacitance measurement TX channel is similar to the charge ADCs (e.g. 605 ) for the countercapacitance detection RX channels; however, the charge ADC can 604 They exhibit different gains to compensate for the larger detected capacitance. The self-capacitance detection TX channel measures a sum of induced currents from multiple TX ports (e.g., 601-1-601-N ), while the countercapacitance detection RX channels (e.g., charge ADC) 605 ) each measure currents induced at a single RX electrode.

[0038] In one embodiment, two or more of the TX terminals apply complementary signals to their respective TX electrodes, as defined by matrix S. For example, the TX terminal applies 601-1 a signal is sent to the first TX electrode by actuating the switches SW1-1 , SW2-1 and SW3-1 alternating the voltages Vtx , Vref and ground is applied to the TX electrode. The TX connection 601-2 applies a signal to the second TX electrode, which is in addition to the signal received through the TX connector. 601-1 The signal applied to the first TX electrode is complementary. If the TX connector 601-1 Vtx When applied to the first TX electrode, the TX connector connects 601-2 The second TX electrode is connected to ground. If the TX connection 601-1 When the first TX electrode is connected to ground, the TX connector 601- 2 Vtx to the second TX electrode. At a sufficient distance from the TX electrodes, the emissions generated by the two signals cancel each other out due to the different excitation.

[0039] Fig. Figure 6 illustrates, according to one embodiment, a timing diagram for signals that occur during the operation of the detection system. 100 The waveforms are generated. SW1 , SW2 and SW3 show the control signals for actuating the switches in the TX connectors, such as... SW1-1 , SW2-1 and SW3-1 To generate the out-of-phase excitation signal, the control signals for the switches are SW1 and SW2 exchanged. As previously described, each TX terminal applies a sequence of voltages corresponding to that TX electrode to its TX electrode, as indicated by the multiphase excitation sequence matrix S. The waveforms +TX and -TX show the excitation signal patterns that correspond to the elements +1 and -1 in matrix S.

[0040] The waveforms I-SC-Eigen and I-RX-Gegen illustrate the currents that pass through the self-capacitance detection channel (e.g. 401 ) and the counter-capacity measurement channel (e.g. 402) are received. In one embodiment, the intrinsic and countercapacitance sensing channels integrate the I-SC intrinsic and I-RX countercurrents in the positive and negative directions. Accordingly, SC-VintP represents the integration of positive pulses of I-SC intrinsic, SC-VintN represents the integration of negative pulses of I-SC intrinsic, MC-VintP represents the integration of positive pulses of I-RX countercurrent, and MC-VintN represents the integration of negative pulses of I-RX countercurrent.

[0041] The arrows 701 show the relationship between current pulses in the I-SC intrinsic current and the resulting increases or decreases in the integrated waveforms SC-VintP and SC-VintN on. The arrows 702 show the relationship between current pulses in the I-RX counter-current and the resulting increases or decreases in the integrated waveforms MC-VintP and MC-VintN to.

[0042] The counter / self-sync signal (which is sent to the charge ADCs) 604 and 605 The supplied sync signal is activated during periods with positive current pulses and deactivated during periods with negative current pulses, allowing the positive and negative pulses to be integrated using different integration capacitors. The rising and falling transitions of the negative / negative sync signal indicate the start and end times of integration for positive currents and negative currents, respectively. SC-VintP , SC-VintN , MC-VintP and MC-VintN represent the voltages of the integrating capacitors and are characterized by increases or decreases due to the positive or negative current pulses of I-SC intrinsic and I-RX counter (as by 701 , 702(displayed), followed by a linear discharge through a reference current. The discharge time is influenced by the amount of incoming charge received.

[0043] In one embodiment, the countercapacitances for each intersection of TX- and RX sensor electrodes are determined based on the excitation pattern matrix S and the measured charge transferred as a result of the induced currents. Each row of the matrix S corresponds to an excitation pattern that is applied to the TX electrodes in the sensor array at each step of sensor excitation. 130 A matrix is ​​created. Cx can be used to provide the counter-capacitances for the sensor arrangement 130 To represent each column of values ​​in the matrix. Cx represents the countercapacitances corresponding to the intersection points with TX electrodes along the length of a single RX electrode. The product of the matrices S and Cx , scaled by the excitation voltage difference Utx , is a matrix QXm , which represents the signals measured through the RX channels, according to equation 8 below. Q X m = U t x ⋅ S ⋅ C x

[0044] The rows of the matrix QXm represent the signals (i.e., the measured charge) generated by each excitation pattern, represented by corresponding rows of the excitation matrix S. The matrix QXm represents convoluted data that can be deconvolved to calculate the counter-capacities. QXm The interrelated data is processed using a solution matrix S. -1 multiplied, which is the inverse of the excitation matrix, as shown in Equation 9. Cx = S − 1 ⋅ QXm U t x The values ​​in the resulting matrix Cx represent the counter-capacitances between the TX electrodes and the RX electrodes.

[0045] To calculate the intrinsic capacitances for each of the TX electrodes, the parasitic capacitances are first calculated based on the voltages applied to the TX electrodes and the induced currents. The parasitic capacitances can be represented as a column vector Cp. The result of the intrinsic capacitance calculation is a column vector QXp, as expressed in Equation 10 below. Q X p = U t x ⋅ S ⋅ C p Using the inverse excitation matrix S -1 A deconvolution calculation can be performed to recover the intrinsic capacitance values ​​for the TX electrodes, as shown in Equation 11. C p = S - 1 ⋅ Q X p U t x

[0046] The column vector Cp represents the values ​​of the parasitic capacitances as measured by the TX acquisition channels; each of these parasitic capacitances includes the intrinsic capacitance of the associated TX electrode and the reverse capacitance between the TX electrode and the intersecting RX electrodes. The intrinsic capacitance for each TX electrode is calculated by subtracting the sum of the previously calculated reverse capacitances for the TX electrode from the parasitic capacitance for the TX electrode. The relationship is shown in Equation 12 below. C p = C m s + C s

[0047] The values ​​for the vector Cms can be calculated from the previously determined counter-capacitance map Cx, as shown in Equation 13. C m s = ∑ r C x [ r , c ] In equation 13, r represents the row index and c the column index of the countercapacitance map Cx. The desired intrinsic capacity values ​​(as matrix Cs) can be calculated as shown in equation 14. C s = C p − C m s

[0048] The above calculations for determining counter-capacities, parasitic capacities, and own capacities are performed in a processing logic (e.g., channel engine). 118 , deconvolution module 119 etc.) in the processing device 110 performed. In alternative embodiments, these calculations can be performed in the host device. 150 or be carried out in another device.

[0049] Fig. Figure 7 illustrates part of the capacity measurement system. 100for carrying out a six-stage acquisition process for the simultaneous measurement of self-capacitances and counter-capacitances according to one embodiment. The measuring circuit, as described in Fig. Figure 7 is similar to the circuit in Fig. 5, but additionally includes a TX self-capacitance channel switch SWsc and RX channel switch SWRx , which allow the acquisition channels to be selectively separated. Furthermore, the TX sequence generator controls 115 the switches ( SWsc , SW3-1 , SW1-1 etc.) according to different timings to perform the measurements using a six-step process as described below.

[0050] In the four-stage process, as it is described in relation to the Fig. As described in 4A-4D, the self-capacitance detection channel is subject to different time constants of the TX sensor electrodes connected to its input at the beginning of the stages.B and D high current spikes. These current spikes can saturate an input stage of the self-capacitance sensing channel and distort the channel readings. In one embodiment, a six-stage process avoids this problem by adding two additional stages, with one extra stage between each pre-charge stage (i.e., when the TX electrode is charged with Vtx or ground is connected) and detection stage (i.e., when the TX electrode is connected to the detection channel).

[0051] During the additional stages, the TX acquisition electrodes are connected to the self-capacitance read bus. 602 connected while the switch SWsc is open to the bus 602 from the charging ADC 604to separate. During this “combination” stage, the charge accumulated in several TX electrode leads is distributed among all of the TX electrode leads. At the end of the combination stage, the charge is equal to the sum of the excitation sequence elements, as provided in matrix S, multiplied by a charge accumulated in a single TX electrode lead, as described by equation 15 below. Q x = U e x ⋅ C x ⋅ ∑ S i Thus, the current states upon reaching the detection stages are predictable, and the occurrence of current spikes that negatively affect the values ​​read by the TX detection channel can be avoided. The switch is activated at the detection stage. SWsc closed and the switches will be SWRx opened. The switch SW3-1 and the corresponding SW3 switches in the other TX terminals remain closed to connect each of the TX sensor electrodes to the self-capacitance read bus 602 to connect.

[0052] Fig. Figure 8 is a timing diagram illustrating the six-stage operation of the capacity measurement system, as described in Fig. Figure 7 illustrates one embodiment. The six stages are shown in Fig. 8 as stages A , B , C , D , E and F is displayed. The levels A and D are pre-loading stages, the stages B and E are composite steps and the steps C and F These are detection levels. The waveforms SW1 , SW2 and SW3 show the control signals for actuating the switches in the TX connectors, such as... SW1-1 , SW2-1 and SW3-1 The Txx waveform illustrates the signal at the TX sensor electrode resulting from actuating the switches. The waveforms SWsc and SWRx show the control signals for the respective actuation of the switches. SWsc and SWRx .

[0053] The waveforms linSC and InMC illustrate the flows that each pass through the self-capacity measurement channel 604 and a counter-capacity measurement channel (e.g. 605 ) will be received. SC-VintP represents the integration of positive impulses from InSC SC-VintN represents the integration of negative pulses of InSC dar MC-VintP MC-VintN represents the integration of positive pulses of IinMC, and MC-VintN represents the integration of negative pulses of IinMC.

[0054] The arrows 901 show the relationship between current pulses in the linSC current and the resulting increases or decreases in the integrated waveforms SC-VintP and SC-VintN on. The arrows 902 They also show the relationship between current pulses in the I-RX counter-current and the resulting increases or decreases in the integrated MC waveforms. WintP and MC-VintNon. The signal CintP It is activated during periods with positive current pulses and deactivated during periods with negative current pulses, allowing the positive and negative pulses to be integrated using different integrating capacitors. Similarly, CintN the reverse of CintP and is deactivated during periods in which positive current pulses occur and activated during periods in which negative current pulses occur. Falling edge transitions of CintP and CintN The signals indicate the integration end times for their respective integration capacitors in each acquisition channel. SC-VintP , SC-VintN , MC-VintP and MC-VintN represent the voltages of the integrating capacitors and are characterized by increases or decreases due to positive or negative current pulses from InSC and linMC characterized (as by 901 ,902 (displayed), followed by a linear discharge through a reference current. The discharge time is influenced by the amount of incoming charge received.

[0055] In the approaches described above, the intrinsic capacitances are calculated by subtracting the effects of the counter-capacitances from the measured parasitic capacitances, as described in Equation 14 above. The parasitic capacitance for a TX electrode is the sum of the intrinsic capacitance of the TX electrode (between the TX electrode and ground) and the counter-capacitances between the TX electrode and intersecting RX electrodes. In one embodiment, the effectiveness of this approach may be limited by the accuracy of the gain of the intrinsic and counter-capacitance sensing channels. An inaccuracy in the gain of the sensing channel can introduce distortions into the intrinsic capacitance measurements, similar to signals generated by objects located at a moderate distance from the sensing surface, such as a finger performing a hovering gesture or covered by a glove.In one embodiment, such objects are more easily detected in a detection system that removes the potential difference across the counter-capacitances by providing a conductive path between the sensor electrodes during the compounding and detection stages. In this way, the charge accumulated in the counter-capacitances is eliminated.

[0056] Figs. Figure 9 illustrates, according to one embodiment, a part of a detection system. 100 , in which the charge stored in the countercapacitances between sensor electrodes is eliminated during the compounding and sensing stages. In Figs. 9 is each of the sensor electrodes in the KxM arrangement 130 The sensor electrodes are connected to the acquisition channels via a uniform pin multiplexer (MUX). For example, the KTX sensor electrodes are connected to the pin multiplexers. 1001-1 , 1001-2 , 1001-3 ... 1001-K connected. The M RX sensor electrodes are connected to the pin-MUX. 1002-1, 1002-2 ... connected to 1002-M. Each of the pin MUX units is a type of connector that allows the application of an excitation signal (via switching of SW1 and SW2 ) to the connected sensor electrode, allowing the electrode to be accessed via the SC bus 1015 (by closing SW3 ) with the self-capacitance channel (SC channel) 1011 is connected or so that the electrode is connected via the RX bus 1014 (by closing SWRx) with one of the counter-capacitance channels (MC channels) 1012 is connected.

[0057] Each pin MUX stores its configuration in its own software control logic unit (e.g. 1003-1 The configuration is done via the sequence configuration buses. 1010 and 1013 from a host device 150 transmitted to each pin multiplex. In one embodiment, the buses 1010 and 1013 implemented as a single bus.

[0058] If SW3If the switch is closed and all other switches are open, all sensor electrodes are connected to a common bus conductor (i.e., SC bus). 1015 ) connected. Thus, the switch can SW3 act as a discharge switch to selectively provide a conductive path between the TX electrodes and the RX electrodes, so that charge stored in the countercapacitance between the TX and RX electrodes can be discharged.

[0059] Figs. 10A, Figs. 10B, Figs. 10C and Figs. Figure 10D illustrates, according to one embodiment, a four-stage process for measuring self-capacitances and counter-capacitances using a counter-capacitance discharge technique. The illustrated sensing circuit includes the TX electrodes. Tx1 and TxK and an RX electrode RxM , which cuts the TX electrodes. The intrinsic capacitances of the TX electrodes Tx1 and TxK are each as Csx1 and CsxK displayed. The counter capacity between Tx1 and RxM is as Cm1 displayed and the counter capacity between TxK and RxM is as CmK displayed. Although for the sake of clarity only Tx1 and TxK As illustrated, in practice the other TX sensor electrodes and their associated switches are connected in the circuit and operate in a similar way to Tx1 and TxK .

[0060] Figs. 10A illustrates a pre-charging stage A , in which the TX electrodes are connected according to the multiphase excitation sequence defined in a matrix S Tx1 and TxK through the switches SW1-1 , SW2-1 , SW1-K and SW2-K each to ground and the TX voltage Vtx to be pre-charged. At this point, the RX electrode is RxM above SWRx with the counter-capacity detection channel 1102connected, which at its input carries the reference voltage Vref maintains. The counter-capacities Cm1 and CmK are charged across these capacities due to potential differences. The counter-capacity detection channel 1102 measures the current Irx , which is generated by charging the counter capacities.

[0061] Figs. 10B illustrates a recording level C of the process, which leads to the stage A follows (an optional stage) B (described in the following paragraphs). During the recording stage C is the counter-capacity detection channel 1102 by opening the switch SWRx from RxM Disconnected. All of the sensor electrodes are disconnected by closing the SW3 switches (i.e., SW3-1 , SW3-K , SW3-M ) for each electrode with the SC bus 1015 connected and the own capacity measurement channel 1101is by closing the SWsc switch with the SC bus 1015 connected. The counter-capacities Cm1 and CmK are via the electricity Icm unloaded. At the same time, the self-capacity measurement channel receives 1101 at its entrance, with which the TX electrodes Tx1 and TxK are connected, maintaining the reference voltage Vref. Accordingly, the intrinsic capacitances share Csx1 and CsxK their cargo via the SC bus 1015 between the TX electrodes, while they are recharged to the reference voltage Vref by the induced current Itx. The intrinsic capacitance Csrx the RX electrode RxM The accumulated charge does not affect the measurement, as it occurs before the detection stage. C on Vref was summoned.

[0062] Figs. 10C illustrates a pre-charging stage D , which is at the level CThis follows, in which the TX electrodes are connected according to the multiphase excitation sequence defined in matrix S. Tx1 and TxK through the switches SW1-1 , SW2-1 , SW1-K and SW2-K each to the TX voltage Vtx and ground are pre-charged. At this point, the RX electrode RxM is connected to the counter-capacitance detection channel via SWRx. 1102 connected, which maintains the reference voltage Vref at its input. The counter-capacitances Cm1 and CmK are charged across these capacities due to potential differences. The counter-capacity detection channel 1102 measures the current Irx generated by charging the counter-capacitances.

[0063] Figs. 10D illustrates one level of data capture. F of the process (an optional stage) E (described in the following paragraphs). During the recording stage F is the counter-capacity detection channel1102 by opening the SWRx switch from RxM. All of the sensor electrodes are disconnected by closing the SW3 switch (i.e. SW3-1 , SW3-K , SW3-M ) for each electrode with the SC bus 1015 connected and the own capacity measurement channel 1101 is by closing the SWsc switch with the SC bus 1015 connected. The counter-capacities Cm1 and CmK are discharged via the current Icm. Simultaneously, the self-capacity measurement channel receives power. 1101 at its entrance, with which the TX electrodes Tx1 and TxK are connected, the reference voltage Vref upright. Accordingly, the own capacities are divided. Csx1 and CsxK their cargo via the SC bus 1015 between the TX electrodes while they are subjected to the induced current Itx back to the reference voltage Vref to be charged. The capacity is available on-site. Csrx the RX electrode RxMThe accumulated charge does not affect the measurement, as it occurs before the detection stage. C on Vref was summoned. Relative to the level C flows Itx in the stage F in the opposite direction, since in the previous pre-loading stage D the TX electrodes Tx1 and TxK were charged to voltages that corresponded to those in the pre-charging stage A The voltages used are complementary.

[0064] Figs. Figure 11 illustrates, according to one embodiment, a timing diagram for signals generated during the four-stage self-capacitance and counter-capacitance measurement process implementing the counter-capacitance discharge technique, as shown in the Figs. 10A-10D illustrated. The four levels are in Figs. 11 as stages A , C , D and F displayed. The levels A and D are pre-charging stages and the stagesC and F These are detection levels. The waveforms SW1 , SW2 and SW3 show the control signals for actuating the switches in the TX-Pin-MUX, such as... SW1-1 , SW2-1 and SW3-1 The Tx1 waveform illustrates the signal at the TX sensor electrode. Tx1 , which results from the activation of the switches. The waveforms SWsc and SWRx show the control signals for the respective actuation of the switches. SWsc and SWRx .

[0065] The waveforms linSC and InMC illustrate the flows that each pass through the self-capacity measurement channel 1101 and a counter-capacity measurement channel 1102 be received. SC-VintP represents the integration of positive impulses from InSC dar SC-VintN represents the integration of negative pulses of IinSC, MC-VintP represents the integration of positive impulses from InMC there and MC-VintNrepresents the integration of negative pulses from InMC dar.

[0066] The method for the combined recording of own capacity and counter capacity with the counter capacity discharge mechanism can also be implemented as a six-stage process, in which the combined stages B and E to be added. The compound stage B is in Figs. 12A illustrates and occurs after the pre-charging stage A and before the recording stage C up. The combined stage E is in Figs. 12B illustrates and occurs after the pre-charging stage D and before the recording stage F up. The steps A , C , D and F work as before in Figs. 10A-10D described. During the compound stages B and E are all of the TX sensor electrodes (e.g. Tx1 , TxK ) via closed SW3 switches (e.g. SW3-1 and SW3-K) with the SC bus 1015 connected. Any charge that is in the company's own capacities at this time (e.g. Csx1 , CsxK The data stored on the TX electrode is transmitted via the SC bus. 1015 The signal is distributed among all of the TX electrodes. Simultaneously, the countercapacitance detection channel receives the signal. 1102 Charge due to the current Irx , which is due to the potential differences over the counter-capacities such as Cm1 and Cmk is induced away.

[0067] Figs. Figure 13 is a timing diagram according to an embodiment showing signals generated during the six-stage self-capacitance and counter-capacitance measurement process implementing the counter-capacitance discharge technique, as illustrated in Figures Ea1-Eb2.

[0068] Figs. 14A and Figs. Figure 14B illustrates a capacity sensing circuit according to one embodiment. 1900for performing a six-stage combined self-capacitance and counter-capacitance sensing process with counter-capacitance discharge, which includes a baseline compensation circuit. The sensing circuit 1900 includes two TX sensor electrodes Tx1 and TxK and two RX sensor electrodes Rx1 and RxM The capacities Cstx1 , CstxK , Csrx1 and CsrxM represent the respective intrinsic capacities for the electrodes Tx1 , TxK , Rx1 and RxM The electrode Tx1 is with the pin-MUX 1001-1 connected, the electrode TxK is with the pin-MUX 1001-K connected, the electrode Rx1 is with the pin-MUX 1002-1 connected and the electrode RxM is with the pin-MUX 1002-M connected. The electrodes Tx1 , TxK , Rx1 and RxM can be accessed via the respective switches SW3-1 , SW3-K , SW3-18 and SW3-M selectively connect the SC bus to the pin MUX 1015 can be connected and can be controlled via respective switches SWref-1 , SWref-K , Figure 18 and SWref-M selectively with a reference bus 1901 be connected.

[0069] The switches SWRx-1 , SWRx-K , SWRx-18 and SWRx-M allow the electrodes Tx1 , TxK , Rx1 and RxM , via the Rx bus 1014 selectively connected to separate Rx acquisition channels. As in Figs. 14A illustrates the electrodes Rx1 and RxM each with the recording channels 1012-18 and 1012-M connected. Similar to the SW1 and SW2 switches, which are connected to the TX electrodes, they can SW1-18 , SW2-18 , SW1-M and SW2-M must be activated to activate the RX electrodes Rx1 and RxM selectively with Vtx- and ground voltages to generate excitation signals for these electrodes.

[0070] As in Figs. Figure 14A illustrates the detection circuit. 1900 in a pre-charging stage in which the sensor electrode Tx1 with the excitation voltage Vtx is connected Vref to Rx1 is set up. Figs. Figure 14B illustrates the detection stage in which the sensor electrodes are connected via the SC bus. 1015 together and via the SWsc switch with the low-impedance input of the self-capacitance detection channel 1101 are connected. During this stage, the counter-capacities (e.g. Cm1 , CmK ) about the current IcmThe sensor electrodes discharge and store a charge approximately equal to the charge accumulated in a single line multiplied by the sum of the multiphase excitation sequence elements (i.e., from matrix S). This charge is then processed by the charge ADC of the self-capacitance sensing channel. 1101 received.

[0071] This charge can be generated by the sensor's operation, even if no object is present on the detection surface, resulting in a baseline signal. A baseline compensation signal generator can be used to correct this. 1903 A baseline compensation voltage is generated and applied to a shield. 1902 Applied to compensate for the baseline signal. By applying a baseline compensation voltage that has the opposite polarity to the voltage at the sensor electrodes, a voltage is applied to the input of the self-capacitance detection channel. 1101a current is generated that can be used to compensate for the current generated by the sensor electrodes. If the shielding 1902 The applied compensation voltage is the same as the sensor voltage relative to the reference voltage. Vref The charge ADC of the detection channel receives this signal. 1101 The charge is zero. A modulation of the signal applied to the shield. 1902 The applied baseline compensation voltage is applied by actuating the switches SWup, SWmid and SWdn.

[0072] The capacitances between the sensor electrodes can vary with temperature; however, these capacitances are used to generate the baseline compensation signal, as the baseline compensation voltage is applied to the shield. As a result, the charge collected in the sensor and the charge dissipated by the shield are equal. 1902 The introduced charge correlates and reduces sensitivity to temperature fluctuations.

[0073] Figs. Figure 15 illustrates three configurations of an equivalent circuit in which a baseline compensation voltage is applied to a shield conductor. 1902 is created. In a sensor arrangement 150 , which has N TX electrodes, a multiphase sequence S can contain the elements [S1, S2, ... S N ] comprise, where each element S x is equal to +1 or -1. Each element S x is a multiphase sequence weight coefficient that has a sign representing the phase of the excitation signal applied to the corresponding electrode.

[0074] If the sum of the elements is equal to 1 (i.e., ΣS = +1), then the sequence S comprises an odd number of elements. The sensor can be considered equivalent to a sensor in which a single electrode leads to the excitation voltage. Vtxis pre-charged, while the average charge in the remaining electrodes is zero. The configuration 2101 This scenario illustrates the inherent capacity Cs1 a single electrode on Vtx is pre-charged, while the positively charged capacities Cs2 and the negatively charged capacities CsN an even number of remaining electrodes are connected to each other and collectively store a charge of zero.

[0075] After all the sensor electrodes are connected to the SC bus 1015 are connected (as in the configuration) 2102 ), will be in Cs1 The stored charge is shared with the other electrodes, so the voltage at the SC bus is 1015 - Vref + (Vtx - Vref) / N, where N is the number of connected electrodes. The voltage of the shield is then... 1902 Reduced by a quantity Δ (equal to (Vtx - Vref) / N), the resulting voltage across the shield is 1902Vref - (Vtx - Vref) / N (as in the configuration 2103 (shown). The resulting voltage on the SC bus 1015 The reference voltage is increased by the same amount. Vref reduced. Accordingly, it receives when the voltage Vref on the SC bus 1015 When a current is applied to one input of a detection channel ADC and its other input is also connected to the reference voltage Vref, the ADC outputs a current of zero.

[0076] Figs. Figure 16 illustrates a timing diagram showing the signals present at an example TX electrode and the shield. 1902 be generated. As in Figs. Figure 16 illustrates how this varies depending on the shielding. 1902The applied baseline compensation signal spans a range Δ, with a transition at the beginning of each compounding stage. The dashed lines indicate signals generated in an alternative configuration where the compounding and acquisition stages are temporally separated.

[0077] Figs. 17A and Figs. Figure 17B illustrates a capacity sensing circuit according to one embodiment. 2300 for performing a six-stage combined self-capacitance and counter-capacitance sensing process with counter-capacitance discharge, which includes a baseline compensation circuit. The sensing circuit 2300 It works in a similar way to the detection circuit. 1900 , with the exception that the voltage at the shield 1902 is constant and that the charge ADC of the detection channel 1101 The supplied reference voltage is modulated with the baseline compensation signal. As in the Figs.17A and Figs. Figure 17B illustrates the baseline compensation signal generator. 2303 a baseline compensation signal that is not connected to the shield 1902 , but to the lower input of the ADC for the acquisition channel 1101 is created.

[0078] Figs. Figure 18 illustrates an equivalent circuit 2500 , which the detection circuit 2300 during a detection stage, in which a baseline compensation voltage is applied to an input of the detection channel to establish a baseline signal for the detection circuit 2300 to compensate. In the circuit 2500 The baseline compensation signal generator 2303 The baseline signal Vref - (Vtx - Vref) / N is applied to the lower input of the ADC, while the same voltage is applied to the upper input. Therefore, the acquisition channel 1101 No power detected.

[0079] Figs.Figure 19 illustrates a timing diagram showing the signals generated at an example TX electrode and the lower input of the acquisition channel ADC. Figs. 19. The baseline compensation signal applied to the ADC varies over a range Δ, exhibiting a transition at the beginning of each compounding stage. The dashed lines indicate signals generated in an alternative configuration where the compounding and acquisition stages are separated in time.

[0080] Figs. 20A, Figs. 20B, Figs. 20C and Figs. Figure 20D illustrates, according to one embodiment, steps for carrying out a measurement process in which the charge that is in the capacitance Cf between the sensor electrodes and a conductive object is measured. 2701 (e.g., a user's finger) is collected near the sensor array and measured without being affected by capacitances between the electrodes and the shield. The object2701 can be modeled as a node connected to ground via a resistor Rb. Figs. Figure 20A illustrates a pre-charge stage in which an excitation signal pattern is applied to the sensor electrodes, which increases the capacitances Cs between the excited electrodes and the shield. 2702 , the counter-capacitances Cm between electrodes and the capacitances Cf between the object 2701 and charges the electrodes near the object.

[0081] Figs. 20B illustrates a countercapacitance discharge stage, in which the charge that is in the countercapacitances Cm The charge that has accumulated between the sensor electrodes is discharged by connecting the sensor electrodes to each other. After connection, the charge stored in the countercapacitances is distributed among all electrodes. The capacitances Cs and CfThey store an amount of charge corresponding to the total countercapacitance charge averaged across all sensor electrodes. At this stage, the switch... 2704 also opened to improve shielding 2702 to separate from the reference voltage Vref.

[0082] Figs. Figure 20C illustrates a self-capacitance discharge stage in which the sensor electrodes are discharged by closing the switch. 2703 with the shielding 2702 be connected. The capacities Cs between the electrodes and the shielding 2702 are being unloaded. The cargo that is in the capacities Cf between the object 2701 and is stored on the sensor electrodes.

[0083] Figs. 20D illustrates a detection stage in which the remaining charge, which is in the capacities Cf The data is stored and measured. The sensor electrodes are connected via the closed switch. 2703 with the shielding2702 connected and the shielding 2702 is via the closed switch 2705 with the acquisition channel 2706 connected. Thus, the capacities are increased. Cf stored charge through the detection channel 2706 received. Fluctuations in sensor temperature do not affect the measurement of Cf Furthermore, the theoretical baseline signal is zero, as the baseline signal results from shielding deficiencies. However, an LCD display could 2707 , which have a capacity Cshld capacitively coupled to the shielding, noise into the shielding 2702 be introduced.

[0084] Figs. 21 is a flowchart that depicts a measurement process 3100 The process for performing combined self-capacitance and counter-capacitance measurements of a capacitive sensor arrangement according to one embodiment is illustrated. The measurement process 3100 is achieved through components of the detection system100 carried out, which involved the sensor arrangement 130 , the processing device 110 and the host 150 include the process 3100 includes operations for performing a six-stage measurement process, where the stages A , B , C , D , E and F Each represents a pre-loading, a combination, a capture, a pre-loading, a combination and a capture stage, which are repeated in a loop.

[0085] The operations in the preload stage A of the process 3100 correspond to the circuit configurations that are in Fig. 4A, Stage A (for phase +1); Fig. 4C, Stage C (for phase -1); Fig. 10A, Stage A (for phase +1); and Fig. 10C, level D (for phase -1) are illustrated. The stage A includes the blocks 3101 and 3103 .

[0086] In block 3101 The processing device loads 100 during the pre-charging stage A the company's own capacities Cstx for each TX electrode and the counter-capacitance Cm between the TX electrode and the RX electrodes that intersect the TX electrode, by applying an excitation voltage to the TX electrode. In one embodiment, the TX electrodes are each subjected to one of the excitation voltages. Vtx or pre-charged to 0 V, depending on the corresponding value (e.g. +1 or -1) for the TX electrode, which is specified in the excitation matrix S is stored.

[0087] The excitation matrix S can indicate an excitation voltage for one TX electrode that is complementary to the excitation voltage for another TX electrode. In one embodiment, complementary voltages are located at opposite ends of the dynamic range of the signal; accordingly, Vtx and 0 V are complementary to each other, since the TX signal is between 0 V and Vtx varies. The complementary excitation voltages are applied to different TX electrodes at the same time.

[0088] Applying the excitation voltage Vtx or 0 V induces a current Irx for each TX electrode, which flows through the counter-capacitance Cm, where the direction of Irx depends on whether the excitation voltage Vtx or 0 V. Thus, the block generates 3101 a first set of induced currents, comprising a current Irx for each TX electrode to which a corresponding excitation voltage is applied. The current Irx is measured by the counter-capacity measurement channel (e.g. 402 in figures C1, C3 or 1102 measured in figures Ea1, Ea3).

[0089] In block 3103 stops the processing logic 110 at the end of the stage Aany previous integration processes through an in-house capacity measurement channel (e.g. 401 , 1101 ), which occurred during a previous iteration of the measurement process loop 3100 (e.g. in block 3131 ) may have been started before the next stage B The process continues. In one embodiment, the integration process is terminated by initiating a discharge of integration capacitors by a reference current in response to a rising or falling edge of the negative / self-sync signal or the CintP or CintN signal. At the end of the stage A The integration is facilitated by the counter-capacity acquisition channels (e.g. 402 , 1102The polarity is reversed; for example, the integration of positive charge is stopped and the integration of negative charge is started, or vice versa. The integration capacitors of the counter-capacitance detection channels are also discharged by a reference current, which starts the discharge of the capacitors when the integration ends.

[0090] In one embodiment, the composite stage B This can optionally be bypassed to implement a four-stage measurement process. In this case, the process runs 3100 after the stage A in block 3107 with the recording level C continues. In a six-stage process, the process continues. 3100 after the stage A in block 3107 with the combined stage B continued. The operations in the combined stage B of the process 3100 correspond to the circuit configurations that are in Fig. 12A, Stage B(for phase +1) and Fig. 12B, Level E (for phase -1) are illustrated. The stage B includes the block 3105 .

[0091] In block 3105 connects the processing device 110 Each of the TX electrodes shares a common bus conductor. With reference to Fig. For example, 9 are those with the pin-MUX. 1001-1-1001-K connected TX electrodes via their respective SW3 switches to the SC bus 1015 connected before the switch SWsc is closed. Similarly, with reference to Fig. 7, which are connected to the TX connectors 601-1-601-N connected TX electrodes to the SC bus 602 connected before SWsc will be closed. After block 3105 level B The process continues 3100 in block 3107 with the level C on.

[0092] The operations in the acquisition stage C of the process 3100correspond to the circuit configurations that are in Fig. 4B, Level B (for phase +1); Fig. 4D, Level D (for phase -1); Fig. 10B, Level C (for phase +1); and Fig. 10D, Level F (for phase -1) are illustrated. The stage C includes the blocks 3107-3115 .

[0093] In block 3107 connects the processing device 110 each TX electrode via the switches SW3 and SWsc with a charge-to-code converter of a self-capacitance sensing channel (e.g. 401 in figures C2, C4 or 1101 (in Figures Ea2, Ea4). The detection channel receives a reference voltage at its inputs. Vref upright; accordingly, the reference voltage Vref A potential change is applied to each of the connected TX electrodes. The change in potential induces a current at each TX electrode. Itx , which is through the detection channel401 or 1101 can be measured. Thus, block generates 3107 a second set of induced currents, comprising a current Itx for each TX electrode connected to the sensing channel.

[0094] In one embodiment, the processing device 110 in block 3109 a conductive Pfad ready to provide the counter capacity Cm to discharge between each TX electrode and an RX electrode that intersects the TX electrode. With reference to Fig. 10B will be the counter capacity Cm1 for example, discharge by discharging both the TX electrode Tx1 as well as the RX electrode RxM by closing the switches SW3-M and SW3-1 with the SC bus 1015 be connected.

[0095] In one embodiment, the process includes 3100 the block 3111 , in which a baseline compensation circuit 1903is used to send a baseline compensation signal to a shield 1902 to apply, which connects with all electrodes in the sensor arrangement 130 It is capacitively coupled, as described with reference to Figures Fa1-Fa4. The application of the baseline compensation signal to the shielding 1902 reduces a baseline current applied to a charge-to-code converter of the self-capacitance sensing channel (e.g. 1101 ) is received.

[0096] In one embodiment, the process includes 3100 the block 3113 , in which a baseline compensation circuit 2303 , as in Fig. Figure 17A illustrates how to apply a baseline compensation signal to a reference input of the charge-to-code converter of the self-capacitance sensing channel, as shown in the Fig. As described in 17A-19, applying the baseline compensation signal to the reference input of the charge-to-code converter reduces the baseline output of the charge-to-code converter.

[0097] In various embodiments, the baseline compensation signal can only be connected to the shield. 1902 , as in block 3111 provided, or only to the reference input of the charge-to-code converter, as in block 3113 provided, created; alternatively, a combination of these two approaches can be used to compensate for a baseline signal.

[0098] In block 3115 The processing device measures 110 a sum of the second set of Itx streams, which are in block 3107This is achieved by integrating charge from the second set of Itx currents in a charge-to-code converter (i.e., a charge ADC) of the self-capacitance measurement channel, whose input is connected to the TX electrodes. The integration begins with the start of the acquisition stage. C and continues until the end of the next pre-charging stage (i.e., in block). 3119 ) continued.

[0099] The operations in the preload stage D of the process 3100 correspond to the circuit configurations that are in Fig. 4C, Stage C (for phase +1); Fig. 4A, Stage A (for phase -1); Fig. 10C, level D (for phase +1); and Fig. 10A, Stage A (for phase -1) are illustrated. The stage D includes the blocks 3117 and 3119 .

[0100] The pre-charging stage D includes similar operations to the pre-charging stage A, with the exception that the processing device 110 , as in block 3117 provided, applies a second excitation voltage to each TX electrode, which corresponds to the voltage applied to the same TX electrode during the stage A in block 3101 The applied excitation voltage is complementary. For example, in stage A If 0 V is applied to a specific TX electrode, then in block 3117 level D the complementary excitation voltage Vtx applied to the same X-electrode. In block 3119 The previously started self-capacitance charge integration is stopped and the polarity of the ongoing counter-capacitance charge integration is switched, in a similar way to block 3103 provided.

[0101] The operations in the network stage E of the process 3100 correspond to the circuit configurations that are in Fig. 12B, Level E (for phase +1) and Fig. 12A, Stage B (for phase -1) are illustrated. The stage E includes the blocks 3119 and 3121 During the combined phase E connects the processing device 110 Each TX electrode with a common bus conductor (e.g. SC bus). 1015 ), as in block 3105 provided in a similar manner.

[0102] The operations in the acquisition stage F of the process 3100 correspond to the circuit configurations shown in Figure C4, stage D (for phase +1); Figure C2, stage B (for phase -1); Figure Ea4, stage F (for phase +1); and figure Ea2, level C (for phase -1) are illustrated. The stage F includes the blocks 3123-3131 .

[0103] The recording level F includes similar operations to the acquisition stage C . In block 3123 connects the processing device 110each TX electrode again via the switches SW3 and SWsc with the charge-to-code converter of an intrinsic capacitance sensing channel, similar to that in Block 3107 maintains the reference voltage Vref at the TX electrode. As in block 3125 Provided, the processing device can 110 provide a conductive path to measure the counter-capacitance Cm similarly to block 3109 to unload.

[0104] Baseline compensation can also be performed in a similar manner to that described previously, by following the steps outlined in Block [number]. 3127 provided, a baseline compensation signal to a shield 1902 is created by, as in block 3129 The baseline compensation signal is provided by applying it to a reference input of the charge-to-code converter, or by a combination of these approaches. The operations of the blocks 3127 and 3129are each similar to those in the blocks 3111 and 3113 provided operations.

[0105] In block 3131 The processing device measures 110 a sum of the second set of Itx streams, which are in block 3123 This is achieved by integrating charge from the second set of Itx currents in a charge-to-code converter (i.e., a charge ADC) of the self-capacitance measurement channel, whose input is connected to the TX electrodes. The integration begins with the start of the acquisition stage. F and continues until the end of the next pre-charging stage (i.e., in block). 3103 ) continued.

[0106] From Block 3131 The process returns 3100 to block 3101 level A back. The process 3100 Thus, the steps are repeated. A , B , C , D , E and F (or alternatively the levels) A , C, D and F ) in a sequential loop to continuously generate the currents used to measure the self-capacitances and counter-capacitances of the sensor electrodes.

[0107] Fig. 22 is a flowchart that shows a process 3200 to calculate the own capacities and counter-capacities based on the measurements obtained through the process 3100 The calculation process is illustrated according to one embodiment. 3200 is achieved through components of the capacity measurement system 100 carried out, which the processing device 110 and / or the host device 150 include.

[0108] In block 3201 of the process 3200 The processing device calculates 110 for each TX electrode in the sensor arrangement 130 the counter-capacitance between the TX electrode and each RX electrode of the sensor assembly 130based on the measurements recorded for the first set of Irx currents. In particular, the processing device performs 110 based on the charge values ​​measured at the RX channels QXm a deconvolution operation as previously described with reference to Equation 8 and Equation 9.

[0109] In block 3203 calculates the processing logic 110 a parasitic capacitance for each TX electrode in the sensor array 130 based on the reference voltage Vref applied to the TX electrode and the induced TX currents Itx obtained charge measurements QXp , as previously described with reference to Equation 10 and Equation 11.

[0110] In block 3205 The processing device calculates 110for each TX electrode an intrinsic capacitance according to equation 14, where the calculated counter-capacitances are subtracted from the parasitic capacitances as previously described with reference to equation 12, equation 13 and equation 14.

[0111] In block 3207 determines the processing device 110 , whether a signal detected in the calculated counter-capacitances correlates with a signal detected in the calculated intrinsic capacitances. For example, the calculated counter-capacitance map 120 Countercapacitance values ​​include those that are elevated as a result of a conductive object, such as a finger, near the sensor electrode intersection points, corresponding to the elevated values. The processing device 110 determines whether intrinsic capacity values ​​of the intrinsic capacity vector 121for the corresponding locations as well. This is particularly true if the intrinsic capacitances are also increased for electrodes associated with intersections where opposing capacitances are increased. In one embodiment, the processing device recognizes 110 an increase in internal capacity by comparing each internal capacity value with a threshold quantity.

[0112] In block 3207 Increases in counter-capacitance that are not correlated with corresponding increases in own capacitance can indicate the presence of water or other liquids on the detection surface. To ensure that these types of contacts are correctly interpreted as unintended touches, the process... 3200 in block 3209 continues and rejects the presence of the object in response to recognition in block 3207that the object changes the counter capacity without changing its own capacity by more than the threshold amount.

[0113] If in block 3207 Since the increases in counter-capacity values ​​correlate with increases in own capacity values, the process continues. 3200 with block 3211 on. In block 3211 The processing device recognizes 110 Thus, in response to the detection that the object changes both the intrinsic capacitance of the TX electrode and the counter-capacitance between the TX and RX electrodes, the presence of the object at an intersection between a TX and an RX electrode is determined. The counter-capacitances therefore indicate the location of contact on the touch sensing surface.

[0114] In block 3213 The host device receives 150The device determines the location of the contact, as indicated by the calculated counter-capacitances, and performs a function in response to the contact. For example, the host device can 150 an advertisement 202 Update to show an updated cursor position or keystroke. In one embodiment, the host device controls this. 150 in response to the detected contact point electronic subsystems 201 in a vehicle 200 .

[0115] Various modifications can be made to the preceding embodiments; for example, signals described as being activated at a high voltage can instead be activated at a low voltage, or specified components can be replaced by other components that have similar functionality. As described herein, conductive electrodes that are "electrically connected" or "electrically coupled" can be coupled such that a conductive path with a relatively low resistance exists between the conductive electrodes.Quantities, measures, or other values ​​described as "essentially" the same may be nominally equal but need not be exactly the same (with variations due to manufacturing tolerances, environmental conditions, quantization or rounding errors, and / or other factors), or may be sufficiently close to the same to achieve an intended effect or benefit.

[0116] The embodiments described herein include various operations. These operations may be performed by hardware components, software, firmware, or a combination thereof. As used herein, the term "coupled with" may mean direct or indirect coupling through one or more intermediary components. Any signals provided via different buses described herein may be time-division multiplexed with other signals and provided via one or more common buses. Additionally, the interconnection between circuit components or blocks may be shown as buses or as individual signal lines. Each of the buses may alternatively be one or more individual signal lines, and each of the individual signal lines may alternatively be a bus.

[0117] Certain embodiments may be implemented as a computer program product, which may include instructions stored on a computer-readable medium. These instructions can be used to program a general-purpose or specialized processor to perform the described operations. A computer-readable medium includes any mechanism for storing or transmitting information in a form (e.g., software, processing application) that can be read by a machine (e.g., a computer). The computer-readable storage medium may, but is not limited to, include: a magnetic storage medium (e.g., a floppy disk); an optical storage medium (e.g., a CD-ROM); a magneto-optical storage medium; a fixed-order memory (ROM); a working memory (RAM); a erasable programmable memory (e.g., a programmable memory).EPROM and EEPROM); a flash memory or other type of medium suitable for storing electronic instructions.

[0118] Additionally, some implementations can be carried out in distributed computing environments where the computer-readable medium is stored on and / or executed by more than one computer system. Furthermore, the information transferred between computer systems can be transmitted either by pull or by push over the transmission medium connecting the computer systems.

[0119] Although the operations of the method(s) herein are shown and described in a specific order, the order of operations of each method may be changed so that certain operations may be performed in reverse order or so that a certain operation may be performed at least partially concurrently with other operations. In another embodiment, instructions or sub-operations of individual operations may take place in an intermittent and / or alternating manner.

[0120] In the preceding patent description, the claimed subject matter was described with reference to specific embodiments thereof. However, it will be evident that various modifications and changes can be made to it without deviating from the broader spirit and scope of the invention as set forth in the appended claims. Accordingly, the patent description and the drawings are to be regarded in an illustrative rather than a limiting sense. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 15850119

[0001] US 62535402

[0001]

Claims

[1] A capacity assessment procedure that includes the following: Generating a first set of one or more currents by precharging, for each transmitting (TX) electrode of a set of one or more TX electrodes, an intrinsic capacitance of the TX electrode and a counter-capacitance between the TX electrode and a receiving (RX) electrode of a set of one or more RX electrodes by applying a first excitation voltage corresponding to the TX electrode to the TX electrode to induce a first current of the first set of currents; Generating a second set of one or more currents by applying, for each TX electrode of the set of TX electrodes, a reference voltage to the TX electrode to induce a second current of the second set of currents; and for each TX electrode of the set of TX electrodes, Calculating the self-capacitance of the TX electrode based on the second set of currents and Calculating the counter-capacitance between the TX electrode and each RX electrode in the set of RX electrodes based on the first set of currents. [2] Method according to claim 1, wherein for each TX electrode of the set of TX electrodes, the calculation of the intrinsic capacitance of the TX electrode comprises the following: Calculating a parasitic capacitance for the TX electrode based on the reference voltage applied to the TX electrode and the induced second current; Calculating a counter-capacitance between the TX electrode and each RX electrode of the set of RX electrodes by performing a deconvolution operation based on the first set of currents; and Subtracting the sum of the counter-capacities from the parasitic capacity. [3] Method according to claim 1, wherein for each TX electrode of the set of TX electrodes the application of the first excitation voltage is carried out during a first stage, wherein the application of the reference voltage is carried out during a second stage following the first stage, and wherein the method further comprises for each TX electrode of the set of TX electrodes: Applying a second excitation voltage, complementary to the first excitation voltage, to the TX electrode during a third stage following the second stage; and Applying the reference voltage to the TX electrode during a fourth stage, following the third stage. [4] Method according to claim 1, wherein for each TX electrode in the set of TX electrodes, applying the reference voltage to the TX electrode includes connecting the TX electrode to a charge-in-code converter, wherein, prior to connecting the TX electrode to the charge-in-code converter, the method further includes connecting each of the set of TX electrodes to a common bus conductor. [5] Method according to claim 1, wherein for a first TX electrode and a second TX electrode of the set of TX electrodes the first excitation voltage corresponding to the first excitation voltage corresponding to the second TX electrode is complementary. [6] Method according to claim 1, further comprising for each TX electrode of the set of TX electrodes, before applying the reference voltage to the TX electrode, discharging the counter-capacitance between the TX electrode and an RX electrode of the set of RX electrodes by providing a conductive path between the TX electrode and the RX electrode. [7] Method according to claim 1, further comprising applying a baseline compensation signal to a shield to reduce a baseline current received at a charge-to-code converter from the set of TX electrodes, wherein for each TX electrode in the set of TX electrodes the intrinsic capacitance of the TX electrode is a capacitance between the TX electrode and the shield. [8] The method according to claim 1, further comprising: Measuring a sum of the second set of currents by integrating charge from the second set of currents in a charge-to-code converter having a first input coupled to each TX electrode of the set of TX electrodes; and Applying a baseline compensation signal to a second input of the charge-to-code converter to reduce a baseline output of the charge-to-code converter. [9] The method according to claim 1, further comprising for one or more TX electrodes of the set of TX electrodes: Detecting the presence of an object at the TX electrode in response to the detection that the object changes both the intrinsic capacitance of the TX electrode and the counter-capacitance between the TX electrode and one of the set of RX electrodes; and Rejecting the presence of the object in response to the recognition that the object changes the counter capacity without changing its own capacity by more than a threshold amount. [10] A capacity sensing circuit comprising the following: a set of one or more transmit (TX) ports configured for the following: Generating a first set of one or more currents, wherein for each TX terminal of the set of TX terminals the TX terminal is coupled to a TX electrode of a set of one or more TX electrodes and is configured to precharge an intrinsic capacitance of the TX electrode and a counter-capacitance between the TX electrode and a receive (RX) electrode of a set of one or more RX electrodes by applying a first excitation voltage corresponding to the TX electrode to the TX electrode to induce a first current of the first set of currents, and Generating a second set of one or more currents, wherein for each TX terminal of the set of TX terminals the TX terminal is configured to apply a reference voltage to the TX electrode, to induce a second stream of the second set of streams; and a processing logic coupled to the set of TX terminals, wherein the processing logic for each TX electrode of the set of TX electrodes is configured for the following: Calculating the self-capacitance of the TX electrode based on the second set of currents; and Calculating the counter-capacitance between the TX electrode and each RX electrode in the set of RX electrodes based on the first set of currents. [11] Capacity monitoring circuit according to claim 10, further comprising: a self-capacitance measurement channel coupled to the set of TX ports and configured to measure a sum of the second set of one or more currents; and a set of counter-capacitance detection channels coupled to the set of RX electrodes and configured to measure the first set of currents, each TX terminal of the set of TX terminals further comprising: a first switch to apply the reference voltage to the TX electrode coupled to the TX connector and a second switch to apply the first excitation voltage to the TX electrode. [12] Capacitance sensing circuit according to claim 10, wherein for a first TX terminal and a second TX terminal of the set of TX terminals: the first excitation voltage applied by the first TX terminal to the TX electrode coupled to the first TX terminal is complementary to the first excitation voltage applied by the second TX terminal to the TX electrode coupled to the second TX terminal. [13] Capacitance sensing circuit according to claim 10, wherein for each TX port of the set of TX ports: the TX terminal is configured to apply the initial excitation voltage during a first stage to the TX electrode coupled to the TX terminal, and the TX port is configured to apply the reference voltage to the TX electrode during a second stage following the first stage, and wherein the TX connector is further configured to provide, for each TX connector of the set of TX connectors: to apply a second excitation voltage, complementary to the first excitation voltage, to the TX electrode during a third stage following the second stage, and to apply the reference voltage to the TX electrode during a fourth stage following the third stage. [14] Capacitance sensing circuit according to claim 10, wherein the processing logic for each TX electrode of the set of TX electrodes is further configured for the following: Calculating a parasitic capacitance for the TX electrode based on the reference voltage applied to the TX electrode and the second current induced by the reference voltage; Calculate a counter-capacitance between the TX electrode and each RX electrode of the set of RX electrodes by performing a deconvolution operation based on the first set of currents; and subtract a sum of the counter-capacitances from the parasitic capacitance. [15] Capacity monitoring circuit according to claim 10, wherein: The set of TX terminals further includes a first set of switches configured to connect each TX electrode in the set of TX electrodes to a common bus conductor; and The capacitance sensing circuit further includes a self-capacitance channel switch configured to connect the common bus conductor to a charge-to-code converter, while each TX electrode of the set of TX electrodes is connected to the common bus conductor. [16] Capacitance sensing circuit according to claim 10, wherein for each TX terminal of the set of TX terminals the TX terminal further includes a discharge switch configured to selectively provide a conductive path between the TX electrode coupled to the TX terminal and each RX electrode of the set of RX electrodes. [17] A capacity measurement system that includes the following: a capacitive sensor arrangement comprising a set of one or more TX electrodes and a set of one or more RX electrodes; a set of one or more transmit (TX) ports configured for the following: Generating a first set of one or more currents, wherein for each TX terminal of the set of TX terminals the TX terminal is coupled to a TX electrode of the set of TX electrodes and is configured to precharge an intrinsic capacitance of the TX electrode and a counter-capacitance between the TX electrode and a receive (RX) electrode of a set of one or more RX electrodes by applying a first excitation voltage corresponding to the TX electrode to the TX electrode to induce a first current of the first set of currents, and Generating a second set of one or more currents, wherein for each TX terminal of the set of TX terminals the TX terminal is configured to apply a reference voltage to the TX electrode in order to induce a second current of the second set of currents; a processing logic coupled to the set of TX terminals, wherein the processing logic for each TX electrode of the set of TX electrodes is configured for the following: Calculating the self-capacitance of the TX electrode based on the second set of currents, Calculating the countercapacitance between the TX electrode and each RX electrode in the set of RX electrodes based on the first set of currents; and a host device that is coupled with the processing logic and configured to perform one or more functions based on the following: a set of intrinsic capacitances that includes the intrinsic capacitance for each TX electrode of the set of TX electrodes, and a set of counter-capacitances that includes the counter-capacitance between each TX electrode in the set of TX electrodes and each RX electrode in the set of RX electrodes. [18] Capacity measurement system according to claim 17, wherein for a first TX port and a second TX port of the set of TX ports: the first excitation voltage applied by the first TX terminal to the TX electrode coupled to the first TX terminal is complementary to the first excitation voltage applied by the second TX terminal to the TX electrode coupled to the second TX terminal. [19] Capacity recording system according to claim 17, further comprising: a display coupled to the host device, wherein the capacitive sensor array is located on the display and wherein the host device is configured to update the display in response to the set of own capacitances and the set of counter-capacitances. [20] Capacity monitoring system according to claim 17, further comprising: a vehicle coupled to the host device, wherein the host device is configured to control one or more vehicle subsystems in the vehicle based on the set of own capacities and the set of counter-capacities.

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