Semiconductor device, power module and power supply

Abstract

Semiconductor device comprising: a heat source (8(TS)) comprising a semiconductor component, wherein the semiconductor component generates heat in an operating state;a heat diffusion unit (10) which is thermally connected to the heat source, wherein the heat diffusion unit forms a space (OA+AP) at a position opposite the heat source, by means of a first section extending from a connecting section (8(TS)) connected to the heat source on two sides along a first direction parallel to a connecting surface connected to the heat source, and by means of a second and a third section extending from two ends of the first section in a second direction away from the heat source, a first heat conduction layer (12SA) attached to a surface of the second section facing the space, and a second heat conduction layer (12SB) attached to a surface of the third section facing the space;a first heat dissipation unit (6) attached to the first heat conduction layer (12SA) comprising a first base unit (14PA) and a plurality of first fin units (16FA1,16FA2,..., 16FAm) arranged to extend outwards from the first base unit into the space (OA+AP); and a second heat dissipation unit (6) attached to the second heat conduction layer (12SB) and comprising a second base unit (14PB) and a plurality of second fin units (16FB1, 16FB2, ..., 16FBm) arranged to extend into space from the first base unit, wherein, at least in a section parallel to a plane defined by the first direction and the second direction, tips of the first and second fin units extend into space (OA+AP) to a position directly below a position where the semiconductor device is located.

Description

TECHNICAL AREA The embodiments described here relate to a semiconductor device, a power module, and a power supply. STATE OF THE ART Traditionally, one type of power module known is one in which a perimeter or outline of a semiconductor component or components, including a power element or power elements (chip(s)), such as an insulated gate bipolar transistor (IGBT), is encapsulated with resin. In an operating state, it is generally intended or common practice to arrange heat radiators, e.g., a heat sink and a fin, in a semiconductor component that generates heat, and to radiate the heat towards the back surface of the substrate in such a way as to cool the semiconductor component. In recent years, the increasing heat generation density of electronic materials has become a problem. Consequently, to improve the performance of cooling devices, it is desirable to suppress or limit the junction temperature (Tj) of components to values ​​within predefined limits. For example, in power modules used for power conversion units in electric vehicles, water-based cooling devices have been the predominant choice. However, water-based cooling devices require coolant storage tanks, pumps for supplying water, and similar components, making the entire cooling system complex and large, thus increasing its weight. Patent literature 1: JP 2009 - 033 799 APatent literature 2: JP 2009 - 277 699 APatent literature 3: JP 2001 - 223 308 A . Further semiconductor devices with cooling arrangements are known from documents DE 10 2014 212 097 A1 , US 6 538 892 B2 , DE 11 2013 006 640 T5 , DE 10 2011 077 543 A1 , JP 2012 - 49 167 A , WO 01 / 41 520 A1 and JP H10 - 270 616 A . OVERVIEW OF THE INVENTION Technical problem The embodiments provide a semiconductor device, a power module and a power supply, each of which is of the air-cooled type, each of which has high heat dissipation performance and achieves a low weight. Solution to the problem According to one aspect of the invention, a semiconductor device with the features of claim 1 is provided. According to another aspect of the invention, a semiconductor device with the features of claim 8 is provided. According to another aspect of the invention, a semiconductor device with the features of claim 9 is provided. According to another aspect of the invention, a semiconductor device with the features of claim 12 is provided. According to another aspect of the embodiments, a power module is provided with a semiconductor device according to the invention as per claim 19. According to yet another aspect of the embodiments, a power supply according to claim 21 is provided which is configured to convert an input voltage and output the converted input voltage using the semiconductor device or power module according to the invention. Preferred embodiments are defined in the dependent claims. Advantageous effects of the invention According to the embodiments, the semiconductor device, the power module and the power supply can be provided, each of which is of the air-cooled type, each of which has high heat dissipation performance and each of which achieves a low weight. BRIEF DESCRIPTION OF THE DRAWING [Fig. 1] A conceptual diagram illustrating a state of heat transfer generated by a power module (hereinafter also referred to as PM, "power module"). [Fig. 2] A comparison diagram of the heat transfer capability of different cooling methods. [Fig. 3] A schematic configuration diagram of a semiconductor device according to the embodiments. [Fig. 4] A schematic cross-sectional diagram of a configuration providing a heat diffusion unit for diffusing heat using highly thermally conductive material(s), and a heat contact space unit between an air cooling fin unit and the heat diffusion unit, in the semiconductor device according to the embodiments. [Fig.[5] A schematic configuration diagram of a thermal resistance circuit representing a configuration in which air-cooling fin units are in thermal contact with a heat diffusion unit at a plurality of points to achieve a reduction of thermal resistance or a thermal resistance value in the semiconductor device according to the embodiments. [Fig. 6] A schematic cross-sectional structure diagram of a semiconductor device according to a first embodiment. [Fig. 7] A schematic cross-sectional structure diagram of a semiconductor device according to a second embodiment. [Fig. 8] A schematic cross-sectional structure diagram of a semiconductor device according to a third embodiment. [Fig. 9] A schematic cross-sectional structure diagram of a semiconductor device according to a fourth embodiment. [Fig.[Fig. 10] An explanatory diagram of a computational evaluation method for a thermal fluid simulation in the semiconductor device according to the embodiments. [Fig. 11] An explanatory diagram of the respective composite materials applied to the thermal fluid simulation in the semiconductor device according to the embodiments. [Fig. 12] (a) An explanatory diagram of an equivalent thermal resistance of an air cooling fin unit in the semiconductor device according to the embodiments, and (b) a configuration diagram of an equivalent thermal resistance circuit of an air cooling fin unit. [Fig. 13] (a) An explanatory diagram of an equivalent thermal resistance of three air cooling fin units in the semiconductor device according to the embodiments, and (b) a configuration diagram of an equivalent thermal resistance circuit of three air cooling fin units in the semiconductor device according to the embodiments.[Fig. 14] A simulation result of a relationship between a thermal resistance Rth (fin) (K / W) and a length LF (mm) of an air cooling fin using a material as a parameter when a base unit and an air cooling fin are made of the same material, in the semiconductor device according to the embodiments. [Fig. 15] A simulation result of a relationship between a ratio RATIO and the length LF (mm) of the air cooling fin, using a material as a parameter when the base unit and the air cooling fin unit are made of the same material, in the semiconductor device according to the embodiments. [Fig.[Fig. 16] (a) A schematic configuration diagram when the base unit and the air-cooling fin unit are made of the same material, in the semiconductor device according to the embodiments; (b) a schematic configuration diagram when the base unit and the air-cooling fin unit are made of different materials; and (c) a diagram showing a performance list of each of the materials graphite, Cu, Al, an alloy, and Fe. [Fig. 17] A thermal resistance simulation result when the base unit and the air-cooling fin unit are made of different materials (air-cooling fin length LF = 80 mm), in the semiconductor device according to the embodiments. [Fig.[Fig. 18] A thermal resistance simulation result when the base unit and the air cooling fin unit are made of different materials (air cooling fin length LF = 40 mm) in the semiconductor device according to the embodiments. [Fig. 19] A thermal resistance simulation result when the base unit and the air cooling fin unit are made of different materials (air cooling fin length LF = 20 mm) in the semiconductor device according to the embodiments. [Fig. 20] A thermal resistance simulation result when the base unit and the air cooling fin unit are made of different materials (air cooling fin length LF = 10 mm) in the semiconductor device according to the embodiments. [Fig.21 ] (a) A thermal resistance simulation result of the ratio RATIO and the thermal resistance when the base unit and the air-cooling fin unit are made of Cu-Cu, Cu-graphite, Al-graphite, alloy-graphite, or Fe-graphite (air-cooling fin length LF = 80 mm), in the semiconductor device according to the embodiments, and (b) a thermal resistance simulation result of the ratio RATIO and the thermal resistance when the base unit and the air-cooling fin unit are made of Cu-Cu, Cu-graphite, Al-graphite, alloy-graphite, or Fe-graphite (air-cooling fin length LF = 10 mm), in the semiconductor device according to the embodiments. [Fig.22 ] (a) A simulation result of a relationship between the thermal resistance and the number of fins using the length LF of the air-cooling fin as a parameter, in the semiconductor device according to the embodiments, and (b) a simulation result of a relationship between the ratio RATIO and the number of fins using the length LF of the air-cooling fin as a parameter, in the semiconductor device according to the embodiments. [Fig. 23] A schematic cross-sectional structure diagram of a semiconductor device according to a fifth embodiment. [Fig. 24] A schematic cross-sectional structure diagram of a semiconductor device according to a sixth embodiment. [Fig.

[25] (a) A bird's-eye view configuration diagram of a SiC-PM (2-in-1) 8 according to the embodiments, mounted on the semiconductor device according to the embodiments, (b) a front view diagram of the SiC-PM (2-in-1) 8 according to the embodiments, viewed from the direction of arrow A in Fig. 25(a), and (c) a top view diagram of the SiC-PM (2-in-1) 8 according to the embodiments, mounted on the semiconductor device according to the embodiments. [Fig. 26] A schematic cross-sectional structure diagram of a configuration example in which the SiC-PM is mounted on the semiconductor device according to the embodiments. [Fig.[Fig. 27] (a) A process view of an assembly method of the SiC-PM (2-in-1) according to the embodiments, wherein the SiC-PM is attached to a vapor chamber, (b) a process view of the assembly method of the SiC-PM (2-in-1) according to the embodiments, wherein the air cooling fin unit is attached to the vapor chamber, and (c) a process view of the assembly method of the SiC-PM (2-in-1) according to the embodiments, wherein a fan is attached to it. [Fig. 28] (a) A bird's-eye view configuration diagram of a SiC-PM (6-in-1) according to the embodiments, mounted on the semiconductor device according to the embodiments, (b) a side view diagram of the SiC-PM (6-in-1) according to the embodiments, mounted on the semiconductor device according to the embodiments, and (c) a top view diagram of the SiC-PM (6-in-1) according to the embodiments, mounted on the semiconductor device according to the embodiments. Fig.[Fig. 29] (a) A process view of an assembly method of the SiC-PM (6-in-1) according to the embodiments, wherein the SiC-PM is attached to a vapor chamber, (b) a process view of the assembly method of the SiC-PM (6-in-1) according to the embodiments, wherein the air-cooling fin unit is attached to the vapor chamber, and (c) a process view of the assembly method of the SiC-PM (6-in-1) according to the embodiments, wherein a fan is attached to it. [Fig. 30] A schematic cross-sectional structure diagram of another configuration example of the SiC-PM (6-in-1) according to the embodiments. [Fig. 31] (a) A bird's-eye view of an upper container of a vapor chamber applicable to the semiconductor device according to the embodiments, (b) a bird's-eye view of a lower container thereof, and (c) an explanatory diagram of an operating principle of the vapor chamber. [Fig.[Fig. 32] A schematic configuration diagram from a bird's-eye view showing a laminated structure of a graphite sheet (graphite layer) forming a graphite substrate, applicable to the semiconductor device according to the embodiments. [Fig. 33] (a) A schematic configuration diagram from a bird's-eye view of an application example of a graphite substrate with an XY orientation in an example of a graphite substrate applicable to the semiconductor device according to the embodiments, (b) a schematic configuration diagram from a bird's-eye view showing an application example of a graphite substrate with an XZ orientation, and (c) an explanatory diagram showing an aspect in which a graphite substrate with an XZ orientation is obtained by rotating the graphite substrate with the XY orientation by 90 degrees. [Fig. 34] A simulation result of an effect verification orEfficiency verification of a cooling device according to a comparative example. [Fig. 35] A simulation result of an efficiency verification of the semiconductor device according to the embodiment (Cu). [Fig. 36] A simulation result of an efficiency verification of the semiconductor device according to the embodiment (CuVC). [Fig. 37] A simulation result of a thermal resistance Rth (fin) of the semiconductor devices according to a comparative example 1, a comparative example 2, the embodiment (Cu) and the embodiments (CuVC). [Fig. 38] A schematic circuit diagram of a silicon carbide-based metal oxide semiconductor field-effect transistor (SiC MOSFET) of a 1-in-1 module, wherein the PM is mounted on the semiconductor device according to the embodiments. [Fig. 39] A detailed circuit diagram of the SiC MOSFET of the 1-in-1 module, which is the PM to be mounted on the semiconductor device according to the embodiments. is. [Fig.][Fig. 40] A schematic circuit diagram of a SiC MOSFET of a 2-in-1 module, which is the PM to be mounted on the semiconductor device according to the embodiments. [Fig. 41] A schematic cross-sectional structure diagram showing a SiC MOSFET with a source pad electrode SP and a gate pad electrode GP, which is an example of the semiconductor device to be applied to the PM to be mounted on the semiconductor device according to the embodiments. [Fig. 42] A schematic cross-sectional structure diagram showing an IGBT with an emitter pad electrode EP and a gate pad electrode GP, which is an example of the semiconductor device to be applied to the PM to be mounted on the semiconductor device according to the embodiments. [Fig.[Fig. 43] A schematic cross-sectional structure diagram of a doubly implanted SiC-MOSFET (SiC-DIMOSFET), which is an example of a semiconductor device applicable to the PM to be mounted on the semiconductor device according to the embodiments. [Fig. 44] A schematic cross-sectional structure diagram of a trench SiC-MOSFET (SiC-TMOSFET), which is an example of the semiconductor device applicable to the PM to be mounted on the semiconductor device according to the embodiments. [Fig.[Fig. 45] An example of a circuit configuration in which the SiC MOSFET is used as a semiconductor device, and wherein a snubber capacitor is connected between a power terminal PL and a ground terminal NL, in a circuit configuration of a three-phase alternating current inverter (AC inverter) constructed by incorporating the PM, which is to be mounted on the semiconductor device according to the embodiments. [Fig. 46] An example of a circuit configuration in which the SiC MOSFET is used as the semiconductor device, in a circuit configuration of a three-phase alternating current inverter (AC inverter) constructed by incorporating the PM, which is to be mounted on the semiconductor device according to the embodiments. DESCRIPTION OF EXECUTION FORMS The embodiments are described below with reference to the drawing. In the description of the drawing below, identical or similar reference numerals are assigned to identical or similar parts. However, it should be noted that the drawings are schematic in nature, and therefore the relationship between thickness and plane size, and the ratio of the thickness(es), may differ from an actual object. Therefore, a detailed thickness and size should be determined taking into account the explanation below. Naturally, this also includes parts where the relationship and ratio of a mutual size differs even in other drawings. Furthermore, the embodiments shown below represent, by way of example, the device and the method for materializing or implementing the technical idea; and the embodiments do not specify the material, shape, structure, arrangement, etc., of each component part, as shown below. The embodiments may be modified without departing from the basic concept or scope of the claims. [First embodiment] (Basic technology) Fig. 1 shows a conceptual diagram to illustrate a state of heat transfer generated by a PM 80. The PM 80 is mounted on a cooling device 90. The cooling device 90 is located in a refrigerant 28. The refrigerant 28 is water in the case of water cooling, or air in the case of air cooling. The PM 80 includes a semiconductor component Q20, which corresponds to a heat source (hereinafter referred to as TM or TS, "thermal source") that generates heat during operation. The semiconductor component Q20 is, for example, arranged on an insulating ceramic substrate. The insulating ceramic substrate can, for example, be formed with a direct bonding copper substrate (DBC substrate, "Direct Bonding Copper"). In the example shown in Fig. 1, the insulating ceramic substrate includes a ceramic substrate 21, a front-side electrode layer 23 of the ceramic substrate 21, and a back-side electrode layer 22 of the ceramic substrate 21. The semiconductor component Q20 is bonded to the front-side electrode layer 23, for example, by means of a fired silver layer 27. Furthermore, the back-side electrode layer 22 is connected to the cooling device 90 via a thermal conductivity layer 25.The semiconductor component Q20 can, for example, include an IGBT, a diode, a Si-based MOSFET, a SiC-based MOSFET, or a GaN-based FET. The thermal conductivity layer 25 can include any layer of a thermal conductivity layer, a solder layer, or a burnished Ag layer, to name a few examples. The PM 80 is resin-encapsulated with a casting resin layer 300, such as silicone resin or a polyimide resin. Heat from the semiconductor component Q20, which corresponds to the heat source TS that generates heat in the operating state, is transferred to the cooling device 90 via the fired Ag layer 27, the insulating ceramic substrate (23 / 21 / 22), and the heat-conducting layer 25, as indicated by thick arrows. Furthermore, heat is transferred from the cooling device 90 to the coolant 28, such as water or air, as shown by thin arrows. Below, the thermal resistance or thermal resistance value Rja of the semiconductor component Q20 to the coolant 28 is expressed by the total sum of a thermal resistance in a heat conduction unit TC and a thermal resistance in a heat transfer unit TT. The thermal resistance of the heat conduction unit TC is a thermal resistance in PM 80 and is expressed as t / λA. Here, t denotes the thickness of the heat conduction unit TC, λ denotes the heat transfer coefficient of the heat conduction unit TC, and A denotes the heat transfer area. The thermal resistance in the heat transfer unit TT is a thermal resistance in the cooling device 90 and is expressed as 1 / HA. In this context, H denotes a heat transfer coefficient in the cooling device 90. The thermal resistance Rja is expressed by equation (1): Although the thermal resistance in the water-cooled heat transfer unit TT is lower than the thermal resistance in the heat conduction unit TC, the thermal resistance in the air-cooled heat conduction unit TC is essentially the same as the thermal resistance in the heat transfer unit TT, and is about 50% of the total thermal resistance Rja. In this context, a comparison between heat transfer capabilities in the different cooling methods is carried out or expressed as shown in Fig. 2. In the case of air cooling, where the coolant is air, the heat transfer coefficient ranges from a few W / m²K to several hundred W / m²K. In the case of water cooling, where the coolant is water, the heat transfer coefficient ranges from a few tens of W / m²K to several thousand W / m²K. The heat transfer efficiency of air cooling is lower than that of water cooling, and the cooling performance of air cooling is relatively low. Furthermore, since a water cooling system requires water circulation, the entire system becomes more complex. On the other hand, the mechanism for circulating the coolant in air cooling can be greatly simplified, making the system less complex compared to water cooling.Accordingly, in order to simplify the cooling system, it is desirable to implement an air-cooled cooling device with a thermal resistance value generated in the heat transfer unit of the same degree or level as that of the water-cooled cooling device. The semiconductor device 2 according to the embodiments shown in Fig. 3 comprises: a heat source 8 (TS); a thermal diffusion unit 10 connected to the heat source 8 (TS); a base unit 14 connected to the thermal diffusion unit 10; and air-cooling fin units 161, 162, 163, ..., 16n connected via the base unit 14, and thermal contact units CP1, CP2, CP3, ..., CPn. A plurality of thermal contact units CP are present, and the base unit 14 is connected to the respective thermal contact units CP1, CP2, CP3, ..., CPn via the air-cooling fin units 161, 162, 163, ..., 16n. Alternatively, the semiconductor device 2 according to the embodiments shown in Fig. 4 can include: a heat source 8 (TS); a heat diffusion unit 10 connected to the heat source 8 (TS); and a heat contact space unit SPACE between the heat diffusion unit 10 and the air cooling fin unit (not shown). The heat diffusion unit 10 incorporates a thermally highly conductive material and can diffuse heat. The heat diffusion unit 10 can, for example, be made of copper (Cu) as the thermally highly conductive material, and a vapor chamber can be used for the heat diffusion unit 10. The heat diffusion unit 10 and the air cooling fin unit (not shown) are connected to each other via the thermal contact unit CP. The semiconductor device 2 according to the embodiments includes a heat diffusion unit 10 configured to diffuse heat using a thermally highly conductive material, and a heat contact space SPACE between the heat diffusion unit 10 and the (not shown) air cooling fin unit, wherein, due to the fact that the air cooling fin units are thermally contacted with the heat diffusion unit 10 at a plurality of points, a reduction of the thermal resistance of the cooling device can be achieved. Fig. 5 shows a schematic configuration of a thermal resistance circuit to illustrate a configuration in which a plurality of the air cooling fin units 161, 162, 163, ..., 16ns are in thermal contact or heat contact with the heat diffusion unit 10, namely on a plurality of heat contact units CP1, CP2, CP3, ..., CPn, in order to realize the reduction of the thermal resistance in the semiconductor device 2 according to the embodiments. The semiconductor device 2 according to the embodiments comprises: the heat diffusion unit 10, which is configured to diffuse heat using the thermally highly conductive material; the base unit 14, which is connected to the heat diffusion unit 10; and the heat contact units CP1, CP2, CP3, ..., CPn in thermal contact with the base unit 14 and the plurality of air cooling fin units 161, 162, 163, ..., 16n at the plurality of points, wherein the plurality of air cooling fin units 161, 162, 163, ..., 16n are thermally contacted with the heat diffusion unit 10 via the base unit 14 at the plurality of points, and thereby the reduction of the thermal resistance of the cooling device can be achieved. [Configuration of the first embodiment] Fig. 6 shows a schematic cross-sectional structure of a semiconductor device 2 according to a first embodiment. The semiconductor device 2 shown in Fig. 6, which includes a cooling device according to the first embodiment, has two heat dissipation units 6. As shown in Fig. 6, the semiconductor device 2 according to the first embodiment includes a heat source 8 (TS) which has or is formed by a semiconductor component, wherein the semiconductor component generates heat in an operating state; a heat diffusion unit 10 which is connected to the heat source 8 (TS); and a plurality of air cooling fin units (16FA1, 16FA2, 16FA3, ..., 16FAm), (16FB1, 16FB2, 16FB3, ..., 16FBm) which are connected to the heat diffusion unit 10. Furthermore, the semiconductor device includes two base units 14PA, 14PB, which are connected to the heat diffusion unit 10 via heat conduction layers 12SA, 12SB. The heat conduction layers 12SA, 12SB can be thermal conductivity layers or solder layers, to name a few examples. In addition, a plurality of air-cooling fin units (16FA1, 16FA2, 16FA3, ..., 16FAm), (16FB1, 16FB2, 16FB3, ..., 16FBm) are connected to the base units 14PA, 14PB via a plurality of thermal contact units. Furthermore, the semiconductor device 2 includes a thermal contact space unit OA between the thermal diffusion unit 10 and the plurality of air-cooling fin units (16FA1, 16FA2, 16FA3, ..., 16FAm), (16FB1, 16FB2, 16FB3, ..., 16FBm), wherein the thermal contact space unit OA is surrounded by the thermal diffusion unit 10 and a plurality of air-cooling fin units (16FA1, 16FA2, 16FA3, ..., 16FAm), (16FB1, 16FB2, 16FB3, ..., 16FBm). In this case, the thermal contact space unit OA can be an air layer formed by natural air cooling or forced air cooling. The semiconductor device 2 can further include an opening AP to an external space. Alternatively, as long as a structure is present that ensures airflow, the opening AP can also be omitted. The heat diffusion unit 10 can be configured to efficiently diffuse heat using a thermally highly conductive material or materials. For example, the heat diffusion unit 10 can include copper (Cu) or a vapor chamber. Furthermore, the base units 14PA, 14PB and the air cooling fin units (16FA1, 16FA2, 16FA3, ..., 16FAm), (16FB1, 16FB2, 16FB3, ..., 16FBm) can be made of the same material, or can be made of materials that differ from each other. Furthermore, the thermal diffusion unit 10 or the base units 14PA, 14PB can incorporate a graphite substrate that has anisotropic thermal conductivity. More precisely, the thermal diffusion unit 10 or the base units 14PA, 14PB can efficiently utilize the anisotropic thermal conductivity of the graphite substrate by orienting the graphite substrate in a direction where its heat transfer coefficient is relatively high. [Second embodiment] Fig. 7 shows a schematic cross-sectional structure of a semiconductor device 2 according to a second embodiment. The semiconductor device 2 according to the second embodiment includes two heat dissipation units 6, as shown in Fig. 7. As shown in Fig. 7, the semiconductor device 2 according to the second embodiment includes a heat source 8 (TS) which has a semiconductor component or is composed of a semiconductor component which generates heat in an operating state; a heat diffusion unit 10 which is connected to the heat source 8 (TS); and a plurality of air cooling fin units (16FA1, 16FA2, 16FA3, ..., 16FAm), (17FB1, 17FB2, 17FB3, ..., 17FBm) which are connected to the heat diffusion unit 10. Furthermore, the semiconductor device includes two base units 14PA, 15PB, which are connected to the heat diffusion unit 10 via heat conduction layers 12SA, 12SB. The heat conduction layers 12SA, 12SB can be, for example, thermal conductivity layers or solder layers. In addition, the plurality of air-cooling fin units (16FA1, 16FA2, 16FA3, ..., 16FAm), (17FB1, 17FB2, 17FB3, ..., 17FBm) are each connected to the base units 14PA, 15PB via a plurality of thermal contact units. In the semiconductor device 2 according to the second embodiment, the base unit 14PA and the air-cooling fin units (16FA1, 16FA2, 16FA3, ..., 16FAm) are made of the same material. Furthermore, the base unit 14PB and the air-cooling fin units (17FB1, 17FB2, 17FB3, ..., 17FBm) are made of the same material. On the other hand, the base unit 14PA and the base unit 14PB are made of materials that differ from each other, and the air cooling fin units (16FA1, 16FA2, 16FA3, ..., 16FAm) and the air cooling fin units (17FB1, 17FB2, 17FB3, ..., 17FBm) are made of materials or composed of materials that differ from each other. For example, the base unit 14PA can be made of a material with relatively low thermal conductivity, and the base unit 14PB can be made of a material with relatively high thermal conductivity. Similarly, the air-cooling fin units (16FA1, 16FA2, 16FA3, ..., 16FAm) can be made of a material with relatively low thermal conductivity, and the air-cooling fin units (17FB1, 17FB2, 17FB3, ..., 17FBm) can be made of a material with relatively high thermal conductivity. Further configurations are the same as for the semiconductor device 2 according to the first embodiment. [Third embodiment] Fig. 8 shows a schematic cross-sectional structure of a semiconductor device 2 according to a third embodiment. The semiconductor device 2 according to the third embodiment includes two heat dissipation units 6, as shown in Fig. 8. As shown in Fig. 8, the semiconductor device 2 according to the third embodiment includes a heat source 8 (TS) comprising or consisting of a semiconductor component that generates heat in an operating state; a heat diffusion unit 10 connected to the heat source 8 (TS); and a plurality of air cooling fin units (16FA1S, 16FA2S, 16FA3S, ..., 16FAmS), (16FB1L, 16FB2L, 16FB3L, ..., 16FBmL) connected to the heat diffusion unit 10. Furthermore, the semiconductor device includes two base units 14PA, 14PB, which are connected to the heat diffusion unit 10 via heat conduction layers 12SA, 12SB. The heat conduction layers 12SA, 12SB can be, for example, thermal conductivity layers or solder layers. In addition, the plurality of air-cooling fin units (16FA1S, 16FA2S, 16FA3S, ..., 16FAmS), (16FB1L, 16FB2L, 16FB3L, ..., 16FBmL) are each connected to the base units 14PA, 14PB via a plurality of thermal contact units. Furthermore, the basic units 14PA, 14PB and the air cooling fin units (16FA1S, 16FA2S, 16FA3S, ..., 16FAmS), (16FB1L, 16FB2L, 16FB3L, ..., 16FBmL) are made of the same material or are composed of the same material. In the semiconductor device 2 according to the third embodiment, the configuration is such that the length of one air-cooling fin unit (16FA1S, 16FA2S, 16FA3S, ..., 16FAmS) is relatively shorter than the length of one air-cooling fin unit (16FB1L, 16FB2L, 16FB3L, ..., 16FBmL). Further configurations are the same as those of the semiconductor device 2 according to the first embodiment. [Fourth embodiment] Fig. 9 shows a schematic cross-sectional structure of a semiconductor device 2 according to a fourth embodiment. The semiconductor device 2 according to the fourth embodiment includes two heat dissipation units 6, as shown in Fig. 9. As shown in Fig. 9, the semiconductor device 2 according to the fourth embodiment includes a heat source 8 (TS) comprising or consisting of a semiconductor component that generates heat in an operating state; a heat diffusion unit 10 connected to the heat source 8 (TS); and a plurality of air cooling fin units (16FA1S, 16FA2S, 16FA3S, ..., 16FAmS), (17FB1L, 17FB2L, 17FB3L, ..., 17FBmL) connected to the heat diffusion unit 10. Furthermore, the semiconductor device includes two base units 14PA, 15PB, which are connected to the heat diffusion unit 10 via heat conduction layers 12SA, 12SB. The heat conduction layers 12SA, 12SB can be, for example, thermal conductivity layers or solder layers. In addition, the multiple air-cooling fin units (16FA1S, 16FA2S, 16FA3S, ..., 16FAmS), (17FB1L, 17FB2L, 17FB3L, ..., 17FBmL) are connected to the base units 14PA, 15PB via multiple thermal contact units. In the semiconductor device 2 according to the fourth embodiment, the base unit 14PA and the air-cooling fin units (16FA1S, 16FA2S, 16FA3S, ..., 16FAmS) are made of the same material. Furthermore, the base unit 14PB and the air-cooling fin units (17FB1L, 17FB2L, 17FB3L, ..., 17FBmL) are made of the same material. On the other hand, the base unit 14PA and the base unit 14PB are made of materials that differ from each other, and the air cooling fin units (16FA1S, 16FA2S, 16FA3S, ..., 16FAmS) and the air cooling fin units (17FB1L, 17FB2L, 17FB3L, ..., 17FBmL) are made of materials that differ from each other. For example, the base unit 14PA can be made of a material with relatively low thermal conductivity, and the base unit 14PB can be made of a material with relatively high thermal conductivity. Similarly, the air cooling fin units (16FA1S, 16FA2S, 16FA3S, ..., 16FAmS) can be made of the material with relatively low thermal conductivity, and the air cooling fin units (17FB1L, 17FB2L, 17FB3L, ..., 17FBmL) can be made of the material with relatively high thermal conductivity. In the semiconductor device 2 according to the fourth embodiment, a configuration is provided such that the length of the air cooling fin units (16FA1S, 16FA2S, 16FA3S, ..., 16FAmS) is relatively shorter than the length of the air cooling fin units (16FB1L, 16FB2L, 16FB3L, ..., 16FBmL). Further configurations are the same as those of the semiconductor device 2 according to the third embodiment. As explained above, as shown in Fig. 5, the semiconductor device 2 according to the embodiments includes the heat diffusion unit 10, which is configured to diffuse heat using a thermally highly conductive material, wherein the base unit 14 is connected to the heat diffusion unit 10, and wherein the heat contact units CP1, CP2, CP3, ..., CPn are in thermal contact with the base unit 14 and the plurality of air cooling fin units 161, 162, 163, ..., 16n at the plurality of points, wherein the plurality of air cooling fin units 161, 162, 163, ..., 16n are thermally contacted with the heat diffusion unit 10 via the base unit 14 at the plurality of points, thereby enabling the reduction of the thermal resistance of the cooling device within a limited space (heat contact space unit OA). Various combinations are possible for the air cooling fin (the base unit 14 + the air cooling fin units 161, 162, 163, ..., 16n) that occupies or is arranged within the space (heat contact space unit OA). For example, the air cooling fins can be made of a uniform material or of different materials. Furthermore, the air cooling fins can be made of a material with relatively high thermal conductivity, of materials with relatively low thermal conductivity, or of a combination thereof. (Thermal fluid simulation) Figure 10 is an explanatory diagram of a calculation evaluation method for a thermal fluid simulation in the semiconductor device according to the embodiments. In a thermal fluid simulation model, the heat source 8 (TS) is arranged on the base unit 14 so that it heats the entire surface of the base unit. In Figure 10, T1 denotes a surface temperature of the base unit, T2 denotes a base temperature of the air cooling fin unit, and T3 denotes a tip temperature of the air cooling fin unit. W1 denotes a thickness of the cooling device, WP denotes a width of the air cooling fin unit, LF denotes a length of the air cooling fin unit, LB denotes a base length, and L1 denotes a base width. In this case, the thickness of the cooling device is W1 = 70 mm, the base length is LB = 5 mm, the base width is L1 = 70 mm, and the volume of the air cooling fin unit is FS = LF / 20.The cooling conditions are air cooling at an air velocity of 10 m / s at the front surface of the fins, and an outside air temperature Ta = 20°C. In the following calculation, the thermal resistance of the air-cooling fin unit 16 is investigated by setting the tonnage ratio (LF / FS) to 20 and by changing the length of the air-cooling fin LF. The fin evaluation objects are defined as the thermal resistance value Rth (fin) (K / W) of the fin and a temperature difference ratio or temperature difference ratio RATIO within the fin and applied by the following equations (2) and (3): In equation (2), W denotes a dissipation lead in the heat source 8 (TS) and corresponds to a dissipation lead of the semiconductor device, to give an example. RATIO is an index that indicates a temperature distribution within the air cooling fin unit 16 and corresponds to a temperature difference of the base unit / temperature difference of the air cooling fin unit 16. Fig. 11 shows an explanation of each composite material applied to the thermal fluid simulation in the semiconductor device according to the embodiments. Here, the materials comprising the air-cooling fins, which are built from the base unit 14 and the air-cooling fin unit 16, are assumed to be graphite, copper (Cu), aluminum (Al), an alloy, and iron (Fe). The heat transfer coefficient of graphite is 1500 W / mK in the x-direction, 5 W / mK in the y-direction, and 1500 W / mK in the z-direction. The heat transfer coefficients of copper (Cu), aluminum (Al), the alloy, and iron are 400 W / mK, 237 W / mK, 100 W / mK, and 50 W / mK, respectively. The length of the air cooling fin LF is 10 mm to 80 mm, the air cooling fin space FS is 0.5 mm to 4 mm, and the number of fins is 61 to 16. The thermal fluid simulation of the semiconductor device according to the embodiments is evaluated with respect to the thermal resistance Rth (fin) (K / W) of the air-cooling fin unit by changing the material of the air-cooling fin and the length of the air-cooling fin LF. In addition, a correlative relationship between the thermal resistance Rth (fin) and the temperature difference inside the fin is also evaluated by introducing the temperature difference ratio RATIO within the fin. (Equivalent thermal resistance circuit) In the thermal fluid simulation of the semiconductor device according to the embodiments, the air cooling fin unit is divided into an optional number of elements. In the following example, the division is into two, each with a width Δ. Fig. 12(a) shows an explanation of an equivalent thermal resistance of an air cooling fin unit, and Fig. 12(b) shows the equivalent thermal resistance circuit of one air cooling fin unit 1 in the semiconductor device according to the embodiments. In Fig. 12(b), r1, r2 and r3 denote thermal resistances, V1, V2 and V3 denote temperatures, and I1, I2 and I3 denote heat fluxes or heat flows. Similarly, Fig. 13(a) shows an explanation of an equivalent thermal resistance of three air-cooling fin units, and Fig. 13(b) shows the equivalent thermal resistance circuit of the three air-cooling fin units in the semiconductor device according to the embodiments. Fig. 13(b) denote r1, r2, r3, r1', r2', r3', r1", r2" and r3" as thermal resistances, V1, V2, V3, V1', V2', V3', V1", V2" and V3" as temperatures and I1, I2, I3, I1', I2', I3', I1", I2" and I3" as heat flows or currents. (Result of the thermal fluid simulation) Fig. 14 shows a simulation result of a relationship between a thermal resistance Rth (fin) (K / W) and a length LF (mm) of the air cooling fin using a material from which the fin is constructed as a parameter when the base unit 14 and the air cooling fin unit 16 are made of the same material in the semiconductor device according to the embodiments. Fig. 15 shows a simulation result of a relationship between RATIO and the length LF (mm) of the air cooling fin, using a material from which the fin is composed as a parameter, when the base unit 14 and the air cooling fin unit 16 are made of the same material, in the semiconductor device according to the embodiments. As shown in Fig. 14, the thermal resistance Rth (fin) (K / W) tends to decrease when the length LF of the air cooling fin is equal to or less than 20 (mm), regardless of the material used. If the length LF of the air cooling fin is 20 mm and the composite material of the air cooling fin unit is copper (Cu), the lowest thermal resistance Rth (fin) (K / W) is obtained when the length of the air cooling fin is 20 mm. Furthermore, as shown in Fig. 15, a tendency to reduce thermal resistance can be observed when the value of RATIO is as low as 5 or less than 5, regardless of the composition material of the air cooling fin unit. Based on the aforementioned thermal fluid simulation results, the temperature difference within the air cooling fin is reduced by shortening the fin length (LF) to less than or equal to 20 mm (ratio equal to or less than 5). Furthermore, as a result of the narrower fin interval, it becomes possible to increase the number of fins, thereby increasing the area for efficient heat transfer to the air and thus reducing thermal resistance. It is also shown that the influence of the heat transfer coefficient of the fin materials can be reduced. The above thermal fluid simulation results show that in the semiconductor device according to the embodiments, a structure for reducing thermal resistance is effective in which a plurality of small air cooling fin units are connected together. - Example of the use of composite materials - In the semiconductor component according to the present embodiment, the performance of the air cooling fin is investigated by combining different materials for the base unit 14 and the air cooling fin unit 16, based on the criterion or scale of a fin made of copper (Cu). Fig. 16(a) shows a schematic configuration when the base unit 14 and the air-cooling fin unit 16 are made of the same material in the semiconductor device according to the embodiments. Fig. 16(b) shows a schematic configuration when the base unit 14 and the air-cooling fin unit 16 are made of different materials in the semiconductor device according to the embodiments. Fig. 16(c) is a diagram showing a performance list for each material—graphite, copper, aluminum, an alloy, and iron—in the semiconductor device according to the embodiments. The performance items or parameters considered are the heat transfer coefficient (W / mK), the cost of the materials, and their weight. While the heat transfer coefficient of fins made of copper (Cu) is 400 (W / mK), the heat transfer coefficient of graphite in the orientation direction is as high as 1500 (W / mK), and the heat transfer coefficients of Al, an alloy and Fe are as low as 237, 100 and 50 respectively. Based on the material cost of the copper fins, the graphite is expensive, while the aluminum and iron are inexpensive. The overall material cost of the alloy depends on these materials. Based on the criterion of weight, copper fins are light, graphite and aluminum are light, and iron is heavy. The weight of the alloy depends on the materials used. - Thermal resistance calculation result (example of using composite materials) - The benefit of using the composite materials is calculated and analyzed for each material. Copper (Cu), aluminum (Al), the alloy, and iron (Fe) are used as the materials of the base unit 14, and graphite, copper (Cu), aluminum (Al), the alloy, and iron (Fe) are used as the materials of the air-cooling fin unit 16. The numerical values ​​in Figures 17, 18, 19 to 20 below denote the thermal resistance Rth (fin) (K / W). Regarding the values ​​given as a percentage (%) for the base unit 14 and the air-cooling fin unit 16, the black triangles “▼” indicate a reduction rate of the thermal resistance Rth (fin) (K / W), and the white triangles “Δ” indicate an increase rate of the thermal resistance Rth (fin) (K / W), based on the criterion or scale in the case of copper (Cu). Fig. 17 shows a thermal resistance simulation result for the case where the base unit 14 and the air cooling fin unit 16 are made of different materials (length of the air cooling fin unit LF = 80 mm), in the semiconductor device according to the embodiments. Fig. 18 shows a thermal resistance simulation result for the case where the base unit 14 and the air cooling fin unit 16 are made of different materials (length of the air cooling fin unit LF = 40 mm), in the semiconductor device according to the embodiments. Fig. 19 shows a thermal resistance simulation result for the case where the base unit 14 and the air cooling fin unit 16 are made of different materials (length of the air cooling fin unit LF = 20 mm), in the semiconductor device according to the embodiments. Fig. 20 shows a thermal resistance simulation result for the case where the base unit 14 and the air cooling fin unit 16 are made of different materials (length of the air cooling fin unit LF = 10 mm), in the semiconductor device according to the embodiments. The results above demonstrate that the reduction in thermal resistance is significant when the thermally highly conductive material is used for the air cooling fin unit 16, provided the length of the air cooling fin unit LF is relatively long. This is because a fin with a high RATIO value is strongly influenced by the heat transfer coefficient of the air cooling fin unit 16. On the other hand, it is demonstrated that when the length LF of the air cooling fin of the air cooling fin unit 16 is relatively short, there is no significant increase in thermal resistance, even when the material with the low assumed thermal conductivity is used for the air cooling fin unit 16 and the base unit 14. This is because the fin with a small RATIO value is less affected by the heat transfer coefficient of the air cooling fin unit 16. - Simulation result of RATIO and thermal resistance Rth (fin) (K / W) - Fig. 21(a) shows a thermal resistance simulation result of RATIO and the thermal resistance Rth (fin) (K / W) when the base unit 14 and the air-cooling fin unit 16 are made of Cu-Cu, Cu-graphite (Cu-Gr), Al-graphite (Al-Gr), alloy graphite, or Fe-graphite (length of the air-cooling fin unit 16 is LF = 80 mm), in the semiconductor device according to the embodiments. As shown in Fig. 21(a), when the material of the base unit 14 of the air-cooling fin unit 16 is Cu-Cu, which is shown as the criterion or scale, the value of RATIO tends to be large, and the cooling efficiency tends to be inaccurate or excessively high. For this result, if graphite is used for the air-cooling fin unit 16 to increase its thermal conductivity, the thermal resistance can be reduced. The values ​​given in percent (%) indicate the reduction rate of thermal resistance in relation to the criterion value.If the base unit 14 and the air-cooling fin unit 16 are made of Cu-Gr, the thermal resistance value is reduced by approximately 30%. Similarly, the RATIO value is also reduced by approximately 30%. Fig. 21(b) shows a thermal resistance simulation result of RATIO and the thermal resistance value Rth (fin) (K / W) when the base unit 14 and the air-cooling fin unit 16 are made of Cu-Cu, Cu-graphite, Al-graphite, alloy-graphite, or Fe-graphite (length of the air-cooling fin unit 16 is LF = 10 mm), in the semiconductor device according to the embodiments. As shown in Fig. 21(b), when the material of the base unit 14 and the air-cooling fin unit 16 is Cu-Cu, which is specified as the criterion, the value of RATIO tends to be small and the cooling efficiency tends to be high. In contrast, even when graphite (Gr) is used for the air-cooling fin unit 16 to increase the thermal conductivity, the cooling performance is hardly changed. Even if an inexpensive and lightweight material is used for the base unit 14 and the air cooling fin unit 16, the cooling performance will hardly be changed.The values ​​given in percent (%) indicate the rate of increase in thermal resistance relative to the criterion value or scale. If the base unit 14 and the air-cooling fin unit 16 are made of Fe-Gr, the thermal resistance increases by up to approximately 13%. Conversely, the RATIO value is reduced. - Simulation result of thermal resistance value Rth (fin) (K / W) and RATIO - Calculations are performed to determine whether a reduction in thermal resistance is possible, even with a further, smaller air-cooling fin unit, by increasing the tonnage ratio (LF / FS) and reducing the fin space (FS) to increase the number of air-cooling fins, specifically in regions where the air-cooling fin length (LF) is short (equal to or less than 20 mm). Copper (Cu), with a thermal conductivity of 400 W / mK, is used for the air-cooling fin unit. The length of the air-cooling fin (LF) is 2 mm to 20 mm, the fin space (FS) is 0.2 mm to 1 mm, and the number of fins is 40 to 100. Fig. 22(a) shows a simulation result of a relationship between the thermal resistance Rth (fin) (K / W) and the number of fins using the length LF of the air cooling fin as a parameter, and Fig. 22(b) shows a simulation result of a relationship between the value of RATIO and the number of fins using the length LF of the air cooling fin as a parameter, in the semiconductor device according to the embodiments. As shown in Fig. 22(a), the reduction in thermal resistance Rth (fin) (K / W) is more significant when the number of fins is increased, particularly when the length LF of the air-cooling fin is shorter. For a precision-machining fin, the air-cooling fin space FS is approximately 0.2 mm. As shown in Fig. 22(b), the reducing effect of the RATIO value is more pronounced when the number of fins is increased and the length LF of the air-cooling fin is longer. As shown in Fig. 15, when the value of RATIO is equal to or less than 5, the material dependence of the air-cooling fin unit is reduced. The value of RATIO is preferably equal to or less than 5. In addition, if the above calculation is performed under the assumption that the material of the air cooling fin unit is Al, which has a heat transfer coefficient of 237 (W / mK), no significant changes can be observed in the above calculation results. [Fifth embodiment] Fig. 23 shows a schematic cross-sectional structure of a semiconductor device 2 according to a fifth embodiment. The semiconductor device 2 according to the fifth embodiment includes four heat dissipation units 6. The semiconductor device 2 according to the fifth embodiment comprises: a heat source 8 (TS) consisting of or having a semiconductor component which generates heat in an operating state; a heat diffusion unit 10 which is thermally connected to the heat source 8 (TS); and a plurality of heat dissipation units 6 which are connected to the heat diffusion unit 10, wherein the heat diffusion unit 10 has a cooling device which spatially contains the heat dissipation unit or the heat dissipation units 6 (by means of the heat contact space unit OA). The heat diffusion unit 10 includes an opening AP, and the space (heat contact space unit OA) containing the heat dissipation unit is open at the opening AP. Alternatively, the heat diffusion unit 10 can contain the heat dissipation unit 6 in a spatially closed state (without an opening AP). The heat dissipation unit 6 can comprise base units 14PA, 14PB and a variety of air-cooling fin units 16FA, 16FB connected to the base units 14PA, 14PB, and the base units 14PA, 14PB can be in contact with the heat diffusion unit 10. For example, the base units 14PA, 14PB are each connected to the heat diffusion unit 10 via the heat conduction layers 12SA, 12SB. The heat conduction layers 12SA, 12SB can be, for example, thermal conductivity layers or solder layers. A section of the heat dissipation unit 6 may contain a non-contact unit (NC), excluding the heat diffusion unit 10 and the opening AP. This is used to prevent direct contact between the air cooling fin unit 16FA, 16FB and the heat diffusion unit 10, thereby ensuring heat dissipation performance. The value of RATIO = (T2-T3) / (T1-T2) is equal to or less than 25 / LB (mm), where T1 is a surface temperature of the base unit, T2 is a base temperature of the air cooling fin unit, T3 is a top temperature of the air cooling fin unit, and LB (mm) is a base length of the base unit. For example, if LB (mm) = 5 (mm), the value RATIO = 25 / LB (mm) = 5 or less. In addition, the heat transfer coefficient of the material forming or comprising the heat diffusion unit 10 is preferably equal to or greater than the heat transfer coefficient of the material forming or comprising the heat dissipation unit 6. This is intended to improve the heat radiation performance and to dissipate heat effectively. Furthermore, the semiconductor device 2 according to the fifth embodiment, shown in Fig. 23, includes a heat source 8 (TS) comprising or consisting of a semiconductor component that generates heat in an operating state; a heat diffusion unit 10 connected to the heat source 8 (TS); a plurality of air-cooling fin units 16FA, 16FB connected to the heat diffusion unit 10; and a heat contact space unit OA between the heat diffusion unit 10 and the plurality of air-cooling fin units 16FA, 16FB. In this case, the heat contact space unit OA can be an air layer formed by natural air cooling or forced air cooling. Furthermore, the semiconductor device includes two base units 14PA, 14PB, which are connected to the heat diffusion unit 10 via heat conduction layers 12SA, 12SB. Additionally, the plurality of air-cooling fin units 16FA, 16FB are each connected to the base units 14PA, 14PB via a plurality of thermal contact units. The semiconductor device 2 may also have an opening AP to an external space. Alternatively, the opening AP may not be provided, as long as a structure is provided that ensures airflow. The heat diffusion unit 10 can be configured to efficiently dissipate or diffuse heat using a thermally highly conductive material(s). For example, the heat diffusion unit 10 can include copper (Cu) or a copper vapor chamber (CuVC). Furthermore, the base units 14PA, 14PB and the air cooling fin units 16FA, 16FB are made of the same material or are composed of the same material. Furthermore, the thermal diffusion unit 10 or the base units 14PA, 14PB can feature a graphite substrate with anisotropic thermal conductivity. More precisely, the thermal diffusion unit 10 or the base units 14PA, 14PB can efficiently utilize the anisotropic thermal conductivity of the graphite substrate by orienting the graphite substrate in a direction where the heat transfer coefficient of the graphite substrate is relatively high. [Sixth embodiment] Fig. 24 shows a schematic cross-sectional structure of a semiconductor device 2 according to a sixth embodiment. The semiconductor device 2 according to the sixth embodiment includes four heat dissipation units 6. The semiconductor device 2 according to the sixth embodiment comprises: a heat source 8 (TS) which has a semiconductor component or is composed of a semiconductor component which generates heat in an operating state; a heat diffusion unit 10 which is thermally connected to the heat source 8 (TS); and a plurality of heat dissipation units 6 which are connected to the heat diffusion unit, wherein the heat diffusion unit 10 has a cooling device which spatially contains the heat dissipation unit 6 (by means of the heat contact space unit OA). The heat diffusion unit 10 includes an opening AP, and the space (heat contact space unit OA) containing the heat dissipation unit 6 is open above or within the opening AP. Alternatively, the heat diffusion unit 10 can contain the heat dissipation unit 6 in a spatially closed state (without an opening AP). The heat dissipation unit 6 comprises: base units 14PA, 14PB, 14PA, 15PB; and a variety of air-cooling fin units 16FA, 17FB, 16FAS, 17FBL, which are connected to the base units 14PA, 14PB, 14PA, 15PB, the base units 14PA, 14PB, 14PA, 15PB being in contact with the heat diffusion unit 10. The base units 14PA, 14PB, 14PA, 15PB are each connected to the heat diffusion unit 10 via the heat conduction layers 12SA, 12SB. The heat conduction layers 12SA, 12SB can be, for example, thermal conductivity layers or solder layers. In addition to the heat dissipation unit 10 and the opening AP, a section of the heat dissipation unit 6 may include a contactless or non-contact unit NC. This is used to prevent direct contact between the air cooling fin units 16FA, 17FB, 16FAS, 17FBL and the heat diffusion unit 10, thus ensuring heat dissipation performance. The value of RATIO = (T2-T3) / (T1-T2) is preferably equal to or less than 25 / LB (mm), where T1 is a surface temperature of the base unit, T2 is a base temperature of the air-cooling fin unit, T3 is a top temperature of the air-cooling fin unit, and LB (mm) is a base length of the base unit. For example, in the case of LB (mm) = 5 (mm), it is preferred if RATIO = 25 / LB (mm) = 5 or less. In addition, the heat transfer coefficient of the material that forms or is composed of the heat diffusion unit 10 is preferably equal to or greater than the heat transfer coefficient of the material that forms or is composed of the heat dissipation unit 6. Furthermore, the semiconductor device 2 according to the sixth embodiment shown in Fig. 24 includes a heat source 8 (TS) comprising, consisting of, or being constructed from a semiconductor component that generates heat in an operating state; a heat diffusion unit 10 connected to the heat source 8 (TS); and a plurality of air cooling fin units 16FA, 17FB, 16FAS, 17FBL connected to the heat diffusion unit 10. Furthermore, the semiconductor device includes two base units 14PA, 14PB, 14PA, 15PB, which are connected to the heat diffusion unit 10 via heat conduction layers 12SA, 12SB. Additionally, the plurality of air-cooling fin units 16FA, 17FB, 16FAS, 17FBL are each connected to the base units 14PA, 14PB, 14PA, 15PB via a plurality of thermal contact units. Furthermore, the semiconductor device 2 includes a thermal contact space unit OA between the thermal diffusion unit 10 and the plurality of air-cooling fin units 16FA, 17FB, 16FAS, 17FBL, which surrounds or is enclosed by the thermal diffusion unit 10 and the plurality of air-cooling fin units 16FA, 17FB, 16FAS, 17FBL. The thermal contact space unit OA can be an air layer formed by natural air cooling or forced air cooling. The semiconductor device 2 may also have an opening AP to an external space. Alternatively, the opening AP may not be provided, as long as a structure is provided that ensures airflow. The heat diffusion unit 10 can be configured to efficiently diffuse heat using a thermally highly conductive material or materials. For example, the heat diffusion unit 10 can contain copper (Cu) or a copper vapor chamber (CuVC). In the semiconductor device 2 according to the sixth embodiment, the base units 14PA, 14PB and the air-cooling fin units 16FA are made of the same material. Furthermore, the air-cooling fin unit 16FA and the air-cooling fin unit 17FB are made of different materials. On the other hand, the 14PA base unit and the 16FAS air cooling fin unit are made of the same material. The 15PB base unit and the 17FBL air cooling fin unit are made of the same material. The 16FAS air cooling fin unit and the 17FBL air cooling fin unit are made of different materials. For example, the base units 14PA and 14PB can be made of a material with relatively low thermal conductivity or a material with high thermal conductivity. Conversely, the air cooling fin unit 16FA can be made of a material with relatively low thermal conductivity or a material with high thermal conductivity, and the air cooling fin unit 17FB can be made of a material with relatively high thermal conductivity. Furthermore, in the semiconductor device 2 according to the sixth embodiment, the base unit 14PA and the air-cooling fin unit 16FAS are made of the same material. In addition, the base unit 15PB and the air-cooling fin unit 17FBL are made of the same material. On the other hand, the base unit 14PA and the base unit 15PB are constructed from materials that differ from each other, and the air cooling fin unit 16FAS and the air cooling fin unit 17FBL are constructed from materials that differ from each other. For example, the base unit 14PA can be made of a material with relatively low thermal conductivity, and the base unit 15PB can be made of a material with relatively high thermal conductivity. Similarly, the air cooling fin units 16FA and 16FAS can be made of a material with relatively low thermal conductivity, and the air cooling fin units 17FB and 17FBL can be made of a material with relatively high thermal conductivity. In the semiconductor device 2 according to the sixth embodiment, the configuration is such that the length of the air cooling fin unit 16FAS is relatively short compared to the length of the air cooling fin unit 17FBL. Other configurations are the same as those of the semiconductor device 2 according to the fifth embodiment. The semiconductor device 2 according to the embodiments includes the heat diffusion unit 10, which is configured to diffuse heat using a thermally highly conductive material, includes the base unit connected to the heat diffusion unit, and includes the heat contact unit, which is in thermal contact with the base unit and the plurality of air cooling fin units at the plurality of points, wherein the plurality of air cooling fin units are in thermal contact with the heat diffusion unit via the base unit at the plurality of points, thereby enabling the reduction of the thermal resistance of the cooling device in a limited space (heat contact space unit OA). Furthermore, the heat diffusion unit 10 or the base units 14PA, 14PB, 14PA, 15PB can feature a graphite substrate with anisotropic thermal conductivity. More precisely, the heat diffusion unit 10 or the base units 14PA, 14PB, 14PA, 15PB can efficiently utilize the anisotropic thermal conductivity of the graphite substrate by orienting the graphite substrate in a direction where its heat transfer coefficient is relatively high. (Configuration example of SiC-PM (2-in-1)) Fig. 25(a) shows a bird's-eye view of a configuration of a (2-in-1) SiC-PM 8 according to the embodiments, mounted on the semiconductor device 2 according to the embodiments; Fig. 25(b) is a front view diagram thereof, viewed in the direction of arrow A in Fig. 25(a); and Fig. 25(c) is a top view diagram thereof. The SiC-PM 8 according to the embodiments shown in Figures 25(a) to 25(c) can be mounted in the semiconductor device 2 disclosed in the embodiments. The SiC-PM 8 according to the embodiments can be mounted in any of the semiconductor devices 2 disclosed in the first to sixth embodiments. The SiC-PM 8 according to the embodiments is arranged by pressurizing it between a pressure plate 40 and the heat diffusion unit 10. In this case, the pressurization can be implemented by a screwing operation. The heat diffusion unit 10 can, for example, be made of copper (Cu) or be a copper vapor chamber. The SiC-PM 8 according to the embodiments incorporates a 2-in-1 configuration. The circuit configuration is similar to that shown in Fig. 40, as described below. In Figures 25(a) to 25(c), reference numerals SS1 and GT1 denote a source-sensing terminal electrode and a gate-signal terminal electrode, respectively, of transistor Q1 on one side of an upper branch of the SiC PM 8 containing the 2-in-1 configuration, and reference numerals SS4 and GT4 denote a source-sensing terminal electrode and a gate-signal terminal electrode, respectively, of transistor Q4 on one side of a lower branch of the SiC PM 8 containing the 2-in-1 configuration. Furthermore, reference numerals P and N denote a positive-side power-input terminal electrode (first power source) and a negative-side power-input terminal electrode (second power source), respectively, of the SiC PM 8 containing the 2-in-1 configuration, and reference numeral O denotes an output terminal electrode thereof. Fig. 26 shows a schematic cross-sectional structure of a configuration example in which the SiC-PM 8 is mounted on a central section of the heat diffusion unit 10 of the semiconductor device 2 according to the first embodiment. PM 8 includes a semiconductor component Q20 corresponding to the heat source TS, which generates heat during operation. The semiconductor component Q20 is, for example, mounted on an insulating ceramic substrate. The insulating ceramic substrate can, for example, be a DBC substrate. In the example shown in Fig. 26, the insulating ceramic substrate comprises a ceramic substrate 21, a front-side electrode layer 23 of the ceramic substrate 21, and a back-side electrode layer 22 of the ceramic substrate 21. The semiconductor device Q20 is bonded to the front-side electrode layer 23, for example, by means of a fired Ag layer 27. Furthermore, the back-side electrode layer 22 is connected to the semiconductor device 2 via a thermal conductivity layer 25. The semiconductor device Q20 can, for example, be an IGBT, a diode, a Si-based MOSFET, or a GaN-based FET. The thermal conductivity layer 25 can be any layer of a thermal conductivity layer, a solder layer, or an Ag-fired layer.Furthermore, the PM 8 is resin-molded with a 300 cast resin layer, such as a silicone resin or a polyimide resin. Heat from the semiconductor component Q20, which corresponds to the heat source TS that generates heat in the operating state, is transferred to the semiconductor device 2 via the fired Ag layer 27, the insulating ceramic substrate (23 / 21 / 22) and the heat conduction layer 25. (Assembly method of the SiC-PM (2-in-1)) In an assembly method of the SiC-PM (2-in-1) 8 according to the embodiments, Fig. 27(a) shows a process of attaching the SiC-PM 8 to the vapor chamber 10, Fig. 27(b) shows a process of attaching the air cooling fin unit 16F to the vapor chamber 10, and Fig. 27(c) shows a process of attaching the fan 50F thereto. (A) First, as shown in Fig. 27(a), a heat conduction layer is placed on a bottom surface of the SiC-PM 8, and the pressure plate 40 is positioned on the SiC-PM 8. The pressure plate 40 is pressed under pressure by means of a screw fastening, and the SiC-PM 8 is attached to the vapor chamber 10. In this case, a soldering process can be carried out instead of using the heat conduction layer. The heat conduction layer and the screw thread are not shown in Fig. 27(a). (B) Next, as shown in Fig. 27(b), a heat conduction layer is arranged between the base units 14A, 14B of the air-cooling fin unit 16F and the vapor chamber 10. A pressure plate is applied under pressure by screw fastening to attach the air-cooling fin unit 16F to the vapor chamber 10. In this case, a soldering process can be carried out instead of using the heat conduction layer. The heat conduction layer and the screw thread are not shown in Fig. 27(b). (C) Next, as shown in Fig. 27(c), the fan 50F is attached to a front of the air cooling fin unit 16F. (Configuration example of a SiC PM (6-in-1)) Fig. 28(a) shows a bird's-eye view of a configuration of a (6-in-1) SiC-PM 8 according to the embodiments, mounted on the semiconductor device 2 according to the embodiments; Fig. 28(b) shows a side view diagram thereof; and Fig. 28(c) shows a top view diagram thereof. The SiC-PM 8 according to the embodiments can be mounted on the semiconductor device 2 disclosed in the embodiments as shown in Figures 28(a) to 28(c). The SiC-PM 8 according to the embodiments can be mounted on any of the semiconductor devices 2 disclosed in the first to sixth embodiments. In this context, the structure of the semiconductor device shown in Figures 28(a) to 28(c) corresponds to a further, or even more extensive, structure of the semiconductor devices 2 disclosed in the fifth and sixth embodiments. More precisely, three thermal contact space units OA, which surround or are surrounded by the thermal diffusion unit 10, are provided, as shown in Figure 30, which is described below. In the figures...28(a) to 28(c) the heat diffusion units (vapor chambers corresponding to 10V and 10W) ​​are also arranged on the front and rear surfaces of the cooling device in a similar manner to Fig. 30; however, a representation of the heat diffusion units has been omitted to show the internal structure. The SiC-PM 8 according to the embodiments is arranged by pressurizing it between the pressure plate 40 and the heat diffusion unit 10, as shown in Figures 28(a) to 28(c). In this case, the pressurization can be implemented by a screwing operation. The heat diffusion unit 10 can, for example, be made of copper (Cu) or a copper vapor chamber. The SiC-PM 8 according to the embodiments incorporates a 6-in-1 configuration. The circuit configuration is similar to that shown in Fig. 45, which is described below. In Figures 28(a) to 28(c), the reference numerals SS, GT, and CS denote a source sensing terminal, a gate signal terminal, and a current sensing terminal, respectively, of each transistor Q1 to Q6 of the SiC PM 8 containing the 6-in-1 configuration. Furthermore, the reference numerals TH1 and TH2 denote thermistor terminals for temperature sensing. Additionally, the reference numerals P and N denote a positive-side power input terminal (first power source) and a negative-side power input terminal (second power source) of the SiC PM 8 containing the 6-in-1 configuration. Furthermore, the reference numerals U, V, and W denote output terminals. (Assembly method of the SiC-PM (6-in-1)) In an assembly method of the SiC-PM (6-in-1) 8 according to the embodiments, Fig. 29(a) shows a process of attaching the SiC-PM 8 to the vapor chamber 10, Fig. 29(b) shows a process of attaching the air cooling fin unit 16F to the vapor chamber 10, and Fig. 29(c) shows a process of attaching the fans 50F1, 50F2 to it. (A) First, as shown in Fig. 29(a), a heat conduction layer is placed on a base surface of the SiC-PM 8, and the pressure plate 40 is positioned on the SiC-PM 8. The pressure plate 40 is clamped under pressure by screw fastening, and the SiC-PM 8 is attached to the vapor chamber 10. Instead of using the heat conduction layer, a soldering process can be performed in this case. The heat conduction layer and the screw thread are not shown in Fig. 29(a). (B) Next, as shown in Fig. 29(b), a heat conduction layer is placed between the base units 14PA, 14PB of the air-cooling fin unit 16F and the vapor chamber 10, and a pressure plate is applied under pressure by screw fastening to attach the air-cooling fin unit 16F to the vapor chamber 10. Instead of using the heat conduction layer, a soldering process can be carried out in this case. The heat conduction layer and the screw thread are not shown in Fig. 29(b). (C) Next, as shown in Fig. 29(c), the fans 50F1, 50F2 are attached to a front of the air cooling fin unit 16F. (Another configuration example of a SiC PM (6-in-1)) Fig. 30 shows another configuration of a SiC-PM (6-in-1) according to the embodiments, mounted on the semiconductor device 2 according to the embodiments. The vapor chamber 10, which is applicable to the semiconductor device according to the embodiments, can contain a monolithic structure, or can contain a structure that is divided, as shown in Fig. 30. In the configuration shown in Fig. 30, heat diffusion units 10U, 10V, 10W are provided, which are separate from each other or subdivided. Furthermore, power modules PM 80U, 80V, 80W, which are subdivided to correspond to a U-phase, a V-phase, and a W-phase, respectively, are arranged on the subdivided heat diffusion units 10U, 10V, 10W, thereby further improving the efficiency of heat dissipation. Although in Fig. 30 the base unit and the heat conduction layer connected to the air-cooling fin unit 16F are formed in the same way as in Fig. 23, a representation of these is omitted. (Steam chamber) Fig. 31(a) shows a bird's-eye view of an upper container 10UP of a vapor chamber 10 applicable to the semiconductor device according to the embodiments, Fig. 31(b) shows a bird's-eye view of a lower container 10DW thereof, and Fig. 31(c) shows an explanatory diagram of an operating principle thereof. A plurality of wicks 10WK are formed on the lower container 10DW. The plurality of wicks 10WK enables liquid flow by surface tension. (A) Initially, because heat is generated when the PM 8 (TS) is in operation, which is in contact with the steam chamber 10, a working fluid evaporates to generate steam (VP). (B) Next, a steam flow VF is generated, with the steam moving due to a pressure difference between a high-pressure section HP and a low-pressure section LP caused by the evaporation (VP) of the working fluid, as shown in Fig. 31(c). (C) Next, heat is dissipated or dissipated at one end of the steam chamber 10, and a state of steam flow VF changes into a state of liquid (COD) through condensation effects. (D) Next, as shown in Fig. 31(c), a fluid flow LP (SURFACE TENSION) is generated by a capillary force, in conjunction with or accompanied by the surface tension, by the plurality of wicks 10WK. In the vapor chamber 10, which is applicable to the semiconductor device according to the embodiments, the heat transfer efficiency is extremely high due to the phase change, and, for example, a heat transfer coefficient value of about 3000 (W / mK) in degrees can be obtained. (Graphite plate) Fig. 32 shows a schematic bird's-eye view of a configuration of a laminated structure of a graphite plate (graphite layer) having a graphite substrate or being made up of a graphite substrate, applicable to the semiconductor device according to the embodiments. As shown in Fig. 32, graphite layers GS1, GS2, GS3, ..., GSn of each face, consisting of n layers, have many covalent bonds or bond connections of hexagonal crystal in a laminated crystal structure, and the graphite layers GS1, GS2, GS3, ..., GSn of each face are bonded to each other by means of van der Waal forces. More precisely, the graphite, which is a carbon-based material with an anisotropic thermal conductivity, is a laminated crystal body consisting of a hexagonal lattice structure of carbon atoms, and its thermal conductivity is also anisotropic. The graphite layers GS1, GS2, GS3, ..., GSn, shown in Fig. 32, have a thermal conductivity with respect to one crystal face direction (on the XY plane) that is higher than that in one thickness direction of the Z-axis. In an example of the graphite substrate applicable to the semiconductor device according to the embodiments, Fig. 33(a) shows a schematic bird's-eye view of a configuration of an application example of a graphite substrate GP (XY) of an XY orientation, Fig. 33(b) shows a schematic bird's-eye view of a configuration of a graphite substrate GP (XZ) in an XZ orientation, and Fig. 33(c) shows an explanatory diagram showing an aspect in which a graphite substrate GP (XZ) of an XZ orientation is obtained by rotating the graphite substrates GP (XY) of an XY orientation by 90 degrees. In the semiconductor device according to the embodiments, two types of graphite substrates can be applied to the heat diffusion unit 10. More precisely, a graphite substrate GP (XZ) with an XZ orientation and a higher heat transfer coefficient in a thickness direction than in a plane direction, and a graphite substrate GP (XY) with an XY orientation and a higher heat transfer coefficient in the plane direction than in the thickness direction, can be applied. Accordingly, for example, as shown in Fig. 33(a), the graphite substrate GP (XY), which has the XY orientation, is provided with thermal conductivities of X = 1500 (W / mK), Y = 1500 (W / mK) and Z = 5 (W / mK). Meanwhile, for example, as shown in Fig. 33(b), the graphite substrate GP (XZ), which has the XZ orientation, is provided with thermal conductivities of X = 1500 (W / mK), Y = 5 (W / mK) and Z = 1500 (W / mK). In addition, the density of each graphite substrate GP (XY) and GP(XZ) is approximately 2.2 (g / cm3), and the thickness of this is, for example, approximately 0.7 mm to approximately 10 mm, and the size of this is, for example, equal to or less than approximately 40 mm × approximately 40 mm. Furthermore, in the semiconductor device 2 according to the embodiments, the graphite substrate can be applied to the heat dissipation unit 6. More precisely, the graphite substrate can be applied to the base unit 14 of the air cooling fin, which forms the heat dissipation unit 6. The reason why two types of graphite substrates can be used is the same as described above. In these embodiments, graphite substrates GP(XY) and GP(XZ), which are anisotropic and have a high coefficient of thermal conductivity, can be used, thereby providing the semiconductor device with satisfactory thermal diffusivity and a simple structure, with the ability to further reduce thermal resistance. (Simulation result of impact verification) Fig. 34 shows a simulation result of an effect verification of a cooling device 90 according to a comparative example. In Fig. 34, the heat diffusion unit, made of copper (Cu) or a copper vapor chamber (CuVC), is arranged on a base surface, and the air-cooling fin unit extends vertically from the base surface. In Fig. 34, the base width L1 is 70 mm, and the base length LB is 5 mm. The air-cooling fin unit is made of copper (Cu), with a fin width WP of 0.6 mm, a fin spacing FS of 2.5 mm, and a fin length LF of 80 mm. The thickness W1 of the cooling device is 70 mm. According to the simulation result of the effectiveness verification of the cooling device 90 according to the comparison example, it is demonstrated that the heat is not transferred up to a head section of the air cooling fin unit, as shown in Fig. 34. Fig. 35 shows a simulation result of an effectiveness verification of the semiconductor device 2, which includes the cooling device (Cu) according to the embodiments. In Fig. 35, the heat diffusion unit and the air cooling fin unit are constructed in a similar manner to that shown in Fig. 6. In Fig. 35, the heat diffusion unit is formed with copper (Cu), wherein the base width L1 is 80 mm and the base length LB is 5 mm. The air cooling fin unit is formed with copper (Cu), wherein the width WP of the air cooling fin is 0.3 mm, the fin space FS is 1.5 mm, and the length LF of the air cooling fin is 30 mm. The thickness of the cooling device W1 is 70 mm. According to the simulation result of the effectiveness verification of the semiconductor device 2, which contains the cooling device according to the embodiments (Cu), it has been shown that the heat transfer state is reduced relatively on a side surface of the heat diffusion unit that is in contact with the base unit, as shown in Fig. 35. Fig. 36 shows a simulation result of an effectiveness verification of the semiconductor device 2, which includes the cooling device (CuVC) according to the embodiments. In Fig. 36, the heat diffusion unit and the air cooling fin unit are constructed in a similar manner to that shown in Fig. 6. In Fig. 36, the heat diffusion unit is made of copper (CuVC), with a base width L1 of 80 mm and a base length LB of 5 mm. The air cooling fin unit is made of copper (Cu), with a width WP of the air cooling fin of 0.3 mm, a fin space FS of 1.5 mm, and a length LF of the air cooling fin of 30 mm. The thickness W1 of the cooling device is 70 mm. According to the simulation result of the effectiveness verification of the semiconductor device 2, which includes the cooling device (CuVC) according to the embodiments shown in Fig. 36, it has been demonstrated that the heat can be transferred up to the head section of the air cooling fin unit. Fig. 37 shows simulation results of the thermal resistance, thermal resistance value, or heat resistance Rth (Finne) of the semiconductor devices incorporating cooling devices according to Comparative Examples 1 and 2, according to the embodiment (Cu) and the embodiment (CuVC). The semiconductor device incorporating the cooling device according to Comparative Example 1 corresponds to an example of forming the heat diffusion unit with copper (Cu) in the configuration shown in Fig. 34. The semiconductor device incorporating the cooling device according to Comparative Example 2 corresponds to an example of forming the heat diffusion unit with the copper vapor chamber (CuVC) in the configuration shown in Fig. 34. The semiconductor device incorporating the cooling device (Cu) according to the embodiment corresponds to the configuration shown in Fig.35 is shown, and the semiconductor device containing the cooling device (CuVC) according to the embodiment corresponds to the configuration shown in Fig. 36. The values ​​of the thermal resistance or heat resistance Rth (Finne) (K / W) of comparative example 1, comparative example 2, embodiment (Cu) and embodiment (CuVC) are approximately 0.12 (K / W), approximately 0.12 (K / W), approximately 0.14 (K / W) and approximately 0.065 (K / W). In the semiconductor device which includes the cooling device according to comparative example 2, the effect of a low thermal resistance, which is obtained by forming the heat diffusion unit with the copper vapor chamber (CuVC), is not obtained due to the fact that the heat spreads on the base surface. In the semiconductor device which contains the cooling device according to the embodiment (Cu), heat transfer to the side surface of the heat diffusion unit which is in contact with the base unit of the air cooling fin is reduced. In the semiconductor device containing the cooling device (CuVC) according to the embodiment, heat transfer to the lateral surface of the heat diffusion unit in contact with the base unit of the air cooling fin can be achieved. Therefore, the cooling efficiency is increased and the thermal resistance value Rth (fin) (K / W) is reduced by approximately 46% compared to that of comparative examples 1 and 2. (Specific example of a semiconductor component) Fig. 38 shows a schematic circuit representation of a SiC MOSFET of a PM of 1-in-1 module type 52, applicable as a semiconductor component in the PM, which is to be mounted on the semiconductor device according to the embodiments. The diode DI, which is connected in reverse parallel to the SiC MOSFET Q, is shown in Fig. 38. This can also be omitted if a parasitic diode is used as diode DI. A main electrode of the SiC MOSFET Q is represented by a drain terminal DT and a source terminal ST. Furthermore, Fig. 39 shows a detailed circuit diagram of a SiC MOSFET of a PM 52 of the 1-in-1 module type, applicable as a semiconductor component in the PM, which is to be mounted on the semiconductor device according to the embodiments. The PM, which is to be mounted on the semiconductor device according to the embodiments, includes a configuration in which the semiconductor component is, for example, the PM 52 of the 1-in-1 module type. More precisely, one piece of the MOSFET Q is contained in a module. As an example, five chips (MOSFET × 5) can be mounted on it, and a maximum of five pieces of MOSFET Q can be connected in parallel with each other. It should be noted that it is also possible to mount some of the five chips for the diode DI on it. More precisely, as shown in Fig. 39, a sensing MOSFET Qs is connected in parallel with the SiC MOSFET Q. The sensing MOSFET Qs is implemented as a very small transistor on the same chip as the SiC MOSFET Q. In Fig. 39, reference numeral SS denotes a source sensing terminal, reference numeral CS denotes a current sensing terminal, and reference numeral G denotes a gate terminal. It should be noted that, according to the embodiments of the SiC MOSFET Q, the sensing MOSFET Qs can also be implemented as a very small ("minuteness") transistor on the same chip. (Circuit configuration) Next, a circuit configuration example of the semiconductor component in the PM, which is to be mounted on the semiconductor device according to the embodiments, will be explained in detail. A semiconductor package component (the so-called 2-in-1 type module) is now described in which two semiconductor components are sealed in a casting resin, namely as a module that can be used as the semiconductor component of the PM, which is to be mounted on the semiconductor device according to the embodiments. Fig. 40 shows a circuit configuration of the PM of the 2-in-1 module type (2-in-1 module) 100, to which, for example, the SiC MOSFETs Q1 and Q4 can be applied as the semiconductor component. More precisely, as shown in Fig. 40, the 2-in-1 module 100 includes a configuration of a module with the built-in half-bridge, in which two SiC MOSFETs Q1 and Q4 are included as one module. Each of the SiC MOSFETs Q1 and Q4 contained in the module can be considered a single large transistor; however, one or more chips can be connected in parallel. Furthermore, the modules include 1-in-1 modules, 2-in-1 modules, 4-in-1 modules, 6-in-1 modules, and so on. For example, a module containing two transistor chips is called a 2-in-1 module, a module containing two 2-in-1 modules is called a 4-in-1 module, and a module containing three 2-in-1 modules is called a 6-in-1 module. As shown in Fig. 40, the 2-in-1 module 100 includes two SiC MOSFETs Q1 and Q4 and diodes DI1 and DI4, which are connected in reverse parallel to the SiC MOSFETs Q1 and Q4 as one module. In Fig. 40, reference numeral G1 designates a terminal for a gate signal (the so-called gate terminal) of the SiC MOSFET Q1, and reference numeral S1 designates a terminal for a source signal (the so-called source sensing terminal) of the SiC MOSFET Q1. Similarly, reference numeral G4 designates a terminal for a gate signal of the SiC MOSFET Q4, and reference numeral S4 designates a terminal for a source signal of the SiC MOSFET Q4. The reference symbol P denotes a positive-side power input terminal electrode, the reference symbol N denotes a negative-side power input terminal electrode, and the reference symbol O denotes an output terminal electrode. The semiconductor components (Q2 and Q5) and semiconductor components (Q3 and Q6) applicable to the PM to be mounted on the semiconductor device according to the embodiments can be implemented in a similar manner. - Benefit provision - A power supply according to the embodiments includes the aforementioned PM, which is to be mounted on the semiconductor device according to the embodiments. A power supply is provided that is configured to convert an input voltage and output the converted input voltage using the aforementioned semiconductor device or power module. According to the 2-in-1 module 100, which is to be mounted on the semiconductor device according to the embodiments as shown in Fig. 40, a SiC MOSFET (first switching element) Q1 and a SiC MOSFET (second switching element) Q4 are connected in series between a positive-side power input terminal electrode (first power source) P and a negative-side power input terminal electrode (second power source) N; and the power supply (power supply circuit), which is configured to output the voltage of the above-mentioned connection point from the output terminal electrode O, can be constructed in this way. The PM to be mounted on the semiconductor device according to the embodiments can be not only the 1-in-1 module and the 2-in-1 module, but also a 4-in-1 module (four in one), a 6-in-1 module (six in one), a 7-in-1 module (seven in one) in which a snubber capacitor etc. is provided in the 6-in-1 module, an 8-in-1 module (eight in one), a 12-in-1 module (twelve in one), a 14-in-1 module (fourteen in one) and the like. (Component structure) Fig. 41 shows a schematic cross-sectional structure of a SiC MOSFET 130A, which includes a source pad electrode SP and a gate pad electrode GP, where this is an example of the semiconductor components (Q1 and Q4) applicable to the PM to be mounted on the semiconductor device according to the embodiments. As shown in Fig. 41, the SiC MOSFET 130A comprises: a semiconductor layer 31 formed by incorporating a high-resistivity layer of the n-type; a p-body region 32 formed on a front face of the semiconductor layer 31; a source region 33 formed on a front face of the p-body region 32; a gate insulating film 34 arranged on a front face of the semiconductor layer 31, between the p-body regions 32; a gate electrode 35 arranged on the gate insulating film 34; a source electrode 36 connected to the source region 33 and the p-body region 32; and an n+ drain region 37 arranged on a back face opposite the surface of the semiconductor layer 31. and a drain electrode 38 connected to the n+-type drain region 37. The gate pad electrode GP is connected to the gate electrode 35, which is arranged on the gate insulating film 34, and the source pad electrode SP is connected to the source electrode 36, which is connected to the source region 33 and the p-body region 32. Furthermore, as shown in Fig. 41, the gate pad electrode GP and the source pad electrode SP are arranged on an intermediate insulating film 39, which is provided for passivation and covers the surface of the SiC MOSFET 130A. In addition, a microstructure transistor structure (not shown) can be formed in the semiconductor layer 31 below the gate pad electrode GP and the source pad electrode SP. Furthermore, as shown in Fig. 41, the source pad electrode SP can be arranged so that it extends onto the interlayer insulating film 39, which serves for passivation, even in the transistor structure of the middle section. Although the SiC MOSFET 130A is constructed by incorporating an n-channel SiC MOSFET of the planar-gate type, as shown in Fig. 41, the SiC MOSFET 130A can be constructed by incorporating a vertical n-channel SiC TMOSFET of the trench-gate type 130C, etc., as shown in Fig. 44, which is mentioned below. Alternatively, instead of the SiC-MOSFET 130A, a GaN-based FET etc. can also be assumed as the semiconductor component to be applied to the PM, which is to be mounted on the semiconductor device according to the embodiments. The semiconductor components ((Q2 and Q5) and (Q3 and Q6)), which are applicable to the PM to be mounted on the semiconductor device according to the embodiments, can be implemented in a similar manner. Furthermore, for the semiconductor components Q1 to Q6, which are applicable to the PM to be mounted on the semiconductor device according to the embodiments, for example a wide bandgap semiconductor can be used whose bandgap energy is in a range of 1.1 eV to 8 eV. Similarly, Fig. 42 shows a schematic cross-sectional structure of an IGBT 130B, which has an emitter pad electrode EP and a gate pad electrode GP, being an example of the semiconductor components (Q1, Q4) applicable to the PM to be mounted on the semiconductor device according to the embodiments. As shown in Fig. 42, the IGBT 130B comprises: a semiconductor layer 31, which is constructed by incorporating a high-resistance n-type layer; a p-body region 32, which is formed on a front face of the semiconductor layer 31; an emitter region 33E, which is formed on a front face of the p-body region 32; a gate insulating film 34, which is arranged on a front face of the semiconductor layer 31, between the p-body regions 32; a gate electrode 35, which is arranged on the gate insulating film 34; an emitter electrode 36E, which is connected to the emitter region 33E and the p-body region 32; a p+ collector region 37P, which is arranged on a back face opposite the face of the semiconductor layer 31; and a collector electrode 38 connected to the p+ collector region 37P. The gate pad electrode GP is connected to the gate electrode 35, which is arranged on the gate insulating film 34, and the emitter pad electrode EP is connected to the emitter electrode 36E, which is connected to the emitter region 33E and the p-body region 32. Furthermore, as shown in Fig. 42, the gate pad electrode GP and the emitter pad electrode EP are arranged on an intermediate insulating film 39, which serves for passivation and covers the area of ​​the IGBT 130B. In addition, a microstructure IGBT structure (not shown) may be formed in the semiconductor layer 31 below the gate pad electrode GP and the emitter pad electrode EP. Furthermore, as shown in Fig. 42, the emitter pad electrode EP can be arranged so that it extends onto the intermediate insulating film 39, which serves for passivation purposes, even in the IGBT structure of the middle section. Although the IGBT 130B in Fig. 42 is constructed by incorporating a vertical n-channel IGBT of the planar-gate type, the IGBT 130B can be constructed by incorporating a vertical n-channel IGBT of the trench-gate type, and the like. The semiconductor components ((Q2 and Q5) and (Q3 and Q6)), which are applicable to the PM to be mounted on the semiconductor device according to the embodiments, can also be implemented in a similar manner. For MOSFETs Q1 to Q6, SiC-based power devices, e.g., a SiC DIMOSFET and a SiC TMOSFET, or GaN-based power devices, e.g., a GaN-based high electron mobility transistor (HEMT), can be used. In some cases, power devices such as Si-based MOSFETs and IGBTs can also be used. - SiC-DIMOSFET - Fig. 43 shows a schematic cross-sectional structure of a SiC-DIMOSFET 130C, which is an example of a semiconductor component 110 to be applied to the PM to be mounted on the semiconductor device according to the embodiments. As shown in Fig. 43, the SiC-DIMOSFET 130C comprises: a semiconductor layer 31 formed by incorporating a high-resistance n-type layer; a p-body region 32 formed on a front face of the semiconductor layer 31; an n+ source region 33 formed on a front face of the p-body region 32; a gate insulating film 34 arranged on a front face of the semiconductor layer 31 between the p-body regions 32; a gate electrode 35 arranged on the gate insulating film 34; a source electrode 36 connected to the source region 33 and the p-body region 32; and an n+ drain region 37 arranged on a rear face opposite the surface of the semiconductor layer 31. and a drain electrode 38 connected to the n+-type drain region 37. In the SiC-DIMOSFET 130C shown in Fig. 43, the p-body region 32 and the n+-source region 33, which is formed on the front surface of the p-body region 32, are formed with double ion implantation (DII), and the source pad electrode SP or SPD is connected to the source region 33 and the source electrode 36, which are connected to the p-body region 32. Furthermore, a gate pad electrode GP (not shown) is connected to the gate electrode 35, which is arranged on the gate insulating film 34. In addition, as shown in Fig. 43, the gate pad electrode GP and the source pad electrode SP and SPD, respectively, are arranged on an intermediate insulating film 39, which serves for passivation purposes and covers the area of ​​the SiC DIMOSFET 130C. As shown in Fig. 43, due to the formation of a depletion layer, indicated by dashed lines, in the semiconductor layer 31, which consists of a high-resistance n-type layer inserted into or between the p-body regions 32, a channel resistance RJFET is formed in the SiC DIMOSFET 130C. This channel resistance accompanies or is associated with the action of the junction-type FET (JFET). Furthermore, as shown in Fig. 43, body diodes BD are formed between the p-body regions 32 and the semiconductor layers 31. - SiC TMOSFET - Fig. 44 shows a schematic cross-sectional structure of a SiC TMOSFET, which is an example of a semiconductor component that can be applied to the PM to be mounted on the semiconductor device according to the embodiments. As shown in Fig. 44, the SiC TMOSFET 130D comprises: a semiconductor layer 31N formed by embedding an n-layer; a p-body region 32 formed on a front face of the semiconductor layer 31N; an n+ source region 33 formed on a front face of the p-body region 32; a trench-gate electrode 35TG extending through the p-body region 32, the trench-gate electrode 35TG being formed in the trench extending to the semiconductor layer 31N, across the gate insulating film 34 and the interlayer insulating films 39U and 39B; a source electrode 36 connected to the source region 33 and the p-body region 32; an n+-drain region 37, which is arranged on a rear surface opposite the surface of the semiconductor layer 31N; and a drain electrode 38, which is connected to the n+-type drain region 37. In Fig. 44, in the SiC TMOSFET 130D, a trench-gate electrode 35TG, which passes through the p-body region 32, is formed in the trench that extends up to the semiconductor layer 31N, over the gate insulating film 34 and the interlayer insulating films 39U and 39B; and the source-pad electrode SP is connected to the source region 33 and the source electrode 36, which is connected to the p-body region 32. Furthermore, a gate pad electrode GP (not shown) is connected to the trench gate electrode 35TG, arranged on the gate insulating film 34. In addition, as shown in Fig. 44, the gate pad electrode GP and the source pad electrode SP are arranged on the interlayer insulating film 39U, which serves for passivation purposes and covers the area of ​​the SiC TMOSFET 130D. In the SiC TMOSFET 130D, a channel resistance RJFET is formed, which accompanies the FET's transition effect (JFET effect), as in the SiC DIMOSFET 130C. Furthermore, body diodes BD are formed between the p-body regions 32 and the semiconductor layers 31N in the same manner as shown in Fig. 43. (Example of application) Fig. 45 shows an example of a circuit configuration in which the SiC MOSFET is used as a semiconductor component, and a snubber capacitor C is connected between the power terminal PL and the ground terminal (ground terminal) NL in a three-phase alternating current inverter 42 (AC inverter) constructed using the PM, which is to be mounted on the semiconductor device according to the embodiments. When the PM is connected to the power source E according to the embodiments to perform switching operations, a high surge voltage Ldi / dt is generated due to an inductance L contained in a connecting line, resulting from the high switching speed of the SiC MOSFET and SiC IGBT. For example, the surge voltage Ldi / dt can be represented as follows: di / dt = 3×10⁹(A / s), where a current change di = 300A, and where a time variation dt = 100 ns associated with switching. Although the impulse voltage Ldi / dt changes depending on the value of the inductance L, the impulse voltage Ldi / dt is superimposed on the power source E. Such an impulse voltage Ldi / dt can be absorbed by the snubber capacitor C, which is connected between the power terminal PL and the ground terminal NL. (Concrete example) Next, the three-phase AC inverter 44 is described, which is constructed using the PM, which is to be mounted on the semiconductor device according to the embodiments, using the SiC MOSFET as the semiconductor component, the description being given with reference to Fig. 46. As shown in Fig. 46, the three-phase AC inverter 44 comprises: a PM unit 200 connected to a gate driver (GD) 180; a three-phase AC motor unit 51; a power supply or storage battery (E) 53; and a converter 55. A U-phase, a V-phase, and a W-phase inverter are each connected to the three-phase AC motor unit 51, corresponding to the U-phase, the V-phase, and the W-phase of the three-phase AC motor unit 51 in the PM unit 200, respectively. In this case, the GD 180 is connected to SiC MOSFETs Q1 and Q4, to SiC MOSFETs Q2 and Q5, and to SiC MOSFETs Q3 and Q6. The PM unit 200 includes the SiC MOSFETs (Q1 and Q4), (Q2 and Q5) and (Q3 and Q6) which have inverter configurations, connected between a positive terminal (+) P and a negative terminal (-) N of the converter 55, to which the power supply or storage battery (E) 53 is connected. In addition, freewheeling diodes DI1 to DI6 are connected in reverse parallel between the source and drain of the SiC MOSFETs Q1 to Q6. According to the embodiments, the semiconductor device can be of the air-cooled type, the PM and the power supply, each of which has high heat dissipation performance and achieves a low weight. The semiconductor component applicable to the PM, which is to be mounted on the semiconductor device according to the embodiments, can be not only SiC-based power components but also power components of the large or wide bandgap type, such as a GaN-based or a Si-based power component. Furthermore, the application is not only possible on potted power modules (PMs) where resin potting is carried out, but also on power modules that are enclosed in case-type packages. [Other embodiments] As explained above, the embodiments described are to be interpreted as an illustrative disclosure, including associated description and drawings, and not restrictively. The present disclosure clarifies for those skilled in the art a multitude of alternative embodiments, working examples, and operating techniques. COMMERCIAL APPLICABILITY The power semiconductor device, the PM and the power supply according to the embodiments can be used for semiconductor module technologies, including power supplies, e.g. IGBT modules, diode modules, MOS modules (Si, SiC, GaN, gallium oxide), etc., and can be applied to a wide range of applications, e.g. inverters for electric hybrid vehicles (HEVs), electric vehicles (EVs), industrial inverters or converters. Reference symbol list 2 Semiconductor device 6 Heat dissipation unit 8, 80, 80U, 80V, 80W Power module (PM) (TS) 10, 10U, 10V, 10W Heat diffusion unit (vapor chamber) 12, 12SA, 12SB Thermal conduction layer (heat conduction layer, solder layer) 14, 14PA, 14PB, 14C, 14P Base unit 15PB Base unit (thermally highly conductive material) 16, 16FA, 16FB, 16C, 16F, 161, 162, 163, ..., 16n Air cooling fin unit 17FB Air cooling fin unit 20, Q, Q1 to Q6 Semiconductor component (SiC MOSFET) 21 Ceramic substrate 22 Backside electrode pattern (backside electrode layer of the ceramic substrate) 23 Surface electrode pattern (frontside electrode layer of the ceramic substrate) 25 Thermal conduction layer (thermal conduction layer, solder layer, baked Ag layer) 26 Solder layer 27 Baked Ag layer 40 Pressure plate 42, 44 Three-phase AC inverter 50, 50F1, 50F2 Fan 51 Three-phase AC motor unit 52 PM of 1-in-1 module type 53 Power supply or storage battery (E) 55 Converter 90 Cooling device 100 PM of 2-in-1 module type 130A Vertical N-channel SiC MOSFET, planar gate type 130B; Vertical N-channel IGBT, planar gate type 130C; Vertical N-channel SiC TMOSFET, trench gate type 130D; SiC DIMOSFET 180; Gate driver (GD) 200; PM unit 300; Cast resin layer GS (GS1, GS2, GS3, ..., GSn) Graphite layer GP (XY), GP (XZ) Graphite substrate CP1, CP2, CP3, ..., CPn Thermal contact unit AP Opening OA, SPACE Thermal contact space unit NC Non-contact unit T1 Base unit surface temperature T2 Air cooling fin unit base temperature T3 Air cooling fin unit top temperature Ta Outside air temperature W1 Thickness of cooling device WP Width of air cooling fin LF Length of air cooling fin FS Fin space LB Base length L1 Base width Rth (Fin) Thermal resistance value (K / W) of air cooling fin RATIO Temperature difference ratio within air cooling fin r1, r2, r3, r1', r2', r3', r1", r2", r3" Thermal resistance value V1, V2, V3, V1', V2', V3', V1", V2", V3" Temperature I1, I2, I3, I1', I2', I3', I1", I2", I3" heat flow or-current SS1, SS4 Source detection terminal electrode GT1, GT4 Gate signal terminal electrode P Positive-side power input terminal electrode (first power source) N Negative-side power input terminal electrode (second power source) O, U, V, W Output terminal electrode.

Claims

Semiconductor device comprising: a heat source (8(TS)) comprising a semiconductor component, wherein the semiconductor component generates heat in an operating state;a heat diffusion unit (10) which is thermally connected to the heat source, wherein the heat diffusion unit forms a space (OA+AP) at a position opposite the heat source, by means of a first section extending from a connecting section (8(TS)) connected to the heat source on two sides along a first direction parallel to a connecting surface connected to the heat source, and by means of a second and a third section extending from two ends of the first section in a second direction away from the heat source, a first heat conduction layer (12SA) attached to a surface of the second section facing the space, and a second heat conduction layer (12SB) attached to a surface of the third section facing the space;a first heat dissipation unit (6) attached to the first heat conduction layer (12SA) comprising a first base unit (14PA) and a plurality of first fin units (16FA1,16FA2,..., 16FAm) arranged to extend outwards from the first base unit into the space (OA+AP); and a second heat dissipation unit (6) attached to the second heat conduction layer (12SB) and comprising a second base unit (14PB) and a plurality of second fin units (16FB1, 16FB2, ..., 16FBm) arranged to extend into space from the first base unit, wherein, at least in a section parallel to a plane defined by the first direction and the second direction, tips of the first and second fin units extend into space (OA+AP) to a position directly below a position where the semiconductor device is located. Semiconductor device according to claim 1, wherein the space is configured such that air flows in a direction perpendicular to the plane defined by the first direction and the second direction. Semiconductor device according to claim 1 or 2, further comprising a thermal contact space unit surrounded by the thermal diffusion unit, wherein the thermal contact space unit spatially contains the plurality of first fin units and the plurality of second fin units. Semiconductor device according to any one of claims 1-3, wherein the heat diffusion unit comprises Cu or a vapor chamber. Semiconductor device according to any one of claims 1-3, wherein the thermal diffusion unit comprises a graphite substrate with anisotropic thermal conductivity. Semiconductor device according to claim 2, wherein the first and second base unit (14PA, 14PB) comprises a graphite substrate with anisotropic thermal conductivity. Semiconductor device according to claim 5 or 6, wherein the graphite substrate is arranged in an orientation direction in which the heat transfer coefficient of the graphite substrate is relatively high. Semiconductor device comprising: a heat source comprising a semiconductor device, wherein the semiconductor device generates heat in an operating state; a heat diffusion unit thermally connected to the heat source; wherein the heat diffusion unit comprises a first section extending from a connecting section (8(TS)) connected to the heat source on two sides along a first direction parallel to a connecting surface connected to the heat source, a second and a third section extending from two ends of the first section in a second direction away from the heat source, and a fourth section extending from a central section of the first section in the second direction, wherein the first, second and third sections form a first space (OA+AP) at a position opposite the heat source, and wherein the first,The third and fourth sections form a second space (OA+AP) at a position opposite the heat source, and a first and a second heat dissipation unit (6) connected to the heat diffusion unit and formed in the first space, as well as a third and a fourth heat dissipation unit (6) connected to the heat diffusion unit and formed in the second space, wherein the heat diffusion unit has a cooling device that spatially contains the first to fourth heat dissipation units, wherein the heat diffusion unit has a first opening (AP) and a second opening (AP), wherein the first space containing the first and second heat dissipation units is open via the first opening, and wherein the second space containing the third and fourth heat dissipation units is open via the second opening. Semiconductor device comprising: a heat source comprising a semiconductor component, wherein the semiconductor component generates heat in an operating state; a heat diffusion unit thermally connected to the heat source;wherein the heat diffusion unit comprises a first section extending from a connecting section connected to the heat source (8(TS)) on two sides along a first direction parallel to a connecting surface connected to the heat source, a second and a third section extending from two ends of the first section in a second direction away from the heat source, and a fourth section extending from a central section of the first section in the second direction, wherein the first, second and third sections form a first space (OA+AP) at a position opposite the heat source, and wherein the first, third and fourth sections form a second space (OA+AP) at a position opposite the heat source;and a first and a second heat dissipation unit (6) connected to the heat diffusion unit and formed in the first space, and a third and a fourth heat dissipation unit (6) connected to the heat diffusion unit and formed in the second space, wherein the heat diffusion unit has a cooling device spatially containing the first to fourth heat dissipation units, wherein the heat diffusion unit contains the first to fourth heat dissipation units in a spatially closed state, and wherein a heat transfer coefficient of a material forming the heat diffusion unit is equal to or greater than a heat transfer coefficient of a material forming the heat dissipation unit. Semiconductor device according to claim 8, wherein each of the first to fourth heat dissipation units comprises a base unit and a plurality of air cooling fin units connected to the base unit, the base unit being in contact with the heat diffusion unit. Semiconductor device according to claim 8 or 10, wherein a section of each of the first to fourth heat dissipation units, apart from the heat diffusion unit and the opening, comprises a contactless or non-contact unit. Semiconductor device comprising: a heat source (8(TS)) comprising a semiconductor component, wherein the semiconductor component generates heat in an operating state;a heat diffusion unit (10) thermally connected to the heat source, a plurality of heat dissipation units (6) connected to the heat diffusion unit, a cooling device spatially containing the heat dissipation units, wherein the heat diffusion unit has an opening (AP) and wherein a space containing the heat dissipation unit is open via the opening, wherein the heat dissipation unit comprises a base unit and a plurality of air cooling fin units connected to the base unit, wherein the base unit is in contact with the heat diffusion unit, wherein a value of a ratio RATIO = (T2-T3) / (T1-T2) is equal to or less than 25 / LB (mm), where T1 is a surface temperature of the base unit, where T2 is a base temperature of the air cooling fin unit, where T3 is a top temperature of the air cooling fin unit, and where LB (mm) is a base length of the base unit. Semiconductor device according to any one of claims 8, 10-12, wherein a heat transfer coefficient of a material forming the heat diffusion unit is equal to or greater than a heat transfer coefficient of a material forming the heat dissipation unit. Semiconductor device according to any one of claims 8-13, wherein the heat diffusion unit comprises Cu or a vapor chamber. Semiconductor device according to any one of claims 8-13, wherein the thermal diffusion unit comprises a graphite substrate with anisotropic thermal conductivity. Semiconductor device according to claim 10, wherein the base unit comprises a graphite substrate with anisotropic thermal conductivity. Semiconductor device according to claim 15 or 16, wherein the graphite substrate is arranged in an orientation direction in which the heat transfer coefficient of the graphite substrate is relatively high. Semiconductor device according to any one of claims 1-17, wherein the semiconductor component comprises any component selected from a group consisting of an IGBT, a diode, a MOSFET, each Si-based or SiC-based, and a FET, namely GaN-based. Power module with a semiconductor device according to any one of claims 1-17, wherein the semiconductor component has a configuration of any module selected from a group consisting of a 1-in-1 module, a 2-in-1 module, a 4-in-1 module, a 6-in-1 module, a 7-in-1 module, an 8-in-1 module, a 12-in-1 module and a 14-in-1 module. Power module according to claim 19, wherein the semiconductor component forms an inverter or a converter of the 6-in-1 module type. Power supply configured to convert an input voltage and output the converted input voltage, using the semiconductor device or power module according to any one of claims 1-17. Semiconductor device according to claim 1, wherein the length of the first and second fin units is longer than the distance (=AP) between the first fin unit and the second fin unit that are located in the space (OA+AP). Semiconductor device according to claim 1, wherein the first and second heat conduction layers are solder layers. Semiconductor device according to claim 1, wherein the first and second base unit and the first and second fin unit are made of the same material. Semiconductor device according to claim 1, wherein the first and second base unit and the first and second fin unit are constructed or composed of different materials.

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