Light-emitting semiconductor device and method for manufacturing a light-emitting semiconductor device

Abstract

Light-emitting semiconductor device (100) comprising: a conductive support substrate (80); a metal layer (60) comprising a reflective metal (60A) provided on the conductive support substrate (80); a semiconductor laminate (30) provided on the metal layer (60), wherein the semiconductor laminate (30) is a stack of a plurality of III-V group compound semiconductor layers (31, 35, 35B, 35W, 37, 39) based on InGaAsP, containing at least In and P; an n-type InGaAs contact layer (20A) provided on the semiconductor laminate (30); and an n-side electrode (93) provided on the n-type InGaAs contact layer (20A), wherein a central emission wavelength of light emitted by the semiconductor laminate (30) is 1000 nm to 2200 nm, and wherein the n-type InGaAs contact layer (20A) has an In composition ratio of 0.54 or more and 0.60 or less.

Description

TECHNICAL AREA The present disclosure relates to a light-emitting semiconductor device and a method for its manufacture, in particular a light-emitting semiconductor device of the compound type with a central emission wavelength of 1000 nm to 2200 nm, and a method for its manufacture. BACKGROUND Light-emitting semiconductor devices are known that emit light with a wavelength of 750 nm or more in the infrared range. They are widely used in applications such as sensors, gas analysis, and surveillance cameras. If the central emission wavelength of such a light-emitting semiconductor device is 1000 nm to 2200 nm in the near-infrared range, a III-V semiconductor based on InGaAsP containing In and P is commonly used as the light-emitting layer. For epitaxial growth of a III-V semiconductor layer based on InGaAsP, such as an InP layer, an InP substrate is conventionally used as the growth substrate, so that the III-V semiconductor layer based on InGaAsP containing In and P has a lattice match with the growth substrate. For example, PTL 1 discloses a light-emitting semiconductor device based on InGaAsP-InP, comprising an n-type InP substrate; and active layers, a p-type plating layer, a p-type InGaAs layer, and an Ohmic p-type InGaAsP contact layer, which are provided on the n-type InP substrate in that order. PTL 2 describes a light-emitting semiconductor device. PTL 3 discloses a fabrication of a light-emitting semiconductor device. PTL 4 describes a surface emission-type light-emitting semiconductor device. DOCUMENT LIST Patent document PTL 1: JP H06 - 112 531 APTL 2: JP 2008 - 283 096 APTL 3: JP H04 - 249 384 APTL 4: JP H07 - 111 339 A SUMMARY (Technical problem) As in the technique disclosed in PLT 1, to fabricate a light-emitting semiconductor device with a central emission wavelength of 1000 nm to 2200 nm in the near-infrared range, an InP substrate, serving as a growth substrate, is used as the support substrate for the light-emitting semiconductor device. This is because InP substrates are transparent to light in the near-infrared range and consequently do not impede the transmission of infrared light. Meanwhile, the demand for portable devices has created a need for size reduction in light-emitting semiconductor devices that emit light in the infrared range, and in particular the need for a reduction in the thickness (i.e., the overall thickness) of light-emitting semiconductor devices has increased. Commercially available InP substrates generally have a thickness of 350 µm for 5.08 cm (2-inch) substrates. On the other hand, the thicknesses of components other than the InP substrate, such as III-V semiconductor layers and electrodes based on InGaAsP, provided in a light-emitting semiconductor device, are at most several micrometers. Consequently, the substrate thickness contributes the majority of the thickness of an optical semiconductor device. We have conducted investigations into thinning substrates to reduce device thicknesses and have found only that InP substrates break when the substrates are excessively ground to thicknesses of, for example, 150 µm or less. We therefore attempted to fabricate a compound-type light-emitting semiconductor device by forming a semiconductor laminate with an n-type semiconductor layer, active layers, and a p-type semiconductor layer on an n-type InP growth substrate; then bonding the semiconductor laminate to a conductive support substrate with an interposed metal layer; and removing the growth substrate. Since a compound-type light-emitting semiconductor device can utilize a conductive support substrate instead of an InP substrate, a reduction in the overall thickness of the light-emitting semiconductor device can be achieved by thinning the conductive support substrate. In the compound-type light-emitting semiconductor device fabricated by the aforementioned processes, the n-type semiconductor layer must be grown to exhibit lattice matching with the grown n-type InP substrate and the active layers that sandwich the n-type semiconductor layer. For this reason, a III-V group compound semiconductor layer based on InGaAsP, containing at least In and P, such as an n-type InP layer, is used as the n-type semiconductor layer. This n-type semiconductor layer (e.g., an n-type InP layer serving as an n-type plating layer) will form an ohmic contact with an n-side electrode. In a conventional light-emitting semiconductor device in which an n-type InP substrate serves as a support substrate, such as the one disclosed in PTL 1, an n-side electrode is provided on the surface opposite the growth surface of the n-type InP substrate in such a way that an ohmic contact is formed between the n-type InP substrate and the n-side electrode. Instead of a conventional light-emitting semiconductor device with an n-type InP substrate as a support, we fabricated a compound-type light-emitting semiconductor device and evaluated its light emission characteristics. For this compound-type device, the degradation of both the light output power and the forward voltage was investigated over time. In particular, the degradation of the forward voltage over time was an unexpected finding. Consequently, improving the reliability with respect to the variations in light output power and forward voltage over time was identified as a new challenge. Accordingly, the present disclosure is intended to provide a light-emitting semiconductor device of the compound type with a central emission wavelength of 1000 nm to 2200 nm, which exhibits improved reliability with smaller deviations in light output power and forward voltage over time, and a method for its fabrication. (Solution to the problem) We have carefully investigated ways to overcome the aforementioned challenge and focused on an n-type semiconductor layer intended to form an ohmic contact with an n-side electrode. We then developed the concept of providing an n-type InGaAs contact layer (InGaAs lacking P) instead of a III-V group compound semiconductor layer based on InGaAsP containing at least In and P. We found that the n-type InGaAs contact layer improved the time-vary deviations of the light-emitting power and forward voltage of the light-emitting semiconductor device, thus completing the present disclosure. In particular, the subject matter of the present disclosure is as follows: (1) Light-emitting semiconductor device comprising: a conductive support substrate; a metal layer comprising a reflective metal provided on the conductive support substrate; a semiconductor laminate provided on the metal layer, the semiconductor laminate being a stack of a plurality of III-V group compound semiconductor layers based on InGaAsP, containing at least In and P; an n-type InGaAs contact layer provided on the semiconductor laminate; and an n-side electrode provided on the n-type InGaAs contact layer, wherein a central emission wavelength of light emitted by the semiconductor laminate is 1000 nm to 2200 nm, and wherein the n-type InGaAs contact layer has an in-composition ratio of 0.54 or more and 0.60 or less. (2) Light-emitting semiconductor device according to (1), wherein the n-side electrode of a material consisting of Au and Ge, and Ti,(3) Light-emitting semiconductor device according to (1) or (2), wherein the semiconductor laminate comprises a p-type plating layer, active layers, and an n-type plating layer in that order from one side of the metal layer. (4) Method for fabricating a light-emitting semiconductor device, comprising: a first step of forming an n-type InGaAs contact layer comprising an n-side electrode-forming region on an n-type InP growth substrate; a second step of forming a semiconductor laminate by stacking a plurality of III-V group compound semiconductor layers based on InGaAsP, comprising at least In and P, on the n-type InGaAs contact layer; a third step of forming a reflective metal layer on the semiconductor laminate; a fourth step of bonding a conductive support substrate having a surface provided with a metal compound layer. is,with the reflective metal layer, wherein the metal compound layer is arranged between; a fifth step of removing the n-type InP growth substrate; and a sixth step of partially removing the n-type InGaAs contact layer to provide the semiconductor laminate with an exposed surface while forming an n-side electrode on the n-side electrode-forming region of the n-type InGaAs contact layer, wherein a central emission wavelength of light emitted by the semiconductor laminate is 1000 nm to 2200 nm, and wherein an In-composition ratio of the n-type InGaAs contact layer formed in the first step is set to 0.54 or more and 0.60 or less. (5) Method for producing a light-emitting semiconductor device according to (4), wherein the n-side electrode of a material composed of Au and Ge, and Ti,(6) Method for manufacturing a light-emitting semiconductor device according to (4) or (5), wherein the semiconductor laminate comprises an n-type plating layer, active layers and a p-type plating layer in that order from one side of the n-type InGaAs contact layer. (Beneficial effect) According to the present disclosure, a light-emitting semiconductor device of the compound type with a central emission wavelength of 1000 nm to 2200 nm, exhibiting excellent reliability with small deviations in light emission power and forward voltage over time, and a method for its fabrication can be provided. BRIEF DESCRIPTION OF THE DRAWINGS In the accompanying drawings: Fig. 1 is a schematic cross-sectional view showing parts of the steps for manufacturing a light-emitting semiconductor device according to an embodiment of the present disclosure; Fig. 2 is a schematic cross-sectional view of Fig. 1 showing parts of the steps for manufacturing the light-emitting semiconductor device according to an embodiment of the present disclosure; Fig. 3 is a schematic cross-sectional view of Fig. 2 showing parts of the steps for manufacturing the light-emitting semiconductor device according to an embodiment of the present disclosure; Fig. 4 is a schematic cross-sectional view of Fig. 3 showing parts of the steps for manufacturing the light-emitting semiconductor device according to an embodiment of the present disclosure; Fig.Figure 5 is a schematic cross-sectional view of a light-emitting semiconductor device according to an embodiment of the present disclosure; Figure 6 is a schematic cross-sectional view showing a preferred mode of an environment of a dielectric layer and a p-type contact section in a light-emitting semiconductor device according to a preferred embodiment of the present disclosure; Figure 7 is a schematic cross-sectional view showing a preferred embodiment in a method for producing a light-emitting semiconductor device according to the present disclosure; Figure 8 is a schematic top view of steps 72 and 74 in Figure 7; Figure 9 is a schematic cross-sectional view of Figure 7 showing the preferred embodiment in the method for producing a light-emitting semiconductor device according to the present disclosure; FigureFigure 10A is a schematic top view showing the structure of an Ohmian electrode section in examples; and Figure 10B is a schematic top view showing the structure of an n-sided electrode in examples. DETAILED DESCRIPTION Before describing embodiments of this disclosure, the following points are described in advance. First, in this description, the expression "InGaAsP" alone, for which the composition ratio is not specified, represents a given compound with a chemical composition ratio of Group III elements (total amount of In and Ga) to Group V elements (As and P) of 1:1, where the ratio between In and Ga, which are Group III elements, and the ratio between As and P, which are Group V elements, is not specified. In this case, it is possible that one of the In and Ga is not included as a Group III element; or it is possible that one of the As and P is not included as a Group V element.InGaAsP, defined as containing "at least In and P", means that the Group III elements contain more than 0% and 100% or less In, and the Group V elements contain more than 0% and 100% or less P. Furthermore, the term "InGaP" means that As is not included in the aforementioned "InGaAsP", except for unavoidable impurities introduced during production, and the term "InGaAs" means that P is not included in the aforementioned "InGaAsP", except for unavoidable impurities introduced during production. Similarly, the term "InAsP" means that Ga is not included in the aforementioned "InGaAsP", except for unavoidable impurities introduced during production, and the term "GaAsP" means that In is not included in the aforementioned "InGaAsP", except for unavoidable impurities introduced during production.Furthermore, the term "InP" means that Ga and As are not present in the aforementioned "InGaAsP," except for unavoidable impurities resulting from the manufacturing process. It should be noted that the compositional ratios of InGaAsP, InGaAs, and the like can be determined, for example, by photoluminescence or X-ray diffraction measurements. Furthermore, the term "unavoidable impurities resulting from the manufacturing process" refers to unavoidable impurities originating from the manufacturing apparatus when source gases are used, as well as to the diffusion of atoms at interfaces between layers during crystal growth or subsequent heat treatment, and the like. In this description, a layer acting as an electrical p-type layer is referred to as a p-type layer, and a layer acting as an electrical n-type layer is referred to as an n-type layer. Furthermore, a layer that has not been intentionally doped with certain foreign atoms, such as Zn, S, and Sn, and that does not act as an electrical p-type or n-type layer, is referred to as an "i-type" or "undoped" layer. An undoped layer may contain foreign atoms that are inevitably introduced during the fabrication process. In particular, if the substrate density is low (for example, less than 4 × 10¹⁶ / cm³), the layer is considered "undoped" in this description. The values ​​of the foreign atom concentrations of Zn, Sn, etc., are determined by SIMS analysis. The total thickness of formed layers can be measured using an interference thickness measurement system. Furthermore, the thickness of each layer can be calculated by examining a cross-section of the growth layer using a thickness measurement system employing optical interferometry and a transmission electron microscope. If the thickness of each layer is small, as in a superlattice structure, the thickness can be measured using TEM-EDS. It should be noted that if a particular layer has a sloping surface in cross-section, the thickness of that layer is determined by the maximum height of the layer above a flat surface of the underlying layer. Embodiments of the present disclosure are described below with reference to the drawings. For convenience, a method for manufacturing a light-emitting semiconductor device 100 according to one embodiment of the present disclosure is described first, and then the details of the light-emitting semiconductor device 100 are described. The light-emitting semiconductor device 100 can be manufactured according to one embodiment of a method for manufacturing a light-emitting semiconductor device 100, which is described with reference to Figures 1, 2, 3 to 4, and can be obtained by at least the first to sixth steps. For the sake of simplicity, each of the steps 0 to 80 shown in Figures 1, 2, 3 to 4 is shown to comprise one or more steps.Accordingly, each step in the drawings need not necessarily correspond one-to-one with each step according to the present embodiment. In principle, corresponding components are designated by the same reference numerals, and the description of such components is not repeated. For the sake of clarity, the substrate and layers in each drawing are exaggerated with respect to width and thickness, so that the ratio between the vertical and horizontal dimensions of each component shown does not correspond to the actual ratio. (Method for manufacturing a light-emitting semiconductor device) A method for manufacturing a light-emitting semiconductor device 100 according to an embodiment of the present disclosure comprises at least a first, second, third, fourth, fifth, and sixth step, which are described in detail below. Optionally, additional steps may be included. An interlayer formation step comprising steps 30 to 36 (see Figs. 1 and 2), and a surface roughening step for the surface of an n-type plating layer 31, comprising steps 71 to 76 (see Figs. 7, 8 to 9), which will be described in detail later, are specific examples of preferred steps that are preferably included in the manufacturing method according to the present disclosure. In the first step, an n-type InGaAs contact layer 20 is formed on an n-type InP growth substrate 10 (steps 0 and 10 in Fig. 1). In the second step, a semiconductor laminate 30 is formed on the n-type InGaAs contact layer 20 (step 20 in Fig. 1). In the third step, a reflective metal layer 60A is formed on the semiconductor laminate 30 (step 40 in Fig. 3). In the fourth step, a conductive support substrate 80 with a surface provided with a metal compound layer 60B is bonded to a reflective metal layer 60A, with the metal compound layer 60B positioned between them (step 50 in Fig. 4). In the fifth step, the n-type InP growth substrate 10 is removed (step 60 in Fig. 4).In the sixth step, the n-type InGaAs contact layer 20 is partially removed, so that the semiconductor laminate 30 is provided with an exposed surface, while an n-side electrode 93 is formed on an n-side electrode-forming region 20A of the n-type InGaAs contact layer 20 (step 70A or step 70B and step 80 in Fig. 4). The central emission wavelength of light emitted by the semiconductor laminate 30 formed in the second step is adjusted to 1000 nm to 2200 nm. Furthermore, the in-composition ratio of the n-type InGaAs contact layer formed in the first step is adjusted to 0.54 or more and 0.60 or less. The light-emitting semiconductor device 100 according to an embodiment of the present disclosure is produced in this way. The details of each step are described below. <Erster Schritt> As described above, in a first step an n-type InGaAs contact layer 20 is formed on an n-type InP growth substrate 10. First, as shown in step 0 in Fig. 1, the n-type InP growth substrate 10 is provided. Commercially available substrates can be used as the n-type InP growth substrate 10 in the present embodiment, and the size and thickness of the substrate are not specifically limited; a so-called 5.08 cm (2 in) substrate, 7.62 cm (3 in) substrate, 10.16 cm (4 in) substrate, and 15.24 cm (6 in) substrate can be used. Then, in the first step, an n-type InGaAs contact layer 20 is formed on the n-type InP growth substrate 10 (step 10 in Fig. 1). The in-composition ratio of the n-type InGaAs contact layer 20 formed in the first step is adjusted to 0.54 or more and 0.60 or less. If the composition formula of the n-type InGaAs contact layer 20 is expressed as InzGa(1-z)As, where z represents the in-composition ratio, the in-composition ratio z is adjusted to 0.54 or more and 0.60 or less. It should be noted that InGaAs exhibits perfect lattice matching with InP when the in-composition ratio z is 0.532. To exert a compressive deformation on the semiconductor laminate 30, z ≥ 0.54 is satisfied. It should be noted that the n-type InGaAs contact layer 20 is not limited to a single layer with a constant composition and can be composed of multiple layers with different in-composition ratios z. Furthermore, the in-composition ratio z of the n-type InGaAs contact layer 20 can exhibit a gradient, for example, by increasing or decreasing the in-composition ratio zin in the thickness direction. Additionally, the concentration of a dopant in the n-type InGaAs contact layer 20 can also be varied within the layer itself. <Zweiter Schritt> In a second step following the first step, a semiconductor laminate 30 is formed on the n-type InGaAs contact layer 20, which is formed from a stack of a plurality of III-V group compound semiconductor layers based on InGaAsP, containing at least In and P (step 20 in Fig. 1). The semiconductor laminate 30 can comprise an n-type plating layer 31, active layers 35, and a p-type plating layer 37 in that order, and each of these layers is formed as a layer made from a III-V group compound semiconductor based on InGaAsP, containing at least In and P. The composition of each layer in the semiconductor laminate 30 is not specifically restricted, as long as the central emission wavelength of light emitted by the active layers in the semiconductor laminate 30 is between 1000 nm and 2200 nm. The semiconductor laminate 30 can have a double hetero (DH) structure in which the active layers 35 are sandwiched between the n-type plating layer 31 and the p-type plating layer 37. Furthermore, the active layers 35 can have a multiple quantum well (MQW) structure. With a view to improving the light emission power by reducing crystal defects, the semiconductor laminate 30 more preferably has a multiple quantum well structure. The multiple quantum well structure can be formed by alternating and repeated provision of well layers 35W and barrier layers 35B.The layers at both ends of the active layers 35 in the thickness direction (the upper and lower layers) are preferably barrier layers. Accordingly, if the number of repetitions of the well layers 35W and the barrier layers 35B is n, these layers are referred to as a "multi-quantum well structure of n.5 pairs". Furthermore, the well layers 35W can be formed from InGaAsP, and the barrier layers 35B are preferably formed from InGaAsP having a larger band gap than that of the well layers 35W. The provision of such a semiconductor laminate 30, as described above, enables the light-emitting semiconductor device 100 to emit light with a wavelength in a desired near-infrared range. For example, an emission peak wavelength of 1000 nm to 1650 nm can be achieved by varying the composition of the InGaAsP-based III-V compound.In the case of an MQW structure, an emission peak wavelength of 1000 nm to 1900 nm can be achieved by applying stress to the trough layers by adjusting the composition difference between the trough layers and the barrier layers, in addition to varying the composition of the III-V compound based on InGaAsP. It should be noted that the n-type plating layer 31 is preferably an n-type InP plating layer and the p-type plating layer 37 is preferably a p-type InP plating layer. Furthermore, if the chemical composition of the trough layers 35W is expressed as InxwGa1-xwAsymP1-yw, the conditions 0.5 ≤ xw ≤ 1 and 0.5 ≤ yw ≤ 1 can be met, and 0.6 ≤ xw ≤ 0.8 and 0.3 ≤ yw ≤ 1 are preferably met. Moreover, if the chemical composition of the barrier layers 35B is expressed as InxbGa1-xbAsymP1-yw, the conditions 0.5 ≤ xb ≤ 1 and 0 ≤ yb ≤ 0.5 can be met, and 0.8 ≤ xb ≤ 1 and 0 ≤ yb ≤ 0.2 are preferably met. Furthermore, the total thickness of the semiconductor laminate 30 can be, for example, 2 µm to 8 µm, but is not limited to this. Similarly, the thickness of the n-type plating layer 31 can be, for example, 1 µm to 5 µm, but is not limited to this. Furthermore, the thicknesses of the active layers 35 can be, for example, 100 nm to 1000 nm, but are not limited to this. Similarly, the thickness of the p-type plating layer 37 can be, for example, 0.8 µm to 3 µm, but is not limited to this. If the active layers 35 have a quantum well structure, the thickness of the well layers 35W can be 3 nm to 15 nm and the thickness of the barrier layers 35B can be 5 nm to 15 nm. The number of pairs of both layers can be 3 to 50. Furthermore, the semiconductor laminate 30 preferably has a p-type cap layer 39, made of InGaAsP containing at least In and P, on the p-type plating layer 37. The lattice mismatch can be reduced by providing the p-type cap layer 39. The thickness of the cap layer 39 can be, for example, 50 nm to 200 nm, but is not limited thereto. In the following embodiment, for convenience, a description is given assuming that the outermost surface layer of the semiconductor laminate 30 is the p-type cap layer 39; however, since the p-type cap layer 39 is an optional component, the outermost surface layer of the semiconductor laminate 30 can, for example, be the p-type plating layer 37. Although not shown, the semiconductor laminate 30 preferably has an i-type InP spacer layer between the n-type plating layer 31 and the active layers 35, and between the active layers 35 and the p-type plating layer 37. The provision of the i-type InP spacer layers can impede dopant diffusion. The thickness of the i-type InP spacer layers can be, for example, 50 nm to 400 nm, but is not limited thereto. The n-type InGaAs contact layer 20 formed in the first step and the layers in the semiconductor laminate 30 formed in the second step can be formed by epitaxial growth, for example, by a known thin-film deposition technique such as metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or sputtering. For example, trimethylindium (TMIn) can be used as the In source, trimethylgallium (TMGa) as the Ga source, arsine (AsH3) as the As source, and phosphine (PH3) as the P source at a predetermined mixing ratio. These source gases can be subjected to gas-phase epitaxy using a carrier gas to form an InGaAsP layer of a desired thickness by adjusting the growth time. It should be noted that other InGaAsP layers that are allowed to grow epitaxially can be formed using a corresponding method.If the layers are p-type or n-type doped, a dopant source gas can also be used if necessary. <Dritter Schritt> In a third step following the second step, a reflective metal layer 60A is formed on the semiconductor laminate 30 (step 40 in Fig. 3). It is also preferred that an intermediate layer 40 is formed prior to the third step by carrying out an intermediate layer formation step, which will be described in detail later, and that the reflective metal layer 60A is formed on the intermediate layer 40. The reflective metal layer 60A preferably contains gold as a major component. In particular, gold is present in an amount of preferably more than 50% by weight, more preferably 80% by weight or more in the composition of the reflective metal layer 60A.The reflective metal layer 60A can comprise a plurality of metal layers; however, if it comprises a metal layer made of Au (hereinafter referred to as the “Au metal layer”), the thickness of the Au metal layer is preferably more than 50% of the total thickness of the reflective metal layer 60A. Other than Au, Al, Pt, Ti, Ag, and the like can be used as metals forming the reflective metal layer 60A (in other words, reflective metals). The reflective metal forming the reflective metal layer 60A serves as the source of the reflective metal contained in a metal layer 60 in the light-emitting semiconductor device 100, which is manufactured by an embodiment of the manufacturing process of the present disclosure.For example, the reflective metal layer 60A can be formed as a single layer made entirely of Au; alternatively, the reflective metal layer 60A can comprise two or more Au metal layers. To ensure bonding with a metal compound layer 60B in the subsequent fourth step, the outermost surface layer of the reflective metal layer 60A (the surface facing the semiconductor laminate 30) is preferably an Au metal layer. For example, metal layers of Al, Au, Pt, and Au can be formed in that order on the semiconductor laminate 30 (optionally with an intermediate layer 40) to obtain the reflective metal layer 60A.The thickness of an Au metal layer in the reflective metal layer 60A can, for example, be 400 nm to 2000 nm, and the thickness of any metal layer made of a metal other than Au can, for example, be 5 nm to 200 nm. The reflective metal layer 60A can be deposited on the semiconductor laminate 30 or on the intermediate layer 40 by any of the typical techniques, including vapor deposition. <Vierter Schritt> In a fourth step following the third step, a conductive support substrate 80 with a surface provided with a metal compound layer 60B is bonded to the reflective metal layer 60A, with the metal compound layer 60B positioned between them (step 50 in Fig. 3). The metal compound layer 60 can be formed on a surface of the conductive support substrate 80 by sputtering, vapor deposition, or the like. The metal compound layer 60B and the reflective metal layer 60A are arranged so that they face each other, whereupon the layers are joined by thermocompression bonding at a temperature of approximately 250 °C to 500 °C. By bonding the reflective metal layer 60A and the metal compound layer 60B, a metal layer 60 containing the reflective metal is obtained. The metal compound layer 60B, which is bonded to the reflective metal layer 60A, can be formed from metals such as Ti, Pt, and Au, or from metals forming a eutectic alloy with gold (e.g., Sn), and it is preferably formed from a stack of these materials. For example, a stack obtained by stacking Ti with a thickness of 400 nm to 800 nm, Pt with a thickness of 5 nm to 20 nm, and Au with a thickness of 700 nm to 1200 nm in that order on the surface of the conductive support substrate 80 can be used as the metal compound layer 60B.It should be noted that, to facilitate the bonding between the reflective metal layer 60A and the metal compound layer 60B, an Au metal layer is provided as the outermost surface layer of the metal compound layer 60B, and Au is also provided as a metal layer of the reflective compound layer 60 on the side of the metal compound layer 60B to carry out a bonding between Au and Au by an Au-Au diffusion bonding. The conductive support substrate 80 is preferably a conductive Si substrate. A Si substrate is advantageous in that it is resistant to breakage and can be thinned, since Si substrates have a greater hardness than InP substrates. Alternatively, a conductive GaAs or Ge substrate can also be used as the conductive support substrate 80. <Fünfter Schritt> In a fifth step following the fourth step, the n-type InP growth substrate 10 is removed (step 60 in Fig. 4). The n-type InP growth substrate 10 can be removed, for example, by wet etching using dilute hydrochloric acid, and the n-type InGaAs layer 20 can be used as an etch stop layer. <Sechster Schritt > In a sixth step, the n-type InGaAs contact layer 20 is partially removed, exposing the semiconductor laminate 30, while an n-side electrode 93 is formed on an n-side electrode-forming region 20A of the n-type InGaAs contact layer 20 (step 70A or step 70B and step 80 in Fig. 4). After the n-side electrode 93 has been provided on the n-side electrode-forming region 20A, the n-type contact layer 20 can be partially removed (step 70A in Fig. 4). Alternatively, the n-type contact layer 20, which is distinct from the n-side electrode-forming region 20A, can be removed beforehand, and then the n-side electrode 93 can be formed (step 70B in Fig. 4). The n-type InGaAs contact layer 20 can be removed by wet etching in a sulfuric acid-hydrogen peroxide mixture. After forming the n-side electrode 93 on the n-side electrode-forming region 20A of the n-type InGaAs contact layer 20 (step 80 in Fig. 4), the n-side electrode 93 can comprise a wiring section 93a and a contact section 93b. Furthermore, the n-side electrode 93, in particular the wiring section 93a, preferably contains gold and gold, or more preferably contains titanium, platinum, and gold. The n-side electrode 93 containing these metal elements ensures an ohmic contact with the n-type InGaAs contact layer 20A. Furthermore, after forming the wiring section 93a, a heat treatment is preferably carried out to form an ohmic contact between the contact layer and the electrode. It is also preferred that the contact section 93b is formed after the heat treatment. In the manufacturing process according to the present embodiment, a backside electrode 91 can be formed on the back surface of the conductive support substrate 80 (see Fig. 5). The backside electrode 91 and the n-side electrode 93 can be formed by a known technique; for example, by sputtering, electron beam vapor deposition, resistance heating, and the like. Furthermore, a grinding step to grind the conductive support substrate 80 can be performed before forming the backside electrode 91. Grinding the conductive support substrate 80 can be achieved by a known mechanical grinding process and can be carried out in conjunction with etching. The light-emitting semiconductor device 100 thus obtained is shown in Fig. 5. The light-emitting semiconductor device 100 according to the present embodiment, as shown in Fig. 5, can be produced by the first to sixth steps mentioned above. Next, the interlayer formation step and the surface roughening step, which are preferably additionally carried out in the method for producing a light-emitting semiconductor device 100 according to the present embodiment, are described. <zwischenschichtschritt> After the second step and before the third step, the intermediate layer formation step is preferably carried out to form an intermediate layer 40, which is described in detail below. In this step, a p-type contact layer 41, made of a III-V compound semiconductor, is first formed on the semiconductor laminate 30 (step 30 in Fig. 1). For example, in a preferred mode of step 30 in Fig. 1, the p-type contact layer 41 is formed on the p-type cap layer 39. The p-type contact layer 41 is a layer that is to be in contact with an ohmic metal section 43 to be formed on it and is to be arranged between the ohmic metal section 43 and the semiconductor laminate 30. The p-type contact layer 41 has a composition that exhibits a lower contact resistance with the ohmic metal section 43 than with the semiconductor laminate 30.For example, the p-type contact layer 41 can be a p-type InGaAs layer. The thickness of the contact layer 41 can be, for example, 50 nm to 200 nm, but is not limited to this. Subsequently, an ohmic metal section 43 is formed on portions of the p-type contact layer 41, leaving an exposed area E1 on a surface of the p-type contact layer 41 (step 32 in Fig. 2). The ohmic metal section 43 can be formed into islands distributed in a predetermined structure. If the p-type contact layer 41 is a p-type InGaAs, for example, Au, AuZn, AuBe, AuTi, and the like can be used as the ohmic metal section 43, and a structure in which these materials are stacked is also preferably used as the ohmic metal section 43. For example, Au / AuZn / Au can be used as the ohmic metal section 43. The thickness (or the total thickness) of the ohmic metal section 43 can be, for example, 300 nm to 1300 nm, preferably 350 nm to 800 nm, but is not limited thereto. For example, the ohmic metal section 43, which is formed as islands distributed in a predetermined structure, can be formed by forming a photoresist structure on the surface of the p-type contact layer 41, vapor-phase deposition of the ohmic metal section 43, and removal of the photoresist structure by peeling. Alternatively, the ohmic metal section 43 can be formed by forming a predetermined metal layer on the entire surface of the contact layer 41, forming a mask on the metal layer, and performing, for example, etching. In each case, as shown in step 32 of Fig. 2, the ohmic metal section 43 is formed on portions of the p-type contact layer 41, and the surface of the p-type contact layer 41 that is not in contact with the ohmic metal section 43, i.e., the exposed area E1, can be formed. It should be noted that the shape of the Ohm's metal section 43 may in some cases be trapezoidal in a cross-sectional view, as shown only schematically in step 32 in Fig. 2. The Ohm's metal section 43 may be rectangular or have rounded corners in a cross-sectional view. After step 32, the p-type contact layer 41 of the exposed area E1 is removed such that a surface of the semiconductor laminate 30 is exposed, forming a p-type contact section 45 composed of the ohmic metal section 43 and the contact layer 41a, providing an exposed surface E2 of the semiconductor laminate 30 (step 34 in Fig. 2). In particular, the p-type contact layer 41 is etched in an area distinct from the areas of the ohmic metal section 43 formed in the preceding step 32, exposing a surface of the p-type cap layer 39, which is the outermost surface layer of the semiconductor laminate 30, thus yielding the contact layer 41a after etching.For example, a photoresist mask can be formed on and around the (approximately 2 µm to 5 µm from) ohmic metal section 43, and the exposed area E1 of the p-type contact layer 41 can be wet-etched with a tartaric acid-hydrogen peroxide mixture. Alternatively, wet etching can be performed using an inorganic acid-hydrogen peroxide mixture, an organic acid-hydrogen peroxide mixture, or the like. Furthermore, in the case where a mask is formed on the metal layer and etching to form the ohmic metal section 43 is carried out in step 32, etching can be performed continuously as step 34 alongside the etching of the p-type contact layer 41. It should be noted that the thickness of the p-type contact section 45 corresponds to the total thickness of the p-type contact layer 41 (the p-type contact layer 41a after etching) and the Ohm's metal section 43 and can be 350 nm to 1500 nm, more preferably 400 nm to 1000 nm. Then a dielectric layer 47 is formed on at least a part of the exposed surface E2 of the semiconductor laminate 30 (step 36 in Fig. 2). Such a dielectric layer 47 can be formed, for example, as follows. First, a dielectric layer is deposited over the entire surface of the semiconductor laminate 30 such that it covers both the semiconductor laminate 30 and the p-type contact section 45. A known technique, such as plasma CVD or sputtering, can be used for film deposition. If a dielectric is deposited over the p-type contact section 45 after film deposition, a mask can be formed as desired, and the dielectric on the contact section can be removed by etching or the like. For example, the dielectric on the contact section can be wet-etched using buffered hydrofluoric acid (BHF) or the like. In this way, the intermediate layer 40 can be formed by steps 30 to 36. As shown in Fig. 6, and with reference to step 34 in Fig. 2, it is also preferred that the dielectric layer 47 is formed on a portion of the exposed surface E2 of the semiconductor laminate 30, leaving an exposed section E3 around the p-type contact section 45, thus providing gaps between the dielectric layer 47 and the p-type contact section 45. The dielectric layer 47 and the exposed section E3 described above can be formed, for example, as follows. First, a dielectric layer is deposited over the entire surface of the semiconductor laminate 30, and a window structure completely surrounding the contact section is formed on the surface of the deposited dielectric layer using a photoresist above the p-type contact section 45.The dielectric surrounding the contact section is removed by etching using the photoresist structure employed, thereby providing the exposed section E3 around the p-type contact section 40. In this case, the width W of the exposed section E3 can be 0.5 µm or more and 5 µm or less. It should be noted that the relationship between the thickness H1 of the dielectric layer 47 and the thickness H2 of the p-type contact section 45, which is formed in the dielectric layer formation step, is not specifically restricted; however, as shown in Fig. 6, if the thickness of the dielectric layer 47 is expressed as H1 and the thickness of the contact section is expressed as H2, H1 ≥ H2 can be satisfied, and preferably H1 > H2. This can further ensure the bonding of the reflective metal layer 60A with the metal compound layer 60B. It should be noted that when the exposed section E3 is provided and H1 > H2 is satisfied, as shown in Fig.Figure 6 shows that the formation of the reflective metal layer 60A, so that the gaps are filled, can cause the creation of cavities in parts between the metal compound layer 60B and the reflective metal layer 60A (areas corresponding to the p-type contact section 45 and the gaps). Furthermore, the dielectric layer 47 can utilize SiO2, SiN, ITO, AlN, and the like, and the dielectric layer 47 is particularly preferably made of SiO2. This is due to the fact that SiO2 can be processed by etching using BHF or the like. Moreover, a material is preferably used for the dielectric layer 47a that is transparent to light emitted by the semiconductor laminate 30. <Oberflächenaufrauschritt> When etching to remove portions of the n-type InGaAs contact layer 20, it is also preferred to perform surface roughening with the surface of the semiconductor laminate 30 on the side of the n-type InP growth substrate (the surface of the n-type plating layer 31 in step 80 in Fig. 4). A preferred mode of the surface roughening step is described with reference to Figs. 7, 8 to 9. Although an n-side electrode 93 is not shown in Figs. 7, 8 to 9, the surface roughening step can be performed analogously even in cases where an n-side electrode 93 has been formed. As shown in steps 71 to 74 in Fig. 7, a first surface roughening step is performed in which portions of the n-type InGaAs contact layer 20 are etched to form a structured mask section 20B. Top views in steps 72 and 74 are shown in Fig. 8. Furthermore, after the first surface roughening step, as shown in steps 74 to 76 in Fig. 9, a second surface roughening step is performed in which the surface of the n-type plating layer 31 is etched using the structured mask section 20B. The details of the surface roughening step are described below. <<Erster Oberflächenaufrauschritt> > Step 71 in Fig. 7 corresponds to the state after the fifth step, i.e., the state after removal of the n-type InP growth substrate 10. In a first surface roughening step, a photoresist PR with a desired structure is formed on the n-type InGaAs contact layer 20 (step 72 in Fig. 7). For structuring, a photoresist can be applied and exposure can be carried out. An example of a schematic top view after structuring in step 72 is shown in Fig. 8. The structure of the photoresist PR can be transferred to the n-type InGaAs layer 20 by wet-setting using the photoresist PR as a mask (step 73 in Fig. 7). The photoresist PR is then optionally washed away and removed (step 74 in Fig. 7). A schematic top view of step 74 is shown in Fig. 8. It should be noted that all structures are formed with the photoresist PR.Figure 8 shows an example where the centers of the depressions are arranged two-dimensionally in a square grid arrangement in the region that differs from the n-side electrode-forming region 20A as mask section 20B, without this being a limiting factor. It should be noted that the two-dimensionally arranged structure is <011> -Direction is preferably symmetrical. <<Zweiter Oberflächenaufrauschritt> > After the first surface roughening step, in a second surface roughening step the surface of the n-type InP plating layer 31 is etched using the mask section 20B of the n-type InGaAs layer 20, which was structured in the first surface roughening step, as a mask. An etching solution consisting of a hydrochloric acid-acetic acid mixture or the like is preferably used for etching the n-type plating layer 31. It should be noted that the mask section 20B of the n-type InGaAs layer 20, which is used as a mask, can be removed by wet etching with an etching solution consisting of a sulfuric acid-hydrogen peroxide mixture (step 76 in Fig. 9). The surface roughening step described above is particularly suitable for use when the n-type plating layer is made of n-type InP. This is because InP is strongly anisotropic and the etching rates of InP vary significantly across different crystal planes. Consequently, the etching process differs between plane section II and plane section II-II (see Fig. 7), as shown in each step in Fig. 9. In particular, V-shaped depressions 31C are formed on plane section II, whereas, due to the difference in etching rates, the etching also occurs under the mask on plane section II-II.In cases where the n-type plating layer 31 is made of n-type InP, if the InP were pre-exposed and a typical photoresist were formed on the surface of the InP as a mask, the photoresist would detach during etching due to insufficient adhesion. Consequently, surface roughening of the n-type plating layer 31 by wet etching can be difficult. In contrast, the surface roughening step described above ensures surface roughening of the n-type plating layer 31. (Light-emitting semiconductor device) Next, the light-emitting semiconductor device 100 described above, which has been fabricated by at least the first to seventh steps, will be described. As shown in the Fig.As shown in Figure 5, the light-emitting semiconductor device 100 comprises a conductive support substrate 80, a metal layer 60 containing a reflective metal provided on the conductive support substrate 80, a semiconductor laminate 30 formed from a stack of a plurality of III-V compound semiconductor layers based on InGaAsP, containing at least In and P, provided on the metal layer 60, an n-type InGaAs contact layer 20A provided on the semiconductor laminate 30, and an n-side electrode 93 provided on the n-type InGaAs contact layer 20A, wherein the central emission wavelength of light emitted by the semiconductor laminate 30 is 1000 nm to 2200 nm, and wherein the n-type InGaAs contact layer has an In composition ratio of 0.54 or more. 0.60 or less. The technical significance of the n-type InGaAs contact layer 20A, used as an n-type contact layer in the light-emitting semiconductor device 100, is described. When a junction-type light-emitting semiconductor device is fabricated using an n-type InP growth substrate, an n-type semiconductor layer in a semiconductor laminate could be used as an n-type contact layer. Consequently, an ohmic contact could be formed between the n-side electrode and the n-type semiconductor layer. Referring to the reference numerals in Fig. 5, even in cases where an n-side electrode 93 is provided directly on the n-type plating layer 31 without an n-type InGaAs contact layer arranged between the n-side electrode 93 and the n-type plating layer 31, an ohmic contact would be formed between them.However, in the compound-type light-emitting semiconductor device thus fabricated, we experimentally found that both the light output power and the forward voltage decreased over time. In contrast, it was experimentally found that the deterioration of the light output power and the forward voltage over time was suppressed by providing an n-type InGaAs contact layer 20 according to the present embodiment. It is assumed that the reason why deterioration over time can be suppressed in this way is that n-type InGaAs prevents diffusion of the metal in the n-side electrode into the semiconductor layer, compared to a III-V group compound semiconductor layer based on InGaAsP, which contains at least In and P. As described above, the in-composition ratio z of the n-type InGaAs contact layer 20 is 0.54 or more and 0.60 or less. Furthermore, the n-side electrode 93 preferably contains one of Au and Ge, and Ti, Pt, and Au, as also described above. Furthermore, the semiconductor laminate 30 preferably comprises a p-type plating layer 37, active layers 35, and an n-type plating layer 31 in that order on the side of the metal layer 60. The light-emitting area of ​​the n-type plating layer 31 is also preferably roughened. As described above in one embodiment of the manufacturing process, the light-emitting semiconductor device 100 may include additional components. For example, as shown in Fig. 5, a light-emitting semiconductor device 100 provided with a backside electrode 91 and a light-emitting semiconductor device 100 with an intermediate layer 40 are also preferred embodiments.The intermediate layer 40 is formed in one embodiment of the manufacturing process as described above and has a contact section 45 and a dielectric layer 47, which are positioned parallel to each other between the metal layer 60 and the semiconductor laminate 30. By providing the light-emitting semiconductor device 100 with the intermediate layer 40, a distribution of current within the planes of the active layers 35 is promoted, and the transmission of light to the reflective metal layer 60A is also enabled. EXAMPLES (Example 1) The present disclosure is described in more detail below by means of examples. However, this disclosure is not limited to the following examples. Reference numerals are used in Figures 1, 2, 3, 4 to 5. A light-emitting semiconductor device according to Example 1 was manufactured in the following manner. First, on the (100) level of an n-type InP growth substrate 10, an n-type In0.57Ga0.43As contact layer 20, an n-type InP plating layer 31 (thickness: 2 µm), an i-type InP spacer layer (thickness: 300 nm), active layers 35 with a quantum well structure with an emission wavelength of 1300 nm (total 138 nm), an i-type InP spacer layer (thickness: 300 nm), a p-type InP plating layer 32 (thickness: 1.2 µm), a p-type In0.8Ga0.20As0.5P0.5 cap layer 39 (thickness: 50 nm) and a p-type In0.57Ga0.43As contact layer 41 (thickness: 130 nm) was formed sequentially by MOCVD. During the formation of the active layers 35 with the quantum well structure, an InP junction layer (thickness: 8 nm) was first formed, and In0.73Ga0.27As0.5P0.5 junction layers (thickness: 5 nm) and InP junction layers (thickness: 8 nm) were then alternately and repeatedly stacked, forming a quantum well structure with 10.5 pairs of layers. On the p-type In0.57Ga0.43As contact layer 41, an ohmic p-type electrode section 43 (Au / AuZn / Au, total thickness: 530 nm) was formed in islands distributed as shown in Fig. 10A. The plane section III-III of Fig. 10A corresponds to the schematic cross-sectional view of step 32 in Fig. 2 (although no i-type InP spacer layer is shown). In forming this structure, a photoresist structure was created, and then an ohmic electrode was formed by vapor deposition, after which the photoresist structure was removed. When the semiconductor layer of the wafer was examined in this state in a top view under a light microscope, the contact area fraction of the ohmic p-type electrode section 43 was 4.5% of the semiconductor layer. It should be noted that the external size of the object shown in Fig. 10A was 380 µm square. Next, a photoresist mask was formed on and around the Ohm's p-type electrode section 43, and the p-type In0.57Ga0.43As contact layer 41 was removed, except for areas where the Ohm's electrode section was formed, by wet deposition using a tartaric acid-hydrogen peroxide mixture, resulting in a p-type In0.57Ga0.43As contact layer 41a. Subsequently, a dielectric layer 47 (thickness: 700 nm) made of SiO2 was formed on the entire surface of the p-type In0.80Ga0.20As0.50P0.50 cap layer 39 by plasma CVD.A window structure with a shape that was provided with additional 3 µm extensions in each of the width and length directions in an area above the Ohmic p-type electrode section 43 was formed using a photoresist and the dielectric layer 47 on and around the Ohmic p-type electrode section 43 was removed by wet plating using BHF, so that the p-type In0.80Ga0.20As0.50P0.50 cap layer 39 was exposed. The height (700 nm) of the dielectric layer 47 on the p-type In0.80Ga0.20As0.50P0.50 cap layer 39 was 40 nm greater than the height (660 nm) of the p-type contact section 45, which was composed of the p-type contact layer 41a (thickness: 130 nm) and the Ohmic p-type electrode section 43 (thickness: 530 nm). When the semiconductor layer of the wafer was examined in this state from a top view under a light microscope, the contact area fraction of the dielectric layer 47 (SiO2) was 90%. Next, a reflective metal layer (Al / Au / Pt / Au) was formed over the entire surface area of ​​the p-type In0.80Ga0.20As0.50P0.50 cap layer 39 by vapor deposition. The thicknesses of the metal layers in the reflective metal layer 60A were 10 nm, 650 nm, 100 nm, and 900 nm, in that order. On the other hand, a metal compound layer 60B (Ti / Pt / Au) was formed on a conductive Si substrate 80, which serves as a support substrate (thickness: 300 µm). The thicknesses of the metal layers in the metal compound layer 60B were 650 nm, 10 nm and 900 nm in that order. The reflective metal layer 60A and the metal compound layer 60B were arranged opposite each other and subjected to thermocompression bonding at 300 °C, resulting in an Au-Au bond. The n-type InP growth substrate 10 was then removed by wet etching with dilute hydrochloric acid, exposing the entire surface of the n-type InGaAs contact layer 20. Next, an n-side electrode (Au (thickness: 10 nm) / Ge (thickness: 33 nm) / Au (thickness: 57 nm) / Ni (thickness: 34 nm) / Au (thickness: 800 nm)) was formed on the n-type InGaAs contact layer 20 as a wiring section 93a of an n-side electrode by photoresist structuring, vapor deposition of the n-side electrode, and removal of the photoresist structure, as shown in Fig. 10B. Subsequently, an ohmic contact between the n-type InGaAs contact layer 20 and the wiring section 93a of the n-side electrode was formed by heat treatment (at this time, an ohmic contact was also formed between the p-type InGaAs contact layer 41a and the ohmic p-type electrode assembly 43). Furthermore, a contact point section 93b (Ti (thickness: 150 nm) / Pt (thickness: 100 nm) / Au (thickness: 2500 nm)) was formed on the central section of the n-side electrode, so that the n-side electrode was obtained with a structure as shown in Fig. 10B. Subsequently, the semiconductor layers between devices (width: 60 µm) were removed by mesa etching, creating separation lines. Subsequently, the area of ​​the n-type In0.57Ga0.43As contact layer 20, which differed from the n-side electrode-forming area 20A, was removed by wet etching with a sulfuric acid-hydrogen peroxide mixture, thereby exposing the n-type InP plating layer 31, except for the n-side electrode-forming area 20A. Plane section IV-IV of Fig. 10B corresponds to step 80 in Fig. 4. The external dimensions of the device shown in Fig. 10B were, as in Fig. 10A, 380 µm square. Then, after the silicon substrate was thinned to a thickness of 87 µm by grinding, a backside electrode (Ti (thickness: 10 nm) / Pt (thickness: 50 nm) / Au (thickness: 200 nm)) was formed on the back surface of the silicon substrate, and chip singulation was performed by separation. It should be noted that the chip size was 350 µm × 350 µm. (Example 2) A light-emitting semiconductor device according to Example 2 was manufactured in the same manner as in Example 1, except that the wiring section 93a of the n-side electrode 93 was made of Ti (30 nm) / Pt (50 nm) / Au (450 nm). (Comparative example 1) The same procedures as in Example 1 were carried out until the reflective metal layer 60A and the metal compound layer 60B were joined and the n-type InP growth substrate 10 was removed by wet etching using a dilute hydrochloric acid solution. Thereafter, the n-type In0.57Ga0.43As contact layer was completely removed by wet etching with a sulfuric acid-hydrogen peroxide mixture, thus exposing the n-type InP plating layer 31. Subsequently, an n-side electrode 93 was formed on the n-type InP plating layer 31 in the same manner as in Example 1, and mesa etching, grinding of the Si substrate, provision of a backside electrode on the back surface of the Si substrate, and chip singulation were performed in the same manner as in Example 1, so that a light-emitting semiconductor device according to Comparative Example 1 was fabricated.The final product of the light-emitting semiconductor device according to Comparative Example 1 differed from Example 1 in that it lacked an n-type InGaAs contact layer 20A. <Bewertung 1: Bewertung von Emissionseigenschaften> For each of the light-emitting semiconductor devices in Examples 1 and 2 and Comparison Example 1, the forward voltage Vf and the light-emitting power Po were measured using an integrating sphere when a current of 20 mA was supplied by a constant-current voltage supply. Measurements were performed on 10 samples of each device, and the mean values ​​were calculated. The results are given in Table 1. The emission peak wavelengths of Example 1 and Comparison Example 1 were measured using an optical fiber spectrometer and were both in the range between 1290 nm and 1310 nm. <Bewertung 2: Bewertung der Abweichungen von Emissionseigenschaften im Zeitverlauf> Each of the light-emitting semiconductor devices according to Examples 1 and 2 and Comparative Example 1 was illuminated by applying a current for 100 hours under the same conditions as in Evaluation 1, and the forward voltage Vf and the luminous efficacy Po were measured after 1000 hours. According to Evaluation 1, measurements were performed with 10 samples each of Examples 1 and 2 and Comparative Example 1, and the mean was calculated from the results. The results are given in Table 1. See example 1n-type InP plating layer AgGe base 2.540.8690.9531.0280.075 Example: 1n-type InGaAs contact layer AgGe base 2,580,9090,9420,9420,000 Ex. 2n-type InGaAs contact layerTiPtAu base2,660,9360,9530,952-0.001 Based on the above results, it was confirmed that the light output power retention rate Po was low and the forward voltage Vf was significantly increased due to the long-term current supply in Example 1, because the n-type InP plating layer 31 was in contact with the n-side electrode 93. In contrast, in Example 1, it was confirmed that a decrease in the light output power retention rate Po after 1000 hours of current supply and an increase in Vf were suppressed because the n-type InGaAs contact layer 20 was in contact with the n-side electrode 93. Furthermore, in Example 2, which differed from Example 1 only with respect to the electrode materials of the n-side electrode, it was confirmed that a decrease in the light output power retention rate Po after 1000 hours of current supply and an increase in Vf were suppressed, as in Example 1.It should be noted that it was also confirmed that the absorption of light by the n-type InGaAs contact layer 20 in the emission wavelengths of the light-emitting semiconductor device 100 had no effect on the light output power, since the n-type InGaAs contact layer 20 was only provided as a contact layer directly below the n-side electrode. COMMERCIAL APPLICABILITY According to the present disclosure, a light-emitting semiconductor device of the compound type with a central emission wavelength of 1000 nm to 2200 nm, exhibiting excellent reliability with small deviations in light emission power and forward voltage over time, and a method for its fabrication can be provided. REFERENCE MARK LIST 10 n-type InP growth substrate 20 n-type InGaAs contact layer 20A n-side electrode forming area; n-type InGaAs contact layer 20B Structured mask section 30 Semiconductor laminate 31 n-type plating layer 31C Depression 35 Active layers 35B Barrier layer 35W Well layer 37 p-type plating layer 39 p-type cap layer 40 Intermediate layer 41 (41a) p-type contact layer 43 Ohmic metal section 45 p-type contact section 47 Dielectric layer 60 Metal layer 60A Reflective metal layer 60B Metal compound layer 80 Conductive support substrate 91 Backside electrode 93 n-side electrode 93a Wiring section 93b Contact section 100 Light-emitting semiconductor device E1 Exposed area E2 Exposed surface E3 Exposed section H1 Dielectric layer thickness H2 p-type contact section thickness PR Photoresist< / zwischenschichtschritt>

Claims

Light-emitting semiconductor device (100) comprising: a conductive support substrate (80); a metal layer (60) comprising a reflective metal (60A) provided on the conductive support substrate (80); a semiconductor laminate (30) provided on the metal layer (60), wherein the semiconductor laminate (30) is a stack of a plurality of III-V group compound semiconductor layers (31, 35, 35B, 35W, 37, 39) based on InGaAsP, containing at least In and P; an n-type InGaAs contact layer (20A) provided on the semiconductor laminate (30); and an n-side electrode (93) provided on the n-type InGaAs contact layer (20A), wherein a central emission wavelength of light emitted by the semiconductor laminate (30) is 1000 nm to 2200 nm, and wherein the n-type InGaAs contact layer (20A) has an In composition ratio of 0.54 or more and 0.60 or less. Light-emitting semiconductor device (100) according to claim 1, wherein the n-side electrode (93) contains one of Au and Ge, and Ti, Pt and Au. Light-emitting semiconductor device (100) according to claim 1 or 2, wherein the semiconductor laminate (30) comprises a p-type plating layer (37), active layers (35, 35B, 35W) and an n-type plating layer (31) in that order from one side of the metal layer (60). Method for fabricating a light-emitting semiconductor device (100), comprising: a first step (step 10) of forming an n-type InGaAs contact layer (20) comprising an n-side electrode-forming region (20A) on an n-type InP growth substrate (10); a second step (step 20) of forming a semiconductor laminate (30) by stacking a plurality of III-V group compound semiconductor layers (31, 35, 35B, 35W, 37, 39) based on InGaAsP, comprising at least In and P, on the n-type InGaAs contact layer (20); a third step (step 40) of forming a reflective metal layer (60A) on the semiconductor laminate (30); a fourth step (step 50) of bonding a conductive support substrate (80) comprising a surface provided with a metal compound layer (60B) with the reflective metal layer (60A), wherein the metal compound layer (60B) is arranged between them;a fifth step (step 60) of removing the n-type InP growth substrate (10); and a sixth step (step 70A, step 70B, step 80) of partially removing the n-type InGaAs contact layer (20) to provide the semiconductor laminate (30) with an exposed surface, while an n-side electrode (93) is formed on the n-side electrode-forming region (20A) of the n-type InGaAs contact layer (20), wherein a central emission wavelength of light emitted by the semiconductor laminate (30) is 1000 nm to 2200 nm, and wherein an in-composition ratio of the n-type InGaAs contact layer (20) formed in the first step (step 10) is set to 0.54 or more and 0.60 or less. Method for manufacturing a light-emitting semiconductor device (100) according to claim 4, wherein the n-side electrode (93) contains one of Au and Ge, and Ti, Pt and Au. Method for manufacturing a light-emitting semiconductor device (100) according to claim 4 or 5, wherein the semiconductor laminate (30) comprises an n-type plating layer (31), active layers (35, 35B, 35W) and a p-type plating layer (37) in that order from one side of the n-type InGaAs contact layer (20).

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