A / D converter and electronic device

Abstract

A / D converter (10) comprising: a comparator circuit that performs a comparison with a threshold voltage to determine whether an excessive injection of a pixel signal (SVSL) has occurred or not, and a first transistor (TR17) having a control terminal and forming a clamping circuit, the control terminal being configured to receive an input of a result of the comparison, and further comprising: a pair of transistors of a differential pair (TR13, TR15) forming an input current line and a reference current line, and a pair of bias transistors (TR14, TR16) controlling a bias current flowing to the transistors of a differential pair (TR13, TR15), the first transistor (TR17) being arranged either upstream or downstream of the pair of bias transistors (TR14, TR16).

Description

[Technical field]

[0001] The present disclosure relates to an A / D converter and an electronic device. [Background technology]

[0002] In recent years, CMOS (Complementary Metal Oxide Semiconductor) image sensors and other imaging devices, which use semiconductor microfabrication technology, have become widely used, for example in digital cameras and smartphones.

[0003] In these imaging devices, light incident on an object is photoelectrically converted in a photodiode, which is arranged in each pixel as a photoelectric conversion element. A voltage signal corresponding to the amount of electrical charge obtained through such photoelectric conversion is then read via an amplifier transistor and a vertical signal line, subjected to an analog-to-digital (A / D) conversion by an A / D converter with a comparator, and output as imaging data.

[0004] If an image of a high-brightness object is acquired by an imaging device using a CMOS or other imaging device, streaky line noise running in a left-right direction across the acquired image, known as streaking, can be generated due to power supply noise caused by simultaneous inversion in an A / D conversion section. A technology for suppressing the occurrence of streaking is proposed (see, for example, PTL 1). [List of citations][Patent literature]

[0005] [PTL 1] Published Japanese Patent No. 2005-252529 [Summary][Technical Problem]

[0006] Furthermore, in a case where an imaging device utilizing a CMOS or other imaging device acquires an image of a high-brightness object using a sequential A / D converter, that is, in a case where excessive input is applied to pixel signal lines, significantly different currents flow in transistors of differential pairs in a preamplifier section containing an A / D conversion section.

[0007] Consequently, even during the conversion of a single low-order bit, significantly different currents flow to the transistors of differential pairs, and the time of comparison by a comparator changes exponentially with respect to the input signals. As a result, a comparison time difference caused by such input differences could manifest as streaking.

[0008] The present disclosure was created in light of the above circumstances. One objective of the present disclosure is to provide an A / D converter and an electronic device capable of suppressing banding in a case where excessive input is applied to pixel signal lines. [Solution to the problem]

[0009] To solve the above problem, an analog-to-digital converter (ADC) according to the present disclosure includes a comparator circuit and a first transistor. The comparator circuit performs a comparison with a threshold voltage to determine whether an excessive pixel signal has been injected. The first transistor has a control terminal and forms a clamping circuit, the control terminal being configured to receive an input of the comparison result.

[0010] When the clamping circuit is switched on (closed), the first transistor balances currents or voltages flowing between a first and second predetermined position, where the first and second predetermined positions are connected at the time of clamping. This makes it possible to suppress the occurrence of striping. [Advantageous effect of the invention]

[0011] The present disclosure makes it possible to suppress banding by reducing the difference between voltages generated at differential amplifier outputs. It should be noted that the advantageous effects described above are for illustrative purposes only and are not limiting. The present disclosure may provide any advantageous effects described in this document. List of characters [ Fig. 1] Fig. Figure 1 is a block diagram illustrating a configuration example of a solid-state imaging device according to one embodiment. [ Fig. 2] Fig. Figure 2 is a diagram illustrating a configuration example of an embodiment of an A / D converter for which the present technology is used. [ Fig. 3] Fig. Figure 3 is a set of diagrams illustrating a relationship between the voltage of a pixel signal and the voltage of a threshold voltage signal in a case where a 7-bit A / D converter is used. [ Fig. 4] Fig. Figure 4 is a diagram illustrating a detailed configuration of a preamplifier section according to a first embodiment. [ Fig. 5] Fig. Figure 5 is a diagram illustrating a circuit configuration example of a threshold voltage determination circuit. [ Fig. 6] Fig. Figure 6 is a flowchart illustrating a process carried out by the threshold determination formwork (threshold determination route). [ Fig. 7] Fig. Figure 7 is a diagram illustrating a detailed configuration of a preamplifier section according to a second modification of the first embodiment. [ Fig. 8] Fig. Figure 8 is a diagram illustrating a detailed configuration of a preamplifier section according to a third modification of the first embodiment. [ Fig. 9] Fig. Figure 9 is a diagram illustrating a detailed configuration of a preamplifier section according to a second embodiment. [ Fig. 10] Fig. Figure 10 is a diagram illustrating a detailed configuration of a preamplifier section according to a first modification of the second embodiment. [ Fig. 11] Fig. Figure 11 is a diagram illustrating a detailed configuration of a preamplifier section according to a third embodiment. [ Fig. 12] Fig. 12 a diagram illustrating a detailed configuration of a preamplifier section according to a first modification of the third embodiment. [ Fig. 13] Fig. Figure 13 is a diagram illustrating an example of a circuit that sets an initial voltage. [ Fig. 14] Fig. Figure 14 is a block diagram illustrating a schematic configuration of a signal processing section according to a fourth embodiment. [ Fig. 15] Fig. Figure 15 is a block diagram illustrating an example of an indirect distance measurement sensor over a runtime, for which the present technology is used. [ Fig. 16] Fig. Figure 16 is a circuit diagram illustrating a configuration example of a pixel according to an embodiment of the present technology. [Description of embodiments]

[0012] Embodiments of the present disclosure are now described in detail with reference to the accompanying drawings. It should be particularly noted that in the following description of the embodiments, identical elements are designated with the same reference numeral and are not described redundantly. (1) First embodiment [configuration example of a solid-state imaging device]

[0013] Fig. Figure 1 is a block diagram illustrating a configuration example of a solid-state imaging device according to one embodiment.

[0014] The solid-state imaging device 1 comprises a pixel array section 2 , a serial scan circuit 3, a signal processing section 4 , a control section 5 for time control, a column scan circuit 6 and an image processing section 7.

[0015] In the configuration above, the pixel array section contains 2 A multitude of scan lines and a multitude of signal lines. A pixel circuit is located at each intersection between the scan lines and the signal lines, so that a multitude of pixel circuits are arranged in a two-dimensional matrix.

[0016] Under the control of the control section 5 for timing control, the series scan circuit 3 sets any one of the multitude of scan lines into an active state and causes pixel signals to be output by controlling pixel circuits for a series, which pixel circuits the pixel array section. 2 form, according to the scan line that has been put into the active state.

[0017] The signal processing section 4 It contains a variety of A / D converters described later and generates pixel data by performing an A / D conversion or other signal processing on an input pixel signal.

[0018] The control section 5 for time control controls a time at which each of the series scan circuit 3, the signal processing section 4 and column scan circuit 6 is working.

[0019] Under the control of the control section 5 for timing control, the column scan circuit 6 operates synchronously with the operations of the series scan circuit 3 and the signal processing circuit. 4 and sequentially transmits signals that are processed by a signal processor for the respective signal lines in the signal processing section. 4 were subjected to pixel data for image processing section 7.

[0020] The image processing section 7 performs various types of image processing on image data that contain a large number of pieces of pixel data.

[0021] Image processing includes, for example, demosaicing, white balance processing, and similar processes.

[0022] The image data, which has undergone image processing, is then transferred to an external recording device such as an image storage device.

[0023] The preceding description assumes that the image processing section 7 is arranged within the solid-state imaging device 1. However, the image processing section 7 can alternatively be arranged separately outside the solid-state imaging device 1.

[0024] Furthermore, the circuits in the solid-state imaging device 1 can each be arranged on a single semiconductor substrate or can be distributed across a multitude of stacked semiconductor substrates. [Configuration example of an A / D converter]

[0025] Fig. Figure 2 is a diagram illustrating a configuration example of an embodiment of an A / D converter for which the present technology is used.

[0026] As in Fig. As illustrated in point 2, the A / D converter contains 10 a section 11 to generate a local reference voltage, a D / A conversion section 12, a preamplifier section 13 , a comparator section 14 , a logic section 15 for a sequential conversion and a logic section 16 for a rotation.

[0027] A large number of the sections 11 The generation of local reference voltages is located in the signal processing section. 4 arranged. Based on a standard reference signal (standard reference voltage) STref, provided by a 5A reference voltage generation circuit, the sections generate 11 To generate a local reference voltage, a variety of types of local standard reference signals (local standard reference voltages) Sref are used in the A / D converter. 10 They are to be used, and they output them.

[0028] Under the control of the logic section for sequential conversion and the logic section for rotation, which are described later, the D / A conversion section performs 12a digital / analog (D / A) conversion of control data D CNT by outputting a threshold voltage signal Sth, using the multitude of types of local standard reference signals Sref provided by the sections 11 They were generated to create a local reference voltage.

[0029] The preamplifier section 13 amplified by a pixel signal input connector T VSL the pixel array section 2 injected pixel signal S VSL and the threshold voltage signal Sth and outputs differential signals OUTP and OUTN.

[0030] The comparator section 14 compares the differential signals OUTP and OUTN output by the preamplifier section and gives a comparison result D. CMP out of.

[0031] The logic section 15 For a sequential conversion, digital control data D is provided. SAR(e.g., 13 bits) to generate the threshold voltage signal Sth from the comparison result data D CMP out. Furthermore, the logic section stores 15 for a sequential conversion the entered comparison result data D CMP and gives pixel data D VSL from an output port TD OUT based on the stored comparison result data D CMP out. The pixel data D VSL represent a result of an analog-to-digital (A / D) conversion of the pixel signal S VSL .

[0032] The logic section 16 Data D is generated for a rotation ROT based on pseudorandom number data D PN , which are provided by a pseudorandom number generation section 4B located in the signal processing section 5. [Overview of A / D converter operations]

[0033] Now, operations of the A / D converter will be performed. 10 summarized.

[0034] The A / D converter 10 sequentially performs a comparison from the most significant bit to the least significant bit of the pixel data D. VSL through, which represent the result of an A / D conversion to set the values ​​of all bits (to "1" or "0").

[0035] First, the logic section 15 For a sequential conversion, an initial value setting is achieved by setting all bits to a mean voltage (Vrc).

[0036] In parallel with the above operation, the pseudorandom number generation section 4B generates the pseudorandom number data D. PN the logic section 16 ready for rotation.

[0037] The preamplifier section 13 generates the differential signals OUTP and OUTN by calculating a difference between the input pixel signal S VSLand is amplified by a threshold voltage signal Sth, and outputs the generated differential signals OUTP and OUTN to the comparator section. 14 out of.

[0038] The comparator section 14 compares the voltages of the differential signals OUTP and OUTN and outputs the result as the comparison result data D. CMP to the logic section 15 for a sequential conversion.

[0039] The logic section 15 For a sequential conversion, the control data D is generated. SAR and D ROT for the D / A conversion section 12 according to a result of the comparison result data D CMP and stores the comparison result data D CMP .

[0040] The D / A conversion section 12 performs a digital-to-analog (D / A) conversion on the entered control data D CNTusing the multitude of types of local standard reference signals (Sref) provided by the section 11 to generate a local reference voltage, and passes the threshold voltage signal Sth to the preamplifier section. 13 out of.

[0041] Subsequently, all bits from the most significant bit (MSB) to the least significant bit (LSB) are compared sequentially in a similar manner to the above, and the logic section 15 For a sequential conversion, it determines the values ​​of all bits and stores them.

[0042] Once the values ​​of all bits have been determined, the stored data is output from the TD output port. OUT output as A / D conversion result data. [Problem with conventional A / D converters]

[0043] Now, a problem with conventional technologies regarding A / D converters will be described.

[0044] Fig. Figure 3 is a set of diagrams illustrating a relationship between the voltage of the pixel signal and the voltage of the threshold voltage signal in a case where a 7-bit A / D converter is used as an example.

[0045] Regarding the pixel signal S VSL in Fig. The lower side represents a state of low voltage (white side), and the upper side represents a state of high voltage (black side). The horizontal axis represents time.

[0046] Referring to Fig. 3. It is assumed that an xth bit at the time of an A / D conversion is denoted by (x). For example, an input signal at the time of MSB conversion corresponds to (7) and an input signal at the time of LSB conversion corresponds to (1).

[0047] In (a) of Fig. Figure 3 shows a case in which the difference between the voltage of the pixel signal S VSLand the voltage of the threshold voltage signal Sth is large, but lies within an A / D conversion range at the beginning of a comparison. In (b) of Fig. Figure 3 shows a case in which the difference between the voltage of the pixel signal S VSL and the voltage of the threshold voltage signal Sth is small and lies within the A / D conversion range at the beginning of a comparison. In (c) of Fig. Figure 3 shows a case in which the difference between the voltage of the pixel signal S VSL and the voltage of the threshold voltage signal Sth is extremely large (excessive amplitude) and lies beyond the A / D conversion range.

[0048] A sequential A / D converter changes the threshold voltage Sth according to the result of a comparison by a comparator in order to adapt to the pixel signal S. VSL to approximate. In cases where the pixel signal lies within the range ((a) and (b) of Fig. 3), is therefore the difference between the pixel signal S VSL and the threshold voltage Sth is small and not greater than 1 LSB at the time of an LSB conversion (1).

[0049] In the case of the one in (c) of Fig. In the example shown in point 3, the difference between the pixel signal S is... VSL and the threshold voltage Sth is significant and greater than 1 LSB even at the time of an LSB conversion (1). Since the time of a comparison by the comparator changes exponentially with respect to an input signal, a comparison time difference caused by this input difference appears as streaking. [Detailed configuration of a comparator section according to a first embodiment]

[0050] Fig. Figure 4 is a diagram showing a detailed configuration of the preamplifier section. 13 illustrated according to the first embodiment.

[0051] The preamplifier section 13The circuit contains a P-channel MOS transistor TR11, a P-channel MOS transistor TR12, and a constant current supply CC. The P-channel MOS transistor TR11 is configured with one source terminal S connected to a power supply line AVD and one gate terminal G connected to the drain terminal D to form a diode junction. The P-channel MOS transistor TR12 is configured with one source terminal S connected to the power supply AVD and one gate terminal G connected to the gate terminal G of the P-channel MOS transistor TR11, so that the P-channel MOS transistor TR12, in conjunction with the P-channel MOS transistor TR11, acts as a current mirror circuit. The constant current supply CC is connected to the drain terminal D of the P-channel MOS transistor TR11 at one end and to a ground line AVS at the other.

[0052] Furthermore, the preamplifier section contains 13a P-channel MOS transistor TR13, a P-channel MOS transistor TR14, and a first load resistor R1. The P-channel MOS transistor TR13 is configured to receive a pixel signal S VSL A voltage is applied to a gate terminal G of the P-channel MOS transistor TR12, and a source terminal S is connected to a drain terminal D of the P-channel MOS transistor TR13. The P-channel MOS transistor TR14 is configured such that a source terminal S is connected to a drain terminal D of the P-channel MOS transistor TR13, and a bias voltage BIAS is applied to a gate terminal G, causing the P-channel MOS transistor TR14 to operate as a cascode circuit. The first load resistor R1 is connected at one end to a drain terminal D of the P-channel MOS transistor TR14 and at the other end to the ground line AVS.

[0053] Furthermore, the preamplifier section contains 13The circuit consists of a P-channel MOS transistor TR15, a P-channel MOS transistor TR16, and a second load resistor R2. P-channel MOS transistor TR15 is configured such that a threshold voltage signal Sth is applied to a gate terminal G, and a source terminal S is connected to the drain terminal D of P-channel MOS transistor TR12. P-channel MOS transistor TR16 is configured such that a source terminal S is connected to a drain terminal D of P-channel MOS transistor TR15, and a bias voltage BIAS is applied to a gate terminal G, causing P-channel MOS transistor TR16 to operate as a cascode circuit. The second load resistor R2 is connected at one end to a drain terminal D of P-channel MOS transistor TR16 and at the other end to ground (AVS).

[0054] Furthermore, the preamplifier section contains 13 a threshold determination circuit 21An input terminal of the threshold determination circuit 21 is connected to the drain terminal of the P-channel MOS transistor TR14 to receive an input of a first output signal OUTP. Another input terminal of the threshold determination circuit 21 is connected to the drain terminal of the P-channel MOS transistor TR16 to receive an input of a second output signal OUTN. The threshold determination circuit 21 compares the first output signal OUTP and the second output signal OUTN and outputs a determination result signal. S EV out of.

[0055] Furthermore, the preamplifier section contains 13 an N-channel MOS transistor TR17 The N-channel MOS transistor TR17 is configured such that a drain port D is connected to a connection point CP1 between the drain terminal D of the P-channel MOS transistor TR13 and the source terminal of the P-channel MOS transistor TR14, and a source terminal D with a connection point CP2 between the drain terminal D of the P-channel MOS transistor TR15 and the source terminal of the P-channel MOS transistor TR16. The N-channel MOS transistor TR17 functions as a switching element (switch) that creates a short circuit between the connection points CP1 and CP2 forms or sets up when the threshold determination circuit 21 output determination result signal S EV into a gate terminal G of the N-channel MOS transistor TR17 is fed in.

[0056] In the above configuration, the N-channel MOS transistor forms TR17 a clamping circuit. Furthermore, the P-channel MOS transistor TR13, the P-channel MOS transistor TR14, the P-channel MOS transistor TR15, the P-channel MOS transistor TR16, the first load resistor R1 and the second load resistor R2 form a differential amplifier. DA .

[0057] If the pixel signal S VSL within a predetermined A / D conversion range, the difference between the voltage of the pixel signal S VSL and the voltage of the threshold voltage signal Sth at the time of an LSB conversion is small. Therefore, the difference between the first output signal OUTP and the second output signal OUTN, which is generated by the preamplifier section, is small. 13 The amount of money spent will also be small.

[0058] However, if the pixel signal S VSL an excessive input signal beyond the predetermined A / D conversion range and the N-channel MOS transistor TR17 When switched off (put into an open state), the difference between the first output signal OUTP and the second output signal OUTN, which is supplied by the preamplifier section, remains. 13 The output is large, even during an LSB conversion.

[0059] If, in the above case, the N-channel MOS transistor TR17 When switched on (put into a closed state), the currents flowing to the load resistors R1 and R2 can be equalized, so that the first output signal OUTP and the second output signal OUTN are at the same potential.

[0060] Consequently, the time of a conversion can be reduced by the comparator section connected in a subsequent stage. 14 be set up immediately. This makes it possible to reduce the degree of degradation caused by banding resulting from the difference in the speed of a comparator conversion.

[0061] Now, a method for determining an excessive input signal is described.

[0062] Prior to normal A / D conversion processing, the threshold voltage Sth is set to a voltage Vth to determine excessive feed-in, and then the threshold determination circuit is used. 21 used to control the voltage of the pixel signal S VSL with voltage V th to compare in order to determine excessive feed-in. If the result of a comparison indicates that the voltage of the pixel signal S VSL If the voltage Vth used to determine excessive feed-in is lower than the voltage Vth used to determine excessive feed-in (if the voltage Vth considered as the threshold voltage used to determine excessive feed-in is higher), it is determined that the pixel signal S VSL beyond the A / D conversion range (an excessive input signal). Therefore, the N-channel MOS transistor TR17 switched on (put into the closed state).

[0063] However, if the voltage of the pixel signal S VSL If the voltage Vth is higher than the voltage used to determine excessive feed-in (if the voltage Vth, considered as the threshold voltage for determining excessive feed-in, is lower), it is determined that the pixel signal S VSL within the A / D conversion range. Therefore, the N-channel MOS transistor TR17 kept switched off (left in the open state).

[0064] A normal A / D conversion process is then performed. [Circuit configuration example of a comparator section]

[0065] Now, an example circuit configuration of the comparator section will be shown. 14 described.

[0066] Fig. Figure 5 is a diagram showing the circuit configuration example of the comparator circuit. 14 illustrated.

[0067] As in Fig. As illustrated in section 5, this is the comparator section. 14 roughly divided into an amplification section (amplification stage) 14A and a latch section 14B subdivided.

[0068] The reinforcement section 14AIt contains a P-channel MOS transistor TR21, an N-channel MOS transistor TR22, a P-channel MOS transistor TR23, an N-channel MOS transistor TR24, and an N-channel MOS transistor TR25. The P-channel MOS transistor TR21 is configured so that one source terminal S is connected to a digital power supply DVD and one gate terminal G is connected to a clock signal line CLK. The N-channel MOS transistor TR22 is configured so that one drain terminal D is connected to a drain terminal of the P-channel MOS transistor TR21 and one gate terminal G is connected to a positive input terminal INP. The P-channel MOS transistor TR23 is configured so that one source terminal S is connected to the digital power supply DVD and one gate terminal is connected to the clock signal line CLK.The N-channel MOS transistor TR24 is configured such that one drain terminal D is connected to a drain terminal D of the P-channel MOS transistor TR23, and one gate terminal G is connected to a negative input terminal INN. The N-channel MOS transistor TR25 is configured such that one drain terminal D is connected to a source terminal S of the N-channel MOS transistor TR22 and a source terminal S of the N-channel MOS transistor TR24, one gate terminal G is connected to the clock signal line CLK, and one source terminal S is connected to a digital ground DVS.

[0069] Furthermore, the reinforcement section contains 14A Inverters TR31 and TR32, and inverters TR33 and TR34. These inverters work together to achieve signal amplification.

[0070] The Latch section 14BIt contains a P-channel MOS transistor TR41, a P-channel MOS transistor TR42, an N-channel MOS transistor TR43, and an N-channel MOS transistor TR44. The P-channel MOS transistor TR41 is configured so that one source terminal S is connected to the digital power supply DVD and one gate terminal G is connected to the clock signal line CLK. The P-channel MOS transistor TR42 is configured so that one source terminal S is connected to the digital power supply DVD and one drain terminal D is connected to a drain terminal D of the P-channel MOS transistor TR41. The N-channel MOS transistor TR43 is configured such that a drain terminal D is connected to the drain terminal D of the P-channel MOS transistor TR41 and to the drain terminal D of the P-channel MOS transistor TR42, and a gate terminal G is connected to a drain terminal of a P-channel MOS transistor TR31 and to a drain terminal D of an N-channel MOS transistor TR32.The N-channel MOS transistor TR44 is configured such that a drain terminal D is connected to a source terminal S of the N-channel MOS transistor TR43, a source terminal S is connected to the digital ground DVS, and a gate terminal G is connected to a gate terminal of the P-channel MOS transistor TR42.

[0071] Furthermore, the Latch section contains 14BA P-channel MOS transistor TR45, a P-channel MOS transistor TR46, an N-channel MOS transistor TR47, and an N-channel MOS transistor TR48. The P-channel MOS transistor TR45 is configured so that one source terminal S is connected to the digital power supply DVD and one gate terminal G is connected to the clock signal line CLK. The P-channel MOS transistor TR46 is configured so that one source terminal S is connected to the digital power supply DVD, one drain terminal D is connected to a drain terminal D of the P-channel MOS transistor TR45, and one gate terminal G is connected to the drain terminal D of the P-channel MOS transistor TR42 and to the drain terminal D of the N-channel MOS transistor TR43.The N-channel MOS transistor TR47 is configured such that one drain terminal D is connected to the drain terminal D of the P-channel MOS transistor TR45 and to the drain terminal D of the P-channel MOS transistor TR46, and one gate terminal G is connected to a drain terminal D of the P-channel MOS transistor TR33 and to a drain terminal D of the N-channel MOS transistor TR34. The N-channel MOS transistor TR48 is configured such that one drain terminal D is connected to a source terminal S of the N-channel MOS transistor TR47, one source terminal S is connected to digital ground DVS, and one gate terminal G is connected to the gate terminal G of the P-channel MOS transistor TR46.

[0072] In the above configuration, the comparator section 14 a comparator output OUTP according to the signals INP and INN fed into the clock signal line CLK at the time of a rise. [Operations of a threshold determination circuit]

[0073] Fig. Figure 6 is a flowchart illustrating a process performed by an overfeed detection circuit (threshold detection circuit).

[0074] First, the threshold voltage Sth is set to the voltage Vth to determine an excessive feed-in (step S11).

[0075] In the above case, a voltage adjustment can be performed by using a function of the D / A conversion section. 12 is extended or by providing a separate setting circuit.

[0076] Next, the threshold determination circuit will be used. 21 used to process the pixel signal S VSL with voltage V th to compare and determine whether the pixel signal S is excessively high and to determine if it is excessively high. VSLlower than the voltage Vth used to determine excessive feed-in (whether the pixel signal S VSL an excessive feed across the A / D converter area 10 (beyond) (step S12). Alternatively, the threshold determination circuit can use the comparator section. 14 use for determination purposes.

[0077] If the result of a determination in step S12 indicates that the pixel signal S VLS If the voltage is higher than the voltage used to determine excessive feed-in (“NO” in step S12), the threshold determination circuit determines 21 , that no excessive feed (no excessive voltage feed) is applied to the gate terminal G of the P-channel MOS transistor TR13, which is an input terminal of the differential amplifier, and outputs a determination result signal. S EV with an "L" level at the gate terminal G of the N-channel MOS transistor TR17 out of.

[0078] Consequently, the N-channel MOS transistor TR17 Held off (left in the open state) (Step S14).

[0079] As a result, the differential amplifier remains DA in a normal operating condition.

[0080] However, if the result of a determination in step S12 indicates that the pixel signal S VSL lower than the voltage Vth used to determine excessive feed-in (the pixel signal S) VSL an excessive feed above the area of ​​the A / D converter 10 beyond) (“YES” in step S12), determines the threshold determination circuit 21 , that an excessive feed (an excessive voltage feed) to the gate terminal G of the P-channel MOS transistor TR13, which is an input terminal of the differential amplifier DA is created, and gives a determination result signal. S EV with “H” level to the gate terminal G of the N-channel MOS transistor TR17 out of.

[0081] Consequently, the N-channel MOS transistor TR17 switched on (put into the closed state) (step S13). As a result, a short circuit occurs between the connection points. CP1 and CP2 created so that the output voltages OUTP and OUTN are essentially the same.

[0082] Accordingly, a value in the comparator section 14 The applied voltage difference is extremely small, even when an excessive input voltage is applied. Therefore, even during operation with excessive feed-in, the feed-in to the comparator section can be insufficient. 14 The conversion speed can be reduced so that it is similar to that for other pixel signals. This makes it possible to reduce the degradation caused by banding. [Advantageous effect of the first embodiment]

[0083] As described above, even in a case where there is excessive feed to the differential amplifier DA The first embodiment provides a response time required at the time of a conversion of a low-order bit, similar to that in the case where no excessive input is applied to the differential amplifier. DA is applied. This makes it possible to reduce the deterioration caused by streaking. [First modification of the first embodiment]

[0084] The configuration described above assumes that the threshold voltage Sth is set once to the voltage Vth for determining excessive feed-in, and that the result of a determination by the threshold determination circuit 21 directly to the gate terminal G of the N-channel MOS transistor TR17 is issued.

[0085] Without setting the threshold voltage Sth once to the voltage Vth to determine excessive feed-in, an alternative configuration can be adopted to perform an A / D conversion sequentially as a normal operation, to determine excessive feed-in in a case where the results of a determination by the comparator section 14 for several high-order sequential bits, “H” are, and the NMOS transistor TR17 to enable. Adopting the above alternative configuration eliminates the need to set the threshold voltage Sth to the voltage Vth to determine overfeed and to perform an overfeed detection. Therefore, the required A / D conversion time is used only for the actual A / D conversion, and no additional A / D conversion time is required. This increases the processing speed.

[0086] If the configuration described above is adopted, the operations according to the first embodiment can be easily implemented by wiring the N-channel MOS transistor. TR17 and the logic circuit 15 for a sequential conversion to the gate connection G is changed and a control program of the logic section is used. 15 is changed for a sequential conversion. [Second modification of the first embodiment]

[0087] Fig. Figure 7 is a diagram illustrating a detailed configuration of a preamplifier section according to a second modification of the first embodiment.

[0088] In Fig. Seven are elements similar to those found in Fig. The four elements shown are designated with the same reference symbols as the corresponding elements.

[0089] A preamplifier section 13A according to the second modification of the first embodiment differs from the preamplifier section 13 according to the first embodiment, in that the former comprises a comparison determination circuit 25 and an N-channel MOS transistor TR17A The comparison circuit 25 compares the voltage of the pixel signal S. VSL with a standard reference voltage V th , which corresponds to a predetermined state of excessive feed-in, and outputs a determination result signal S EVA out. The N-channel MOS transistor TR17A is configured such that a drain port D is connected to a connection point CP11 between the drain terminal D of the P-channel MOS transistor TR14 and the resistor R1, and a source terminal S with a connection point CP12 between the drain terminal D of the P-channel MOS transistor TR16 and the resistor R2. When the determination result signal S is output by the comparison determination circuit 25 EVA into the gate terminal G of the N-channel MOS transistor TR17A When power is supplied, the N-channel MOS transistor functions TR17A as a switch to prevent a short circuit between the connection points CP11 and CP12 to form.

[0090] The second modification of the first embodiment is also configured to use the N-channel MOS transistor. TR17A to turn on (to close) if the voltage of the pixel signal S VSL lower than the standard reference voltage Vth, which corresponds to the predetermined state of excessive feed-in. Therefore, a short circuit occurs between the connection points. CP11 and CP12 formed such that the voltages of the preamplifier outputs OUTP and OUTN are essentially equal to each other. This makes it possible to calculate the difference between the inputs to the comparator section. 14 to reduce the voltages supplied by the feed-in system. [Third modification of the first embodiment]

[0091] Fig. Figure 8 is a diagram illustrating a detailed configuration of a preamplifier section according to a third modification of the first embodiment.

[0092] In Fig. 8 are elements similar to those found in Fig. The four elements shown are designated with the same reference symbols as the corresponding elements.

[0093] A preamplifier section 13B according to the third modification of the first embodiment differs from the preamplifier section 13according to the first embodiment, in that the former has a comparison determination circuit 25 to determine the voltage of the pixel signal S VSL to compare with a standard reference voltage Vth, which corresponds to a predetermined state of excessive feed-in, and to generate a determination result signal S EVB to output, and by the fact that the result of a determination by the comparison determination circuit 25 is fed into a gate terminal G of an N-channel MOS transistor TR17B is entered.

[0094] The third modification of the first embodiment is also configured to use the N-channel MOS transistor. TR17B to turn on (to close) if the voltage of the pixel signal S VSLlower than the standard reference voltage Vth corresponding to the predetermined state of excessive feed-in. Therefore, the voltages of the preamplifier outputs OUTP and OUTN are essentially equal to each other. This makes it possible to calculate the difference in the comparator section. 14 to reduce the voltages supplied by the feed-in system. [Fourth modification of the first embodiment]

[0095] The preceding description assumes that the MOS transistor in the input stage of preamplifier section 13B is configured as a P-channel MOS transistor. However, alternatively, the MOS transistor in the input stage of preamplifier section 13B can be configured as an N-channel MOS transistor. Second embodiment [Detailed configuration of a comparator section according to a second embodiment]

[0096] Fig. Figure 9 is a diagram illustrating a detailed configuration of a preamplifier section according to a second embodiment.

[0097] In Fig. 9 are elements similar to those of the first embodiment described in Fig. The four elements shown are designated with the same reference symbols as the corresponding elements.

[0098] A preamplifier section 13C according to the second embodiment differs from the preamplifier section 13 according to the first embodiment, in that the first embodiment incorporates an N-channel MOS transistor TR51 It contains the N-channel MOS transistor. TR51 It functions as a diode in place of the N-channel MOS transistor. TR17 and the threshold determination circuit 21 .

[0099] In the above configuration, the N-channel MOS transistor TR51 configured so that a drain port D is connected to a connection point CP11 between the drain terminal D of the P-channel MOS transistor TR14 and the resistor R1, a source terminal S with a connection point CP12 between the drain terminal D of the P-channel MOS transistor TR16 and the resistor R2, and a gate terminal G with the connection point CP11 is connected.

[0100] If the difference between the voltage of the pixel signal S VSL and the voltage of the threshold voltage signal Sth is large and the difference between the first output signal OUTP and the second output signal OUTN is large, the N-channel MOS transistor TR51 switched on (brought into a conductive state). Therefore, the differential voltage between the first output signal OUTP and the second output signal OUTN can affect the threshold voltage of the N-channel MOS transistor acting as a diode. TR51 The time required for comparison is reduced. Compared to the first embodiment, the method described above eliminates the need for comparison time in determining excessive feed-in and a feedback signal from the logic section. 15 is provided for sequential conversion.

[0101] Since excessive input only occurs from the side of the pixel signal S VSL Furthermore, another feature of the second embodiment is that the gate terminal G of the N-channel MOS transistor functioning as a diode is TR51 with the side of the pixel signal S VSL is connected.

[0102] However, to match load capacities, it is also necessary to use an N-channel MOS transistor similar to the TR51 to configure so that a gate and a drain are connected to the CP12 -page are linked and a source with the CP11 -page is connected. [Detailed configuration of a comparator section according to a first modification of the second embodiment]

[0103] Fig. Figure 10 is a diagram illustrating a detailed configuration of a preamplifier section according to a first modification of the second embodiment.

[0104] In Fig. 10 are elements similar to those of the first embodiment described in Fig. The elements described in section 4 are designated with the same reference symbols as the corresponding elements.

[0105] A preamplifier section 13D according to the second embodiment differs from the preamplifier section 13 according to the first embodiment, in that the former incorporates an N-channel MOS transistor functioning as a diode. TR52 instead of the N-channel MOS transistor TR17 and the threshold determination circuit 14 contains.

[0106] In the above configuration, the N-channel MOS transistor TR52 configured so that a drain port D is connected to the connection point CP1 between the drain terminal D of the P-channel MOS transistor TR13 and the source terminal S of the P-channel MOS transistor TR14, a source terminal S with the connection point CP2 between the drain terminal D of the P-channel MOS transistor TR15 and the source terminal S of the P-channel MOS transistor TR16, and a gate terminal G with the connection point CP1 is connected.

[0107] According to the configuration above, the N-channel MOS transistor TR52 switched on (put into a conductive state) if the difference between the voltage of the pixel signal S VSLand the voltage of the threshold voltage signal Sth is large, and the difference between the first output signal OUTP and the second output signal OUTN is large. This makes it possible to reduce the differential voltage between the first output signal OUTP and the second output signal OUTN. Compared with the first embodiment, the method described above eliminates the need for the comparison time in threshold determination and the feedback signal from the logic section. 15 is provided for sequential conversion.

[0108] In the above case, similar to the second embodiment, excessive input also occurs only from the side of the pixel signal S. VSL Therefore, another feature of the first modification of the second embodiment is that the gate terminal G of the N-channel MOS transistor functioning as a diode is designed. TR52 with the side of the pixel signal S VSL is connected.

[0109] However, to match load capacities, it is also necessary to use an N-channel MOS transistor similar to the TR52 to configure so that a gate and a drain are connected to the CP2 -page are linked and a source with the CP1 -page is connected. [Second modification of the second embodiment]

[0110] The preceding description assumes that the MOS transistor in the input stage of preamplifier section 13C is configured as a P-channel MOS transistor. However, alternatively, the MOS transistor in the input stage of preamplifier section 13C can be configured as an N-channel MOS transistor. Third embodiment [Detailed configuration of a comparator section according to a third embodiment]

[0111] Fig. Figure 11 is a diagram illustrating a detailed configuration of a preamplifier section according to a third embodiment.

[0112] In Fig. 11 are elements similar to those of the first embodiment described in Fig. The four elements shown are designated with the same reference symbols as the corresponding elements.

[0113] A preamplifier section 13E according to the third embodiment differs from the preamplifier section 13 according to the first embodiment, in that the former replaces the N-channel MOS transistor. TR17 a P-channel MOS transistor TR53 contains, which is based on the threshold determination circuit 21 output determination result signal S EV an initial voltage VSET, corresponding to the case of a standard pixel signal conversion, is applied to the gate terminal G of the P-channel MOS transistor TR13.

[0114] In the configuration above, the P-channel MOS transistor TR53 configured so that a drain terminal D is connected to the gate terminal G of the P-channel MOS transistor TR13 and a gate terminal G is connected to an output terminal OUTP1 of the threshold determination circuit 21 is connected.

[0115] If the threshold determination circuit 21 detected that the voltage of the pixel signal S VSL If the voltage is lower than the standard reference voltage Vth corresponding to a predetermined state of excessive feed-in, the present third embodiment switches off the P-channel MOS transistor. TR53 a (closes it). Therefore, the initial voltage VSET is applied to the gate terminal G of the P-channel MOS transistor TR13 in the preamplifier section 13E to perform a conversion similar to standard pixel signal conversion. Consequently, any effect exerted on other columns is the same as during standard pixel signal conversion. This reduces any effect exerted after CDS (correlated double sampling). This makes it possible to reduce the deterioration of any banding. [Detailed configuration of a preamplifier section according to a first modification of the third embodiment]

[0116] Fig. Figure 12 is a diagram illustrating a detailed configuration of a preamplifier section according to a first modification of the third embodiment.

[0117] In Fig. 12 are elements similar to those of the third embodiment, which are described in Fig. The elements described in section 11 are designated with the same reference symbols as the corresponding elements.

[0118] A preamplifier section 13F according to the first modification of the third embodiment differs from the preamplifier section 13E according to the third embodiment in that the former includes a threshold determination circuit 30. The threshold determination circuit 30 compares the voltage of the pixel signal S VSL with the standard reference voltage Vth, which corresponds to the predetermined state of excessive feed-in, and outputs a determination result signal S EVF to the gate terminal G of the P-channel MOS transistor TR53 out of.

[0119] Even in a case where the voltage of the pixel signal S VSLIf the voltage is lower than the standard reference voltage Vth corresponding to the predetermined state of excessive feed-in, the first modification of the third embodiment switches off the P-channel MOS transistor. TR53 also (closes it). Therefore, the initial voltage VSET is applied to the gate terminal G of the P-channel MOS transistor TR13 in the preamplifier section 13F to perform a conversion similar to the standard pixel signal conversion. Consequently, the effect exerted on the other columns is the same as at the time of the standard pixel signal conversion. This reduces the effect exerted after a CDS (correlated double sampling). This makes it possible to reduce the deterioration of the extent of banding.

[0120] Now, a configuration of a circuit for setting an initial voltage, as used in the embodiment above, will be briefly described. Fig. Figure 13 is a diagram illustrating an example of the circuit that sets an initial voltage.

[0121] The circuit setting an initial voltage ensures a voltage Vds between the drain terminal and source terminal of the P-channel MOS transistor TR12, which acts as a current source, when the voltage across a resistor R3 drops, and also defines a voltage at the gate terminal G of the P-channel MOS transistor TR13 in the preamplifier section. 13 The initial voltage value VSET to be applied is set. Fourth embodiment

[0122] The preceding embodiments were described in relation to an A / D converter processing a single pixel. However, a fourth embodiment described below is an embodiment of a signal processing section containing a plurality of A / D converters configured to sequentially perform A / D conversion processing on a plurality of pixels. [Schematic configuration of a signal processing section according to a fourth embodiment]

[0123] Fig. Figure 14 is a block diagram illustrating a schematic configuration of a signal processing section according to the fourth embodiment.

[0124] One in Fig. The signal processing section 4A shown in Figure 14 is an example illustrating a case where each A / D converter performs time-sharing processing on eight pixels. For simplified illustration, Fig. The figure represents 14n A / D converters, ranging from 10⁻¹ to 10⁻ⁿ (n being a natural number), although 2n A / D converters are contained in signal processing section 4A. In reality, the remaining n A / D converters are arranged along one side of upward-running output signal lines from the pixels in the figure.

[0125] In the above case, the A / D converter configurations are 10 -1 to 10-n similar to that of the in Fig. 2 illustrated A / D converters 10 . In Fig. 14 are the D / A conversion section 12 , the preamplifier section 13 , the comparator section 14 , the logic section 15 for a sequential conversion and the logic section 16 represented for a rotation.

[0126] In the Fig. In the 14 case shown, pixels, that is, half of a total of 16 pixels, comprising pixels PX1 to PX4, pixels PX11 to PX14, pixels PX21 to PX24 and pixels PX31 to PX34, are assigned to each of the A / D converters 10-1.

[0127] More precisely, a total of eight pixels, namely pixels PX1, PX3, PX11, PX13, PX21, PX23, PX31 and PX33, are assigned to the A / D converter 10-1 shown in the figure.

[0128] Similarly, a total of eight pixels, namely pixels PX2, PX4, PX12, PX14, PX22, PX24, PX32, and PX3, are assigned to each of the A / D converters not shown. (Basic operations of a signal processing section according to a fourth embodiment)

[0129] The basic operations of the signal processing section 4A according to the fourth embodiment are now described.

[0130] The A / D converters 10-1 to 10-n and the n A / D converters not shown, which are contained in signal processing section 4A, perform independent processing synchronously. Therefore, the basic operation of, for example, A / D converter 10-1 is described below.

[0131] For example, when a single data read operation is performed, the A / D converter 10-1 sequentially processes the pixel PX1, the pixel PX3, the pixel PX11, the pixel PX13, the pixel PX21, the pixel PX23, the pixel PX31 and the pixel PX33 in the specified order.

[0132] More precisely, at the first processing point for a single data read operation, the D / A conversion section is used. 12 of the A / D converter 10-1 the multitude of types of local standard reference signals Sref, which are provided by the sections 11to generate local reference voltages in order to perform a digital / analog (D / A) conversion on the control data D CNT under the control of the logic section described later for a sequential conversion and the logic section for a rotation, and outputs the threshold voltage signal Sth to the preamplifier 13 out of.

[0133] Consequently, the preamplifier section amplifies 13 the pixel signal S fed in by a pixel signal input port TSL1 VSL , which corresponds to the Pixel PX1, and that from the D / A converter 12 The input threshold voltage signal Sth and outputs the amplified signals to the comparator section. 14 out of.

[0134] The comparator section 14 compares the amplifier outputs above and gives the comparison result data D CMP to the logic section 15 for a sequential conversion.

[0135] The logic section15 For a sequential conversion, there is not only sequential conversion control data D. SAR to execute a sequential conversion control via an analog-to-digital conversion of the comparison result data D CMP but also saves the entered comparison result data D CMP and then, based on the stored comparison result data, gives D CMP the pixel data D VSL , which is the result of the analog-to-digital (A / D) conversion of the pixel signal S VSL represent, from the output port TD OUT out of.

[0136] Subsequently, at times from a second processing time to an eighth processing time, the A / D converter 10-1 similarly performs a process to carry out an analog-to-digital (A / D) conversion on the pixel data S. VSLthrough, corresponding to the respective pixels, that is, pixel PX3, fed from a pixel signal input port TSL2, pixel PX11, fed from a pixel signal input port TSL3, pixel PX13, fed from a pixel signal input port TSL4, pixel PX21, fed from a pixel signal input port TSL5, pixel PX23, fed from a pixel signal input port TSL6, pixel PX31, fed from a pixel signal input port TSL7, and pixel PX33, fed from a pixel signal input port TSL8, and outputting the result of the conversion from the output port TD OUT out of .

[0137] In the above case, the A / D converters 10-2 to 10-n and the n A / D converters not shown also perform a process similar to the one above in parallel.

[0138] As described above, the fourth embodiment provides an additional advantage beyond that of the first embodiment. More precisely, compared to a case where the number of A / D converters is equal to the number of pixels, the fourth embodiment can reduce the number of A / D converters to approximately 1 / 8, thereby reducing the circuit area of ​​the signal processing section 4A. This makes it possible to reduce the footprint of the solid-state imaging device and to miniaturize the device containing it. Fifth embodiment

[0139] Fig. Figure 15 is a block diagram illustrating an example of an indirect distance measurement sensor over a runtime, for which the present technology is used.

[0140] The sensor for indirect time-of-flight distance measurement contains a sensor chip 101 and a circuit chip 102. The circuit chip 102 is stacked on top of the sensor chip 101.

[0141] A pixel array section 112 contains a plurality of pixels 111 arranged in a two-dimensional grid pattern on the sensor chip 101 in an array. The pixel array section 112 can be arranged in a matrix and can contain a plurality of column signal lines. The column signal lines are connected to the respective pixels.

[0142] The circuit chip 102 includes a vertical control circuit 113, a column signal processing section 114, a timing circuit 115 and an output circuit 116.

[0143] The vertical control circuit 113 is configured to control the pixels and output pixel signals to the column signal processing section 114. The column signal processing section 114 performs A / D conversion on the input pixel signals and outputs the A / D-converted pixel data to the output circuit 116.

[0144] For example, output circuit 116 performs CDS (correlated double sampling) processing on the pixel data from column signal processing section 114 and outputs the processed pixel data to a signal processing circuit in a subsequent stage.

[0145] The timing control circuit 115 is configured to control the respective activation times of the vertical control circuit 113. The column signal processing section 114 and the output circuit 116 operate synchronously with vertical synchronization signals output by the timing control circuit 115.

[0146] The pixels 111 contained in pixel array section 112 will now be described in detail.

[0147] Fig. Figure 16 is a circuit diagram illustrating a configuration example of a pixel according to an embodiment of the present technology.

[0148] The pixel array section 112 contains the multitude of pixels 111 arranged in a two-dimensional grid pattern in an array. Each of the pixels 111 is configured to receive infrared light and to convert the received infrared light into a pixel signal photoelectrically.

[0149] Furthermore, vertical signal lines VSL1 and VSL2 are vertically wired to each column of pixel 111. If the total number of columns in the pixel array section is 112M (M being an integer), then a total of 2 × M vertical signal lines are wired. Each pixel has two taps. Vertical signal line VSL1 is connected to tap A of each pixel 111, while vertical signal line VSL2 is connected to tap B of each pixel 111. Moreover, vertical signal line VSL1 carries a pixel signal AINP1, while vertical signal line VSL2 carries a pixel signal AINP2.

[0150] The vertical control circuit 113 sequentially selects and controls the rows of the pixel area 112 to cause each row to simultaneously output the pixel signals AINP1 and AINP2 for each pixel block 221. That is, the vertical control circuit 113 controls the 2k-th and (2k+1)-th rows of pixels 111 simultaneously.

[0151] Each pixel 111 contains a photodiode 121, two transmission transistors 122 and 123, two reset transistors 124 and 125, two taps (floating diffusion layers 126 and 127), two amplifier transistors 128 and 129 and two selection transistors 130 and 131.

[0152] Photodiode 121 converts received light photoelectrically to generate an electrical charge. Photodiode 121 is located on the back surface of a semiconductor substrate, while circuitry is located on the front surface of the semiconductor substrate. This type of solid-state imaging device is called a back-illuminated solid-state imaging device. Alternatively, a front-illuminated configuration can be used instead of the back-illuminated configuration, in which photodiode 121 is located on the front surface of the semiconductor substrate.

[0153] The transmission transistor 122 and the transmission transistor 123 sequentially transfer electrical charge from the photodiode 121 to the TAP A 126 or the TAP B 127 according to the transmission signal TRG from the vertical control circuit 113.

[0154] The TAP A 126 and the TAP B 127 accumulate the transferred electrical charge and generate a voltage corresponding to the amount of accumulated electrical charge.

[0155] An overflow transistor 132 is a transistor that sequentially discharges the electrical charge of the photodiode 121 to a power supply VDD at a high potential and serves to reset the photodiode 121.

[0156] The reset transistors 124 and 125 withdraw the electrical charge from the TAP A 126 and the TAP B 127 respectively according to a reset signal RSTp from the vertical control circuit 113 in order to initialize the amount of electrical charge.

[0157] Amplifier transistors 128 and 129 amplify the respective voltages of TAP A 126 and TAP B 127. Selection transistors 130 and 131 output signals of the amplified voltages as pixel signals via two vertical signal lines (e.g., VSL1 and VSL2) according to a selection signal SELp from the vertical control circuit 113 to the column signal processing section 114. The vertical signal lines VSL1 and VSL2 are connected to an input of an A / D inverter 10 in the signal processing section 114.

[0158] It should be particularly noted that the circuit configuration of the Pixel 111 does not correspond to that in Fig. 15 illustrated is limited as long as pixel signals can be generated by means of photoelectric conversion.

[0159] As is the case with the fourth embodiment, the fifth embodiment can reduce the footprint of the solid-state imaging device and shrink the sensor for indirect distance measurement over a runtime.

[0160] It should be particularly noted that the beneficial effects described in this document are for illustrative purposes only and are not limiting. The technology presented here may produce other beneficial effects than those described in this document.

[0161] It should be particularly mentioned that the present technology can also handle the following configurations. (1)

[0162] An A / D converter, comprising: a comparator circuit that performs a comparison with a threshold voltage to determine whether an excessive injection of a pixel signal has occurred or not, and a first transistor having a control terminal and forming a clamping circuit, the control terminal being configured to receive an input of a result of the comparison. (2)

[0163] The A / D converter as described in (1) wherein currents flowing to a first predetermined position and a second predetermined position are balanced or voltages flowing to the first predetermined position and the second predetermined position are balanced, wherein the first predetermined position and the second predetermined position are connected to each other at the time of a clamping. (3)

[0164] The A / D converter, as described in (1) or (2), further comprising: a pair of transistors of a differential pair, forming an input current line and a reference current line, and a pair of bias transistors that control a bias current flowing to the transistors of a differential pair, where the first transistor is arranged either upstream or downstream of the pair of bias transistors. (4)

[0165] The A / D converter, as described in one of (1) to (3), wherein the clamping circuit includes a threshold determination circuit that determines whether a signal with a value equal to a predetermined threshold for excessive feed-in or greater than the pixel signal has been fed in or not, and Based on an output from the threshold determination circuit, the first transistor forms a short circuit between the first predetermined position and the second predetermined position that are connected at the time of clamping. (5)

[0166] An A / D converter, comprising: a pair of transistors of a differential pair, forming an input current line and a reference current line, a pair of bias transistors that control a bias current flowing to the transistors of a differential pair, and a diode comprising an anode and a cathode, wherein the anode is connected to a first predetermined position, the cathode is connected to a second predetermined position, and the first predetermined position and the second predetermined position are connected at the time of clamping. (6)

[0167] Electronic device, comprising: a pixel array section containing a multitude of pixels that perform a photoelectric conversion and are arranged in an array form, and a signal processing section that reads an analog pixel signal from the pixel array section and performs signal processing, wherein the signal processing section includes an A / D converter that performs an analog-to-digital conversion on the analog pixel signal, and the A / D converter a comparator circuit that performs a comparison with a threshold voltage to determine whether a pixel signal and excessive feed-in have been introduced or not, and a first transistor which has a control terminal and forms a clamping circuit, with a result of the comparison being input into the control terminal. (7)

[0168] Electronic device, comprising: a pixel array section containing a multitude of pixels that perform a photoelectric conversion and are arranged in an array form, and a signal processing section that reads an analog pixel signal from the pixel array section and performs signal processing, wherein the signal processing section includes an A / D converter that performs an analog-to-digital conversion on the analog pixel signal, and the A / D converter a pair of transistors of a differential pair, forming an input current line and a reference current line, a pair of bias transistors that control a bias current flowing to the transistors of a differential pair, and a diode comprising an anode and a cathode, wherein the anode is connected to a first predetermined position, the cathode is connected to a second predetermined position, and the first predetermined position and the second predetermined position are connected at the time of a clamping. Reference symbol list 2: Pixel array section 4: Signal Processing Section 10: A / D converter 11: Section for generating a local reference voltage 12: D / A conversion section 13, 13A to 13F: Preamplifier section 14: Comparator section 14A: Amplifier section 14B: Latch section 15: Logic section for a sequential conversion 16: Logic section for a rotation 21: Threshold determination circuit CP1, CP11: Connection point (first predetermined position) CP2, CP12: Connection point (second predetermined position) TR17, TR17A, TR17B: N-channel MOS transistor (clamp circuit) TR51, TR52: N-channel MOS transistor (clamp circuit) TR53: P-channel MOS transistor (switching element) DA: Differential amplifier S EV : Determination result signal QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2005252529

[0005]

Claims

[1] A / D converter comprising: a comparator circuit that performs a comparison with a threshold voltage to determine whether an excessive injection of a pixel signal has occurred or not, and a first transistor having a control terminal and forming a clamping circuit, the control terminal being configured to receive an input of a result of the comparison. [2] A / D converter according to claim 1, wherein currents flowing at a first predetermined position and a second predetermined position are balanced or voltages flowing at the first predetermined position and the second predetermined position are balanced, wherein the first predetermined position and the second predetermined position are connected to each other at the time of a clamping. [3] A / D converter according to claim 2, further comprising: a pair of transistors of a differential pair, forming an input current line and a reference current line, and a pair of bias transistors that control a bias current flowing to the transistors of a differential pair, where the first transistor is arranged either upstream or downstream of the pair of bias transistors. [4] A / D converter according to claim 1, wherein the clamping circuit includes a threshold determination circuit that determines whether a signal with a value equal to a predetermined threshold for excessive feed-in or greater than the pixel signal has been fed in or not, and Based on an output from the threshold determination circuit, the first transistor forms a short circuit between the first predetermined position and the second predetermined position that are connected at the time of clamping. [5] A / D converter, comprising: a pair of transistors of a differential pair, forming an input current line and a reference current line, a pair of bias transistors that control a bias current flowing to the transistors of a differential pair, and a diode comprising an anode and a cathode, wherein the anode is connected to a first predetermined position, the cathode is connected to a second predetermined position, and the first predetermined position and the second predetermined position are connected at the time of a clamping. [6] Electronic device comprising: a pixel array section containing a multitude of pixels that perform a photoelectric conversion and are arranged in an array form, and a signal processing section that reads an analog pixel signal from the pixel array section and performs signal processing, wherein the signal processing section includes an A / D converter that performs an analog-to-digital conversion on the analog pixel signal, and the A / D converter a comparator circuit that performs a comparison with a threshold voltage to determine whether a pixel signal and excessive feed-in have been introduced or not, and a first transistor which has a control terminal and forms a clamping circuit, with a result of the comparison being input into the control terminal.