Intelligent charge pump architecture for flash arrays

Abstract

A charge pump architecture (2) for storage devices structured in a plurality of subarrays (400), wherein the architecture (2) includes: a chain of pump stages for increasing the value of an input voltage and for achieving an overvoltage output value; at least one register block (640) coupled to the chain of pump stages and controlled by a logic circuit section (660) to receive at least one activation signal that selects a specific charge pump architecture (2) connected to a storage subarray (90) of the plurality of subarrays (400), wherein the at least one register block (640) includes a JTAG finite state machine (750).

Description

TECHNICAL AREA The present invention relates to non-volatile semiconductor memory devices and in particular to a novel flash memory array component which includes an intelligent charge pump architecture for a flash memory section to which SoC devices are assigned. STATE OF THE ART Flash memory is a type of non-volatile memory that stores data without periodic recharging. A key feature of flash memory is its ability to erase data block by block, rather than byte by byte. Each erasable block of memory comprises a multitude of non-volatile memory cells arranged in a matrix of rows and columns. Each cell is connected to a word line, a bit line, and a source line. The cells are programmed and erased by manipulating the voltages across these lines. A flash memory device is typically powered by low-voltage power sources, such as 1.8 V and / or 3.3 V. However, this low voltage is insufficient to perform all operations within the array. Flash memory devices are typically equipped with charge pumps to boost the voltage levels provided by reference voltage generators; these boosted voltage levels are used at memory cells during write and erase operations. A charge pump is an externally controlled device in which the output is compared to a specific reference value, except for a ratio that allows the comparison values ​​to be adjusted, for example, like the well-known Dickinson charge pump with diodes and MOSFETs to drive capacitors. Fig. 1A shows a schematic view of a Dickinson positive charge pump, while Fig. 1B shows a schematic view of a Dickinson negative charge pump. The operating mechanism is implemented using a non-overlapping two-phase clock. Its purpose is to store charge in one capacitor using one phase and transfer this charge to another capacitor using a different phase. Appropriate phase modulation allows the charge pump to store charge in one capacitor and transfer it to the other, thereby increasing the equivalent value relative to a reference. In the first stage, a capacitor is connected across the supply, charging it to the same voltage. In the second stage, the circuit is reconfigured so that the capacitor is in series with both the supply and the load. This doubles the voltage across the load as the sum of the original supply voltage and the capacitor voltages. The pulsating nature of the switched, higher-voltage output is often smoothed by using an output capacitor. The number of stages affects the final output voltage of the circuit. The architecture of a charge pump is of major importance in all memory components embedded or allocated in systems-on-chips, with reliability, architecture, and the ability to use the charge pump to maintain a variety of internal voltage values ​​being crucial. US 2012 / 020161A1 discloses a multi-layer flash memory device in which high-voltage pulses for programming (setting) or erasing (resetting) are timed to occur simultaneously. By controlling the timing at which each memory layer (e.g., each logical or physical memory partition with its own array controller and side buffer) applies high-voltage pulses, the circuitry required to control multiple concurrent operations can be reduced, thus saving valuable on-chip space. Both the "programming phase" and the "verification phase" of each state-change cycle can be coordinated simultaneously across all layers, sharing timing and high-voltage distribution. US 2002 / 0104031A1 discloses a programmable integrated circuit for power management, comprising analog input monitoring circuits that receive analog input signals corresponding to voltage, current, or temperature measurements. The analog input monitoring circuits apply programmable thresholds to the measurements and output the results to a programmable logic circuit, which can generate various status and / or control signals for the monitored system. The programmable logic device controls FET drivers that can switch the power supply to the monitored system on and off.The programmable integrated circuit for power management may also include an internal oscillator, a serial interface, a system-programmable interface, a common test action interface, a memory to store identification information, and a register to capture system information during shutdown. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A shows a schematic view of a positive charge pump of known structures used in semiconductor memory devices; Fig. 1B shows a schematic view of a positive charge pump of known structures used in semiconductor memory devices; Fig. 2 shows a schematic view of a host device, for example a system-on-chip, coupled with a non-volatile memory component according to embodiments of the present disclosure; Fig. 3 shows a schematic view of a memory component of the present disclosure, connected to the host device or SoC structure and comprising at least one microsequencer and dedicated circuitry for the programming, reading, and erase phases with charge pumps; Fig. 4 shows a schematic view of the internal layout of a section of the memory component of Fig. 3 according to an embodiment of the present disclosure; Fig.Figure 5 is a schematic view of a JTAG logic structure integrated into the memory component of the present disclosure; Figure 6 is a schematic view of the intelligent charge pump architecture for the memory component of the present disclosure; Figure 7A shows a more detailed schematic view of part of the charge pump architecture shown in Figure 6; Figure 7B shows a more detailed schematic block view of the components of the charge pump architecture of the present disclosure; Figure 8 is a diagram showing a finite state machine evolving through a plurality of states according to a JTAG standard protocol. DETAILED DESCRIPTION Non-volatile flash memory is one of the fundamental building blocks of modern electronic systems, especially for real-time operating systems (RTOS). The operation of non-volatile flash memory is managed by a controller containing embedded firmware, which performs the necessary read / write / erase operations. Non-volatile memory can provide persistent data by retaining stored data when power is not supplied and can include, among others, NAND flash memory, NOR flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), and variable resistance memory such as phase-change random access memory (PCRAM), chalcogenide-based self-selecting memory, resistive random access memory (RRAM), 3D X-point memory (3DXP), and magnetoresistive random access memory (MRAM). In particular, flash memory is a type of non-volatile memory that stores data and is characterized by very fast access times. Furthermore, it can be erased in blocks rather than by a single byte. Each erasable memory block comprises a multitude of non-volatile memory cells arranged in a matrix of rows and columns. Each cell is connected to an access line and / or a data line. The cells are programmed and erased by manipulating the voltages on the access and data lines; for this, the memory chip requires voltage values ​​higher than the supply voltages, and for this reason the memory structure contains one or more positive charge pumps for the read and programming phase of the memory cells, as well as negative charge pumps for the erasing phase of the memory cells. With reference to these accompanying figures and in particular to the example of Fig. 2, devices and methods are disclosed herein which include a non-volatile storage device 1 or component and a host device 10 for such a storage device. The host device 10 can be a system-on-chip with an embedded memory component 1 or a more complex electronic device comprising a system coupled with a memory device, as described in the description of other embodiments of the present disclosure with reference to other figures. Currently, the technology of complex semiconductor structures, known as systems-on-chips (SoCs), allows for the integration of at least one embedded non-volatile memory. However, such embedded memory becomes a large macro component within an SoC and is increasingly difficult to manage when the lithography node is below 28 nm, especially when trying to increase its size to more than 128 Mbit. The problems mentioned above are solved by the features of the independent claims. Advantageous embodiments can be derived from the respective dependent claims. The present disclosure proposes to improve the memory size by providing a structurally independent memory component 1 coupled to the host device 10 or to the system-on-a-chip. The memory component 1 is structured as a self-contained device implemented on a single chip using a technology specifically designed for the manufacture of flash memory devices. The size of this memory area is increased to over 256 Mbit or even 512 Mbit. This non-volatile memory component 1 contains an array of 90 flash memory cells and circuitry arranged around the memory array and closer to a variety of peripheral pads, as will be revealed later. This memory component 1 has a variable size corresponding to the size of its memory array, which is manufactured according to the user's requirements in a range of values ​​from 128 Mbit to 512 Mbit or more. In particular, the flash memory component 1 includes an I / O circuit 5, a microsequencer 3 and a read amplifier 9. The flash memory component 1 also includes a command user interface CUI 4, voltage and current reference generators 7, a charge pump architecture 2 and a decoding circuit 8 located at the periphery of the array. To read the memory cells of the array 90, a dedicated circuit section is provided, containing an optimized read finite-state machine, which is used to ensure high read performance, as will be shown soon. To write and erase the memory cells of the array 90, a dedicated logic circuit section is provided, which contains a simplified reduced instruction set computer (RISC) or a modify finite-state machine, or that is the logic circuit for handling the programming and erasing algorithms. The memory component 1 is assigned and connected to the host component 10 or to the SoC structure partially overlapping such a structure, while the corresponding semiconductor area of ​​the SoC structure is used for other logic circuitry and to provide support for the overlapping structurally independent memory section 1'. The coupling between the SoC structure 10 and the memory component 1 is realized by connecting several respective pads or pin connections facing each other in a circuit layout that maintains the orientation of the pads even if the size of the memory component 1' should be changed. For the sake of completeness, it should be noted that the memory component 1 can be coupled to the SoC or host structure 10 using flip-chip technology or other coupling techniques. Flip-chip technology, also known as C4 (Controlled Collapse Chip Connection), is a method for connecting semiconductor devices, such as IC chips and / or microelectromechanical systems (MEMS), to external circuits via solder bumps deposited on the chip pads. These solder bumps are deposited on the chip pads on the top side of the wafer during the final wafer processing step. To mount the chip to an external circuit (e.g., a printed circuit board or another chip or wafer), the chip is flipped over so that its top side faces down and aligned pad-to-pad so that its pads are correctly aligned with the external circuit.Then the solder is melted to complete the connections. In one embodiment of the present disclosure, the arrangement of the pads of the memory component 1 on a surface of the memory component 1 is realized opposite corresponding pads of the SoC structure 10. Even a larger memory component can be supported and connected to the pads of the SoC structure 10, with only the position and offset of its connection pads being maintained. In one embodiment of the present disclosure, the charge pump architecture 2 was specifically provided for a storage component 1 that is strictly connected to the host or SoC structure 10 and includes a JTAG logic structure. This flash memory component 1 uses the connection pads of the array and logic circuit part to enable connection to the host device or SoC structure 10. The final configuration could be, for example, a SoC / Flash array with face-to-face connection, with read amplifiers connected to the SoC in a Direct Memory Access type memory configuration, as well as a JTAG logic structure and control pins for testing and other purposes. Fig. 3 shows a more detailed schematic view of the flash memory component 1 of the present disclosure, comprising: the memory array 90, the microsequencer 3, a control and JTAG logic structure 500 and circuit parts 20, 25 and 30 for managing the charge pumps during the programming, reading and erasing phase. In embodiments of the present disclosure, the memory array is structured as a collection of subarrays 400, as shown in the schematic view of Figure 4. In this way, with smaller sectors compared to known solutions, the access time is significantly reduced and the overall throughput of the memory component is improved. The sampling chains of each subarray 400 are connected to form a unique shift register 450 in order to properly test the connections mentioned above. The advantage of this architecture is that it is highly scalable and can increase and / or decrease the density of the final device by mirroring only one subarray and creating the link. Direct Memory Access makes it possible to reduce the final latency that the SoC may experience when reading data. In the following sections of this disclosure, it will be evident that the outputs of the read amplifiers SA assigned to each subarray 400 are buffered by an internal circuit to enable the read amplifiers to perform a further internal read operation to prepare the second nibble, or group, of at least 128 bits. This second nibble is transferred to the output of the flash array using the clock signal or an additional enable signal, which transmits the content read at the read amplifier level to the channel of the host device or SoC. Each of the SA read amplifiers is directly connected to a modified JTAG cell 420 to integrate these modified JTAG cells and the read amplifiers into a single output circuit section. This allows the delay in passing the memory array output to the SoC to be reduced as much as possible. Fig. 4 shows a schematic view of a JTAG logic structure 500 integrated into the memory component 1 of the present disclosure and using boundary scan cells configured according to IEEE Standard No. 1149.1. A JTAG logic structure is a special interface added to a chip. Depending on the JTAG version, two, four, or five pins are added. The connection pins are: TDI (Test Data In); TDO (Test Data Output); TCK (Test Clock); TMS (Test Mode Select) and an optional TRST (Test Reset). The TRST pin is an optional active-low reset for the test logic, usually asynchronous, but sometimes synchronous depending on the chip. If the pin is unavailable, the test logic can be reset by synchronously switching to the reset state using TCK and TMS. Note that resetting the test logic does not necessarily imply resetting anything else. Generally, there are some processor-specific JTAG operations that can reset all or part of the chip being debugged. Since only one data line is available, the protocol is serial. The clock input is located at the TCK pin. On each rising clock edge of the TCK, a data bit is transferred from the TDI to the TDO. Various instructions can be loaded. Instructions for typical ICs can read the chip ID, sample input pins, read drive output pins (or float), manipulate or bypass chip functions (forward TDI to TDO to logically shorten chains of multiple chips). As with any clocked signal, the data presented to the TDI must be valid for a specific chip-specific setup time before and for a hold time after the corresponding (here, rising) clock edge. TDO data is valid for a certain chip-specific time after the falling edge of TCK. The example in Fig. 4 and Fig. 5 shows a set of four dedicated test pins - Test Data In (TDI), Test Mode Select (TMS), Test Clock (TCK), Test Data Out (TDO) - and an optional test pin Test Reset (TRST). These pins are collectively referred to as the Test Access Port (TAP). However, the 500 architecture includes a finite state machine called the TAP controller 570, which receives three signals as inputs: TCK, TMS, and TRST. The TAP controller 570 is a 16-state finite state machine (FSM) that controls each step of the operations of the JTAG logic structure 500. Each instruction to be executed is stored in the instruction register 520. Fig. 5 shows the composition of the registers integrated into the JTAG logic structure 500 of the present disclosure. A boundary-scan shift register 550 is coupled in serial mode to the TDI pin and provides an output to the TDO output pin via the multiplexer 560. The test clock, TCK, is fed in via another dedicated device input pin, and the operating mode is controlled by a dedicated serial control signal “Test Mode Select” (TMS), both of which are applied to the TAP controller 570. The various control signals assigned to the command are then provided by a 590 decoder. The instruction register (IR) 520 contains n bits (where n = 2) and is implemented to hold each current instruction. The architecture includes a 1-bit bypass register (not shown in Fig. 4) and the identification register 530. An additional register 580 is used as a shift data register to enable interaction with the core of the host device during the write and / or read phase of the memory chip. The command user interface represented by the TAP controller 570 is based on the IEEE1149 and IEEE1532 standards, which implement a low-signal-count interface, i.e., TMS, TCK, TDI, TDO, TRST (optional), with the ability to modify the internal contents of each of the associated 400 memory subarrays. In one embodiment of the present disclosure, as shown in Fig. 6, the charge pump architecture 2 is provided with at least one register block 640 and a simple charge pump logic circuit 660 to assign it to the flash memory array 90, thereby obtaining an intelligent charge pump architecture 2. This type of intelligent charge pump architecture 2 is assigned to each subarray 400 of the flash memory array 90. This intelligent charge pump architecture 2 can be used to great advantage during the testing phase of the flash array. It supplies all the required voltage without external support (e.g., test machine, external generators). However, the charge pump of the present disclosure is also fully usable for other different purposes and can also be shared by subarrays 400 of the storage array 90. To fully understand the differences between the present invention and known solutions, it must be noted that in a self-contained flash memory, which performs one operation at a time, the resident microsequencer controls the output voltage of the charge pumps to carry out the proper operations within the array. In contrast, according to embodiments of the present disclosure, shown for example in Fig. 3, the structure of the memory component 1 including the flash memory array 90 is connected to the microsequencer 3, which exchanges signals with the circuit sections 20, 25 and 30, which are dedicated to the programming, reading and erasing phases, and which include the charge pump architecture 2 of the present disclosure. A multi-operation flash memory array 90, such as the memory array contained in memory component 1, would have required multiple independent charge pumps 2 to ensure the different execution in different blocks. In contrast, the solution disclosed herein provides a pump architecture 2 capable of supplying the required voltage for different phases during operations on the memory array. The need for simultaneous operation also leads to a change in the procedure that operates the charge pump architecture 2, i.e., it requires an independent charge pump logic 660 for operation so that the unique micro-sequencer 3 can control high-performance operation in different sub-arrays of the storage array 90. The pumps 2 assigned to each subarray 400 can be configured using the microsequencer 3, as explained below. A more detailed view of the registers of block 780 is shown in Fig. 7B, which also shows the presence of a register 710 for setting the specific pump for the specific storage subfield or a register for the target steps to achieve the desired output voltage. A non-volatile pump address register 720 is used to assign a procedure for addressing each pump in each subarray, that is, a code for addressing. The pump address register 720 is a volatile copy of the pump address for independent pump operations. (An external FSM and / or RISC can provide inputs and start signals to this logic and then wait for the result.) In Figures 6 and 7A, a general block numbered 650 is indicated, containing either a positive or a negative pump chain, such as the one shown in Figures 1A and 1B. This is because the memory array requires both positive and negative pumps for various operations performed by the memory cells, and it may be necessary to activate both positive and negative pumps simultaneously. After configuration, pumps 2 (positive or negative) can be used simultaneously as soon as a trigger (start or run signal) is activated. This is because some operations, such as erasing, require a positive (flash cell source / body terminals) and a negative (flash cell gate terminals) voltage at the same time. There is also a signal (pump_halt) that allows the voltage development to be suspended when it is applied and restarted as soon as this signal is deactivated (this enables support for some functions such as suspending the erase). To better understand all the features of the charge pump architecture 2, it is appropriate to explain how the logic circuit section 660 is fed and how the register block 640 can be viewed as a JTAG pump register block. As is known in this technical field, a JTAG (Joint Test Action Group) standard protocol provides a method for testing connections on printed circuit boards, which is implemented at the IC level and uses a serial shift register located around the boundary of a device. IEEE Standard No. 1149.1, commonly referred to as digital boundary scan, provides a means of testing interconnects between integrated circuits on a circuit board without using physical test probes. It does this by adding a boundary-scan cell containing a multiplexer and latches for each pin on the device. Furthermore, the IEEE 1532 standard, adopted in systems programming, enables the use of the JTAG infrastructure to modify the internal configuration of components in both programmable and non-programmable ways. Figure 8 shows a diagram of the states of the Finite State Machine (FSM) operating according to the IEEE 1149.1 standard. This FSM comprises sixteen states, two of which—the shift instruction register (ShiftIR) and the shift data register (ShiftDR)—allow interaction with the memory array during the write and / or read phases. There are six "stable states" where the stability of the TMS prevents the state from changing. In all other states, the TCK always changes the state. Fig. 8 schematically shows the test access port TAP 800 as a finite state machine that performs all operations relating to testing an integrated circuit such as a storage device. The sequence of logic signals “0” and “1” applied to the TMS pin controls the operation of the chip architecture through the boundary scan structure. Let's begin with the reset state of the test logic, which is displayed as number 810 when the circuit is powered on. In this specific state, all boundary-scan cells are in a so-called transparent state, with the parallel input PIN internally connected to the parallel output POUT and all input pins connected to the core of the integrated circuit. By applying a corresponding sequence of logical values ​​"1" and "0" as a TMS signal, it is possible to configure the output multiplexer so that the TDI input is shifted as the first instruction to obtain the output TDO. The TMS signal then controls the TAP FSM in ShiftDr or ShiftIr to link the TDI and TDO with a register. To shift an instruction, we need to enter state ShiftIR number 830, and to reach this state, we need to apply the following sequence: setting 0 as TMS and applying a clock pulse to TCK, we reach the Run / Idle state 820. If we now select a "1" from state 820, we proceed to a selection of a data register scan 840 and an instruction register scan 845. With another "0" on the TMS, we reach the capture phase of the instruction register 850. The capture phase allows capturing on the last two bits of instruction register 520 in Fig. 7A. Capturing means using the parallel input to capture the value in each cell of the selected register. Another "0" leads to the Shift IR, which allows the input value TDI to be passed to the output TDI. The TDI value at the input appears at the output TDO after a number of clock cycles equal to the size of the register. If we keep the TMS at "0", we can remain in the Shift IR state 830, which allows the bits received at the TDI pin to be shifted to the output TDO. It is possible to remain in this state 830 for the entire clock cycle required to shift all input bits. We remain in ShiftIR state 830 for a number of clock cycles equal to the number of bits in IR 720 minus one. At the end of the sequence, the Exit-1 IR state 855 is reached. From this initial state 855, we move to an update state 860, which triggers a "1" TMS, and this is the moment when the new instruction becomes valid. The boundary scan cells are reset to test mode, with the input pins isolated from the core circuitry. It is now possible to send the test vector to the core circuit by reaching the Shift-DR state 870. The states of the data register are similar to the states of the instruction registers. Therefore, we can achieve ShiftDR state 870 with the sequence 1-0-0. During the Capture DR 875 cycle, the first multiplexer MO1 of the boundary scan cell is connected to the parallel input PIN and all input pins of the boundary scan register have captured their input value. Switching to the Shift DR 870, the multiplexer changes its state, making it possible to capture the serial input SIN, and the sampling path is shifted from the TDI input through the boundary scan register to the output pin TDO. The circuit remains in this state for a number of clock cycles equal to the number of boundary scan cells minus one. However, the boundary scan is one of the possible data registers that can be selected with a suitable instruction in the IR register. The new test vector is output at the output pins when the Exit -1 DR 880 state is passed and the Update DR 885 state is reached. The sequence is repeated from update to capture to allow a new test vector to be introduced into the circuit. An example of a sequence for addressing a specific charge pump architecture 2 is shown schematically in Fig. 8 as an example of the development of FSM in different states and can be as follows: ShiftIR: Pump_Address_Instruction ShiftDR: Pump_address_shift_in to select the desired pump ShiftIR: Vo_Target_Instruction This last instruction will only be loaded into the selected pump. An alternative example of a command flow for addressing a specific charge pump architecture 1 could be the following: ShiftDR: Vo_target_value Shift to ShiftIR: Vo_Target_Steo_Instruction This last instruction will only be loaded into the selected pump. An alternative example of a command flow for addressing a specific charge pump architecture 2 could be the following: ShiftDR: Vo_Target_SteP_value Shift to ShiftIR: Vo_Target_Size_Instruction This last instruction will only be loaded into the selected pump. An alternative example of a command flow for addressing a specific charge pump architecture 1 could be the following: ShiftDR: Vo_Target_Size_Value Shift to ShiftIR: Pump_Service_Instruction This last instruction will only be loaded into the selected pump. An alternative example of a command flow for addressing a specific charge pump architecture 2 could be the following: ShiftDR: Vo_Service_value Shift In This command can provide the charge pump with additional information, such as standby info, test mode inputs, etc. Another example of a command flow for addressing a specific charge pump architecture 1 might be: Run / Test_Idle It starts the pump execution and / or forces a service register bit for the selected pumps, which can determine whether the pump must run when the run / test_idle bit is set. As we have seen, the TAP contains a test data input and a test data output, as well as a clock signal. Specifically, the shift data register ShiftDR reports a state in which the TDI is connected to a register. In this state, the register contents are transferred into and / or out of the device. Similarly, the shift instruction register ShiftIR also reports a state in which the TDI is connected to a register. Instructions are loaded in this state. In particular, the shift data register ShiftDR reports a state in which the signal TDI is connected to a register. In this state, the register contents are transferred into and / or out of the device. Similarly, the shift register ShiftIR also reports a state in which the TDI is connected to a register. Instructions are loaded in this state. Due to the requirement for multiple cores within the host device 10 or the SoC, the internal register 580 of the JTAG interface must be able to support up to address and data registers. Specifically, the creation of four address registers (one from each subarray 400) is provided, each with a different address for a subarray 400, triggering four different data outputs for the read register [0:3] per subarray section. Communication with the SoC is achieved by directly connecting the selected read register, i.e., the output named POU [127:0], to the input of the channel of the host device or SoC 10. This mechanism makes it possible to preload the data for the controller, thereby reducing the latency to a very low value. For the sake of completeness, it should be noted that the JTAG state machine can be reset, access an instruction register, or access data selected by the instruction register. To use JTAG, a host device is connected to the target's JTAG signals (TMS, TCK, TDI, TDO, etc.) via a JTAG adapter, which may need to handle issues such as level shifting and galvanic isolation. The adapter connects to the host via an interface such as USB, PCI, Ethernet, etc. Host device 10 communicates with TAP block 570 by manipulating TMS and TDI in conjunction with TCK and reading the results via TDO (which is the only standard host-side input). TMS / TDI / TCK output transitions create the basic JTAG communication primitive upon which higher-layer protocols are built. State change: where all TAPs signals are in the same state and this state changes during TCK transitions. Essentially, using JTAG involves reading and writing instructions and their associated data registers; and sometimes includes executing a series of test cycles. Behind these registers lies hardware that is not specified by JTAG and has its own states, which are affected by JTAG activities. Each primary input signal and each primary output signal is augmented by this multi-purpose storage element, which is called the boundary scan cell and is essentially the 550 shift register. A parallel loading operation, referred to as the "capture" operation, causes signal values ​​at device input pins to be loaded into input cells, and signal values ​​that pass from the core logic to device output pins are loaded into output cells. A parallel discharge operation—referred to as the "update operation"—causes signal values ​​already present in the output scan cells to be output through the device output pins. Depending on the nature of the input scan cells, signal values ​​already present in the input scan cells are passed to the core logic. The update operation also enables the confirmation of the values ​​in the register (i.e., the shift introduces the bits that can be stopped). When the update state is reached in IEEE 1149.1 FSM, the register value is fixed; that is, it is a sorting of the latch signal to update the value of the destination registers. Data can also be shifted around the shift register in serial mode, starting with a dedicated device input pin called "Test Data In" (TDI) and ending at a dedicated device output pin called "Test Data Out" (TDO). There is an Edge Connector input called TDI, which is connected to the TDI of the first device. The TDO of the first device is connected to the TDI of a second device, and so on, creating a global scan path that terminates at the Edge Connector output also called TDO. The test clock, TCK, is fed in via another dedicated input pin, and the operating mode is controlled by a dedicated serial control signal “Test Mode Select” (TMS). In one embodiment of the present disclosure, the TDI and TDO signals are used to control the register block 640 of the charge pump architecture 2 shown in Fig. 6. The present disclosure provides several hardware modifications compared to the configuration of the charge pumps of a standalone flash memory device, in particular: • the conversion of the charge pump into an intelligent subsystem by providing register block 640 and logic circuit section 660; • the generation of the correct output voltage with a correct shape, i.e.Stair step amplitude and size as Vo output value of pump chain section 650; with a modest delay in generating the steps; • integration with a JTAG protocol; • assignment of a programmable address to the charge pump architecture 2 to enable identification of the different pumps of each different subarray 400 of the flash memory array 90; • provision of at least some registers in register block 640 interconnected using TDI / TDO logic: - an address register to drive the specific pump of a specific subarray; - an amplitude of the stair step register to define the size of the Vo value increment. One embodiment of the present disclosure relates to a charge pump architecture for storage devices structured in a plurality of subarrays, wherein the architecture includes: - a stage chain for increasing the value of an input voltage and obtaining an overvoltage output value; - at least one register block 640 coupled to the chain of stages 650 and driven by a logic circuit section 660 to receive at least one activation signal that selects a specific charge pump architecture associated with a storage subarray. Register block 640 contains at least a few registers: one to activate the specific charge pump architecture 2, which is assigned to a memory subfield 400, and the other to define the value of the pump output voltage. In addition, register block 640 contains a JTAG finite-state machine, shown in Fig. 7A with the number 750. The logic circuit section 660 selects and activates the corresponding pump chain 650 of each subarray 400 of the memory array 90, which passes through register block 640, in order to select not only the pump but also its activity. Thus, when the pump architecture is requested to provide a suitable overvoltage value for the read phase, the logic circuit section 660 selects the pumps of the subarrays involved in the read phase. When the pump architecture is requested to provide a suitable overvoltage value for the write phase, the logic circuit section 660 similarly selects the overvoltage values ​​and the number and position of the pumps of the subarrays 400 involved in the write phase. When the pump architecture 2 is requested to provide a suitable overvoltage value for the quenching phase, the logic circuit part 660 selects the overvoltage values ​​as well as the number and position of the pumps of the subgroups involved in the quenching phase. Alternatively, the above-mentioned address register is a lock table provided to record the quality and position of the pumps requested to attend to specific operational activities on the flash memory field 90; thus, there are pumps for the read or erase phases and pumps for the write phase, and the logic circuit section 660 selects and activates the appropriate pumps by selecting only one logic value. It should also be taken into account that no read phase is performed during an erase phase and therefore no special pump architecture is required for reading and erase, whereas the multi-purpose structure of the charge pump architecture 1 is used for both read and erase phases, which are obviously driven in a suitable manner to obtain the required overvoltage values ​​for the specific operation on the corresponding storage sub-arrangement. More precisely, the erasure process is performed in (3) macro steps: 1) Pre-programming phase: All cells of the selected block are programmed; 2) Erase pulse; 3) Verification by a read operation with marginal reference voltages to ensure reliability; Loops (2) and (3) are repeated until the block is deleted or a predefined timeout is reached. If the timeout occurs, the deletion results in an error. Pump architecture 1 is activated while the storage array controller handles other activities, such as preparing the circuit sections dedicated to the read and / or write phases. Pump architecture 1 thus achieves the required overvoltage values ​​during the timeframe in which the controller is occupied with these other activities. Further features of the circuit structure associated with the charge pump of the present disclosure are disclosed below, for example, with reference to Fig. 7A, in which the basic internal structure of the register block 580 is shown schematically. A finite automaton 750 is bidirectionally connected to the pump chain 650 to apply the correct value of the input reference voltage Vin and the modulation of the phases and to regulate the correct value at the output Vout. Even this state machine 750 can be considered a JTAG state machine. However, the pump FSM 750 is connected to the previously disclosed JTAG FSM, but functions differently, employing a kind of step-by-step logic for regulation and maintenance using comparisons. The finite automaton 750 is also bidirectionally connected to a group of registers 780, each containing a target value that the charge pump architecture 2 is to achieve, for example: the target output voltage, the target time within which the output voltage is to reach its value, and the status of some other registers. Referring to the more detailed view of the registers of block 780 shown in Fig. 7B, as already indicated, register 710 is used to set the specific pump for the specific memory subarray or a register for the target steps to achieve the target output voltage. The non-volatile pump address register 720 is used to assign a method for addressing each pump in each subarray, that is, a code for addressing. The pump address register 720 is a volatile copy of the pump address. (For independent pump operation, external FSM and / or RISC provide inputs and start signals to this logic and then wait for the result.) In any case, all registers of block 780 are selectable according to the values ​​of the TDI input signal. More precisely, the content is loaded with the TDI signal while the register is addressed to control the TMS signal so that it moves within the JTAG finite-state machine. Logic section 660 is responsible for executing the correct phase sequences to correspond to the desired settings in the JTAG pump registers 780 and to output the status. Logic section 660 is connected to the Run / Test_Idle state of the JTAG state machine. The logic circuit section 660 is also responsible for updating the status either in register block 780 and, if necessary, also with direct signals for the microsequencer 3. In particular, the logic circuit section 660 of the charge pump should allow the following settings: • Duration step size to determine how long a specific voltage must be held; • Target end voltage: that is, the value of the Vo target voltage; • Dedicated hardware in the sense of defining the hardware parts affected by the charge pump architecture: - to start the operation when run / test_idle is reached; - to provide feedback to the microsequencer; - to deactivate the pump when not in use to minimize power consumption. The charge pump architecture 2 of the present disclosure is driven by the internal microsequencer 3, which is also the flash controller. The microsequencer 3 configures the pump blocks correctly, and then, once the pumps are triggered with the start signal (run), they implement the requested Vout voltage waveform using a comparison with a proper reference and wait states to reach the final voltage. This is because the pumps have one or more internal voltage regulators that require a reference voltage value, as shown in 7A, with the possibility that the pumps include regulators that implement some kind of high-voltage (positive or negative) digital-to-analog converter. The logic circuit section 660 is also responsible for executing the correct phase sequences to adjust the desired settings in the JTAG pump registers and to report the status. The charge pump logic is linked to the run / test_idle state of the JTAG state machine. The charge pump logic is also responsible for updating the status either in the register and, if necessary, with direct signals for the microsequencer. The proposed charge pump architecture of the present disclosure makes it possible to address multiple operations in the different subarrays of the flash memory array 90. Furthermore, the new pump architecture enables the use of the JTAG protocol to control the charge pump in various situations, such as: - for performance purposes; - for testing purposes; - for field fault analysis purposes. The charge pump architecture of the present disclosure has the great advantage of providing a unique charge pump design and reducing the time to validation and the time to design. Furthermore, thanks to its intelligence and registers, it is a reusable block. Further advantages arise from the complete reusability of the charge pump architecture, which can be used for various purposes and shared by subarrays of the storage device.

Claims

A charge pump architecture (2) for storage devices structured in a plurality of subarrays (400), wherein the architecture (2) includes: a chain of pump stages for increasing the value of an input voltage and for achieving an overvoltage output value; at least one register block (640) coupled to the chain of pump stages and controlled by a logic circuit section (660) to receive at least one activation signal that selects a specific charge pump architecture (2) connected to a storage subarray (90) of the plurality of subarrays (400), wherein the at least one register block (640) includes a JTAG finite state machine (750). Charge pump architecture (2) according to claim 1, wherein the register block (640) includes at least a first register for activating the specific charge pump architecture (2) connected to a memory subarray (90), and a second register for defining the value of the pump output voltage. Charge pump architecture (2) according to claim 1, wherein the JTAG-finite state machine (750) is bidirectionally connected to the chain of pump stages to apply the correct value of the input reference voltage Vin and to regulate the correct value at the output Vout. Charge pump architecture (2) according to claim 1, wherein the logic circuit section (660) is linked to the Run / Test_Idle state of the JTAG finite state machine (750). Charge pump architecture (2) according to claim 4, wherein a register of the register block (640) is selectable according to the values ​​of a TDI input signal of the JTAG protocol, wherein the content is loaded by the TDI signal while the register is addressed by driving a TMS signal to move in the JTAG finite state machine (750). Charge pump architecture (2) according to claim 4, wherein the register is used to assign a pump architecture to a specific storage subarray, at least to provide the overvoltage values ​​for the read and write phases. Charge pump architecture (2) according to one of claims 1 to 4, wherein the contents of all registers of the register block (640) are programmable. Charge pump architecture (2) according to one of claims 1 to 4, wherein a non-volatile pump address register is included in the register block (640) to assign an addressing code to each pump in each subarray (400). A non-volatile storage device structured in a plurality of subarrays (400) comprising: at least one decoding and acquiring circuit (8) associated with each subarray (400); a charge pump architecture (2) for each subarray (400) comprising pumping stages for increasing the value of an input voltage and obtaining an overvoltage output value; a control and JTAG interface in the non-volatile storage device; at least one register block (640) coupled to the charge pump architecture (2) and driven by a logic circuit section (660) to receive at least one activation signal that selects a specific charge pump architecture (2) associated with a storage subarray (90) of the plurality of subarrays (400), wherein the at least one register block (640) includes a JTAG-finite state machine (750). A non-volatile storage device according to claim 9, wherein the register block (640) comprises at least a first register for activating the specific charge pump architecture (2) associated with a storage subarray (90) and a second register for defining the value of the pump output voltage. Non-volatile storage device according to claim 9, wherein the JTAG-finite state machine (750) is bidirectionally connected to the chain of pump stages to apply the correct value of the input reference voltage Vin and to regulate the correct value at the output Vout. Non-volatile storage device according to claim 9, wherein the logic circuit section (660) is linked to the Run / Test_Idle state of the JTAG finite state machine (750). Non-volatile storage device according to claim 9, wherein a register of the register block (640) is selectable according to the values ​​of a TDI input signal of the JTAG protocol, wherein the content is loaded by the TDI signal while the register is addressed by driving a TMS signal to move in the JTAG finite state machine (750). Non-volatile storage device according to claim 9, wherein the JTAG-finite state machine (750) is also bidirectionally connected to a group of registers, each of which contains a target value for the charge pump architecture (2). Non-volatile storage device according to claim 13, wherein the target values ​​are contained in a group of at least one target output voltage and at least one target time to reach the output voltage. Non-volatile storage device according to one of claims 10 to 14, wherein the contents of the registers of the register block (640) are programmable. Non-volatile storage device according to one of claims 10 to 14, wherein a non-volatile pump address register is included in the register block (640) to assign an addressing code to each pump in each subarray (400). A method for generating overvoltage values ​​in a storage device structured in a plurality of subarrays (400) and comprising at least one microsequencer and a charge pump architecture (2), comprising: assigning a programmable address to each charge pump architecture (2) associated with each distinct subarray (400); providing a logic circuit section (660) that receives at least one activation signal that selects a specific charge pump architecture (2) associated with a storage subarray (90) of the plurality of subarrays (400); selecting the charge pump architecture (2) for a read, erase, or write operation to be performed on the storage subarray (90); wherein the activation signals select the specific charge pump architecture (2) integrated into a JTAG protocol. Method according to claim 18, wherein a JTAG register is provided for assigning a programmable address to each charge pump architecture (2) that is assigned to each distinct subarray (400). Method according to claim 18, wherein the logic circuit section (660) also defines the value of the pump output voltage. Method according to claim 19, wherein the JTAG register includes a JTAG-finite state machine. Method according to claim 21, wherein the JTAG-finite state machine is bidirectionally connected to a chain of pump stages of the charge pump architecture (2) to apply the correct value of the input reference voltage Vin and to regulate the correct value at the output Vout. Method according to claim 21, wherein the logic circuit section (660) is linked to the Run / Test_Idle state of the JTAG finite state machine (750).

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