Method for manufacturing a semiconductor superjunction device

Abstract

A method of manufacturing a semiconductor superjunction device, comprising: Forming a first insulating layer (30) on an n-type substrate (20) and etching the first insulating layer (30) to form an opening (41); Forming an insulating side wall (31) in the opening (41); Etching the n-type substrate (20) using the first insulating layer (30) and the insulating sidewall (31) as a mask to form a first groove (42) in the n-type substrate (20); Forming a p-type pillar (21) in the first groove (42) such that the p-type pillar (21) and the n-type substrate (20) form a pn junction structure; forming a second insulating layer (32) on a surface of the p-type pillar (21); Etching away the insulating sidewall (31); and etching the n-type substrate (20) using the first insulating layer (30) and the second insulating layer (32) as a mask to form a second groove (43) in the n-type substrate (20), wherein an etching process combining anisotropic etching and isotropic etching is performed when the second groove (43) is formed by etching; Forming a gate dielectric layer (23) and a gate (24) in the second groove (43) such that the gate (24) is insulated from the p-type pillar (21) by the gate dielectric layer (23), and then etching away the first insulating layer (30) and the second insulating layer (32); Forming a p-type body region (34) in the n-type substrate (20); and Forming an n-type source region (25) in the p-type body region (34).

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor superjunction device technology and relates to a method for manufacturing a semiconductor superjunction device. BACKGROUND

[0002] Based on charge-balancing technology, semiconductor superjunction devices can reduce on-state resistance and parasitic capacitance. With this design, semiconductor superjunction devices have extremely fast switching characteristics. This allows switching losses to be reduced and higher power conversion efficiency to be achieved. The main process for fabricating prior-art semiconductor superjunction devices includes the steps described below. First, as shown in Fig. 1, a first insulating layer 11 is formed on an n-type substrate 10. Photolithography and etching are then performed. An opening is formed in the first insulating layer 11, and a groove 12 is formed in the n-type substrate 10. Subsequently, as shown in Fig. 2, the first insulating layer is removed. A p-type column 13 is formed in the groove by an epitaxial process. Then, as shown in Fig. 3, a photolithography process and an etching process are performed to form a gate dielectric layer 14 and a gate 15. Then, a p-type body region 16 located in the n-type substrate 10 and an n-type source region 17 located in the p-type body region 16 are formed in the n-type substrate 10. Regardless of whether it is a planar semiconductor superjunction device or a groove-type semiconductor superjunction device, a photolithography process is required when forming the p-type pillars. Subsequently, a photolithography process is required again when forming the gate. Due to the high cost of the photolithography process and the risk of misalignment, the manufacturing cost and risk of semiconductor superjunction devices are high.

[0003] US Pat. No. 5,620,930 A discloses a method for fabricating an integrated semiconductor region, in which a first layer is formed along a trench to be etched, a second spacer layer along an edge of the first layer, and a third layer adjacent to a spacer. The spacer is etched away while the first and third layers remain in place, and the trench is etched into the space between the first and third layers. A preferred etchant consists of CF3Br and oxygen.

[0004] Furthermore, CN 1 05 702 711 A discloses a super junction device with parallel P-pillar trenches in an N-type epitaxial region. SUMMARY

[0005] The object of the present application is to provide a method for manufacturing a semiconductor superjunction device for reducing the manufacturing costs of the semiconductor superjunction device and the risks in manufacturing the semiconductor superjunction device.

[0006] To achieve the above object of the present application, the present application provides a method for fabricating a semiconductor superjunction device. The method comprises the steps described below.

[0007] A first insulating layer is formed on an n-type substrate. The first insulating layer is etched to form an opening.

[0008] An insulating side wall is formed in the opening.

[0009] The n-type substrate is etched using the first insulating layer and the insulating sidewall as a mask to form a first groove in the n-type substrate.

[0010] A p-type pillar is formed in the first groove. The p-type pillar and the n-type substrate form a pn junction structure.

[0011] A second insulating layer is formed on the surface of the p-type pillar.

[0012] Furthermore, the insulating sidewall is etched away, and the n-type substrate is etched using the first insulating layer and the second insulating layer as a mask to form a second groove in the n-type substrate.

[0013] Furthermore, an etching process combining anisotropic etching and isotropic etching is performed when the second groove is formed by etching.

[0014] Furthermore, a gate dielectric layer and a gate are formed in the second groove so that the gate is insulated from the p-type pillar by the gate dielectric layer. Subsequently, the first insulating layer and the second insulating layer are etched away.

[0015] A p-type body region is formed in the n-type substrate.

[0016] An n-type source region is formed in the p-type body region.

[0017] Optionally, the method for manufacturing a semiconductor superjunction device according to the present application further comprises the steps described below.

[0018] Optionally, the first insulating layer contains a silicon oxide layer.

[0019] Optionally, the second insulating layer is the silicon oxide layer.

[0020] Optionally, the insulating sidewall is a silicon nitride layer.

[0021] Optionally, the depth of the second groove is less than the depth of the first groove.

[0022] In the method for manufacturing a semiconductor superjunction device according to the present application, the first groove is formed by a photolithography process, and the n-type substrate is etched in a self-aligned manner using the first insulating layer and the second insulating layer as a mask to form the second groove in the n-type substrate. In the method for manufacturing a semiconductor superjunction device according to the present application, only one photolithography process is required to form the gate and the p-type pillar. Thus, the manufacturing cost of the semiconductor superjunction device can be greatly reduced, and the risks involved in manufacturing the semiconductor superjunction device can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] To better illustrate the solutions in the exemplary embodiment of the present application, the drawings used in the embodiment are described below. The Fig. 1 to 3 are sectional views showing the main structures in the process for manufacturing a semiconductor superjunction device of the prior art. The Fig. 4 to 9 are sectional views showing the main structures in the method for manufacturing a semiconductor superjunction device of an embodiment of the present application. DETAILED DESCRIPTION

[0024] The solutions of the present application are described in detail below through specific implementations in conjunction with the drawings in the embodiment of the present application. It is obvious that the described embodiment is an embodiment of the present application. At the same time, to clearly illustrate the specific implementations of the present application, the thicknesses of the layers and the thicknesses of the regions described in the present application are enlarged in the views shown in the drawings, and the sizes of the graphics shown do not represent the actual dimensions.

[0025] The Fig. 4 to 9 are sectional views showing the main structures in the method for manufacturing a semiconductor superjunction device of an embodiment of the present application.

[0026] First, as in Fig. As shown in Figure 4, the first insulating layer 30 is formed on the provided n-type substrate 20. The n-type substrate 20 is typically a silicon substrate. The first insulating layer 30 includes the silicon oxide layer. The first insulating layer 30 may be, for example, the silicon oxide layer or the layer of silicon oxide layer-silicon nitride layer-silicon oxide layer. The position of the opening is defined by the photolithography process. Then, the first insulating layer 30 is etched to form the opening 41 in the first insulating layer 30. The number of openings 41 is determined by the specification of the designed semiconductor superjunction device. For example, in the embodiment of the present application, only two openings 41 are shown.

[0027] Next, as in Fig. 5, the insulating sidewall 31 is formed in the opening. The insulating sidewall 31 may be the silicon nitride layer. A specific process includes the steps described below: First, a silicon nitride layer is deposited. Then, the deposited silicon nitride layer is etched back. Thus, the insulating sidewall 31 is formed in a self-aligned manner at the position of the sidewall of the opening. After the insulating sidewall 31 is formed, the n-type substrate 20 is etched using the first insulating layer 30 and the insulating sidewall 31 as a mask to form the first groove 42 in the n-type substrate 20.

[0028] Next, as in Fig. As shown in Figure 6, the p-type pillar 21 is formed in the first groove by an epitaxial process. Generally, a layer of p-type silicon is first epitaxially grown. Then, the p-type silicon is etched. The p-type silicon layer remaining after etching forms the p-type pillar 21. The p-type pillar 21 and the n-type substrate form the pn junction structure. Afterward, the second insulating layer 32 is formed on the surface of the p-type pillar 21. The second insulating layer 32 may be the silicon oxide layer formed by a thermal oxidation process.

[0029] Next, as in Fig. 7, the insulating sidewall is etched away. The n-type substrate 20 is etched using the first insulating layer 20 and the second insulating layer 32 as a mask to form the second groove 43 in the n-type substrate 20. The depth of the second groove 43 is less than the depth of the first groove.

[0030] The etching process that combines anisotropic etching and isotropic etching is performed when forming the second groove 43 by etching. In this way, the width of the second groove 43 can be increased. As a result, the width of the second groove 43 is larger than the width of the insulating sidewall. At this time, the upper part of the p-type pillar 21 can be partially etched away. Therefore, the width of the upper part of the p-type pillar 21 is smaller than the width of the lower part of the p-type pillar 21. The width of the gate formed later can be increased by the arrangement in which the width of the second groove 43 is increased. Therefore, the gate can be pulled out more easily, and the reliability of the semiconductor superjunction device is improved.

[0031] Next, as in Fig. 8, the first insulating layer and the second insulating layer are etched away. The gate dielectric layer 23 and the gate 24 are formed in the second groove. The gate 24 is insulated from the p-type pillar 21 by the gate dielectric layer 23. Optionally, the gate dielectric layer 23 and the gate 24 are first formed in the second groove. Then, the first insulating layer and the second insulating layer are etched away.

[0032] Next, as in Fig. 9, the p-type body region 34 is formed in the n-type substrate 20. The n-type source region 25 is formed in the p-type body region 34.

[0033] Finally, the semiconductor superjunction device can be obtained with the arrangement in which an insulating dielectric layer, a metal layer, and the like are formed according to a conventional method.

[0034] In the method for manufacturing a semiconductor superjunction device according to the present application, the first groove is formed by a photolithography process; the p-type pillar is formed in the first groove, and the second insulating layer is formed on the surface of the p-type pillar; then, the n-type substrate is etched in a self-aligned manner using the first insulating layer and the second insulating layer as a mask to form the second groove in the n-type substrate, and the gate dielectric layer and the gate are formed in the second groove. Therefore, in the method for manufacturing a semiconductor superjunction device according to the present application, only a single photolithography process is required to form the gate and the p-type pillar.In this way, the manufacturing cost of the semiconductor superjunction device can be greatly reduced and the risks in the manufacturing of the semiconductor superjunction device can be reduced.

[0035] The foregoing implementations and the foregoing embodiment are concrete supports for the technical idea of ​​the present application and therefore do not limit the scope of protection of the present application. The scope of protection of the present application is derived from the claims.

Claims

[1] A method of manufacturing a semiconductor superjunction device, comprising: Forming a first insulating layer (30) on an n-type substrate (20) and etching the first insulating layer (30) to form an opening (41); Forming an insulating side wall (31) in the opening (41); Etching the n-type substrate (20) using the first insulating layer (30) and the insulating sidewall (31) as a mask to form a first groove (42) in the n-type substrate (20); Forming a p-type pillar (21) in the first groove (42) such that the p-type pillar (21) and the n-type substrate (20) form a pn junction structure; forming a second insulating layer (32) on a surface of the p-type pillar (21); Etching away the insulating sidewall (31); and etching the n-type substrate (20) using the first insulating layer (30) and the second insulating layer (32) as a mask to form a second groove (43) in the n-type substrate (20), wherein an etching process combining anisotropic etching and isotropic etching is performed when the second groove (43) is formed by etching; Forming a gate dielectric layer (23) and a gate (24) in the second groove (43) such that the gate (24) is insulated from the p-type pillar (21) by the gate dielectric layer (23), and then etching away the first insulating layer (30) and the second insulating layer (32); Forming a p-type body region (34) in the n-type substrate (20); and Forming an n-type source region (25) in the p-type body region (34). [2] A method of manufacturing the semiconductor superjunction device according to claim 1, wherein the first insulating layer (30) comprises a silicon oxide layer. [3] A method of manufacturing the semiconductor superjunction device according to claim 1, wherein the second insulating layer (32) is a silicon oxide layer. [4] A method of manufacturing the semiconductor superjunction device according to claim 1, wherein the insulating sidewall (31) is a silicon nitride layer. [5] A method of manufacturing the semiconductor superjunction device according to claim 1, wherein a depth of the second groove (43) is less than a depth of the first groove (42).

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