Multi-stage non-volatile storage device based on silicon oxide-nitride oxide-silicon and method for its operation

Abstract

Method for operating a semiconductor device, comprising: - Accessing the semiconductor device, which contains multi-stage storage transistors arranged in rows and columns, wherein the multi-stage storage transistors include silicon-oxide-nitride-oxide-silicon (SONOS)-based charge-trapping transistors designed to store one of N x analog values ​​corresponding to the N levels of a threshold voltage, VT, and a drain current, ID, where N is a natural number greater than 2; - Selecting at least one of the multi-stage storage transistors for a write operation to a setpoint, wherein the setpoint is one of the N x analog values ​​and corresponds to a setpoint ID range extending from a setpoint ID lower bound, LL, to a setpoint ID upper bound, UL;- Performing a partial programming operation on the at least one of the multi-stage storage transistors for ID level reduction, wherein the partial programming operation comprises at least one soft programming operation and one padding programming operation, wherein the partial programming operation is designed to reduce the ID level and increase a VT level for the at least one of the multi-stage storage transistors, and wherein multi-stage storage transistors not selected for the partial programming operation are disabled, wherein an initial check read is performed after the partial programming operation to determine how a reduced ID level compares to a target ID mean;- Performing a partial erase operation on at least one of the multi-stage storage transistors to raise the ID level, wherein the partial erase operation comprises at least one of a soft erase operation, a selective soft erase operation, and an annealing erase operation, wherein the partial erase operation is designed to raise the ID level and decrease the VT level for at least one of the multi-stage storage transistors, and wherein multi-stage storage transistors not selected for the selective soft erase operation are disabled, wherein a second check read is performed after the partial erase operation to determine how a raised ID level compares to the target ID mean; and - Determining that the write operation to the target value is complete when the ID level of the at least one of the multi-stage storage transistors falls within the target ID range.

Description

CROSS-REFERENCE TO RELATED REGISTRATIONS

[0001] The present application is an international application of the non-provisional US application No. 16 / 827.948, filed on March 24, 2020, which claims the benefit under 35 USC § 119(e) of the provisional US application No. 62 / 940.547, filed on November 26, 2019, which is incorporated herein in its entirety by reference. TECHNICAL AREA

[0002] The present disclosure relates generally to non-volatile storage devices and in particular to the use of multi-stage silicon (semiconductor) oxide nitride oxide silicon (semiconductor) (SONOS)-based charge-trapping non-volatile memory (NVM) devices for analog operations including neuromorphic computing in artificial intelligence (AI) applications. BACKGROUND

[0003] Non-volatile memories are commonly used to store data in computer systems and typically consist of a memory array with a large number of memory cells arranged in rows and columns. In some embodiments, each of the memory cells can contain at least one non-volatile element, such as a charge-trapping field-effect transistor (FET) or a floating-gate transistor, which is programmed or erased by applying a voltage of the correct polarity, magnitude, and duration between a control / memory gate and the substrate or drain / source regions. In an n-channel charge-trapping FET, for example, a positive gate-to-substrate bias causes electrons to tunnel out of the channel and be trapped through Fowler-Nordheim (FN) tunnels in a charge-trapping dielectric layer, thereby increasing the threshold voltage (Vth). T) of the transistor is increased. A negative gate-to-channel voltage causes holes to tunnel out of the channel and be trapped in the charge-trapping dielectric layer, thereby increasing the V T The voltage of the SONOS transistor decreases.

[0004] In some embodiments, SONOS-based storage fields are used and operated as digital data storage devices, with binary bit data (0 and 1) based on two unique V T - or drain current (I D ) Levels or values ​​of the SONOS cells are stored.

[0005] There are calls to use NVM technology like SONOS for analog storage and processing, as it is configurable for multiple (more than two) V T - and I D-levels with achievable high precision. SONOS memory cells offer low latency, low power consumption, and low noise, which is desirable for analog processing, including inference calculations such as neuromorphic computing in artificial intelligence (AI) applications.

[0006] It is therefore an objective of the present invention to provide optimized bias conditions, operating procedures (erase, program, lock, etc.) and SONOS-based analog NVM devices and systems to enable the fine-tuning of multiple V T / I D -levels with narrow and unambiguous distributions (low distribution sigma “σ”) to be achieved. List of characters

[0007] The following detailed description, the accompanying drawings, and the claims set forth below will deepen the understanding of the present invention. The following applies: Fig.Figure 1A is a block diagram showing a side sectional view of a SONOS-based non-volatile storage transistor or device; Fig. Figure 1B illustrates a corresponding schematic diagram of the in Fig. 1A SONOS-based non-volatile storage transistor or such device shown; Fig. Figure 2 is a schematic diagram illustrating a SONOS-based non-volatile memory array according to an embodiment of the present disclosure; Fig. Figure 3A is a schematic diagram of a segment of a SONOS-based non-volatile memory field, illustrating an embodiment of a deletion process according to the present disclosure; Fig.Figure 3B is a schematic diagram of a segment of a SONOS-based non-volatile memory array illustrating an embodiment of a programming / locking operation according to the present disclosure; Fig. Figure 4 are representative graphs illustrating the distribution of threshold voltages and drain currents of programmed (Vtp and Idp) and erased (Vte and Ide) storage transistors in a SONOS-based non-volatile memory array according to an embodiment of the present disclosure; Fig. Figure 5 is a representative graph showing the distributions of the drain current level (I). D ) illustrated in a multi-stage SONOS-based non-volatile memory cell according to an embodiment of the present disclosure; Fig. 6 is a graphic that uniquely represents I D-Level of a SONOS-based storage transistor in a non-volatile memory array according to an embodiment of the present disclosure illustrated; Fig. Figure 7A is a graphic illustrating the distribution of trapped charges in the charge-trapping layer of a SONOS-based storage transistor in a non-volatile memory array according to an embodiment of the present disclosure; Fig. 7B is a graphic that I D -Distributions of SONOS-based storage transistors in a non-volatile memory array illustrated, where I D -Sigma- and retention deterioration according to an embodiment of the present disclosure are illustrated; Fig. Figure 8A is a schematic diagram of a segment of a SONOS-based non-volatile memory array illustrating an embodiment of a selective soft erase operation according to the present disclosure; Fig. Figure 8B is a schematic diagram of a segment of a SONOS-based non-volatile memory array illustrating an embodiment of a refill programming / locking operation according to the present disclosure; Fig. 9A and Fig. Figure 9B are schematic flowcharts showing an embodiment of a write operation for a multi-stage SONOS-based NVM field according to the present disclosure; Fig. 10 is a graph that clearly shows a decrease / increase in level I D -Level during a write operation of a SONOS-based storage transistor in a non-volatile memory array according to an embodiment of the present disclosure illustrated; Fig. Figure 11 is a schematic flowchart illustrating an embodiment of a write operation for a multi-stage SONOS-based NVM field according to the present disclosure; Fig.Figure 12 is a schematic flowchart illustrating an embodiment of a refill / annealing process for a multi-stage SONOS-based NVM field according to the present disclosure; Fig. Figure 13 is a schematic block diagram illustrating an embodiment of a multi-stage SONOS-based NVM device according to the present disclosure; Fig. Figure 14 is a representative block diagram illustrating an embodiment of a conventional digital multiplication-accumulation (MAC) system; Fig. Figure 15 is a representative diagram illustrating an embodiment of an artificial neuron of a deep neural network (DNN) system; Fig. Figure 16 is a schematic diagram illustrating an embodiment of an analog neural network (NN) accelerator according to the present disclosure; and Fig.Figure 17 is a schematic flowchart illustrating an embodiment of the operating procedure of the NN acceleration device in Fig. 16 illustrated. DETAILED DESCRIPTION

[0008] The following description presents numerous specific details, such as examples of particular systems, components, methods, and so on, to provide a good understanding of several embodiments of the subject matter under discussion. However, it is obvious to a person skilled in the art that at least some embodiments can be implemented without these specific details. In other cases, well-known components or methods are not described in detail or are presented in a simple block diagram format to avoid unnecessary ambiguity of the techniques described herein. Accordingly, the specific details presented here are merely exemplary. Specific implementations may deviate from these exemplary details and still be considered to be within the concept and scope of protection of the subject matter under discussion.

[0009] Unless expressly stated otherwise, as can be seen from the following explanations, the terms used in the description, such as "processing", "calculating", "calculating", "determining" or the like, refer to the actions and / or processes of a computer or computing system or similar electronic computing device that manipulate and / or convert data represented as physical, e.g. electronic, quantities in the registers and / or memories of the computing system into other data represented in a similar manner as physical quantities in the memories, registers or other information storage, transmission or display devices of the computing system. BRIEF DESCRIPTION OF THE SUBJECT

[0010] According to one embodiment of a method for operating a semiconductor device, the method may comprise the following steps: Obtaining the semiconductor device, which contains multi-stage storage transistors arranged in rows and columns, wherein the multi-stage storage transistors include silicon-oxide-nitride-oxide-silicon (SONOS) based charge-trapping transistors configured to store one of N x analog values ​​corresponding to the N levels of the threshold voltage (V T ) and the drain current (I D ) correspond, and where N is a natural number greater than 2; Selecting at least one of the multi-stage storage transistors for a write process to a setpoint, where the setpoint is one of the N x analog values ​​and a setpoint I D -area corresponds to a target value D -Lower limit (LL) to a target value D-Upper Limit (UL) extends; performing a partial programming operation on at least one of the multi-stage storage transistors for I D -Level reduction, where an initial test read is performed after the partial programming process to determine how a reduced I D -Level compared to a target I D -Average value is; performing a partial erase operation on at least one of the multi-stage storage transistors for I D -Level boost, where a second test read is performed after the partial erase operation to determine how a boosted I D -Level compared to the target I D -Mean value; and determine that the writing process to the target value is complete when the I D -Level of at least one of the multi-stage storage transistors in the target I D -area falls.

[0011] In one embodiment, the method can also include the step of blocking at least one of the multi-stage storage transistors from further programming and erasing operations after completion of the writing process to the setpoint, wherein the blocking includes reducing the magnitude of a gate-to-drain voltage or gate-to-substrate voltage of at least one of the multi-stage storage transistors.

[0012] In one embodiment, the partial programming process may comprise at least one soft programming process and one padding programming process, wherein the partial programming process may be configured to determine the I for the at least one of the multi-stage storage transistors. D -level to reduce and a V T -level to raise, and where multi-stage storage transistors that are not selected for the partial programming process can be disabled.

[0013] In one embodiment, the partial programming process can be performed for a considerably shorter duration than a full programming process, and the programming process can be configured to perform the I D -Level of the multi-stage storage transistors to a fully programmed I D -level to reduce, regardless of the initial I D -Levels of the multi-stage storage transistors.

[0014] In one embodiment, the partial erase process can include at least one of a soft erase process, a selective soft erase process, and an annealing erase process, wherein the partial erase process can be configured to provide the I for at least one of the multi-stage storage transistors. D -level and the V T -level to reduce, and where multi-stage storage transistors not selected for the selective soft erase process can be disabled.

[0015] In one embodiment, the soft erasure process and the selective soft erasure process can be performed for a considerably shorter duration than an erasure process, wherein the erasure process can be configured to... D -Level of the multi-stage storage transistors to a completely cleared I D -level to raise, regardless of the initial I D -Levels of the multi-stage storage transistors.

[0016] In one embodiment, the annealing quenching process can be carried out for a considerably longer duration than a quenching process, wherein the magnitude of a gate-to-drain voltage or a gate-to-substrate voltage of at least one of the multi-stage storage transistors during the quenching process can be greater than during the annealing quenching process.

[0017] In one embodiment, the method may further include a refill and annealing algorithm comprising the following steps: performing the soft erase process on the at least one of the multi-stage storage transistors after the write operation to the setpoint is complete; checking whether the I D -Level at least a level of target I D + X% has been reached, where X is in a range of 20–50; performing the fill programming procedure on at least one of the multi-stage storage transistors; checking if the I D -Level at most a target level of target I D - Y% has been reached, where Y is in a range of 10-20; Performing the annealing quenching process on at least one of the multi-stage storage transistors; Checking the I D-level of each of the at least one multi-stage storage transistor; selection and execution of the selective soft erase process only on the at least one of the multi-stage storage transistors that has an I D -level that is lower than the target I D -LL is, and blocking the unselected multi-stage storage transistor; and checking if the I D -Level of at least one multi-stage storage transistor back to the target I D -Level range has been restored.

[0018] In one embodiment, the filling and annealing algorithm can be configured to perform the I D -Level of at least one multi-stage storage transistor within the target I D-area to maintain while charges in shallow traps are replaced by charges in deep traps in a charge-trapping layer of the at least one multi-stage storage transistor, wherein the refill programming operation can facilitate charges in deep traps by applying a high gate-to-drain voltage and a short programming pulse to the at least one of the multi-stage storage transistors, and wherein the annealing quench operation can be configured to empty charges in shallow traps over Fowler-Nordheim tunnels by applying a low gate-to-drain voltage and a long quench pulse to the at least one of the multi-stage storage transistors.

[0019] In one embodiment, at least one of the multi-stage storage transistors can be arranged in the same row or column.

[0020] According to one embodiment of a method for operating a semiconductor device, the method may comprise the following steps: selecting a first NVM cell of a SONOS-based NVM array for a selective soft erase operation, wherein the SONOS-based NVM array comprises NVM cells arranged in rows and columns, and wherein NVM cells of adjacent first and second columns are coupled by a first common source line; generating and coupling a first negative voltage to a first SONOS word line in a first row of the SONOS-based NVM array and a positive voltage to a first bit line in the first column to apply a gate-to-drain bias to a first NVM transistor in the first NVM cell to partially erase the first NVM cell by means of Fowler-Nordheim (FN) tunneling, wherein a drain current level (I D ) and a threshold voltage level (V T) of the first NVM transistor is raised or reduced; and coupling a reverse voltage to a second bit line in the second column to reduce the gate-to-drain bias on a second NVM transistor in a second NVM cell in the first row that is not selected for the selective soft erase operation, wherein the reverse voltage has the same polarity and a smaller magnitude than the first negative voltage, and wherein the second NVM transistor has approximately the same I before and after the selective soft erase operation. D - and V T -level.

[0021] In one embodiment, the method can also include the step of coupling a ground voltage to a second SONOS word line in a second row of the SONOS-based NVM field in order to deselect all NVM cells in the second row for the selective soft erase process.

[0022] In one embodiment, the method may also include the steps of generating and coupling a second negative voltage to a first word line in the first row and a shallow positive well (SPW) node of the SONOS-based NVM array to turn off a first field-effect transistor (FET) in the first NVM cell and a second FET in the second NVM cell, the second negative voltage being of a smaller magnitude than the first negative voltage; and coupling the positive voltage to a deep negative well (DNW) node.

[0023] In one embodiment, each of the NVM cells can contain an NVM transistor configured to store one of N x values, which are N x levels of I D - and V T-levels correspond, where N is a natural number greater than 2, and where the selective soft erase process can be configured to set the I for the first NVM transistor D -level and the V T -level to reduce so that its stored value changes from a first value to a second value, where the second value can be greater than the first value.

[0024] In one embodiment, each of the N x levels of I can be D - and V T -levels contain a distribution, with two adjacent I D - or V T -Distributions can have an overlap frequency of less than 3% and where the N x levels of I D - and V T -Levels can be linear, incremental, or decremental.

[0025] According to one embodiment of a semiconductor device, the device can be a SONOS-based NVM array containing NVM cells arranged in rows and columns, wherein each NVM cell can include an NVM transistor and a field-effect transistor (FET), and wherein each NVM transistor can be configured to store N x analog values ​​corresponding to the N x levels of its drain current levels (ID). D ) or threshold voltage level (V T) correspond; a digital-to-analog (DAC) function that receives and converts digital signals from external devices, wherein the converted digital signals may be configured to cause the reading of an analog value stored in at least one column of at least one NVM cell; a column multiplexer (Mux) function that is configured to select and combine the analog value read from the at least one NVM cell; and include an analog-to-digital (ADC) function that is configured to convert analog results of the column multiplexer function into digital values ​​and output the digital values.

[0026] In one embodiment, the N x analog values ​​can be written into the NVM transistors by a series of partial programming and selective partial erasing operations, wherein the selective partial erasing operations can be configured to set the I for selected NVM transistors of an equal series D -level and the V T -level to reduce while simultaneously blocking unselected NVM transistors in the same series.

[0027] In one embodiment, each of the partial programming operations and the selective partial deletion operations can be followed by a read operation to check whether the I D - or V T -Level of the selected NVM transistors, the target I D - and target value T have reached the -level.

[0028] In one embodiment, a plurality of semiconductor devices can be arranged and interconnected on the same semiconductor chip, wherein each of the plurality of semiconductor devices can be configured to perform multiply accumulate (MAC) operations based on the analog values ​​stored in the NVM cells and the digital inputs from at least one other semiconductor device of the plurality of semiconductor devices.

[0029] In one embodiment, a first subset of the plurality of semiconductor devices outputs digital results of the MAC operations, wherein the digital results of the first subset are coupled to a second subset of the plurality of semiconductor devices as digital inputs.

[0030] In one embodiment, the multitude of semiconductor devices can be configured to act as artificial neurons in a deep neural network (DNN) that performs neuromorphic computing in an artificial intelligence (AI) application. DESCRIPTION OF EXECUTION FORMS

[0031] Fig. 1A is a block diagram illustrating a side sectional view of a non-volatile memory cell, and the corresponding schematic diagram is in Fig.Figure 1B illustrates that a non-volatile memory (NVM) array or device may contain NVM cells with a non-volatile memory transistor or device implemented using silicon (semiconductor) oxide nitride oxide silicon (semiconductor) (SONOS) or floating-gate technology, and a regular field-effect transistor (FET) arranged adjacently or coupled together.

[0032] In one embodiment, which is in Fig. As illustrated in Figure 1A, the non-volatile storage transistor is a charge-trapping non-volatile storage transistor of the SONOS type. As shown in Fig.As shown in Figure 1A, the NVM cell 90 comprises a stack of NV transistors 94 with a control gate (CG) or a memory gate (MG) formed above the substrate 98. The NVM cell 90 further comprises source 97 / drain 88 regions formed in the substrate 98 or optionally within the shallow positive well (SPW) 93 in the substrate 98 on both sides of the NV transistor 94. The SPW 93 may be at least partially encapsulated in the deep negative well (DNW) 99. In one embodiment, the source / drain regions 88 and 97 are connected by the channel region 91 below the NV transistor 94. The NV transistor 94 contains a dielectric oxide tunnel layer, a charge-trapping nitride or oxynitride layer 92 and an oxide cover or barrier layer, forming the ONO stack.In one embodiment, the charge-trapping layer 92 can be multilayered and trap the charges injected from the substrate 93 through FN tunnels. The V. T - and I D The values ​​of the NV transistor 94 can change, at least partially, due to the amount of trapped charge. In one embodiment, a layer with a high dielectric constant can form at least a section of the depletion region. A poly-silicon (Poly) or metal gate layer lies above the ONO layer and can serve as a control gate (CG) or storage gate (MG). As in Fig.As best illustrated in Figure 1A, the NVM cell 90 further comprises a FET 96 arranged adjacent to the NV transistor 94. In one embodiment, the FET 96 comprises a metal or polysilicon select gate (SG) located above a dielectric oxide or gate layer with a high dielectric constant. The FET 96 further comprises source / drain regions 86 and 97 formed in the substrate 98 or optionally in the recess 93 in the substrate 98 on both sides of the FET 96. As shown in Fig. As shown in Figure 1A, the FET 96 and the NV transistor 94 share the intervening source / drain region 97, which is also referred to as the internal node 97. The SG is biased appropriately by VSG to open or close the channel 95 below the FET 96. The in Fig.1A illustrated NVM cell 90 is considered to have a two-transistor (2T) architecture, in which the NV transistor 94 and the FET 96 can be considered in this patent specification as a storage transistor and as a selection or pass transistor, respectively.

[0033] In one embodiment, it shows Fig. 1B is a SONOS NVM cell 90 with two transistors (2T), in which the non-volatile (NV) transistor 94 is connected in series with the FET 96. The NVM cell 90 is programmed (bit value "1") when the CG is passed through V CG is pre-stressed accordingly, or by applying a positive pulse to the CG with respect to the substrate 98 or the well 93, which causes electrons to be injected from the inversion layer through FN tunnels into the charge-trapping layer 92. The charge trapped in the charge-trapping layer 92 leads to an electron depletion between the drain 88 and the source 97, thereby increasing the threshold voltage (VT ), which is required to switch on the SONOS-based NV transistor 94, and the device is put into a “programmed” state. The NVM cell 90 is activated by applying an opposing bias voltage V CGThe control gate (CG) is erased by a positive pulse at the CG with respect to substrate 98 or well 93, thereby tunneling FN holes from the accumulated channel 91 into the ONO stack. Programmed and erased threshold voltages are designated "Vtp" and "Vte," respectively. In one embodiment, the NV transistor 94 can also be in a blocking state (bit value "0") in which a previously erased cell (bit value "0") is prevented from being programmed (bit value "1") by applying a positive voltage to the source and drain of the NVM cell 90 while the control gate (CG) is positively pulsed with respect to substrate 98 or well 93 (as in the programming state). The threshold voltage (designated "Vtpi") of the NV transistor 94 becomes slightly more positive due to the disturbing vertical field but remains erased (or blocked).In one embodiment, Vtpi is also determined by the ability of the charge-trapping layer 92 of the ONO stack to retain the trapped charges (holes for the erased state) within the charge-trapping layer 92. If the charge traps are shallow, the trapped charges tend to dissipate, and the Vtpi of the NV transistor 94 becomes more positive. In another embodiment, the Vtpi of the NV transistor 94 tends to decay or creep upon further blocking operations. It is understood that the assignment of the bit or binary values ​​"1" and "0" to the respective "programmed" and "erased" states of the NVM cell 90 is here for illustrative purposes only and is not intended as a limitation. In other embodiments, the assignment may be reversed or configured differently.In another embodiment, which will be explained in more detail in a later section, the NVM cell 90 can be configured to store one of several analog values ​​(other than “0” and “1”) by changing its threshold voltage or drain current level.

[0034] In another embodiment, the NV transistor 94 can be a floating-gate MOS field-effect transistor (FGMOS) or a similar device. In general, an FGMOS is constructed similarly to the SONOS-based NV transistor 94 described above, with the main difference being that an FGMOS incorporates a polysilicon (poly) floating gate capacitively coupled to the device's inputs instead of a charge-trapping nitride or oxynitride layer 92. The FGMOS device can therefore be described with reference to Fig. 1A and Fig. 1B described and operated in a similar manner.

[0035] Similar to the SONOS-based NV transistor 94, the FGMOS device can be operated by applying a suitable bias voltage V CG between the control gate and the source and drain areas, thereby setting the threshold voltage V required to switch on the FGMOS device. T is increased. The FGMOS device can be increased by applying an opposing bias V. CG be deleted at the tax gate.

[0036] In one embodiment, the source / drain region 86 can be considered the “source” of the NVM cell 90 and is connected to V SL coupled, while the source / drain area 88 is considered a "drain" and connected to V BL is coupled. Alternatively, SPW 93 is available with V SPW and DNW 99 with V DNW coupled.

[0037] The FET 96 can prevent the injection of hot carrier electrons and junction breakdown during programming or erasing operations. The FET 96 can also prevent large currents from flowing between the source 86 and the drain 88, which can cause high power consumption and parasitic voltage drops in the memory array. As shown in Fig. As shown in Figure 1A, both the FET 96 and the NV transistor 94 can be n-type or n-channel transistors, with the source / drain regions 86, 88, 97 and DNW 99 being doped with n-type material, while SPW 93 and / or the substrate 98 are doped with p-type material. It goes without saying that the NVM cell 90 can additionally or alternatively contain p-type or p-channel transistors, with the source / drain regions and the well being doped oppositely or differently, as is common practice.

[0038] A memory array is constructed by fabricating a grid of memory cells, e.g., NVM cells 90, arranged in rows and columns and connected by a number of horizontal and vertical control lines to peripheral circuitry such as address decoders and comparators, including analog-to-digital (ADC) and digital-to-analog (DAC) functions. Each memory cell contains at least one non-volatile semiconductor device, as described above, and may have a one-transistor (1T) or two-transistor (2T) architecture, as shown in Fig. 1A described.

[0039] Fig. Figure 2 is a schematic diagram representing an NVM field according to one embodiment of the subject matter. In one embodiment, which is described in Fig.As illustrated in Figure 2, the memory cell 90 has a 2T architecture and, in addition to a non-volatile storage transistor, contains a pass-through or select transistor, e.g., a conventional MOSFET, which shares a common substrate connection or internal node with the storage transistor. In one embodiment, the NVM array contains 100 NVM cells 90 arranged in N rows or sides (horizontally) and M columns (vertically). NVM cells 90 in the same row can be considered to be on the same side. In some embodiments, several rows or sides can be grouped together to form memory sectors. The terms "rows" and "columns" of a memory array are used for illustration and not for limitation. In one embodiment, the rows are arranged horizontally and the columns vertically.In another embodiment, the terms for rows and columns of the memory array can be used in reverse or in the opposite direction, or arranged in any orientation.

[0040] In one embodiment, a SONOS word line (WLS) is coupled to all CGs of NVM cells 90 in the same row, while a word line (WL) is coupled to all SGs of NVM cells 90 in the same row. A bit line (BL) is coupled to all drain areas 88 of the NVM cells 90 in the same column, while a common source line (CSL) or common area 86 in one embodiment is coupled to or shared by all NVM cells in the array. In an alternative embodiment, a CSL can be connected between two paired NVM cells, such as C1 and C2, as shown in Fig.As shown in 3A, the same row is shared. A CSL also couples to common source areas of all NVM pairs of the same two columns.

[0041] In flash mode, a write operation can consist of a full erase operation on a selected row (page), followed by programming or locking operations on individual cells in the same row. The smallest block of NVM cells that can be erased at once is a single page (row). The smallest block of cells that can be programmed / locked at once can also be a single page.

[0042] As in Fig. As shown in Figure 2, the NVM cells 90 can be arranged in pairs, such as the NVM cell pair 200. In an embodiment as shown in Fig. 3A, Fig. 3B, Fig. 8A and Fig.As best illustrated in Figure 8B, the NVM cell pair 200 contains two NVM cells 90 with a mirrored orientation, so that selected transistors of each NVM cell, e.g., C1 and C2, are located adjacent to each other. NVM cells 90 of the same NVM cell pair 200 can also use a common source area, which carries the voltage signal V. CSL receives.

[0043] Fig.Figure 3A illustrates a 2 × 2 array 300 of the NVM array 100 to demonstrate an embodiment of an erase operation or a hard erase operation according to the present disclosure. As already explained, the NVM array 100 can adopt a common source line (CSL) configuration. In one embodiment, a single CSL (e.g., CSL0) is shared by all NVM cells in the NVM array or at least by NVM cells (e.g., C1 and C2) of adjacent columns. In another embodiment, the CSLs can be arranged and shared between selection transistors of the NVM cells 90 of adjacent columns. For the sake of clarity and simplicity, the following description assumes that all transistors in the NVM array 100, including the 2 × 2 array 300, are N-type transistors.Without loss of generality, it should be noted that a P-type configuration can be described by reversing the polarity of the applied voltages and that such a configuration is among the embodiments of the disclosure under consideration. Furthermore, the voltages and pulse durations used in the following description are chosen for simplicity and represent only an exemplary embodiment of the subject matter. Other voltages may be used in other embodiments.

[0044] Fig. Figure 3A illustrates an exemplary embodiment of a segment of the NVM array 100, which can be part of a large memory array of memory cells. Fig.3A comprises the 2 × 2 memory array 300 with at least four memory cells C1, C2, C3, and C4, arranged in two rows and two columns. The NVM cells C1–C4 can be arranged in two adjacent columns (shared source line CSL0), but also in two adjacent or two non-adjacent rows. Each of the NVM cells C1–C4 can be structurally similar to the NVM cell 90 described above.

[0045] Each of the NVM cells C1-C4 can contain a Sonos-based storage transistor and a selection transistor. Each storage transistor has a drain coupled to a bit line (e.g., BL0 and BL1), a source coupled to a drain of the selection transistor, and, via the selection transistor, to a single common source line (e.g., CSL0). Each storage transistor also contains a control gate coupled to a Sonos word line (e.g., WLS0). The selection transistors each contain a source connected to the common source line (e.g., CSL0) and a selection gate coupled to a word line (e.g., WL0).

[0046] In Fig.For example, in 3A, side 0 is selected for erasure and side 1 is not selected for an erasure operation. As previously explained, a single side can be the smallest block of NVM cells 90 that is erased in a single operation. Therefore, all NVM cells, including C1 and C2, in a selected row (side 0) are erased at once by applying the appropriate voltages to a SONOS word line (WLSO) shared by all NVM cells in the row, to the substrate connection, and to all bit lines in the NVM array 100. In one embodiment, a negative voltage V is applied. NEG at WLS0 and a positive voltage P VOS applied to the substrate or the p-well via SPW and the deep n-well DNW of all NVM cells in side 0, all bit lines including BL0 and BL1, and the common source lines including CSL. Therefore, a full erase voltage (V) is applied. NEG - V POSA voltage is applied between the CGs and the substrate / P depressions of the storage transistors in C1 and C2 for a pulse duration (Te - 10 ms) to clear any trapped charges (if present). In one embodiment, all word lines, including WL0 and WL1, are supplied with a voltage V PWR coupled.

[0047] If a page (series), continue with reference to Fig. If 3A is not selected for a deletion process, e.g., page 1, a positive voltage V is applied instead. POS applied to WLS1, so that the CGs at the substrate / P depressions of the storage transistors in side 1 including C3 and C4 are approximately 0 V (V POS - V POS ). Therefore, the state of the NVM cells from page 1 remains unchanged (not deleted).

[0048] Table I shows exemplary bias voltages that can be used for a full erase operation of page / row 0 of a non-volatile memory with a 2T architecture, containing memory cells with N-type SONOS transistors and CSLs similar to a 2 x 2 array 300. Table I node Voltages (V) Voltage range (V) WLS0 In NEG , e.g. -3.8 V -4.0 V to -3.2 V BL0 In POS , e.g. +4.2 V +3.8 V to +4.6 V WL0 In PWR , e.g. +1.1 V +1.0 V to +1.2 V SPW In POS , e.g. +4.2 V +3.8 V to +4.6 V DNW In POS , e.g. +4.2 V +3.8 V to +4.6 V CLS0 In POS , e.g. +4.2 V +3.8 V to +4.6 V WLS1 In POS , e.g. +4.2 V +3.8 V to +4.6 V BL1 In POS , e.g. +4.2 V +3.8 V to +4.6 V WL1 In PWR , e.g. +1.1 V +1.0 V to +1.2 V

[0049] Fig. Figure 3B illustrates an exemplary embodiment of a 2 × 2 field segment 300 of the NVM field 100 during a programming or hard programming operation. Fig. For example, in 3B, NVM cell C1 is the target cell to be programmed or written to a logical "1" state (i.e., programmed to an OFF state), while NVM cell C2, which may have already been erased to a logical "0" state by a previous erasure operation, as in Fig.3A is represented, and is held in a logical "0" or ON state. It goes without saying that C1 and C2, shown for illustration as two adjacent cells, can also be two separate NVM cells in the same row, e.g., row 0. These two objectives (programming C1 and locking C2) are achieved by applying an initial or positive high voltage (V). POS ) at WLS0 in side or row 0 of the NVM array 100 is reached; a second or negative high voltage (V NEG ) is applied to BL0 to bias the storage transistor of C1 when programming the selected memory cell, while a blocking voltage (V) INHIB) is applied to BL1 and DNW to bias the storage transistor of C2 when blocking the programming of the unselected memory cell(s), and a common voltage is applied to the common substrate or p-well SPW of all NVM cells and the word lines (WL1 and WL2) which is connected to the second or negative high voltage (V NEG ) are coupled. In one embodiment, the common source line CSL0 between C1 and C2, or between all NVM cells 90, can be connected to a third high voltage or CSL voltage (V). CSL ) are either lying or potential-free. In one embodiment, the third high voltage V can be CSL exhibit a voltage level or absolute quantity that is less than V POS or V NEG is. In one embodiment, V CSL generated by a dedicated circuit with a DAC in the storage device (not shown). V CSLcan have an approximately equal voltage level or an approximately equal absolute quantity as the boundary voltage V MARG exhibit, which will be explained in more detail in later sections. If V POS When the positive V is applied to the storage transistor of C2 via WLS0, the positive V INHIBA voltage is transferred to BL1 and its channel. This voltage reduces the gate-to-drain / channel bias at the storage transistor of C2, thereby reducing the programming field so that the shift in the threshold voltage of Vte is small. Any charge tunneling that may still occur is called blocking disturbance and is quantified as (Vte - Vtpi). In one embodiment, as a result of the programming process, all NVM cells of page 0, including C1 and C2, can reach a binary state of "1" (programmed - Vtp) or "0" (blocked - Vtpi), based on the bit line voltage the NVM cell receives. NVM cells in unselected pages, such as page 1, may retain the binary state "0" (erased - Vte).

[0050] Furthermore, as described in more detail below, a selected edge stress (V) is applied MARG ) with a voltage level or absolute quantity less than V NEGis applied to WLS1 in an unselected row or page (e.g., page 1) to reduce or substantially eliminate the programmed bit line disturbance in the unselected NVM cell C4 due to the programming of the selected C1. In one embodiment, the absolute voltage level or absolute magnitude of V can be MARG with V CSL be identical.

[0051] Table II shows exemplary bias voltages that can be used to program a non-volatile memory with a 2T architecture, containing memory cells with N-type SONOS transistors and CSLs. Table II node Voltages (V) Voltage range (V) WLS0 In POS , e.g. +4.2 V +3.8 V to +4.6 V BL0 In NEG , e.g. -3.8 V -4.0 V to -3.4 V WL0 In NEG , e.g. -3.8 V -4.0 V to -3.4 V SPW In NEG , e.g. -3.8 V -4.0 V to -3.4 V DNW In INHIB , e.g. +1.1 V +1.0 V to +1.2 V CLS0 Float / V MARG , e.g. -2.4 V -3.0 V to -2.0 V WLS1 In MARG , e.g. -2.4 V -3.0 V to -2.0 V BL1 In INHIB , e.g. +1.1 V +1.0 V to +1.2 V WL1 In NEG , e.g. -3.8 V -4.0 V to -3.4 V

[0052] In general, the edge stress (V) MARG ) the same polarity as the second high voltage or V NEG , but is one voltage higher or more positive than V NEG , which are at least equal to the threshold voltage (V T) of the storage transistors, for which the disturbance of the programmed state bit line is reduced.

[0053] Fig. Figure 4 shows the distributions of Vtp and Vte as well as the drain current for programmed (I DP ) and deleted (I DE ) Cells in an example SONOS-based NVM array, such as NVM array 100. A typical write operation includes a delete operation or a hard delete operation, as in Fig. 3A described, followed by a hard programming / locking operation, as described in Fig. 3B described. In one embodiment, after a reliable read operation, it can be determined that the NVM cell is in one of the two unambiguous binary states (“0” or “1”). The in Fig. The deletion process described in 3A can also be considered a hard deletion, since it removes the V T / I D the deleted NVM cells (e.g. C1 and C2) to the levels "Deleted V T / I D“(complete deletion) shifts, regardless of the initial V T / I D -levels of these cells. Similarly, the in Fig. The programming process described in 3B can be considered a hard programming process. In one embodiment, no check or read operation may take place between the hard erase and hard program / lock operations.

[0054] Fig. 5 is a schematic diagram showing several unique drain current levels (I D ) of NVM memory cells in a SONOS-based NVM analog device according to an embodiment of the disclosure described herein. In one embodiment, I D The state of an NVM cell can be determined or checked via the WLSs by applying a predetermined voltage to the CG of the SONOS transistor and read out via the BLs. In other embodiments, I Dcan be determined by other methods known and practiced in engineering. Similar to V T can I D This can be used to determine the binary state of NVM cells 90 in embodiments where the NVM field 100 is used as a digital storage device, such as NOR flash, EEPROM, etc. In other embodiments, the NVM field 100 can be used in analog devices by storing one of several (more than two) analog values. With reference to Fig. 4 and Fig. 5. The NVM cells 90 of the NVM field 100 can be modified using hard programming and erasing operations, as described in Fig. 3A and Fig. 3B described, on several (more than two) I D - or V T-Levels (corresponding to the trapped charges in the charge-trapping layer 92) are written instead of writing one of the two binary values ​​("0" and "1") to the NVM cells 90, using a series of partial programming and partial erasing operations. In some embodiments, by changing the voltage difference or bias applied to the CG and the drain or the substrate, as well as the pulse duration, partial programming and erasing operations can cause V to T / I D the target NVM cells in the direction of the programmed V T / I D -level or of the deleted V T / I D -levels move (or easily reach them). Partial programming and erasing operations include, but are not limited to, soft programming, padding programming, soft erasing (row), selective soft erasing (cell), and burn-in erasing (row), which are explained below.

[0055] In one embodiment as in Fig. As best illustrated in Figure 5, the NVM cells 90 can be configured in an analog configuration / analog mode to function according to their I D -level one of the 2 n (4, 8, 16, ..., 128, etc.) values ​​to represent or store, where n is a natural number greater than 1. In another embodiment, the NVM cells 90 can be configured to represent one of any number of values ​​greater than two. In one embodiment, I D 1 to I D 2 n the middle I D -Values ​​of the 1st to 2nd n -ten I D -Distribution. In each I D -Distribution can be a lower I D -limit and an upper I D -limit (see I D 1) be present. The 1. I D -Distribution can be similar to the distribution of programmed cells σ3 and the 2 n -te I D-Distribution of the deleted cells σ4 in Fig. 4. In some embodiments, the middle I D - or V T Values ​​and their upper and lower limits are specified according to the system design and requirements. In one embodiment, the I D -Operating range of the NVM field approximately 100 (I D 2n-I D 1) amount to, e.g. 1.60μA−50nA=1.550nA.

[0056] It goes without saying that the I D The range of 1,550 nA is merely an example and can assume any other value depending on the NVM cells, operating voltages and pulse durations, as well as system requirements and design. In one embodiment, the NVM field 100 can be set by writing NVM cells 90 to a specific I D -Level within the I D-Operating range, e.g., 1.60 µA to 50 nA, can be used as an analog storage device. In one embodiment, someone with normal technical knowledge would understand that the same concept applies to writing multiple (more than two) V T -Level in NVM cells 90 can apply.

[0057] To avoid multiple unique I D -level within a finite I D -Operating range, in one embodiment it may be necessary that each I D -Distribution exhibits a narrow distribution (low sigma σ), such that adjacent I D -Distributions are clearly separated from each other, especially when n is a large number. The I D Different levels can also be linearly incremental, such that ΔI D in Fig. 5 is approximately constant to enable accurate and efficient read / verify operations. SONOS-based cells, such as NVM Cell 90, are due to their inherently low I D / VT -Sigmas and their low power consumption (V CC (0.81 V - 1.21 V) is a good candidate for multi-stage analog memory. Since both programming and erasing operations (both hard and soft) are performed in SONOS-based cells using FN tunnels, very fine tuning of the I is also possible. D / V T -Levels with very low sigma can be achieved. Furthermore, SONOS-based cells can exhibit very robust continuous performance in the temperature range of -40 °C to 125 °C with minimal degradation after 100,000 cycles, meeting the requirements of most consumer, industrial, and automotive applications. In one embodiment, overlaps of the I D -Values ​​502 between adjacent I D Distributions are coming. To ensure a reliable and accurate reading of the I D To reach a level of 90 in the NVM cells, the sigma σ of the I D-Distribution can be reduced to approximately below 8 nA or other current values, so that the overlap range 502 is kept below 1%–3% of the distributions. Depending on the distance between the I D The sigma value can be higher or lower depending on the signal level. In some cases, a sigma value of 50 nA may be sufficient to keep the overlap area below 1% to 3% of the distribution.

[0058] Fig. 6 is a graphic that shows 16 (2 4 ) I D -Level of an NVM cell according to an embodiment of the present disclosure illustrated. As in Fig. 6 best illustrated, are the I D -Levels are clearly separated (low sigma) and incrementally linear to ensure high functionality of the multi-stage NVM cells as an analog device.

[0059] As previously explained, a conventional write sequence, such as a hard erase and a hard programming sequence, may not be precise enough to define a specific I D / V T -levels from multiple (more than two) levels into NVM cells. In one embodiment, a sequence of hard programming, hard erasing, partial programming, and partial erasing operations may be required to achieve a precise I D / V T -level to write into an NVM cell, such as the NVM cell 90.

[0060] Fig. Figure 7A is a schematic diagram illustrating the distribution of the trap density from the valence band to the conduction band in the charge-trapping nitride layer of a SONOS transistor according to the present disclosure. Fig. 7 is a graphic showing potential impacts on the I D -Distribution in multi-stage NVM cells due to I D- and retention deterioration is illustrated. Although the beginning-of-life (BOL) sigma of the SONOS transistors 94 can be very low, over time, especially at high temperatures, there can be a significant deterioration in retention. As a result, I D -distributions (e.g. I) D 1 and I D 2) be more widely dispersed (increased sigma), and adjacent I D -Distributions can have a larger overlap proportion 710 in Fig. 7B (e.g., more than 3%), which can lead to incorrect readings of levels or values. In one embodiment, the sigma degradation can be attributed to the fact that the trapped charges in “shallow” traps in the nitride layer 92 are lost during retention, while the trapped charges in “deep” traps remain trapped. The loss of trapped charges during retention can also lead to the I D-level shifted upwards, such as I D 8 and I D 8' in Fig. 7B. Although the beginning-of-life (BOL) sigma of the SONOS transistors 94 can be very low, a significant deterioration in retention can occur over time, especially at high temperatures. Referring to Fig. 7A, with conventional write algorithms that use only hard erase and program operations, such as those used in NOR flash or EEPROM, charges tend to be trapped in both shallow and deep traps. In one embodiment, more charges can be trapped in deep traps with a write algorithm that uses a series of partial erase / program operations, such as soft erase, soft programming, selective soft erase, annealing erase, and padding programming. D / V T to bring NVM cells closer to their respective target values, as in Fig. 9A, Fig. 9B, Fig. 11 and Fig. 12 described, and to support the redistribution of charges from shallow traps to deep traps. In one embodiment, the partial clearing and programming operations can empty the charges from the shallow traps and fill deep traps instead. As a result, both the I D / V T -Sigma deterioration as well as the retention of NVM cells are improved, while the target I D / V T -Level remains the same.

[0061] The retention and I D / V T-Sigma degradation can also be improved by modifying the manufacturing process, thereby reducing the density of shallow traps in the charge-trapping layer. In one embodiment, improvements to the manufacturing process can include smoothing the curvature of the shallow trench insulation (STI) corners in SONOS transistors, optimizing the doping profile in the channels, and improving the oxide layers, among other things. Soft deletion process:

[0062] In one embodiment, the operating voltages coupled to different nodes for a soft erasing process are similar to those in a hard erasing process, as previously described in Fig. 3A described. Therefore, a full quenching bias voltage of 8 V (V) is still maintained between the CGs and the substrate / drain. NEG - V POS) pressed. In contrast to the hard erase process, the duration of the WLS pulse (e.g., WLSO, WLS1) is considerably shorter (Tse ~ 20 µs) for a soft erase pulse, compared to Te ~ 10 ms for a hard erase process. Despite the same bias difference between CG and drain (e.g., -8 V), the shorter soft erase pulse can reduce the I D -Only increase the level of the NVM cells in the selected row 0 (e.g., C1, C2), e.g., from L4 to L2 in Fig. 10, but not on the Deleted-I D -level. In one embodiment, a soft deletion process can only be performed for the entire selected row. quenching process:

[0063] The general purpose of an annealing quenching process is to free charges in shallow traps to improve post-retention performance. Table III shows exemplary biases that can be used for an annealing quenching process from page / row 0 of a non-volatile memory with a 2T architecture, incorporating memory cells with N-type SONOS transistors and CSLs similar to the 2 × 2 array 300, as best described in Fig. 3A is shown. Table III node Voltages (V) Voltage range (V) WLS0 In NEG , e.g. -3.8 V -4.0 V to -2.0 V BL0 In AEPOS , e.g. +2.2 V +1.8 V to +2.4 V WL0 In PWR , e.g. +1.1 V +1.0 V to +1.2 V SPW In AEPOS , e.g. +2.2 V +1.8 V to +2.4 V DNW In AEPOS , e.g. +2.2 V +1.8 V to +2.4 V CLS0 In AEPOS , e.g. +2.2 V +1.8 V to +2.4 V WLS1 In AEPOS , e.g. +2.2 V +1.8 V to +2.4 V BL1 In AEPOS , e.g. +2.2 V +1.8 V to +2.4 V WL1 In PWR , e.g. +1.1 V +1.0 V to +1.2 V

[0064] In one embodiment, in contrast to the extinguishing and soft extinguishing processes, a softer extinguishing preload (V) is used. NEG - V AEPOS ) between the CGs and the substrate / drain, since V AEPOS a smaller size than V POSThe softer or lower quenching voltage (e.g., 6 V versus 8 V) is applied to CGs for a much longer pulse duration (Tae ~ 50 ms). In one embodiment, the longer and softer quenching pulse can help remove charges in shallow traps that are closer to the conduction band. In another embodiment, an annealing quenching process can be performed only for the entire selected array. Selective soft deletion:

[0065] Fig. Figure 8A illustrates a 2 × 2 field 800 of the NVM field 100 to demonstrate an embodiment of a selective soft erasure process according to the present disclosure. In one embodiment, the 2 × 2 field 800 can be configured similarly to the 2 × 2 field 300 in Fig. 3A and Fig.3B. For the sake of clarity and simplicity, the following description assumes that all transistors in the 2 × 2 array are 800 N-type transistors. Without loss of generality, it should be noted that a P-type configuration can be described by reversing the polarity of the applied voltages, and that such a configuration is among the embodiments of the disclosure under consideration. Furthermore, the voltages used in the following description are chosen for simplicity and represent only one exemplary embodiment of the subject matter. Other voltages may be used in other embodiments.

[0066] As in Fig.As outlined in Figure 8A, the 2 × 2 memory array 800 comprises at least four memory cells C1, C2, C3, and C4 arranged in two rows and two columns. The NVM cells C1–C4 can be arranged in two adjacent columns (shared source line CSL0), but also in two adjacent or two non-adjacent rows. Each of the NVM cells C1–C4 can be structurally similar to the NVM cell 90 described above. With reference to Fig. 3A, Fig. 3B and Fig. 5 can be a hard deletion process, as in Fig. 3A described, the I D the deleted NVM cells on the Deleted-I D -level in Fig. Raise 5, and similarly, a hard programming process can be applied to the programmed I D -level in Fig. 5 increase. In one embodiment, the deleted and programmed I D -Level above the operating range of I D 1 to I D 2 nbeyond the NVM field 100. In another embodiment, one of the deleted and programmed I D -Levels are within the operating range.

[0067] In Fig. For example, in 8A, page 0 is selected for partial erase / lock, and page 1 is not selected for a selective soft erase (SSE) / lock operation. Unlike the previously explained hard, soft, and burn-out erase operations, where a single page or row is the smallest erase block of NVM cells 90, a single NVM cell / bit, or multiple NVM cells / bits in the same row (e.g., page 0), can be selected for a selective soft erase. The unselected NVM cells (e.g., C2) can be locked instead. Therefore, the I D-Levels of only selected NVM cells, including C1, in a selected row (side 0) are increased (partially erased) by applying the appropriate voltages to a SONOS word line (WLSO) shared by all NVM cells in row 0, to the substrate terminals, and to all bit lines in NVM array 100. In one embodiment, a negative voltage is applied for selective soft erase (SSE) V. SSENEG A positive SSE voltage VSSEPOS is applied to WLS0 and to BL0 and DNW of all NVM cells on side 0. In one embodiment, V SSENEG a smaller absolute size compared to V NEG , which occurs during the hard deletion process in Fig. 3A is used, and V SSEPOS has a larger absolute size than V POS in Fig. 3A. V EINHIB is created at WL0, SPW, BL1 and WL1 to prevent the I DThe voltage of unselected NVM cells, such as C2, is raised during the soft erase process. CLS0 and WLS1 are coupled to either ground or 0 V. In one embodiment, the switching gates (SGs) of all NVM cells C1 to C4, which are normally switched on for a hard erase process, are at least partially switched off (WL = -1.4 V).

[0068] In one embodiment, despite the smaller absolute size of V SSENEG still a relatively full quenching bias (V) SSENEG - V SSEPOS The voltage difference between CG and BL0 of the storage transistor (-7.2 V) is only applied across C1. With C2 not selected, the voltage difference between CG and BL1 is only (V SSENEG - V EINHIB = -0.9 V). Therefore, only I DThe selected C1 is raised, but not the unselected C2 in the same selected row 0. In one embodiment, the pulse duration of the selected erase operation (Tsse ~ 20 µs) coupled to WLS0 is much shorter than that of a hard erase operation (Te - 10 ms). The shorter SSE pulse may not have enough time to erase all previously trapped charges (if any) in the NVM cell C1. In one embodiment, all word lines, including WL0 and WL1 and SPW, are connected to V. EINHIBcoupled so that unselected NVM cells C2, C3, and C4 cannot be partially erased, as in NVM cell C1. In one embodiment, the basic idea of ​​a selected erasure operation is to apply a relatively high erasure bias (e.g., 7.2 V) for a short period (20 µs) to reduce trapped charges only in the selected NVM cell(s) of the same row. In one embodiment, Tae > Te > Tsse and Tse. In one embodiment, more than one NVM cell in the same row (adjacent or not) can be selected for the SSE operation, while more than one NVM cell in the same row (adjacent or not) can be locked, so that its I D The level remains relatively unchanged.

[0069] Table IV shows exemplary bias voltages that can be used for a selective soft erase operation of page / row 0 and column 0 (C1 only) of a non-volatile memory with a 2T architecture, containing memory cells with N-type SONOS transistors and CSLs similar to the 2 × 2 array 800. Table IV node Voltages (V) Voltage range (V) WLS0 In SSENEG , e.g. -2.3 V -2.5 V to -1.5 V BL0 In SSEPOS , e.g. +4.9 V +3.0 V to +5.0 V WL0 In EINHIB , e.g. -1.4 V -1.6 to -0.8 SPW In EINHIB , e.g. -1.4 V -1.6 to -0.8 DNW In SSEPOS , e.g. +4.9 V +3.0 V to +5.0 V CLS0 Ground or 0 V Ground or 0 V WLS1 Ground or 0 V Ground or 0 V BL1 In EINHIB , e.g. -1.4 V -1.6 to -0.8 WL1 In EINHIB , e.g. -1.4 V -1.6 to -0.8 Soft programming process:

[0070] In one embodiment, the operating voltages coupled to different nodes for a soft program (SP) / lock operation are similar to those in a hard program / lock operation, as previously described in Fig. 3B described, with the exception of the voltage coupled to the selected WLS (e.g., WLS0). In one embodiment, V SPPOS a smaller size than V POSDuring the hard programming process, the programming voltage applied to CG of the selected C1 can be reduced. Therefore, a soft programming bias of 6 V (V) is used. NEG - V SPPOS ) between CGs and BL / substrate / P depressions. In contrast to the hard programming process, the duration of the WLS pulse (e.g., WLSO, WLS1) is considerably shorter (Tsp ~ 10 µs) in the soft programming process than in the hard programming process (Tp ~ 5 ms). Due to the smaller voltage difference between CG and drain (e.g., 6 V versus 8 V) and the shorter soft programming pulse (10 µs versus 5 ms), the soft programming process can D The selected NVM cell C1 can only be reduced, but not reduced to the programmed I. D -Level, e.g. from L3 to L2 in Fig. 10. In one embodiment, unselected NVM cells, e.g. C2 in the same row, and unselected rows, e.g. C3 and C4, can be locked. Refill programming process:

[0071] Fig. Figure 8B illustrates an exemplary embodiment of a 2 × 2 field segment 800 of the NVM field 100 during a refill program (RP) / lock operation. Fig. 8B is, for example, the NVM cell C1, the target cell to be partially programmed (reduction or shift of the I). D -level in the direction of the programmed I D -level in Fig. 5), while NVM cell C2 is locked. It is understood that C1 and C2, shown for illustration as two adjacent cells, can also be two separate NVM cells in the same row, e.g., row 0. The general purpose of a replenishment programming operation is to replenish charges in deep traps (see Fig.7A) using a high programming bias to improve post-retention performance. Table V shows example biases that can be used for a page / row 0 fill programming operation of a non-volatile memory with a 2T architecture containing memory cells with N-type SONOS transistors and CSLs resembling a 2 × 2 array 800, as in Fig. 8B is best represented.

[0072] In one embodiment, in contrast to the soft programming processes, a harder programming bias (V) is used. RPPOS - V RPNEG ) pressed between CGs and substrate / drain, since V RPPOS a comparable but larger size than V POS and V RPNEG a comparable but larger size than V NEG The resulting programming bias imposed on the CG of the selected C1 is therefore comparable to, but slightly higher than, that of the one in Fig.The hard programming process described in section 3B (e.g., 9 V versus 8 V) is applied to the selected CG(s) only for a very short duration, Trp ~ 5 µs. This short fill-up programming pulse can... D While reducing the energy level of C1, it does not fully program it. In one embodiment, Tp > Tsp > Trp. The hard programming pulse during the replenishment programming process can help replenish charges in deep traps whose energy level lies between the conduction band and the valence band, as in Fig. 7A best illustrates this. In one embodiment, similar to the hard and soft programming processes, unselected NVM cells C2, C3, C4, etc., can be locked. In one embodiment, the refill programming process can be performed after or before the annealing quenching process. The refill programming process can DRestore selected NVM cells by filling charges into deep traps that were emptied from the shallow traps during the previous annealing quenching process.

[0073] Table V shows exemplary bias voltages that can be used for padding the NVM cell C1 in a 2T architecture non-volatile memory containing memory cells with N-type SONOS transistors and CSLs. Table V node Voltages (V) Voltage range (V) WLS0 In RPPOS , e.g. +5 V +3.8 V to +5.0 V BL0 In RPNEG , e.g. -4 V -4.0 V to -3.4 V WL0 In RPNEG , e.g. -4 V -4.0 V to -3.4 V SPW In RPNEG , e.g. -4 V -4.0 V to -3.4 V DNW In INHIB , e.g. +1.1 V +1.0 V to +1.2 V CLS0 Float / V MARG , e.g. -2.4 V -3.0 V to -2.0 V WLS1 In MARG , e.g. -2.4 V -3.0 V to -2.0 V BL1 In INHIB , e.g. +1.1 V +1.0 V to +1.2 V WL1 In RPNEG , e.g. -4 V -4.0 V to -3.4 V

[0074] It is understood that the voltages and voltage ranges used in the above description of the processes for hard erasure, hard programming, partial erasure, and partial programming were chosen for the sake of simplicity and represent only an exemplary embodiment of the subject matter; they should not be interpreted as limiting. Other voltages may also be used in different embodiments without affecting the generality of the present disclosure.

[0075] Fig. 9A and Fig. Figure 9B are representative flowcharts illustrating a method for the writing process 900A and 900B of multi-stage NVM cells according to an embodiment of the present subject matter. Fig. 10 is a representative graphic that includes several I D - or V TThe level of an NVM cell in an analog NVM field according to an embodiment of the present disclosure is illustrated. As already explained, the writing method 900A and 900B can be used to synchronize multiple V T - as well as I D -levels of NVM cells may be applicable. It goes without saying that, for the sake of clarity and simplicity, procedures 900A and 900B are referred to below only from the I D - perspective is explained. With reference to Fig. 9A and Fig. 9B The main purpose of the writing process 900A and 900B is to write a desired or predetermined I D - or V T -Level (or a target) into one or more selected cells or bits, such as SONOS-based NVM cells 90 in the NVM field 100 or multi-level or analog NVM field 1302 in Fig.13, to write precisely by a series of partial programming, partial erasing, and verification operations. In one embodiment, the written I must D possibly into a relatively narrow I D -Distribution (low sigma) fall to improve the functionality of an analog memory with multiple I D -levels to be maintained. As in Fig. 9A and Fig. As shown in Figure 13, the 900A method begins with a wake-up phase. In one embodiment, a hard programming process similar to that described in Figure 13 can be performed in the entire analog NVM field 1302. Fig. The embodiment described in 3B is performed to reduce leakage in unselected NVM cells in step 902. It is understood that one or more rows and columns of NVM cells can be selected for write operations 900A and 900B. For example, the NVM cells in row A and columns X and Y in the multi-level NVM array 1302 in Fig.13 was selected for a write operation to achieve a target ID2 level, as in Fig. 10 shown. Subsequently, in the selected row A, a sequence of hard deletion operations can be performed in steps 904 and 906 ( Fig. 3A) and hard programming processes ( Fig. 3B). In one embodiment, the I D of the NVM cells in row A first to the deleted-I D -level and then on the programmed-I D be postponed, as in Fig. Figure 10 illustrates this. Steps 904 and 906 can be repeated X times, e.g., 5 times (in step 908), and the wake-up phase can prepare the selected row A for the upcoming operations. After the wake-up phase, the NVM cells in the selected row A can access the fully programmed I D -level (L1). In one embodiment, no testing or reading process can take place during the wake-up phase.

[0076] As in Fig. 9A and Fig. As shown in 10, a soft erasure process is performed on selected bits in row A, so that the I D These NVM cells in step 910 from level L1 to Deleted-I D -level is raised. Unlike write operations of binary NVM cells, a check operation similar to a regular read operation can be performed after each partial programming and erasing operation to verify the I D -level of the selected bit(s) to be checked. In step 912, a check is performed on the selected bits in columns X and Y to check how strongly the soft erase process in step 910 affects the respective I D has raised. If the I D Both bits in columns X and Y are greater than the lower limit of the target I D , i.e. I D 2-LL, is, the procedure can continue with a fine-tuning phase, which in Fig. 9B is described. If in step 914 it is determined that the ID both bits below I D If 2-LL is present, procedure 900A can return to step 910 to perform another soft erase operation to remove the I D to further increase or raise both bits. If only one of the I D the selected bits in columns X and Y below I D If 2-LL is located, a soft programming operation can be performed on the bit that is above I. D 2-LL lies (around its I D to lower), while the bit that is below I D 2-LL is located, is blocked, so that both selected bits in step 916 are on a similar I D -level. The procedure 900A can then return to step 910 to perform another soft erase operation to restore the I D both bits further in the direction of the target I D -level. In one embodiment, steps 912, 914, 916 can be repeated several times until the I D-The level of all selected bits (e.g., bits in row A, column X and Y) was raised by the soft erase process in step 910 and subsequently checked in step 912 so that it is greater than the lower limit of the target I D -levels, such as L2 or L3 in Fig. 10. In one embodiment, the aforementioned steps can be performed for all bits in the selected row A.

[0077] According to Fig. In 9B, the 900B writing process enters the fine-tuning phase, in which a series of soft programming and selective soft erasing operations, each followed by a verification operation, are performed on one or more selected bits to ensure each of their I D in the direction of the target I D -level (e.g. I D 2) to bring. In one embodiment, a test or read operation can be performed on all selected bits to determine whether one of the selected bits contains an I. Dexhibits the upper limit of the target I D (e.g. ID2-UL in Fig. 10) exceeds. If both selected bits (e.g., column X and Y) are less than ID2-UL, the fine-tuning phase continues to step 922. If the I D If one of the selected bits is greater than ID2-UL (e.g., the L3 level), a soft programming operation is performed in step 920 ( Fig. 8B) on these bits to determine their I D slightly back to the I D To lower the distribution limits. Other selected bits can be locked. In one embodiment, steps 918 and 920 can be repeated several times until an I is reached for all selected bits. D smaller than I D 2-UL is determined.

[0078] In test step 922, all selected bits (e.g., columns X and Y) are read to determine whether the I D one of the bits due to the preceding soft programming / locking operations in step 920 under ID 2-LL (e.g., the L4 level) has shifted. If all selected bits are greater than I D If 2-LL are present, the fine-tuning phase can proceed to step 926. If it is determined that one or more selected bits below I are not present, the fine-tuning phase can proceed to step 926. D If 2-LL have been shifted, a selective soft deletion process ( Fig. 8A) only for these bits to determine their I D in the direction of the I D to shift the 2-distribution. As mentioned earlier, a selective soft erase operation, unlike a hard or soft erase operation which can be performed on all bits in a row, can only be performed on a single bit or several bits in a selected row. In one embodiment, selected bits that do not undergo the selective erase operation can be locked (I D (essentially unchanged). Steps 922 and 924 can be repeated several times until the I Dall selected bits above the I D 2-LL is located.

[0079] In test step 926, all selected bits (e.g., columns X and Y) are read to determine whether the I D one of the bits due to the preceding selective soft erase / lock operations in step 924 via the I D has shifted beyond 2-UL (overcorrection). If it is determined that one or more selected bits are shifted beyond the I D If 2-UL has been moved beyond this stage, a soft programming process ( Fig. 8B) only for these bits to determine their I D on the I D to restore the 2-distribution. In one embodiment, selected bits that are not subject to the soft programming process can be locked.

[0080] In one embodiment, the fine-tuning phase can be terminated in step 930 if, in test step 926, it is determined that all selected bits are smaller than the I D2-UL are. It is determined that all selected bits (e.g., row A, column X and Y) meet the target I. D exhibiting the above I D 2-LL and below the I D 2-UL is located. The writing methods 900A and 900B can be combined with one or more other series, e.g., with series B for the same or a different target I. D -level, continue. In one embodiment, the write operation can be repeated until the entire analog NVM field 1302 reaches the target I D -level is programmed.

[0081] In another embodiment, the fine-tuning phase can loop back to step 922 to check whether one or more selected bits have been overcorrected by the soft programming operation in step 928. Steps 922 (check), 924 (SE) and steps 926 (check), 928 (SP) can be reconfigurably repeated multiple times, depending on system requirements, before the fine-tuning phase proceeds to the final step 930 (write). The repeated checks can be advantageous in some embodiments, particularly for multi-level NVM arrays with a high number of In. D -Levels (adjacent target I) D -Levels are closely spaced).

[0082] Fig.Figure 11 is a representative flowchart illustrating another embodiment of the write algorithm according to the present disclosure. In one embodiment, the write algorithm 1100 can be used to write two bits from the same row (e.g., row A, column X and Y in Fig. 13) to write in order to express two different target values D (e.g., column X - I2, column Y - I0) to reach. As in Fig. As shown in Figure 11, the process begins in 1100, and several cycles of hard or heavy programming and erasing operations ( Fig. 3A and Fig. 3B) can be performed in step 1104 (wake-up phase) for both the bits of column X and the bits of column Y. Subsequently, in step 1106, a hard erase operation can be performed on both bits, so that their I D -Level I1 is reached. In another embodiment, the hard deletion process can reach I D Both bits above I1 are raised to the level of the erased I.D The process is shifted. Then, partial programming operations such as the soft programming operation (in step 1108) and the checking or reading (in step 1109) can be repeated several times until at least the bit of column X reaches I2 by comparing the bit of column X with the mean value of I2. Subsequently, the bit of column X can be locked in step 1110 for further programming or erasing operations, since it has already reached its target I2. Then, in step 1112, a selective erasing operation can be performed on the unlocked bit, i.e., the bit of column Y, to determine its I2 value. D-level to shift to I3. In one embodiment, several selective erase operations may be required for the column Y bit to reach I3. Subsequently, partial programming operations such as the soft programming operation (in step 1114) and the check or read operation (in step 1116) can be repeated several times until the column Y bit reaches its target level I0. Once it is determined that the column Y bit has reached its target level I0 by comparing the column Y bit to the I0 mean, it can be locked for further programming / erase operations in step 1118, just like the column X bit. In one embodiment, in this example I2 <I0<I3<I1.

[0083] To determine whether a bit represents the intended I D Once the target level is reached, it can compare the bit with the average of the target ID level. In another embodiment, the lower and upper limit algorithm, which is in Fig.9A and Fig. As detailed in Section 9B, the algorithm can be applied in steps such as steps 920, 924, and 926. In another embodiment, the writing algorithm can continue writing other bits in the selected row or in other rows using the same steps.

[0084] The writing algorithm in Fig. Figure 11 illustrates a basic concept for writing an analog value to an NVM array, e.g., the multi-level NVM array 1302. In an alternative embodiment, more than one bit can be written to the target I2 and target I0 because soft programming and selective soft erase operations can be performed selectively on one or more bits in the same row. In other alternative embodiments, instead of soft programming operations (in steps 1106 and 1114), bits can be written to their respective target I2. DTo bring about or fine-tune, selective soft deletion processes can be used additionally or alternatively. The example in Fig. 11 begins on the Deleted-I D -level (after step 1106); however, it can also be on the programmed I D -Levels begin if, instead, a hard programming operation (all bits on I2 or the programmed I) occurs in step 1106 D -level) is carried out.

[0085] As previously explained, SONOS-based cells, such as NVM Cells 90, are suitable for analog multi-level storage devices due to their long lifespan of 1,000 cycles and low power consumption. SONOS-based NVM arrays also have the advantage of exhibiting low random telegraph noise (RTN) of less than 3 nA. In one embodiment, the retention specification for multi-level NVM devices can be more stringent than for binary NVM devices, such as NOR flash, EEPROM, etc., because more than two adjacent V T / I D Levels that can represent more than two analog values ​​are closely spaced. It may be essential to optimize data retention performance and V. T / I D -Sigma degradation to avoid incorrect or faulty readings of multiple levels in multi-level NVM cells. One of the main factors negatively impacting retention and VT / I D -Sigma effect, is the loss of charges during retention, e.g. of electrons and holes, from flat traps in the charge-trapping layer 92 of the SONOS transistor 94, as in Fig. 1 and Fig. 7A and B are perfectly represented.

[0086] Fig. Figure 12 is a representative flowchart illustrating a method for operating a filling and annealing algorithm according to an embodiment of the present disclosure. As shown in Fig. As shown in Figure 9B, the writing of an analog value to a specific multi-level NVM cell can be considered complete in step 930. In certain embodiments, Algorithm 1200 can be performed for one or more bits or an entire set of programmed bits. Using the same example as in Fig. 9A and Fig. 9B bits can be written in row A, column X and Y and the desired I DStore the 2-value in step 930. In one embodiment, this can improve retention performance and minimize the V T / I D -Sigma degradation can be advantageous, replacing charges (electrons or holes) in shallow traps with charges in deep traps. In one embodiment, the filling and annealing process can be performed on 1200 bits, which are adjusted to their target I D -levels were programmed. The procedure 1200 begins by performing a soft erase operation on selected bits (e.g., row A, column X and Y) to reset their I D -Values ​​in step 1202 to a target level of I D -Mean + X % (e.g. I D to increase by 2+20 to 50%). A verification step may follow to ensure that the selected bits meet the target value of I. D-Average value + 20 - 50% or exceed. In one embodiment, the soft quenching process can empty charges mainly in shallow traps to achieve the I D -value. A refill programming process can then be performed as described previously and in Fig. 8B is best represented, in step 1206 it is carried out on selected bits to determine their I D -values ​​to a target level of I D -Mean - Y % (I D to reduce by 2-10 to 20%). A verification step may follow to ensure that the selected bits do not exceed the target value of I. D-Average - reach or fall below 10-20%. In one embodiment, the short but strong replenishment programming pulse (e.g., 9 V CG to drain) can replenish some of the removed charges during the previous soft erase operation in step 1202 with charges mainly stored in deep traps. Steps 1202 and 1206 can be repeated several times to enhance the replacement of charges in shallow traps with charges in deep traps. It is understood that I D 2-10 to 20% and I D The values ​​2+20 to 50% are merely examples for illustrative purposes. Other percentage offset values ​​can also be assumed, as long as they meet the requirements. D -Values ​​of the selected bits from one side to the other of their target I D - Shift the mean.

[0087] Method 1200 can then proceed with an annealing quenching process, as previously described, on selected bits in step 1208. In one embodiment, the annealing quenching process can discharge charges mainly in shallow traps to achieve the I D -value from level I D to raise by 2-10%, which is the result of step 1206. As previously explained, the soft (6 V CG to drain) and long (-50 ms) annealing pulse can also provide sufficient time to discharge the charges, especially in the shallow traps. A test step can follow to ensure that at least one or more selected bits are at or above the target I level. D -lower limit (e.g. I D 2-LL). Then, in step 1210, procedure 1200 can be used to perform a selective soft erase operation for bits below I. D Continue with 2-LL. Bits whose I D -Value due to the previous annealing quenching process (step 1208) above the I DIf bits 2-LL are present, they can be locked instead. Checks can be performed to ensure that all bits are partially cleared to prevent I D -levels greater than the I D 2-LL are. At the end of step 1210, all selected bits (e.g., row A, column X and Y) can be set to the target I. D -level (e.g. I D 2) are reset, with most charges being in deep traps due to the series of refill programming and annealing quenching operations.

[0088] In an alternative embodiment, steps 1202 (soft erase process) and 1206 (refill programming process) of the refill and annealing routine 1200 can be additionally or alternatively performed directly after step 918 (checked NO) in the write algorithm 900B in Fig. 9B will be carried out.

[0089] Fig.Figure 13 is a schematic block diagram illustrating an embodiment of a multi-stage or analog NVM device 1300 according to the present subject matter. In one embodiment, the analog NVM field 1302 can be assigned to the NVM field 100 in Fig. 2 similar, wherein the multi-stage NVM cells 1310 are arranged in N rows and M columns. Each multi-stage NVM cell 1310 can have a 2T configuration (SONOS transistor and FET transistor) and share a CSL with an adjacent cell of the same row. In one embodiment, other connections such as WLS, WLs, BLs, SPW, DNW, etc., can also be added to the configurations in the NVM array 100 in Fig. 1A, Fig. 1B and Fig. 2 resemble. The multi-stage NVM cell 1310 can be configured to hold more than two different I D / V T -level (see Fig. 10), e.g. 2 4= 16 or 0 to 15 levels. In one embodiment, each analog NVM cell 1310 can store an analog value from 0 to 15, corresponding to its I D / V T -level during reading corresponds. In one embodiment, the multiple unique I D / V T -Levels and their corresponding analog values ​​must be predefined. The analog values ​​can be written to the analog NVM cells 1310 using one or more writing methods / algorithms, as described in Fig. 9A to Fig. Figure 12 illustrates and describes how to write partial programming / locking operations, partial erasing / locking operations, and checks. As an example, a value of 10 is written to bit X in row A (I D / V T(Level = 10), a value of 5 is written to row A, column Y bit, a value of 8 to row B, column X bit, and a value of 2 to row C, column Z. In some embodiments, multi-level NVM cells 1310 can be assigned to any analog value within the predefined I D / V T -Level range (e.g. 0 to 15 for 16 I) D / V T -level). The stored values ​​mentioned above may be used in subsequent examples of operating procedures for explanatory purposes only and should not be interpreted as limitations.

[0090] In one embodiment, the stored values ​​of several multi-level NVM cells 1310 can be combined to store an analog value. For example, two multi-level NVM cells 1310 can be configured to have 8 levels, with one cell storing values ​​from 0 to 7 and the other storing values ​​from -8 to -1. When the two cells are read in a single operation, the combined cell can be considered to have 16 levels (-8 to -7), corresponding to 16 analog values ​​instead of 8. In other embodiments, more than two multi-level NVM cells 1310 can be combined to achieve a higher number of levels without increasing the I D / V T-The operating area of ​​the multi-stage NVM cells 1310 can be further subdivided. In some embodiments, combined cells can be arranged in adjacent columns of the same row or in adjacent rows of the same column, or dispersed in an analogous NVM array 1302 according to predefined algorithms.

[0091] As in Fig.As shown in Figure 13, the analog NVM array 1302 can be coupled to the column multiplexer 1304 via its bit lines (e.g., BL X, Y). In one embodiment, the column multiplexer 1304 can include multiplexers, capacitors, transistors, and other semiconductor devices. During a read operation, the value 10 of the bit in row A, column X, can be read to the column multiplexer 1304 via BL X, similar to a read operation of a digital NVM array. In one embodiment, multiple bits in the same column, e.g., rows A and B, column X, can be selected in a single read operation, such that the read value is the sum of the two selected bits (10 + 8 = 18). In another embodiment, multiple bits in the same row, e.g., rows A, columns X and Y, can be selected for the same read operation.The column multiplexing function 1304 can be configured to select both column X and Y for reading and to add or subtract the two values ​​(10 + 5 = 15 or 10 - 5 = 5). In another embodiment, the analog NVM device 1300 can be configured to perform a multiplication function. For example, the bit of row A, column X can be read 7 times to calculate (7 × 10 = 70). The multiplication (M × stored values) can be performed by using M × multiple pulses at WL (coupled to SGs) or by extending (by a factor of M) the pulse duration of a WL pulse. In one embodiment, for example, the analog value "7" can be an input via a digital-to-analog converter (DAC) 1320 from an external device, which can be coupled to a WL via a series of SGs. As in . Fig.As best illustrated in section 13, each DAC 1320-1326 can be coupled with one or more WLs. One of the functions of the DAC 1320-1326 is to configure the selected row(s) for read operations. It goes without saying that the number and configuration of the DACs and their coupling with the NVM field 1302 in Fig.Figure 13 is only one example for illustration. Other configurations are possible depending on system requirements and design, without altering the general statements of the present embodiment. In various embodiments, the DACs 1320–1326, the analog NVM array 1302, and the column multiplexer 1304 can be configured to perform simple arithmetic functions such as summation, multiplication, etc., as shown in the previous examples, with or without a CPU or GPU. In one embodiment, the analog NVM device 1300 can perform the functions of both a data storage device and an inference device.

[0092] The analog results of the column multiplexing function 1304 can then be input to the analog-to-digital converter (ADC) or comparator 1306, where the analog readout result can be converted into digital data and output. In one embodiment, all or a portion of the analog NVM field 1302 can be refreshed periodically, or its analog value can be rewritten periodically, e.g., every 24 hours or 48 hours, or over another period. The refresh process can mitigate potential effects of I D / V T -Level shift or decay of programmed multi-stage NVM cells due to retention, I D / V T -Deterioration (in Fig. 7B best illustrated) or minimize other causes. In another embodiment, the analog NVM field can contain 1302 reference cells (not shown) in which the usual effects of the potential I D / VT -Level shift of multi-stage NVM cells 1310 can be subtracted.

[0093] Fig. 14 and Fig.Figure 15 are representative block diagrams illustrating a von Neumann architecture of a multiply-accumulate (MAC) system, or artificial neuron, according to one embodiment of the present disclosure. Artificial intelligence (AI) can be defined as the ability of a machine to perform cognitive functions carried out by a human brain, such as reasoning, perceiving, and learning. In machine learning, algorithms can be used to find patterns in data and a model that recognizes these patterns can be used to make predictions about new data or patterns. At the heart of AI applications, or machine learning, is the MAC, or dot product, operation, in which two numbers (input values ​​and weight values) are taken, multiplied together, and the results added in an accumulator. The artificial neuron 1504 in Figure 1504 is used for this purpose. Fig.15 can be part of a deep neural network (DNN) that contains an example of a MAC operation. DNNs mimic the functions of the human brain by implementing a massively parallel computing (neuromorphic) architecture that combines low-power computational elements (neurons) and adaptive memory elements (synapses). One reason for the rapid growth of machine learning is the availability of graphics processing units (GPUs). In a MAC application, such as the System 1402, GPUs can perform necessary calculations much faster than a general-purpose CPU. One of the drawbacks of using GPUs for MAC operations is that GPUs tend to use floating-point arithmetic, which is far beyond the requirements of a relatively simple machine learning algorithm like MAC operations.Furthermore, AI applications, especially those running at the edge, require a highly energy-efficient MAC to reduce power consumption and heat generation. Existing all-digital systems based on the von Neumann architecture, such as the MAC System 1502, can also experience significant bottlenecks between the GPUs performing computations and the memory that only stores data (weights, input values, output values, etc.) due to frequent memory access. Therefore, the use of low-power memory elements that can be configured to function as both an inference device and a data storage device must be considered.

[0094] Fig.Figure 16 is a representative block diagram showing a neural network acceleration system according to one embodiment of the present disclosure. In one embodiment, SONOS-based analog devices can have the unique ability to store analog values ​​of weights locally and process each non-volatile memory element in parallel, thus reducing the massive energy expenditure for data transfers, as in Fig. As shown in Figure 14, this can be significantly reduced. Each NVM cell can have multiple levels (e.g., 4 bits - 8 bits) instead of binary levels (1 bit), and each I D / V T -Level can have a multi-bit weighted value (wi in Fig.15) for performing an inference. In one embodiment, the higher the number of stages, the higher the training accuracy and the lower the error rates in the inferences. The most important performance and reliability requirements for a typical analog memory for neuromorphic computing are sigma of the cells-I D / V T Retention and noise at all levels. As previously explained, SONOS-based NVM devices, such as the analog NVM 1300 in Fig. 13, be a good candidate to perform both the storage and inference functions of an artificial neuron in a DNN system.

[0095] Referring to Fig.16. The neural network acceleration system 1600 can contain multiple analog NVM devices or accelerators 1602 arranged in a single substrate, package, or chip and coupled to each other via a bus system. Each accelerator 1602 can be connected to the analog NVM device 1300 in Fig. 13 be similar and be operated in a similar manner. In one embodiment, the analog NVM device 1602 can be configured to perform MAC operations. Each analog NVM device 1602 can be considered the artificial neuron 1504 in Fig. 15 function in a DNN system. In one embodiment, the SONOS field 1602 can contain multiple SONOS-based NVM cells (in Fig. 16 (not shown) have, which are arranged in rows and columns. In other embodiments, the SONOS field 1602 can contain multiple SONOS NVM sections or fields. Each NVM cell can be configured to have a weight value from 0 to 2 n-1 or other values, which are stored using the write algorithm, as in Fig. 9A to Fig. Figure 12 shows and illustrates this, and a combination thereof can be written. In other embodiments, the analog value of each NVM cell can be written using other writing algorithms.

[0096] As part of the neuromorphic computing algorithm, any analog NVM device 1602, such as the accelerator 1602a, can execute the following MAC function, where xi are inputs from other analog NVM devices 1602 or external devices, wi are the stored weight values, b is a constant, and f is an activation function: ƒ(∑ixiwi+b)

[0097] As in Fig.As best illustrated in Figure 16, xi can be digital inputs from the analog NVM devices 1602b and 1602c or other analog NVM devices. The digital inputs xi can then be converted into analog signals by the DAC 1612, which can then be coupled to low-voltage drivers 1614 and / or high-voltage drivers 1616. In one embodiment, low-voltage drivers can generate control signals via WLs to control SGs of NVM cells according to the analog signals from the DAC 1612. High-voltage column drivers 1604 can generate control signals for BLs and high-voltage drivers for WLSs to control CGs of NVM cells.

[0098] One embodiment of MAC operations in the analog NVM device 1602a can be illustrated by the example in Fig. 13 can be illustrated, where i can be set to 3. As in Fig.As shown in Figure 13, the digital inputs xi can be coupled to the DAC 1320-1326 and be x1=3, x2=5, x3=1. The selected weighting values ​​are stored in bits in row A, column X (w1=10), row B, column X (w2=8), and row C, column Z (w3=2). The selection of weighting values ​​can be based on addresses received from other analog NVM 1602 devices or from external devices such as processors, CPUs, GPUs, etc. The constant b can be chosen to represent the analog value stored in row A, column Y (b=5). To calculate x1 x w1, row A and column X (stored value = 10) can be selected for reading. The read operation can be repeated three times for x1 = 3 to calculate x1 x w1. Similarly, row B, column X (weighting value = 8) can be selected for x2=5 reads to calculate x2 x w2, and row C, column Z (weighting value = 2) for x3 = 1 read to calculate x3 x w3.Alternatively, rows A and B, column X can each be selected for reading 3 times (to accumulate combined weighted values), and only row A, column X can be selected for two further reads. Then the bit in row A, column Y (b=5) can be selected for reading. As previously explained, the column multiplex 1304 or 1606 can be configured to add these results to calculate the MAC result. 3×10+5×8+1×2+2=74 to calculate. It goes without saying that the algorithm above is merely an example of using SONOS-based NVM devices, such as the Inference NVM 1300 and 1602, to calculate MAC results for explanatory purposes and is not intended as a limitation. MAC weighting values ​​(wi) can be stored, organized, and read in various ways to calculate MAC results depending on the system design and requirements. In one embodiment, the activation function (f) can be an algorithm that displays or prioritizes the MAC outputs of the analog NVM 1602 devices from the perspective of the entire neural network. For example, the MAC result of the previous example (result = 74) can be classified as unimportant and assigned a low priority.The output signal can be reduced or amplified depending on its priority, and in some embodiments the execution can take place in the column multiplex function 1606 or in the ADC 1608.

[0099] In one embodiment, the MAC result, in the form of an analog signal, can be converted into a digital signal by the ADC 1306 or 1608. The digital signal can then be output to another analog NVM device or devices 1602 as xi for their own MAC operations. In another embodiment, similar to a DNN, neuromorphic computing can be performed in parallel by all analog NVM devices 1602. The digital MAC outputs of each analog NVM device 1602 can be passed as digital inputs to other analog NVM devices. In some embodiments, the plurality of analog NVM devices 1602 can be divided into several subsets. The digital outputs of one subset of analog NVM devices 1602 can be passed to the next without repetition.The digital output of the last subset can be passed to external devices as a result of neuromorphic computing or machine learning.

[0100] In one embodiment, command and control circuits (in Fig. 16 (not shown), including the digital data flow control block 1610, which is programmable and configured to control data flow traffic within the analog NVM devices 1602. The command and control circuits can also provide control of the low- and high-voltage drivers 1614 and 1616 and the high-voltage column driver 1604 to supply various operating voltage signals to the SONOS array 1602 via SONOS word lines, word lines, bit lines, CSL, etc., including, but not limited to, V POS , V SEPOS , V RPPOS , V NEG V SENEG , V CSL , V MARG , V INHIB , etc. as at least in Fig. 3A, Fig. 3B, Fig. 8A, Fig. 8B is shown.

[0101] For the expert, it goes without saying that the neural network acceleration system 1600 and the analog NVM devices 1602 in Fig. Section 16 has been simplified for clarity and is not intended as a complete description. In particular, analog NVM devices may contain processing functions, serial decoders, column decoders, read amplifiers or other comparators, as well as command and control circuits, which are not shown or described in detail here.

[0102] Fig.Figure 17 is a representative flowchart illustrating an embodiment of the operating procedure of an NN accelerator system 1600 with SONOS-based NVM arrays / cells according to the present disclosure. In one embodiment, analogous weighting values ​​(wi) and other constant values ​​(e.g., b) are written to the SONOS-based NVM arrays in the NN accelerator using the procedures described above in step 1702. In some embodiments, the NVM arrays can be periodically refreshed in an optional step 1712 to improve retention and tighter I D / V T-Sigma. Subsequently, the NVM fields of an accelerator can be configured to perform MAC operations based on at least digital inputs (xi) from other accelerators and their stored weight values ​​(step 1704). After the MAC operations are complete, an accelerator can output its results and, in step 1706, forward them to one or more connected accelerators as digital inputs for their own MAC operations. In one embodiment, steps 1704 and 1706 can be repeated multiple times in parallel. In step 1710, the outputs can be transferred as results of neuromorphic computing in the machine learning of an AI application to external devices such as CPUs or GPUs.

[0103] Thus, embodiments of a SONOS-based multi-stage non-volatile memory and methods for operating it as an analog storage device and MAC device in a neuromorphic computing system, such as a DNN, were described. Although the present disclosure is described with reference to certain exemplary embodiments, it is obvious that various modifications and changes can be made to these embodiments without departing from the spirit and scope of the disclosure. Accordingly, the specification and drawings are to be viewed in an illustrative rather than a limiting sense.

[0104] The summary of the disclosure serves to satisfy 37 CFR §1.72(b), which requires a summary that enables the reader to quickly assess the essential features of one or more embodiments of the technical disclosure. It is provided on the condition that it is not used to interpret or limit the scope of protection or the meaning of the claims. Furthermore, it is evident from the preceding detailed description that, for the purpose of streamlining the disclosure, various features are grouped together in a single embodiment. This method of disclosure is not to be understood as requiring the claimed embodiments to have more features than are expressly listed in the individual claims. Rather, as the following claims demonstrate, the subject matter of the invention consists of fewer than all the features of a single disclosed embodiment.Therefore, the following claims are hereby included in the detailed description, each claim representing a separate embodiment.

[0105] When the description refers to an embodiment or embodiment, this means that a specific feature, structure, or property described in connection with the embodiment is included in at least one embodiment of the circuit or method. The phrase "an embodiment," appearing at various points in the specification, does not necessarily refer to the same embodiment in each instance. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 16 / 827948

[0001] US 62 / 940547

[0001]

Claims

[1] A method of operating a semiconductor device, comprising: - Accessing the semiconductor device including multi-level memory transistors arranged in rows and columns, wherein the multi-level memory transistors include silicon oxide nitride oxide silicon, SONOS, based charge trapping transistors configured to store one of N x analog values corresponding to the N levels of a threshold voltage, V T , and a drain current, I D , where N is a natural number greater than 2; - Selecting at least one of the multi-stage memory transistors for a write operation to a setpoint value, wherein the setpoint value is one of the N x analog values and corresponds to a setpoint I D -range, which differs from a target I D -Lower limit, LL, to a target I D -upper limit, UL, extends; - performing a partial programming operation on at least one of the multi-stage memory transistors for I D -Level reduction, where a first test read is performed after the partial programming operation to determine how a reduced I D -level compared to a target I D -mean is; - performing a partial erase operation on the at least one of the multi-stage memory transistors to raise the ID level, wherein after the partial erase operation a second test read is performed to determine how a raised I D -Level compared to the target I D -mean; and - Determine that the write operation to the setpoint is complete when the I D -Level of at least one of the multi-stage memory transistors in the target I D -area falls. [2] The method of claim 1, further comprising: - Disabling the at least one multi-level memory transistor for further programming and erasing operations after the write operation to the target value is completed, wherein disabling comprises decreasing a magnitude of a gate-drain bias of the at least one multi-level memory transistor. [3] The method of claim 1, wherein the partial programming operation comprises at least one of a soft programming operation and a fill-in programming operation, wherein the partial programming operation is configured for at least one of the multi-stage memory transistors to have the I D -level and a V T level, and multi-stage memory transistors not selected for the partial programming operation are disabled. [4] A method according to claim 1, wherein the partial programming operation is performed for a considerably shorter duration than a programming operation, the programming operation being arranged to D -level of the multi-stage memory transistors to a fully programmed I D -level, regardless of the initial I D -Levels of the multi-stage memory transistors. [5] The method of claim 3, wherein the partial erase operation comprises at least one of a soft erase operation, a selective soft erase operation and an annealing erase operation, wherein the partial erase operation is configured to, for at least one of the multi-stage memory transistors, the I D -level and the V T level, and multi-stage memory transistors not selected for selective soft erase are disabled. [6] A method according to claim 5, wherein the soft erase operation and the selective soft erase operation are performed for a considerably shorter duration than an erase operation, the erase operation being designed to D -level of the multi-stage memory transistors to a completely erased I D -level, regardless of the initial I D -Levels of the multi-stage memory transistors. [7] The method of claim 5, wherein the annealing erase operation is performed for a considerably longer duration than an erase operation, and wherein a magnitude of a gate-to-drain bias of the at least one of the multi-stage memory transistors during the erase operation is greater than in the annealing erase operation. [8] The method of claim 5, further comprising a filling and annealing algorithm comprising: - performing, after the write operation to the target value is completed, the soft erase operation on the at least one of the multi-stage memory transistors; - Check whether the I D -Level at least a target level of I D + X%, where X is in the range 20 to 50; - performing the fill-in programming operation on at least one of the multi-stage memory transistors; - Check whether the I D -level at most a target level of I D - has reached Y%, where Y is in the range of 10 to 20; - performing the annealing erase operation on at least one of the multi-stage memory transistors; - Checking the I D -level of each of the at least one multi-stage memory transistor; - Selecting and performing the selective soft erase operation only on the at least one of the multi-stage memory transistors whose I D-Level less than the target I D -LL, and blocking unselected multi-stage memory transistors; and - Check whether the I D -level of at least one multi-stage memory transistor back to the target I D -level range is returned. [9] Method according to claim 8, wherein the filling and annealing algorithm is designed to D -Level of at least one of the multi-stage memory transistors within the target I Dregion while replacing charges in shallow traps with charges in deep traps in a charge trapping layer of the at least one multi-stage memory transistor, wherein the fill-in programming operation enables charges in deep traps by applying a high gate-drain bias and a short programming pulse to the at least one of the multi-stage memory transistors, and wherein the annealing erase operation is configured to empty charges in shallow traps via Fowler-Nordheim tunneling by applying a low gate-drain bias and a long erase pulse to the at least one of the multi-stage memory transistors. [10] The method of claim 1, wherein the at least one of the multi-stage memory transistors is arranged in a same row or a same column. [11] A method of operating a semiconductor device, comprising: - selecting a first non-volatile memory (NVM) cell of a SONOS-based NVM array for a selective soft erase operation, wherein the SONOS-based NVM array comprises NVM cells arranged in rows and columns, and wherein NVM cells of adjacent first and second columns are coupled to a first common source line; - generating and coupling a first negative voltage to a first SONOS word line in a first row of the SONOS-based NVM array and a positive voltage to a first bit line in the first column to apply a gate-to-drain bias to a first NVM transistor in the first NVM cell to partially erase the first NVM cell by Fowler-Nordheim (FN) tunneling, wherein a drain current level, I D , and a threshold voltage level, V T , of the first NVM transistor is increased or reduced, respectively; and - coupling a reverse voltage to a second bit line in the second column to reduce the gate-to-drain bias to a second NVM transistor in a second NVM cell in the first row that is not selected for the selective soft erase operation, wherein the reverse voltage has the same polarity and a smaller magnitude than the first negative voltage, and wherein the second NVM transistor has approximately the same I before and after the selective soft erase operation D - and V T -level. [12] The method of claim 11, further comprising: - Coupling a ground voltage to a second SONOS word line in a second row of the SONOS-based NVM array to deselect all NVM cells in the second row for the selective soft erase operation. [13] The method of claim 11, further comprising: - generating and coupling the blocking voltage to a first word line in the first row and a shallow positive well (SPW) node of the SONOS-based NVM array to turn off a first field-effect transistor, FET, in the first NVM cell and a second FET in the second NVM cell; and - Coupling the positive voltage to a deep negative well (DNW) node. [14] The method of claim 11, wherein each of the NVM cells includes an NVM transistor configured to store one of N x values corresponding to N x levels of I D - and V T -levels, where N is a natural number greater than 2, wherein the selective soft erase operation is arranged to raise the ID level and the V T level of the first NVM transistor so that its stored value changes from a first value to a second value, the second value being greater than the first value. [15] A method according to claim 14, wherein each of the N x levels of I D - and V T -levels comprises a distribution, with two adjacent I D - or V T distributions have an overlap frequency of less than 3% and where the N x levels of I D - and V T -Levels are linearly incremental and decremental respectively. [16] A semiconductor device comprising: - a semiconductor oxide nitride oxide semiconductor, SONOS, based non-volatile memory (NVM) array comprising NVM cells arranged in rows and columns, each NVM cell comprising an NVM transistor and a field effect transistor, FET, and each NVM transistor configured to store N x analog values corresponding to the N x levels of its drain current levels, I D , or threshold voltage level, V T , are equivalent to; - a digital-to-analog (DAC) function that receives and converts digital signals from external devices, wherein the converted digital signals are configured to cause the reading of an analog value stored in at least one NVM cell in at least one column; - a column multiplexer (Mux) function configured to select and combine the analog value read from the at least one NVM cell; and - an analog-to-digital (ADC) function designed to convert analog results of the column multiplexer function into digital values and output the digital values. [17] A semiconductor device according to claim 16, wherein the N x analog values are written into the NVM transistors by a series of partial programming and selective partial erasing operations, wherein the selective partial erasing operations are arranged to set, for selected NVM transistors of a same row, the I D-level and the V T -level while blocking unselected NVM transistors in the same row. [18] A semiconductor device according to claim 17, wherein each of the partial programming operations and the selective partial erasing operations is followed by a read operation to check whether the I D -level or the V T -level of the selected NVM transistors the target I D -level and the target V T -level have been reached. [19] A semiconductor device according to claim 16, wherein a plurality of semiconductor devices are arranged on the same semiconductor chip and communicatively coupled to one another, each of the plurality of semiconductor devices being arranged to perform multiply-accumulate (MAC) operations based on the analog values stored in the NVM cells and digital inputs from at least one other semiconductor device of the plurality of semiconductor devices. [20] A semiconductor device according to claim 19, wherein a first subset of the plurality of semiconductor devices outputs digital results of the MAC operations, and wherein the digital results of the first subset are coupled to a second subset of the plurality of semiconductor devices as digital inputs. [21] A semiconductor device according to claim 20, wherein the plurality of semiconductor devices are configured to function as artificial neurons in a deep neural network (DNN) that performs neuromorphic computing in an artificial intelligence (AI) application.