METHOD FOR MANUFACTURING INTEGRATED INDUCTOR-CAPACATOR OSCILLATORS, INDUCTOR-CAPACATOR OSCILLATORS AND SYSTEMS-ON-CHIP
Patent Information
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- MICROCHIP TECHNOLOGY INC
- Filing Date
- 2020-04-01
- Publication Date
- 2026-06-11
Smart Images
Figure 00000000_0000_ABST
Abstract
Description
PRIORITY CLAIM
[0001] This application claims the benefit of the filing date of the preliminary US patent application with serial number 62 / 961,635, filed on January 15, 2020, the disclosure of which is incorporated herein in its entirety by this reference. AREA
[0002] This disclosure generally relates to techniques for forming integrated and / or internal inductor-capacitor oscillators and associated methods, inductor-capacitor oscillators, semiconductor devices, systems-on-chips, and systems. In particular, disclosed embodiments relate to techniques for forming integrated and / or internal inductor-capacitor oscillators that can improve the accuracy and reliability of inductor-capacitor oscillators, reduce the number of additional processing operations required to form the inductor-capacitor oscillators, and enhance the ability to adopt system-on-chip approaches for modules that rely on precise timing. STATE OF THE ART
[0003] In conventional integrated circuits (ICs) known to the inventor, a fully functional device with multiple interconnected transistors is formed using transistors monolithically mounted on a silicon substrate and metal wire, usually aluminum or copper, for connecting to the transistors. In addition to the transistors, other components that would conventionally be provided on a printed circuit board (PCB) can be monolithically mounted on the same silicon substrate. This configuration is sometimes referred to in the prior art as a "system-on-a-chip" (SoC). The fabrication of electronic components to create an SoC configuration using techniques known to the inventor generally involves additional dedicated process steps that make the manufacturing processes more expensive and time-consuming. List of characters
[0004] While this disclosure concludes with claims that particularly highlight and unambiguously claim certain embodiments, various features and advantages of embodiments within the scope of protection of this disclosure can be more easily determined from the following description when read in conjunction with the accompanying drawings, in which: Fig. 1 a schematic diagram of a substrate that includes a monolithically integrated inductor-capacitor oscillator according to an embodiment of this disclosure; Fig. 2 a flowchart of a process for manufacturing the inductor-capacitor oscillator of Fig. 1 is; Fig. Figure 3 shows a cross-sectional view of an illustrative capacitor used to form the inductor-capacitor oscillator of Fig. 1 is usable; Fig. 4 A cross-sectional view of a first intermediate product in a process for manufacturing the capacitor of Fig. 3 is; Fig. 5 a cross-sectional view of a second intermediate product in the process for manufacturing the capacitor of Fig. 3 is; Fig. 6 a cross-sectional view of a third intermediate product in the process for manufacturing the capacitor of Fig. 3 is; Fig. 7 a cross-sectional view of a fourth intermediate product in the process for manufacturing the capacitor of Fig. 3 is; Fig. Figure 8 is a top view of an illustrative inductor used to form the inductor-capacitor oscillator of Fig. 1 is usable; Fig. 9 a cross-sectional view of another section of the integrated inductor of Fig. 8 is; Fig. 10 a cross-sectional view of a first section of the inductor of Fig. 8 is; and Fig. 11 a schematic diagram of an electronic system, including the substrate of Fig. 1, is. METHODS OF EXECUTING THE INVENTION
[0005] The illustrations presented in this disclosure are not intended to be actual views of any particular microcontroller, system-on-chip, substrate, integrated inductor-capacitor oscillator, or any component thereof, but are merely idealized representations used to describe illustrative embodiments. Therefore, the drawings are not necessarily to scale. In this description, identical reference numerals refer to the same or similar elements, regardless of whether these elements are expressly highlighted or discussed in connection with a given figure.
[0006] The disclosed embodiments generally relate to techniques for forming integrated and / or internal inductor-capacitor oscillators, which can improve the accuracy and reliability of inductor-capacitor oscillators, reduce the number of additional processing operations required to form the inductor-capacitor oscillators, and enhance the ability to adopt system-on-chip approaches for modules that rely on accurate timing control, compared to oscillators known to the inventor of the subject matter of this invention.More specifically, embodiments of integrated and / or internal oscillators for semiconductor devices are disclosed, which may include an inductor that is at least partially formed on or above a substrate during the formation of a back-end-of-line (BEOL) structure, including semiconductor material, and a capacitor that is deposited on and / or embedded in the semiconductor material of the substrate before or during the formation of the BEOL structure. BEOL is the stage of IC fabrication in which the individual devices are interconnected with wiring on the substrate using one or more metallization layers. For example, the formation of the BEOL structure typically begins when an initial metal layer is deposited on the substrate or when preparations are made to facilitate the deposition of such an initial metal layer.Common metals used as metallization layers are copper and aluminum. BEOL structures conventionally include contacts (e.g., contact pads), insulating layers (dielectrics), metal planes (e.g., wires), and interconnects (e.g., solder bumps, sphere grid arrays) for chip-to-package connections. For example, integrated and / or internal inductors for inductor-capacitor oscillators can be formed, at least partially, using processes for forming BEOL structures on or over substrates that include semiconductor materials. Specific techniques for fabricating such integrated inductors are disclosed in the currently unpublished U.S. patent application with serial number 16 / 549,635, filed on August 23, 2019, and U.S. patent application with serial number 62 / 875,917, filed on July 18, 2019, the respective disclosures of which are incorporated herein in their entirety by this reference.Resulting inductors can be low-resistance and insensitive to temperature fluctuations, allowing high-quality inductors to be produced at low cost (e.g., no cost from a process perspective).
[0007] Integrated and / or internal capacitors for inductor-capacitor oscillators can be formed, at least partially, using unconventional processes for forming BEOL structures on or over substrates, including semiconductor materials disclosed herein, or using prior art processes known to the inventor. For example, an integrated capacitor can be formed using an amount of electrically conductive material that is partially surrounded and / or embedded within a dielectric material as one of the capacitor's plates. In particular, the plate can be formed from one of the topmost wires produced by a damascening process on the substrate. A passivation material can be placed over the dielectric material and the electrically conductive material as part of the BEOL structure formation process.Holes extending through the passivation material to the plate can be formed using a masking and etching process, which can also be performed as part of the BEOL structure formation process. The specific positions and quantities of the holes may differ from prior art techniques known to the inventor for forming the BEOL structure. A dielectric material (e.g., silicon nitride, silicon oxide, but not limited to) can be positioned above the passivation material, above sidewalls defining the holes extending through the passivation material, and above the plate within the hole. The dielectric material can also be used as an additional process step compared to prior art techniques known to the inventor for forming the BEOL structure.A protective material can be positioned within a section of one of the holes, which may be a further additional process step compared to prior art techniques for forming the BEOL structure known to the inventor. For example, the protective material may be a photoresist material that is initially applied over the entire surface of exposed areas of the dielectric material to a thickness less than the depth of the hole and is then partially removed (e.g., by placing a mask over the photoresist material, exposing sections of the photoresist material to which light can pass through the mask).Those quantities of dielectric material that are not covered by the protective material or laterally adjacent to it can be removed, and sections of dielectric material that are laterally adjacent to the protective material in the hole can also be removed, which may be a further additional process step compared to prior art techniques for forming the BEOL structure known to the inventor. The remaining protective material can be removed, whereby dielectric material lying above the plate remains within one of the holes extending into the plate, and dielectric material extending longitudinally along sections of the sidewalls of the passivation material defines the relevant hole.Structuring, etching, and physical vapor deposition of electrically conductive material can create bond junctions within the holes and extend over the passivation material to form another plate of the capacitor in and above the hole, including the dielectric material. One of the bond junctions is used to establish an electrical connection with the plate, utilizing the other bond junction located below the holes. Such a process allows for the cost-effective production of a high-quality, low-resistance, integrated metal-insulator-metal (MIM) capacitor.
[0008] As an alternative embodiment, poly-oxide poly-(POP) capacitors can be formed to fabricate integrated inductor-capacitor oscillators according to this disclosure. As a further alternative embodiment, a metal-oxide-semiconductor (MOS) varactor (e.g., a MOS capacitor) can be formed to fabricate inductor-capacitor oscillators according to this disclosure. For example, the POP capacitor(s) and / or the MOS varactor(s) can be formed prior to the formation of the BEOL.
[0009] A capacitor or capacitor bank configured according to one of the preceding techniques can be operationally connected to an inductor configured according to the preceding techniques to generate an inductor-capacitor oscillator according to this disclosure. For example, the capacitor or capacitor bank can be connected in parallel with the inductor. The capacitance of the inductor-capacitor oscillator can be tuned to generate a desired resonant frequency for the inductor-capacitor oscillator, such as by connecting and / or disconnecting specific capacitors in the bank and / or using non-volatile on-board memory on the substrate.
[0010] Semiconductor devices (e.g., microcontrollers) incorporating integrated inductor-capacitor oscillators according to this disclosure can operate and communicate at a target frequency with a higher degree of accuracy and reliability compared to semiconductor devices relying on in-package resistor-capacitor oscillators without being connected to another external or in-package oscillator (e.g., a crystal-based oscillator). For example, the inductor-capacitor oscillator disclosed herein is more accurate and less temperature-sensitive than a resistor-capacitor oscillator configured to operate at the same resonant frequency. As a result, a wider variety of chip-level modules can be integrated into the semiconductor device, allowing for greater flexibility in system-on-chip approaches.Integrated inductor-capacitor oscillators can also be manufactured at low cost using fewer additional processing functions. Finally, compared to conventional oscillators, integrated inductor-capacitor oscillators can exhibit high quality (e.g., low resistance, little to no temperature variability, more stable frequency response, low noise susceptibility).
[0011] As used herein, the terms “essentially” and “approximately” mean, with respect to a given parameter, property, or condition, and include to such an extent that those skilled in the art would understand that the given parameter, property, or condition is satisfied with a certain degree of variance, such as within acceptable manufacturing tolerances. For example, a parameter that is essentially or approximately a specified value may be at least approximately 90% of the specified value, at least approximately 95% of the specified value, at least approximately 99% of the specified value, or even at least approximately 99.9% of the specified value.
[0012] Fig. Figure 1 is a schematic diagram of a substrate 100 that includes a monolithically integrated inductor-capacitor oscillator 102 according to one embodiment of this disclosure. When the inductor-capacitor oscillator 102 is referred to as "monolithically integrated," it means that the inductor-capacitor oscillator 102 is located on the substrate 100 of a semiconductor device, rather than being a discrete component that is provided and connected to a support structure to which the substrate 100 may be attached, such as a printed circuit board. For example, the integrated inductor-capacitor oscillator 102 may be a component of a system-on-chip configuration for semiconductor devices. The substrate 100 may, for example, include a semiconductor material 104, such as silicon.In some embodiments, the substrate 100 can be configured as a microcontroller or can include a microcontroller as a functional module within the substrate 100. The inductor-capacitor oscillator 102, for example, can be configured as a component of a clock generator or clock module, such as for timing control according to various communication protocols.
[0013] The inductor-capacitor oscillator 102 can include one or more inductors 800 electrically connected to one or more capacitors 300. For simplicity, only a single inductor 800 and capacitor 300 are shown, but the inductor-capacitor oscillators 102 according to this disclosure can include multiple inductors 800, multiple capacitors 300, or multiple inductors 800 and multiple capacitors 300 (e.g., in respective banks or arrangements) mounted on and monolithically integrated into the substrate 100. Each inductor 800 can, for example, include coils 106 that enclose electrically conductive material and overpass / underpass regions 108 that allow adjacent coils 106 to pass over or under each other without being electrically or otherwise operationally connected within the overpass / underpass regions 108.In some embodiments, each capacitor 300 can, for example, include a first plate 112 enclosing an electrically conductive material, a second plate 110 enclosing an electrically conductive material, and a dielectric material 315 (see . Fig. 3), which is arranged between the first plate 112 and the second plate 110. The inductor(s) 800 and the capacitor(s) 300 can, for example, be connected in parallel to form the inductor-capacitor oscillator 102. In particular, the inductor(s) 800 and the capacitor(s) 300 can be connected to each other by one or more connectors 116 in the form of, for example, wires, conductors, traces and / or other structures for conducting electric current, which can be part of the BEOL structure. The inductor-capacitor oscillator 102, which includes the inductor(s) 800 and the capacitor(s) 300, can form at least one section of a timing signal generator 118 (e.g., a clock generator, without being limited thereto) for the substrate 100.
[0014] Fig. Figure 2 is a flowchart of a method 200 for manufacturing an inductor-capacitor oscillator according to this disclosure, such as the inductor-capacitor oscillator 102 of Fig. 1. Method 200 can, for example, form an inductor (e.g., the inductor 800 of Fig. 1, without being limited thereto) at least partially during the formation of a BEOL structure on a substrate comprising a semiconductor material, as specified in Procedure 202. In particular, the inductor may be formed by forming sections of coils of a first thickness and by forming transition regions and underpass regions of a second, lesser thickness, which connect the sections of coils to one another, as further specified in Procedure 202. As a specific, non-limiting example, a section of the inductor may be formed using electrically conductive materials (e.g.,Copper, a copper mixture, or a copper alloy) positioned on or above the substrate, in conjunction with a final layer formed using a damascening process, to create sections of the coils and the transition / underpass regions. Continuing this specific, non-restrictive example, another section (e.g., a remnant) of the inductor can be formed using a different amount of electrically conductive material (e.g., aluminum, an aluminum mixture, or an aluminum alloy) positioned above the substrate in connection with the formation of the BEOL structure to create remnants of the coils and the transition / underpass regions.
[0015] Method 200 can also be used to form a capacitor (e.g., capacitor 300). Fig. 1, without being limited thereto) which is deposited on and / or embedded in the semiconductor material of the substrate, as specified in Procedure 204. In particular, the capacitor may be formed before or during the formation of the BEOL structure, as further specified in Procedure 204. In some embodiments in which the capacitor is formed during the formation of the BEOL structure, a portion of the capacitor may be formed using electrically conductive material (e.g., copper, a copper mixture, or a copper alloy) positioned on or above the substrate, in conjunction with a final layer formed using a damascening process to form the first plate. In these embodiments, another portion (e.g., a remainder) of the capacitor may be formed using a different amount of electrically conductive material (e.g.,Aluminum, an aluminum mixture, or an aluminum alloy) positioned above the substrate, in conjunction with the formation of the BEOL structure to form the second plate and an electrical connection with the first plate, and using dielectric material positioned above the substrate, in conjunction with the formation of the BEOL structure to form the dielectric region of the capacitor. In other embodiments, where the capacitor is formed before the formation of the BEOL structure, the capacitor can be a POP capacitor or a MOS varactor formed at least partially using doped regions of the substrate.
[0016] Finally, method 200 can connect the inductor to the capacitor (e.g. using connectors 116 from Fig. 1, without being limited thereto) in parallel to forming an integrated inductor-capacitor oscillator, as specified in Procedure 206. In particular, the inductor may be at least partially electrically connected to the capacitor using the BEOL structure to form the inductor-capacitor oscillator. As a specific, non-limiting example, the connectors 116 (see Fig. 1) in the form of wires, conductors, conductive tracks and / or other structures for conducting the electric current within the BEOL structure and may be formed simultaneously with the rest of the BEOL structure, including the inductor and / or the capacitor.
[0017] Fig. Figure 3 is a cross-sectional view of an illustrative capacitor 300, which is used to form the inductor-capacitor oscillator 102 of Fig. 1 is usable. The capacitor 300 can, for example, include a first plate 112, which can also be referred to as a "bottom plate", which is placed on or above the substrate 100. The first plate 112 can, for example, include a quantity of electrically conductive material positioned on or above the substrate 100, in conjunction with a final layer of a connector 302 formed using a damascening process. In particular, the first plate 112 can, for example, include a mass of copper, copper mixture, or copper alloy forming the first plate 112, which can also be located within a top layer of the connector 302 formed on the substrate 100 using a damascening process.The connecting element 302 can be used in the capacitor 300 to be electrically and operationally connected to one or more transistor regions 304, which can also be referred to as "other integrated switching logic", including doped regions within the semiconductor material 104 of the substrate 100. In some embodiments, the transistor regions 304 themselves can include one or more capacitors 342 in the form of, for example, a POP capacitor and / or MOS varactor(s).
[0018] The first plate 112 can be mounted within another dielectric material 306 of the connector 302. The connector 302 can, for example, enclose regions of electrically conductive material and regions of the other dielectric material 306 that are selectively positioned to allow the regions of electrically conductive material (e.g., that of the first plate 112 and any other electrically conductive structures of the connector 302) to electrically connect selected electronic components without forming unwanted connections (e.g., short circuits). For example, the first plate 112 can be partially surrounded by and mounted within a barrier material 308 (e.g., Ta, TaN) that is positioned between the first plate 112 and the other dielectric material 306.The barrier material 308 can be positioned to reduce the probability that the material of the first plate 112 can come into contact with and contaminate the semiconductor material of the substrate 100. For the sake of clarity, the illustration is shown in . Fig. Figure 3 shows only the topmost layer of the connecting piece 302; however, connecting pieces according to this disclosure can include additional layers, such as layers arranged between the first plate 112 and the substrate 100, without being limited thereto. The other dielectric material 306 can, for example, include an oxide material (e.g., silicon oxide, silicon dioxide, without being limited thereto).
[0019] A passivation material 310 can be located over at least a section of the first plate 112, any exposed sections of the barrier material 308, and a major surface of the other dielectric material 306 on one side of the other dielectric material 306 facing the substrate 100. For example, the passivation material 310 can cover sections of the first plate 112 and all of the other dielectric material 306. The passivation material 310 can be positioned and configured to laterally surround at least a section of the second plate 110 and partially cover the first plate 112 of the capacitor 300. The passivation material 310 can, for example, include oxides, nitrides, glasses, polymers, or combinations or subcombinations thereof (e.g., silicon oxynitride, silicon oxide, silicon nitride, silicon-rich nitride, phosphosilicate glass, but not limited to).
[0020] A first hole 312 can extend through the passivation material 310 from one side of the passivation material 310 opposite the first plate 112 towards the first plate 112 at a first location located above the first plate 112, and a second hole 314 can extend through the passivation material 310 in the same direction and at a second, offset location located above the first plate 112. For further clarification, reference is made to Fig. Figure 5, which shows the first hole 312 and the second hole 314 in an unoccupied state. For clarity, the lines associated with reference numerals 312 and 314 terminate at the side walls of the passivation material 310, which define the first hole 312 and the second hole 314, instead of terminating within the electrically conductive material that contains the first hole 312 and the second hole 314. Fig. 3 occupied. The first hole 312 can, for example, be positioned and configured such that it carries and defines a dielectric region 316 and a second plate 110 of the capacitor 300 at least partially within the first hole 312, with the dielectric region 316 being located adjacent to the first plate 112 and the second plate 110 being located adjacent to the dielectric region 316 on one side of the dielectric region 316 opposite the first plate 112. For example, the dielectric region 316 of the capacitor 300, which can also be called an "insulator" and which includes the dielectric material 315, can be positioned in the first hole 312 adjacent to the first plate 112. The dielectric region 316 can be positioned and configured to physically and electrically separate the first plate 112 and the second plate 110 of the capacitor 300 from each other and to impart properties (e.g.,The properties (e.g., electrical resistance, mass, thickness) of the dielectric material 315 can at least partially determine the properties (e.g., capacitance, breakdown voltage) of the capacitor 300. The second hole 314, for example, can be positioned and configured to carry and define an electrical connection 330 for electrical connection to the first plate 112 of the capacitor 300 through the passivation material 310. A second plate 110 of the capacitor 300 can, for example, occupy a remnant of the first hole 312 and extend from direct uniform contact with the dielectric region 316 at least to an opening of the first hole 312 that is located opposite the substrate 100, and optionally laterally and longitudinally beyond the opening.
[0021] For example, the dielectric region 316 can extend laterally along a surface 318 of the first plate 112 and cover it, which would otherwise be exposed within the first hole 312. More precisely, a first section 320 of the dielectric material 315 of the dielectric region 316 can, for example, be in direct contact with the surface 318 of the first plate 112 and extend laterally over an entire surface area of the first hole 312, as projected onto the surface 318 of the first plate 112, thereby closing the first hole 312. The dielectric material 315 of the dielectric region 316 can further extend, for example, along a section of the side wall 322 of the passivation material 310, which defines the first hole 312.In particular, a second section 334 of the dielectric material 315 of the dielectric region 316 can, for example, be in direct contact with a section of the side wall 322 of the passivation material 310, which defines the first hole 312 extending from a location near the first plate 112 away from the first plate 112 to a location within the first hole 312 along the side wall 322. A transition from the first section 320 of the dielectric material 315 to the second section 334 can, for example, be gradual. More precisely, at least one internal corner 324 of the dielectric material 315 at the transition from the first section 320 to the second section 334 can be rounded. As a specific, non-limiting example, the dielectric material 315 of the dielectric region 316 can have a cup shape (e.g.,a hollow cylinder (at least substantially straight with a closed end) which is supported on the first plate 112 within the first hole 312. The dielectric material 315 of the dielectric region 316 can, for example, include an oxide or nitride material (e.g., SiO, SiN).
[0022] A second plate 110, which can also be referred to as the "top plate" of the capacitor 300, can be located at least partially within the first hole 312. For example, the second plate 110 can enclose a further quantity of electrically conductive material, which is positioned in the dielectric region 316 in connection with the formation of the BEOL structure 340 and which can, for example, enclose and form at least a section of the second plate 110, at least a section of the electrical connection 330, and the passivation material 310. In particular, the second plate 110 can, for example, enclose a mass of aluminum, aluminum mixture, or aluminum alloy located within a bottom layer of the passivation material 310, which is deposited above the substrate 100 while the BEOL structure 340 is formed. For the sake of simplicity, in Fig. Figure 3 shows only the bottommost layer of a BEOL structure 340; however, BEOL structures according to this disclosure can include additional layers, such as layers located on one side of the illustrated second plate 110 opposite the substrate 100, without being limited thereto. As a specific, non-limiting example, the second plate 110 can include a mass of electrically conductive material that occupies a residue of the first hole 312 and extends from direct, uniform contact with the dielectric material 315 of the dielectric region 316 at least to an opening of the first hole 312 located opposite the substrate 100, and optionally laterally and longitudinally beyond the opening, in the form of a first bond contact point.The dielectric material 315 of the dielectric region 316 can be located longitudinally between the first plate 112 and the second plate 110, can extend longitudinally along a section of a periphery of the second plate 110, and can extend laterally over a surface of the second plate 110 that is bounded by the side walls 322 that define the first hole 312.
[0023] A transition from a surface 326 of the second plate 110, adjacent to the dielectric region 316, to a lateral side surface 328 of the second plate 110, adjacent to the second section 334 of the dielectric region 316 and the side wall 322 of the first hole 312, can, for example, occur gradually. In particular, at least one outer corner 332 of the second plate 110 at the transition from the surface 326 near the first plate 112 to the lateral side surface 328 can be rounded (e.g., chamfered) by adapting the electrically conductive material of the second plate 110 to a shape of the dielectric material 315 within the first hole 312.As a non-restrictive example, rounding the corner 324 of the dielectric region 316 and the corner 332 of the adjacent second plate 110 can increase the breakdown voltage of the capacitor 300, since the rounded corners 324, 332 can reduce the concentration of the electric field that would otherwise occur if the corners 324, 332 were sharp (i.e., not rounded).
[0024] An electrical connection 330 with the first plate 112 of the capacitor 300 can be located within a second hole 314 defined by the passivation material 310. For example, the electrical connection 330 can enclose a quantity of electrically conductive material in direct contact with a section of the surface 318 of the first plate 112 within the second hole 314 and occupy at least substantially an entirety of the second hole 314. In particular, the electrical connection 330 can, for example, enclose a mass of aluminum, aluminum mixture, or aluminum alloy located within a bottom layer of the passivation material 310 deposited above the substrate 100 while the BEOL structure 340 is formed.As a specific, non-restrictive example, the electrical connection 330 can include a mass of electrically conductive material that occupies at least substantially an entirety of the second hole 314 from a point adjoining (e.g., in direct contact, without being limited to) the surface 318 of the first plate 112 to a point near an opening of the second hole 314 and located opposite the substrate 100. Optionally, the mass of electrically conductive material can extend laterally and longitudinally beyond the opening of the second hole 314 in the form of a second bond contact point. The electrical connection with the capacitor 300 can be achieved by direct electrical connection to the second plate 110 and indirectly to the first plate 112 via the electrical connection 330.
[0025] Fig. Figure 4 is a cross-sectional view of a first intermediate product 400 in a process for producing the capacitor 300. Fig. 3. When producing the first intermediate product 400 and with combined reference to Fig. 3 and Fig. 4. The passivation material 310 can be placed above the last layer of the connector 302 on one side of this layer facing the substrate 100. For example, the passivation material 310 can be in direct contact with and cover the first plate 112, with any exposed sections of the barrier material 308 partially surrounding the first plate 112 and the other dielectric material 306, in which the barrier material 308 and the first plate 112 may be embedded. The passivation material 310 can be placed, for example, using plasma-enhanced chemical vapor deposition (PEVCD).
[0026] Fig. Figure 5 is a cross-sectional view of a second intermediate product 500 in the process for manufacturing the capacitor 300. Fig. 3. When producing the second intermediate product 500 and with combined reference to Fig. 3 and Fig. 5. A protective material 502 can be placed on a surface of the passivation material 310 opposite the substrate 100. The protective material 502 can, for example, enclose a photoresist material. A mask can be placed over these remaining sections of the protective material 502 to protect the underlying sections of the passivation material 310, and remaining sections of the protective material 502 can be removed (e.g., by exposure to light). Exposed sections of the passivation material 310 that are not directly beneath the protective material 502 can be removed, forming the first hole 312 and the second hole 314, and exposing the surface 318 of the first plate 112 within the first hole 312 and the second hole 314. The removal of the exposed sections of the passivation material 310 can be achieved, for example, by an etching process.
[0027] Fig. Figure 6 is a cross-sectional view of a third intermediate product 600 in the process for manufacturing the capacitor 300. Fig. 3. Before producing the third intermediate product 600 and with combined reference to Fig. 3 and Fig. 6. The protective material 502 (see Fig. 5) be removed (e.g., by mechanically detaching the protective material 502, exposing the protective material 502 to light, dissolving the protective material 502 in a solvent, and / or performing a combination thereof). A dielectric material 315 can be placed over the exposed surfaces of the passivation material 310 and the first plate 112. For example, the dielectric material 315 can be in direct contact with and cover a surface of the passivation material 310 located on one side of the passivation material 310 facing the substrate 100, the sections of the surface 318 of the first plate 112 in the first hole 312 and the second hole 314, and the side walls 322 of the passivation material 310 that define the first hole 312 and the second hole 314. The dielectric material 315 can be placed, for example, using plasma-enhanced chemical vapor deposition (PEVCD).
[0028] Fig. Figure 7 is a cross-sectional view of a fourth intermediate product 700 in the process for manufacturing the capacitor 300. Fig. 3. When producing the fourth intermediate product 700 and with combined reference to Fig. 3 and Fig. 7. A different amount of the protective material 502 can be placed on the dielectric material 315 on one side of the dielectric material 315 facing the substrate 100. A mask can be placed over these remaining sections of the protective material 502 to protect the underlying sections of the dielectric material 315, and any remaining sections of the protective material 502 can be removed (e.g., by exposure to light). Exposed sections of the dielectric material 315 that are not directly beneath the protective material 502 can be removed, thus preserving the dielectric region 316 of the capacitor 300 (see Figure 7). Fig. 3) and a remainder of the first hole 312, an entirety of the second hole 314, and the surface 318 of the first plate 112 within the second hole 314, and the surface of the passivation material 310, which is located opposite the substrate 100, are exposed. The removal of the exposed sections of the dielectric material 315 can be achieved, for example, by an etching process.
[0029] The protective material 502 can then be used with any combination or subcombination of the previously used in conjunction with Fig. The processes discussed in section 6 are removed. Afterwards, electrically conductive material can be placed in the remainder of the first hole 312 and in the second hole 314, forming the second plate 110 and the electrical connection 330. Electrically conductive material can be placed, for example, using physical vapor deposition (PVD). Afterwards, the capacitor 300 can be at least substantially complete, thus completing the Fig. The structure shown in section 3 is formed.
[0030] Fig. Figure 8 is a top view of an illustrative inductor 800, which is used to form the inductor-capacitor oscillator of Fig. 1 is usable. The inductor 800 can be located in the same layers on the substrate 100 as previously described in connection with certain embodiments for the capacitor 300 (see Fig. 3), wherein the capacitor 300 is formed at least partially during the formation of the BEOL structure. The inductor 800 can include coils 106 extending from an input point 802 to an output point 804, the coils 106 forming a winding path from a radially outermost coil to a radially innermost coil and back again (or vice versa). The coils 106 can be formed, for example, from wires, conductors, traces, and / or other structures for directly conducting electric current through the inductor 800. Amounts of electrically insulating material, such as the passivation material 310 (see Fig. 3) can be located, for example, at a radial center of the inductor 800 (e.g., radially within the coils 106) and radially between each adjacent coils 106. The coils 106 can generally have a rectangular (e.g., square), polygonal (e.g., hexagonal, octagonal), or circular shape when viewed in a plane parallel to a principal surface of the substrate 100 (see Fig. 1) The shape, size, and spacing of the coils 106 may depend, for example, on the magnetic flux, length, and resistance specifications of the inductor 800. In some embodiments, the coils 106 may be symmetrical (e.g., having essentially the same mirrored shape about an axis of symmetry, but for multiple overpass / underpass regions 108). In other embodiments, the coils 106 may be asymmetrical (e.g., having at least one difference when mirrored about an axis of symmetry, such as having an overpass / underpass region 108 on one side without a corresponding overpass / underpass region 108 on the opposite side).
[0031] Electrically isolated sections of the coils 106 within the overpass / underpass regions 108 are in Fig. 8 are shown such that they are aligned at oblique angles to the other sections of the coils 106. Electrically isolated sections of the coils 106 within the overpass / underpass regions 108, however, can take any path between the coils 106 within the plane of the respective isolated section, such as a stair-step pattern, with sections of the stair extending alternately parallel, then perpendicular, then parallel, and so on to the remains of the coils 106. Furthermore, the inductors 800 according to this disclosure can include any number of coils 106 (e.g., turns). Additional details regarding the previously mentioned varying thicknesses of the coils 106 at different locations around the coils 106 can be obtained from a comparison of Fig. 9 with Fig. 10 are derived, which have a cross-section of the coils 106 outside ( Fig. 9) and within ( Fig. 10) of the overpass / underpass regions 108.
[0032] Fig. Figure 9 is a cross-sectional view of a first section of the integrated inductor 800. Fig. 8 along line 806. The one in Fig. Section 9 shown can correspond to the sections of the coils 106 that do not form the transition / underpass regions 108. In such sections, the coils 106 can enclose a first quantity of electrically conductive material 902 embedded in the dielectric material of the connector 302, and a second quantity of electrically conductive material 904 embedded in the passivation material 310 of the BEOL structure in direct contact with the first quantity of electrically conductive material 902. In particular, the first quantity of electrically conductive material 902 can, for example, be partially surrounded by the barrier material 308 embedded in the other dielectric material 306 and be formed as part of a final layer of the connector 302, similar to the first plate 112 of the capacitor 300 (see Fig. 3) At least one section of the second quantity of electrically conductive material 904 can, for example, be laterally surrounded by the passivation material 310, and the second quantity of electrically conductive material 904 can be formed as part of the first layer of the BEOL structure, similar to the second plate 110 of the capacitor 300 (see Fig. 3) These sections of the coils 106 can be formed using procedures previously described in connection with Fig. 4 to Fig. 7 described, which represent the formation of the capacitor 300, and in particular those procedures relating to the first plate 112 and the electrical connection 330.
[0033] Fig. Figure 10 is a cross-sectional view of another section of the inductor 800. Fig. 8 along line 808. The one in Fig. The section shown in Figure 3 can correspond to the sections of the coils 106 that form the transition / underpass regions 108. In such sections, one of the coils 106 passing underneath can enclose the first quantity of electrically conductive material 902, which is embedded in the other dielectric material 306 of the connecting piece 302, thereby forming a first layer 1002. Another of the coils 106, passing underneath, can enclose the second quantity of electrically conductive material 904, which is deposited on the passivation material 310 of the BEOL structure, thereby forming a second layer 1000. The passivation material 310 can physically, electrically, and operationally isolate the first quantity of electrically conductive material 902 from the second quantity of electrically conductive material 904. These sections of the coils 106 can be formed using procedures previously described in connection with Fig. 4 to Fig. 7 described the formation of the capacitor 300, except that no opening can be formed in the passivation material 310 within the overpass / underpass regions 108, thereby keeping the first quantity of electrically conductive material 902 separated from the second quantity of electrically conductive material 904 by the passivation material 310.
[0034] Fig. Figure 11 is a schematic diagram of an electronic system 1100, including the substrate of Fig.1. For example, the electronic system 1100 can include a control unit 1102 and a probe unit 1104. The probe unit 1104 can include a sensor device 1106 configured to generate an electrical signal representative of and responding to a detected physical phenomenon. The probe unit 1104 can be a portable device, such as a handheld device. In some embodiments, the probe unit 1104 can include a semiconductor device, including a substrate 100 according to this disclosure, located within the probe unit 1104, the substrate 100 of the semiconductor device being configured to process the electrical signal at least partially locally within the probe unit 1104. The probe unit 1104 can be operationally connected to the control unit 1102 (e.g.,via a wired or wireless connection) and can send the raw, partially processed, or fully processed electrical signal to the control unit 1102. In some embodiments, the control unit 1102 may include another semiconductor device having a substrate 100 according to this disclosure and / or a microprocessor 1108 that can process or further process the electrical signal. The control unit 1102 may include a storage device 1110 (i.e., a physical hardware storage device that is not a transient signal) configured to store the results of the fully processed electrical signal. The control unit 1102 may optionally include an output device 1112 (e.g., an electronic display, a loudspeaker, a printer, but not limited to) configured to output the results of the fully processed electrical signal.
[0035] Compared to conventional configurations and techniques for forming integrated inductor-capacitor oscillators, configurations and techniques for forming integrated inductor-capacitor oscillators according to this disclosure can involve performing fewer process operations, exhibit greater synergy with process operations used to form other structures (e.g., bond junctions, interconnects, BEOL structures), reduce dependence on dedicated process operations and interconnect structures (e.g., vias and the processes for forming vias), and produce integrated inductor-capacitor oscillators of higher quality.For example, techniques for forming integrated inductor-capacitor oscillators according to this disclosure can enable one or more components of the integrated inductor-capacitor oscillators to be formed simultaneously with and using the same materials as the bond contact points of the same semiconductor device. As another example, integrated inductor-capacitor oscillators having configurations according to this disclosure can feature higher inductance, lower resistance, lower-capacitance inductors, and higher-breakdown-voltage capacitors, thereby producing higher-quality integrated inductor-capacitor oscillators.
[0036] While certain illustrative embodiments have been described in connection with the figures, a person skilled in the art will recognize and acknowledge that the scope of this disclosure is not limited to the embodiments explicitly shown and described herein. Rather, many additions, deletions, and modifications can be made to the embodiments described herein to create embodiments within the scope of protection of this disclosure, such as those specifically claimed, including statutory equivalents. Furthermore, features from one disclosed embodiment can be combined with features from another disclosed embodiment while still remaining within the scope of protection of this disclosure, as the inventor may have considered. QUOTES INCLUDED IN THE DESCRIPTION
[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature
[0000] US 62 / 961635
[0001] US 16 / 549635
[0006]
Claims
[1] System-on-Chip, comprising: an inductor-capacitor oscillator that is monolithically integrated into the system-on-chip, wherein at least one section of an inductor of the inductor-capacitor oscillator is part of a back-end-of-line (BEOL) structure of the system-on-chip. [2] System-on-Chip according to claim 1, wherein the inductor comprises sections of coils within two adjacent layers mounted on a semiconductor substrate of the system-on-chip and crossover regions and underpass regions connecting the sections of the coils, wherein the crossover regions are located within one of the two adjacent layers, and wherein the underpass regions are located within another of the two adjacent layers. [3] System-on-Chip according to claim 1, wherein at least one section of a capacitor of the inductor-capacitor oscillator is part of the BEOL structure of the system-on-chip. [4] System-on-Chip according to claim 3, wherein a second plate of the capacitor is located within a second layer which is mounted on a semiconductor substrate of the system-on-chip, wherein a first plate of the capacitor is located within a first underlying layer which is mounted on the semiconductor substrate, and a dielectric material of the capacitor is located between the first plate and the second plate. [5] System-on-Chip according to claim 4, wherein a transition from a surface of the second plate facing the first plate to a lateral side surface of the second plate is rounded. [6] System-on-Chip according to claim 4, wherein the dielectric material extends laterally between the second plate and the first plate and longitudinally along a section of a circumference of the second plate, such that the dielectric material forms at least substantially a cup shape. [7] System-on-Chip according to claim 4, wherein the second plate comprises a first bond contact point formed in the BEOL structure. [8] System-on-Chip according to claim 7, wherein an electrical connection with the first plate comprises a second bond contact point formed in the BEOL structure. [9] System-on-Chip according to claim 4, wherein the second plate comprises a copper or copper alloy material and the first plate comprises an aluminum or aluminum alloy material. [10] System-on-Chip according to claim 1, wherein a capacitor of the inductor-capacitor oscillator is a poly-oxide-poly capacitor (POP capacitor). [11] System-on-Chip according to any one of claims 1 to 10, wherein the inductor-capacitor oscillator forms at least one section of a timing signal generator of the system-on-chip. [12] System-on-Chip according to any one of claims 1 to 10, wherein the inductor-capacitor oscillator is monolithically integrated with another integrated circuit of the system-on-chip. [13] Method for manufacturing an integrated oscillator, comprising: Forming an inductor at least partially during the formation of a back-end-of-line (BEOL) structure on a substrate comprising a semiconductor material by forming sections of coils of a first thickness and connecting the coil sections with transition regions and underpass regions of a second, lower thickness; Forming a capacitor that is mounted on and / or embedded in the semiconductor material of the substrate, before or during the formation of the BEOL structure; and Parallel connection of the inductor with the capacitor, at least partially, using the BEOL structure to form an integrated inductor-capacitor oscillator. [14] Method according to claim 13, wherein forming the capacitor comprises: Forming a first plate of the capacitor within a top layer of a connector on the substrate using a damascening process; Placing a passivation material over the first plate; Forming a first hole and a second hole through the passivation material to release a respective section of the first plate within each of the first hole and the second hole; Forming a dielectric region of the capacitor by placing a dielectric material within a section of the first hole, wherein the dielectric material covers the respective section of the first plate near the first hole; Forming a second plate of the capacitor and an electrical connection with the first plate by placing an initial amount of an electrically conductive material within a residue of the first hole in contact with the dielectric material while the BEOL structure is formed. [15] Method according to claim 13 or claim 14, wherein forming the dielectric region comprises: Full-surface application of the dielectric material over a surface of the passivation material located opposite the first plate, over side surfaces of the passivation material defining the first hole and the second hole, and over the respective sections of the first plate within the first hole and the second hole; Placing a protective material within a section of the first hole over a section of the dielectric material near the first plate; Removing any remaining dielectric material that is not in contact with the protective material, whereby the passivation material and the respective section of the first plate within the second hole become visible; and removing the protective material.