Semiconductor housing, semiconductor device and power converter device

Abstract

Semiconductor package (100) comprising: - a semiconductor element (1); - a first insulating layer (5) covering the semiconductor element (1) and having a first through-hole (TH1) and a second through-hole (TH2); - a first wiring layer (6) comprising a first layer region (61) covering the first insulating layer (5) and electrically connected to the semiconductor element (1) through the first through-hole (TH1); - a second insulating layer (7) covering the first insulating layer (5) and the first wiring layer (6) and having a third through-hole (TH3) connected to the second through-hole (TH2); and - a second wiring layer (8) comprising a second layer region (81) covering the second insulating layer (7) and electrically connected to the semiconductor element (1) through the second through-hole (TH2) and the third through-hole (TH3).wherein the second layer region (81) of the second wiring layer (8) has a region that lies above the first layer region (61) of the first wiring layer (6), wherein the second insulating layer (7) is arranged between them, wherein the first wiring layer (6) has a first connection region (63), the second wiring layer (8) has a second connection region (83), the first connection region (63) and the second connection region (83) each have an exposed region on one side that is opposite to the semiconductor element (1) with respect to the first insulating layer (5), and a direction of current flowing through the first layer region (61) of the first wiring layer (6) to a direction of current flowing opposite to that flowing through the region of the second layer region (81) that is superimposed on the first layer region (61) of the first wiring layer with the second insulating layer (7) arranged between them.

Description

Technical field The present invention relates to a semiconductor housing, a semiconductor device and a power converter device. State of the art Semiconductor devices are typically referred to as power semiconductor devices. Power semiconductor devices are designed for high voltages and high currents. In some power semiconductor devices, a current-carrying path extends along the vertical direction of the device. A power semiconductor package containing a power semiconductor device, mounted on a printed circuit board and encapsulated in resin, is connected to a heat sink, a control component, and other accessories. The power semiconductor package, connected to a heat sink, is used as a semiconductor device in a variety of applications, ranging from industrial equipment and automobiles to railways. In recent years, with the reduction of the size and weight of devices containing semiconductor devices, there has been a need to further reduce the size and weight of power semiconductor packages. For example, a semiconductor device module (semiconductor package) described in Japanese patent JP 2014-179 612 A (PTL 1) contains a semiconductor device (semiconductor element), a dielectric layer (first insulating layer), and a metallization layer (first wiring layer). The semiconductor module can be used as a power semiconductor package. The dielectric layer is deposited onto the semiconductor element. The dielectric layer has a through-hole that overlaps the semiconductor device. The metallization layer is electrically connected to an electrode of the semiconductor device through this through-hole. The wiring of the metallization layer is thus routed to the surface of the dielectric layer. Therefore, the wiring of the metallization layer is applied directly to the dielectric layer. This configuration allows for a reduction in the size of the semiconductor module along its width. The power semiconductor element of a power semiconductor package operates under high voltage and current during switching. When the power semiconductor element changes from the off state to the on state during the switching process, a surge voltage is applied to it. The magnitude of this surge voltage is proportional to the rate of change of the current and the inductance of the power semiconductor package's wiring. If the surge voltage is high, the power semiconductor element can be damaged. Therefore, it is necessary to reduce the inductance and simultaneously reduce the size of power semiconductor packages. German patent literature DE 10 2016 105 581 A1 (PTL 2) describes a redirection of solder material to a visually inspectable packing surface. The Japanese patent literature JP 2016 - 163 372 A1 (PTL 3) describes a current conversion device in which the elements are mounted on a printed circuit board and multiple conductors and interfaces to other elements are possible in a very small space. Bibliography Patent documents PTL 1: Japanese patent literature JP 2014-179612 APTL 2: German patent literature DE 10 2016 105581 A1 PTL 3: Japanese patent literature JP 2016-163372 A1 Summary of the invention Technical problem In the semiconductor package (semiconductor device module) described in the aforementioned literature, the wiring becomes complex when the wiring of the first wiring layer (metallization layer) is arranged to ensure insulation distance between adjacent wires. With such a complex wiring, it is difficult to control the direction of current flow through adjacent wires, and therefore current can flow in the same direction through them. Consequently, the first wiring layer is affected by the magnetic flux caused by the current. Therefore, reducing the inductance of the semiconductor package becomes challenging. The present invention was conceived with regard to the above problem, and the object of the present invention is to provide a semiconductor package with reduced inductance, a semiconductor device and a power converter device. Solution to the problem A semiconductor package according to the present invention comprises a semiconductor element, a first insulating layer, a first wiring layer, a second insulating layer, and a second wiring layer. The first insulating layer covers the semiconductor element. The first insulating layer has a first through-hole and a second through-hole. The first wiring layer has a first layer region. The first layer region covers the first insulating layer. The first wiring layer is electrically connected to the semiconductor element via the first through-hole. The second insulating layer covers the first insulating layer and the first wiring layer. The second insulating layer has a third through-hole. This third through-hole is connected to the second through-hole. The second wiring layer is electrically connected to the semiconductor element via the second and third through-holes. The second wiring layer contains a second layer region. This second layer region covers the second insulating layer. The second layer region of the second wiring layer includes a region that overlaps the first layer region of the first wiring layer, with the second insulating layer interposed. Advantageous effects of the invention In the semiconductor package according to the present invention, the second layer region of the second wiring layer has a region that lies above the first layer region of the first wiring layer. In this configuration, the direction of the current flowing through the region of the second layer that lies above the first layer region of the first wiring layer can be opposite to the direction of the current flowing through the first layer region. Thus, the effects of the magnetic fluxes from the current flowing through the first layer region and the current flowing through the second layer region can cancel each other out. Accordingly, the inductance of the semiconductor package can be reduced. Brief description of the drawings Fig. 1 is a cross-sectional view schematically showing a configuration of a semiconductor package according to a first embodiment. Fig. 2 is a top view schematically showing a configuration of the semiconductor package according to the first embodiment. Fig. 3 is a top view schematically showing a configuration of a semiconductor element, a conductive plate, and a heat sink in the semiconductor package according to the first embodiment. Fig. 4 is a top view schematically showing a configuration of the semiconductor element, the conductive plate, the heat sink, a first insulating layer, and a first wiring layer in the semiconductor package according to the first embodiment.Figure 5 is a top view schematically showing a configuration of the semiconductor element, the conductive plate, the heat sink, the first insulating layer, the first wiring layer, a second insulating layer, and a second wiring layer in the semiconductor package according to the first embodiment. Figure 6 is a cross-sectional view schematically showing a configuration of a semiconductor package according to a first comparative example. Figure 7 is a top view schematically showing a configuration of the semiconductor package according to the first comparative example. Figure 8 is a cross-sectional view schematically showing a configuration of a semiconductor package according to a second embodiment. Figure 9 is a cross-sectional view schematically showing a configuration of a semiconductor package according to a third embodiment.Figure 10 is a cross-sectional view schematically showing a configuration of a semiconductor package according to a fourth embodiment. Figure 11 is a cross-sectional view schematically showing a configuration of a semiconductor package according to a second comparative example. Figure 12 is a cross-sectional view schematically showing a configuration of a semiconductor package according to a fifth embodiment. Figure 13 is a cross-sectional view schematically showing a configuration of a semiconductor package according to a sixth embodiment. Figure 14 is a cross-sectional view schematically showing a configuration of a semiconductor device according to a seventh embodiment.Figure 15 is a cross-sectional view schematically showing a state in which a first insulating layer, a first wiring layer, a second insulating layer, a second wiring layer, and an organic layer are stacked in a semiconductor package of the semiconductor device according to the seventh embodiment. Figure 16 is a cross-sectional view schematically showing a state in which a semiconductor element and a conductive plate are connected to a heat sink in the semiconductor package of the semiconductor device according to the seventh embodiment. Figure 17 is a cross-sectional view schematically showing a configuration of a semiconductor device according to an eighth embodiment. Figure 18 is a cross-sectional view schematically showing a configuration of a semiconductor device according to a ninth embodiment.Figure 19 is a cross-sectional view schematically showing a state in which a semiconductor package and a heat sink are connected in the semiconductor device according to the ninth embodiment. Figure 20 is a block diagram schematically showing a configuration of a power converter device according to a tenth embodiment. Description of the embodiments The embodiments are described below with reference to the drawings. In the following, identical or corresponding parts are designated with the same reference numerals, and an overlapping description is not repeated. First embodiment With reference to Figs. 1, 2, 3, 4 to 5, a configuration of a semiconductor package 100 according to a first embodiment is described. Fig. 1 is a cross-sectional view along line II in Fig. 2. As shown in Fig. 1, the semiconductor package 100 comprises a semiconductor element 1, a first insulating layer 5, a first wiring layer 6, a second insulating layer 7, and a second wiring layer 8. The semiconductor package 100 according to the present embodiment further comprises a conductive plate 2, a bonding material 3, a heat spreader 4, a sealing area 9, and an organic layer OL. The semiconductor package 100 is a power semiconductor package. The power semiconductor package is a semiconductor package 100 containing a power semiconductor element described later. The semiconductor element 1 according to the present embodiment is a power semiconductor element. In the present embodiment, the power semiconductor element is a semiconductor element for handling high voltage or high current. The power semiconductor element is, for example, a semiconductor element for electrical energy. In particular, the power semiconductor element is a power-control semiconductor element, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated-gate bipolar transistor (IGBT), a freewheeling diode, or the like. The semiconductor element 1 according to the present embodiment is a vertical semiconductor element. Therefore, the current flows in the direction from the front to the back of the semiconductor element 1. The front surface of the semiconductor element 1 is designed as an electrode. The semiconductor element 1 is connected to the heat spreader 4 via the bonding material 3. The bonding material 3 can be, for example, solder, sintered silver (Ag), or a conductive adhesive. The connection between the semiconductor element 1 and the heat spreader 4 is not limited to the bonding material 3. The semiconductor element 1 can, for example, be connected to the heat spreader 4 by liquid-phase diffusion. The conductive plate 2 is connected to the heat spreader 4 via the bonding material 3. Thus, the current flowing through the semiconductor element 1 and the heat spreader 4 is conducted through the conductive plate 2 to the first wiring layer 6. The conductive plate 2 is made of a conductive metal, such as copper (Cu) or aluminum (Al). Its thickness is approximately the same as that of the semiconductor element 1. The connection between the conductive plate 2 and the heat spreader 4 is not limited to the use of the bonding material 3. For example, the conductive plate 2 can be connected to the heat spreader 4 by liquid-phase diffusion. The heat spreader 4 has a first surface 41, a second surface 42, and a side surface 43. The semiconductor element 1 and the conductive plate 2 are connected to the first surface 41. The second surface 42 faces opposite the first surface 41. The side surface 43 connects the first surface 41 to the second surface 42. The material of the heat spreader 4 is, for example, a metal with excellent heat dissipation, such as copper (Cu) and aluminum (Al). The first insulating layer 5 covers the semiconductor element 1. The first insulating layer 5 covers the conductive plate 2. The first insulating layer 5 is, for example, a polymer insulating film formed from a polymer material such as liquid crystal polymer and polyimide. The first insulating layer 5 is attached to the respective surfaces of the semiconductor element 1 and the conductive plate 2, e.g., with a resin adhesive (not shown). The first insulating layer 5 has a first through-hole TH1 and a second through-hole TH2. The first through-hole TH1 and the second through-hole TH2 penetrate the first insulating layer 5. The first through-hole TH1 and the second through-hole TH2 are designed as contact holes. In the first insulating layer 5, the first through-hole TH1 and the second through-hole TH2 are formed, for example, by laser processing. The first through-hole TH1 has a first through-hole TH1a and a second through-hole TH1b. The first through-hole TH1a overlaps the semiconductor element 1. The second through-hole TH1b overlaps the conductive plate 2. The second through-hole TH2 overlaps the semiconductor element 1. The first wiring layer 6 is electrically connected to the semiconductor element 1 via the first through-hole TH1. The first wiring layer 6 is designed as a metallic wiring layer. The first wiring layer 6 is formed by structuring. The first wiring layer 6 is formed by the following procedure. After the first insulating layer 5 has been applied to the semiconductor element 1 and the conductive plate 2, the first through-hole TH1 and the second through-hole TH2 are formed in the first insulating layer 5. Subsequently, a metal sputtering layer is applied to the first insulating layer 5. The metal sputtering layer is also deposited in the first through-hole TH1 and the second through-hole TH2. Finally, a coating is formed on the metal sputtering layer. Once the coating has grown to a sufficient thickness, the metal sputter layer and the coating are etched. This creates a wiring pattern for the first wiring layer 6. The method for creating the wiring pattern of the first wiring layer 6 is not limited to the method described above. For example, the wiring pattern of the first wiring layer 6 can be created by depositing a metal layer onto the first insulating layer 5 and then etching the metal layer. The first wiring layer 6 comprises a first layer area 61, a first connection area 62, and a first terminal area 63. The first layer area 61 covers the first insulating layer 5. The first layer area 61 is electrically connected to the semiconductor element 1 via the first connection area 62. The first layer area 61 has the form of a flat plate. The first connection area 62 is located within the first through-hole TH1. The first terminal area 63 is exposed by the second insulating layer 7. The first terminal area 63 is therefore configured as a terminal for connection to external wiring. The first wiring layer 6 has a first wiring region 6a and a second wiring region 6b. In the present embodiment, the first wiring layer 6 has a plurality of first wiring regions 6a, as described later. The first wiring region 6a is electrically connected to the semiconductor element 1 via the first through-area TH1a. The second wiring region 6b is electrically connected to the conductive plate 2 via the second through-area TH1b. In Fig. 1, the first layer region 61 is contained within the second wiring region 6b. The first wiring region 6a and the second wiring region 6b are connected to each other by the semiconductor element 1, the conductive plate 2, and the heat spreader 4. The second insulating layer 7 covers the first insulating layer 5 and the first wiring layer 6. The second insulating layer 7 has a third through-hole TH3. The third through-hole TH3 penetrates the second insulating layer 7. The third through-hole TH3 is designed as a contact hole. The third through-hole TH3 is connected to the second through-hole TH2. The second insulating layer 7 is, for example, a polymer insulating layer formed from a polymer material such as liquid crystal polymer and polyimide. The second insulating layer 7 is bonded to the respective surfaces of the first insulating layer 5 and the first wiring layer 6, for example, with a resin adhesive (not shown). The second wiring layer 8 is electrically connected to the semiconductor element 1 via the second through-hole TH2 and the third through-hole TH3. The second wiring layer 8 is manufactured using the same method as the first wiring layer 6. Therefore, the second wiring layer 8 has a wiring pattern formed by etching. In the present embodiment, the first wiring layer 6 is configured, for example, as a P-terminal, and the second wiring layer 8 is configured as an N-terminal. The second wiring layer 8 has a second layer area 81, a second connection area 82, and a second terminal area 83 (see Fig. 2). The second layer area 81 covers the second insulating layer 7. The second layer area 81 has the form of a flat plate. The second layer area 81 is superimposed on the first layer area 61 in parallel. That is, the first layer area 61 and the second layer area 81 are configured as parallel flat plates. The second layer area 81 is electrically connected to the semiconductor element 1 via the second connection area 82. The second connection area 82 is located within the second through-hole TH2 and the third through-hole TH3. The configuration of the second terminal area 83 will be described later. The second layer region 81 of the second wiring layer 8 has a region that lies above the first layer region 61 of the first wiring layer 6, with a second insulating layer 7 in between. The second wiring layer 8 is configured such that current flows in a direction opposite to the current flowing through the first layer region 61 through the region of the second layer region 81 that lies above the first layer region 61, with the second insulating layer 7 in between. The sealing area 9 seals the semiconductor element 1 and the conductive plate 2 between the first surface 41 and the first insulating layer 5. The sealing area 9 seals the first surface 41 and the side surface 43 of the heat spreader 4. One surface of the semiconductor element 1, one surface of the conductive plate 2, and the second surface 42 of the heat spreader 4 are exposed by the sealing area 9. The material of the sealing area 9 is, for example, epoxy resin. The sealing area 9 is manufactured, for example, by injection molding using a mold. The organic layer OL lies above the second wiring layer 8. The material of the organic layer OL is, for example, a coating agent. The organic layer OL is formed, for example, by applying a coating agent to a surface of the second wiring layer 8. The surface of the second wiring layer 8 is protected by the organic layer OL. As shown in Fig. 2, the first wiring layer 6 and the second wiring layer 8 are partially exposed by the organic layer OL. In Fig. 2, the outer shapes of the areas of the semiconductor element 1, the conductive plate 2, and the heat spreader 4, onto which other elements are placed, are shown by dashed lines. The outer shapes of the areas of the first insulating layer 5 and the first wiring layer 6, on which other elements are placed, are shown by dash-dotted lines. The outer shapes of the areas of the second insulating layer 7 and the second wiring layer 8, on which other elements are located, are shown by dashed and dotted lines. The first wiring layer 6 and the second wiring layer 8 are exposed at the outer edge of the organic layer OL. The second connection area 83 of the second wiring layer 8 is exposed by the organic layer OL. The second connection area 83 is therefore designed as a connection for the external connection. Although not shown in the drawings, the semiconductor package 100 may also include a third insulating layer and a third wiring layer. The third insulating layer covers the second insulating layer 7 and the second wiring layer 8. The third wiring layer is electrically connected to the second wiring layer 8. The third wiring layer has a third layer region. This third layer region covers the second wiring layer 8. The third layer region has a region that lies above the second layer region 81 of the second wiring layer 8, with the third insulating layer interposed. The organic layer OL may cover the third wiring layer. With reference to Fig. 3, Fig. 4 to Fig. 5, the semiconductor housing 100 according to the first embodiment will now be described in detail. As shown in Fig. 3, the semiconductor element 1 has a plurality of first semiconductor regions 1a and a plurality of second semiconductor regions 1b. For clarity, the sealing region 9 is not shown in Fig. 3. The conductive plate 2 has a plurality of first conductive areas 2a, a second conductive area 2b, and a plurality of third conductive areas 2c. The second conductive area 2b is located between the first semiconductor areas 1a and the second semiconductor areas 1b. A plurality of third conductive areas 2c are located on a side opposite the first semiconductor areas 1a with respect to the second conductive area 2b. The heat spreader 4 has a first heat spreader region 4a and a second heat spreader region 4b. The first heat spreader region 4a is arranged at a distance from the second heat spreader region 4b. A plurality of first semiconductor regions 1a, a plurality of first conductive regions 2a, and second conductive regions 2b are connected to the first heat spreader region 4a. A plurality of second semiconductor regions 1b and a plurality of third conductive regions 2c are connected to the second heat spreader region 4b. As shown in Fig. 4, the first wiring layer 6 has a plurality of first wiring regions 6a, a second wiring region 6b, a plurality of third wiring regions 6c, a plurality of fourth wiring regions 6d, and a plurality of fifth wiring regions 6e. In Fig. 4, the outer shapes of the regions of the semiconductor element 1, the conductive plate 2, and the heat spreader 4, onto which other parts are placed, are shown by dashed lines. Each of a plurality of first wiring regions 6a is connected to the corresponding one of a plurality of first semiconductor regions 1a. The second wiring region 6b is connected to the second conductive region 2b and to each of a plurality of second semiconductor regions 1b. Each of a plurality of third wiring regions 6c is connected to the corresponding one of a plurality of first conductive regions 2a. Each of a plurality of fourth wiring regions 6d is connected to the corresponding one of a plurality of second semiconductor regions 1b. Each of a plurality of fifth wiring regions 6e is connected to the corresponding one of a plurality of third conductive regions 2c. The first wiring layer 6 has an area equal to or greater than that of the semiconductor element 1. In particular, the second wiring region 6b has an area equal to or greater than that of the semiconductor element 1. The first layer region 61 has an area equal to or greater than that of the semiconductor element 1. As shown in Fig. 5, each of a plurality of first wiring regions 6a, a plurality of third wiring regions 6c, a plurality of fourth wiring regions 6d, and a plurality of fifth wiring regions 6e is partially exposed by the second insulating layer 7. In Fig. 5, the outer shapes of the regions of the first insulating layer 5 and the first wiring layer 6, on which other elements are superimposed, are shown by dashed-dotted lines. Each of a plurality of first wiring regions 6a, a plurality of second wiring regions 6b, a plurality of fourth wiring regions 6d, and a plurality of fifth wiring regions 6e is connectable to an external terminal. Each of the plurality of first wiring regions 6a, the plurality of third wiring regions 6c, the plurality of fourth wiring regions 6d, and the plurality of fifth wiring regions 6e contains a first connection region 63. The second wiring region 6b is covered with a second insulating layer 7. The second wiring layer 8 overlaps the second wiring region 6b. The second wiring layer 8 has an area equal to or greater than that of the semiconductor element 1. The current flowing through the semiconductor housing 100 according to the first embodiment will now be described. The semiconductor package 100 according to the present embodiment performs a switching operation with high current and high voltage. As shown in Fig. 1, when the semiconductor element 1 changes from the on-state to the off-state during the switching operation, a surge voltage ΔV is applied to the semiconductor element 1. The surge voltage ΔV is calculated based on the rate of change di / dt of the current when the semiconductor element 1 changes from the on-state to the off-state, and the inductance L of the wiring contained in the semiconductor device 200. In particular, the surge voltage ΔV is expressed by the following equation. If the inductance L and the rate of change of the current di / dt are large, a surge voltage ΔV can occur that exceeds the withstand voltage of semiconductor element 1. This can lead to damage of semiconductor element 1. It is therefore necessary to reduce the inductance. The operational effects of the present embodiment will now be described. In the semiconductor package 100 according to the first embodiment, as shown in Fig. 1, the second layer region 81 of the second wiring layer 8 has a region that lies above the first layer region 61 of the first wiring layer 6, with the second insulating layer 7 lying between them. In this configuration, the direction of the current flowing through the first layer region 61 of the first wiring layer 6 can be opposite to the direction of the current flowing through the region of the second layer region 81 that lies above the first layer region 61 of the first wiring layer 6, with the second insulating layer 7 lying between them.Thus, the change in current over time through the first layer area 61 of the first wiring layer 6 and the change in current over time through the area of ​​the second layer area 81 of the second wiring layer 8, which lies above the first layer area 61 with the intervening second insulating layer 7, have opposite signs. The magnetic fluxes caused by the rate of change di / dt of the current cancel each other out. This allows the wiring inductance due to a commutation loop flowing through the first layer region 61 and the second layer region 81 to be reduced. In the present embodiment, the commutation loop is the current generated when the semiconductor element 1 performs a switching operation. Accordingly, the inductance of the semiconductor package 100 can be reduced. Since the inductance of the semiconductor package 100 can be reduced, the occurrence of a surge voltage exceeding the withstand voltage of the semiconductor element 1 can be suppressed. Accordingly, damage to the semiconductor element 1 can be prevented. As shown in Fig. 1, the first layer region 61 of the first wiring layer 6 covers the first insulating layer 5. In this configuration, the protrusion of the first wiring layer 6 along the direction of the first insulating layer 5 in the plane can be suppressed. Accordingly, the size of the semiconductor package 100 can be reduced. The operational effects of the semiconductor package 100 according to the present embodiment are described in detail in comparison with a semiconductor package 101 according to a first comparative example shown in Figs. 6 and 7. Fig. 6 is a cross-sectional view along line VI-VI in Fig. 7. As shown in Figs. 6 and 7, in the semiconductor package 101 according to the first comparative example, the semiconductor element 1 is connected to an insulating substrate 47 by solder. A conductor frame LF is used as a connection point for the external wiring. The conductor frame LF and the semiconductor element 1 are connected, for example, by a bonding wire 69. The bonding wire 69 is made, for example, of copper (Cu) or aluminum (Al). The conductor frame LF is typically manufactured by stamping a metal plate made of copper (Cu), iron (Fe), or a similar material. Therefore, an inner conductor IL, which serves as a connection area to the bonding wire 69 within the conductor frame LF, is arranged on the same plane. The inner conductor IL extends beyond the outer circumference of the insulating substrate 47. Accordingly, the conductor frame LF increases the dimensions of the semiconductor package 100 along the plane of the insulating substrate 47. In comparison, according to the present embodiment, since the first layer area 61 of the first wiring layer 6 covers the first insulating layer 5, the size of the semiconductor package 100 can be reduced along the direction of the first insulating layer 5 in the plane. As shown in Figs. 4 and 5, the first wiring layer 6 and the second wiring layer 8 each have an area equal to or larger than that of the semiconductor element 1. In this configuration, the allowable current (capacitance) of the first wiring layer 6 and the second wiring layer 8 is large. The allowable current of the first wiring layer 6 and the second wiring layer 8 is greater than, for example, if the first wiring layer 6 and the second wiring layer 8 were thin conductors. Accordingly, a large current can be applied to the semiconductor element 1 through the first wiring layer 6 and the second wiring layer 8. As shown in Fig. 1, the organic layer OL lies above the second wiring layer 8. This configuration can suppress the occurrence of discharges due to foreign substances adhering to the second wiring layer 8. Furthermore, if external wiring is connected to the first wiring layer 6 by solder, the flow of the solder on the second wiring layer 8 can be suppressed. In other words, the organic layer OL can be used as a solder masking agent. Moreover, the semiconductor package 100 can be insulated, and its size reduced, if the first wiring layer 6, the second wiring layer 8, and the semiconductor element 1 are arranged inside a package (not shown) and the interior is sealed with silicone gel or a similar material. As shown in Fig. 1, the first wiring area 6a and the second wiring area 6b are connected by the semiconductor element 1, the conductive plate 2, and the heat spreader 4. In this configuration, even if the semiconductor element 1 is a vertical semiconductor element, current can be supplied to the semiconductor element 1 through the first wiring area 6a and the second wiring area 6b. As shown in Fig. 1, the sealing area 9 seals the semiconductor element 1 and the conductive plate 2 between the first surface 41 and the first insulating layer 5. With this configuration, the side faces of the semiconductor element 1 and the conductive plate 2 can be insulated. As shown in Fig. 1, the first insulating layer 5 and the second insulating layer 7 are polymer films. With this configuration, the insulating properties of the semiconductor package 100 can be improved compared to using an insulating layer made of a glass-epoxy substrate. Furthermore, the semiconductor package 100 can be made thinner compared to an insulating layer made of a glass-epoxy substrate. With this configuration, the thickness of the semiconductor package 100 can be reduced. Although not shown in the drawings, the thickness of the semiconductor package 100 can also be reduced, for example, if the semiconductor package 100 has a third insulating layer and a third wiring layer. Accordingly, the size of the semiconductor package 100 can be reduced. In addition, the weight of the semiconductor package 100 can be reduced. Second embodiment With reference to Fig. 8, a configuration of the semiconductor package 100 according to a second embodiment is now described. The second embodiment has the same configuration and the same operating effects as the first embodiment, unless otherwise specified. Therefore, the same configuration as the preceding first embodiment is designated by the same reference numerals, and a description thereof is not repeated. As shown in Fig. 8, the organic layer OL in the semiconductor package 100 according to the present embodiment has an organic-layer-side through-hole OOP. The organic-layer-side through-hole OOP penetrates the organic layer OL. The second termination area 83 of the second wiring layer 8 is located within the organic-layer-side through-hole OOP. The second termination area 83 is exposed through the organic-layer-side through-hole. The semiconductor housing 100 according to the present embodiment differs from the semiconductor housing 100 according to the first embodiment in that the location where the first wiring layer 6 and the second wiring layer 8 are exposed is not on the outer circumference of the second insulating layer 7. The operational effects of the present embodiment will now be described. In the semiconductor package 100 according to the second embodiment, as shown in Fig. 8, the second connection area 83 is exposed through the organic layer-side through-hole OOP. In this configuration, an external connection can be arranged on the front surface of the organic layer OL. Accordingly, the degree of freedom in the design of the semiconductor package 100 is improved. Third embodiment With reference to Fig. 9, a configuration of the semiconductor package 100 according to a third embodiment is now described. The third embodiment has the same configuration and operating effects as the first embodiment, unless otherwise specified. Therefore, the same configuration as in the preceding first embodiment is designated by the same reference numerals, and a description thereof is not repeated. As shown in Fig. 9, in the semiconductor housing 100 according to the third embodiment, the first insulating layer 5 has a first opening OP1. The first opening OP1 penetrates the first insulating layer 5. The first opening OP1 is spaced apart from the semiconductor element 1 and the conductive plate 2. The sealing area 9 fills the first opening OP1. Thus, the sealing area 9 is fitted into the first insulating layer 5. Although not shown in the drawing, the first opening OP1 penetrates the resin adhesive layer if a resin adhesive layer is arranged between the first insulating layer 5, the semiconductor element 1, and the conductive plate 2. The second insulating layer 7 has a second opening OP2. The second opening OP2 penetrates the second insulating layer 7. The second opening OP2 is connected to the first opening OP1. The sealing area 9 fills the first opening OP1 and the second opening OP2. Thus, the sealing area 9 is fitted into the first insulating layer 5 and the second insulating layer 7. Although not shown in the drawing, the second opening OP2 penetrates the resin adhesive layer if a resin adhesive layer is arranged between the second insulating layer 7, the first insulating layer 5, and the second wiring layer 8. The operational effects of the present embodiment will now be described. In the semiconductor package 100 according to the third embodiment, as shown in Fig. 9, the sealing area 9 fills the first opening OP1. In this configuration, the first insulating layer 5 and the sealing area 9 can be firmly connected to each other. Accordingly, a separation between the first insulating layer 5 and the sealing area 9 can be suppressed. As shown in Fig. 9, the sealing area 9 fills the first opening OP1 and the second opening OP2. In this configuration, the second insulating layer 7 and the sealing area 9 can be firmly connected to each other. Accordingly, separation between the second insulating layer 7 and the sealing area 9 can be suppressed. Fourth embodiment Figure 10 now describes a configuration of the semiconductor package 100 according to a fourth embodiment. The fourth embodiment has the same configuration and the same operating effects as the first embodiment, unless otherwise specified. Therefore, the same configuration as in the preceding first embodiment is designated by the same reference numerals, and a description thereof is not repeated. As shown in Fig. 10, the semiconductor package 100 according to the fourth embodiment further comprises a control board SB and a control component SP. The control board SB is electrically connected to the first wiring layer 6. The control component SP comprises a first control element SP1 and a second control element SP2. In Fig. 10, the control component SP comprises two first control elements SP1 and a second control element SP2. The first control elements SP1 are mounted on the control board SB. The second control element SP2 is attached to the organic layer OL. The second control element SP2 is electrically connected to the second wiring layer 8. The second control element SP2 penetrates the organic layer OL and is connected to the second wiring layer 8. The control board SB has a wiring area SB1, a substrate area SB2, and a connection area SB3. The first control element SP1 is electrically connected to wiring area SB1. Wiring area SB1 is electrically connected to the first wiring layer 6 via connection area SB3. The operational effects of the present embodiment will now be described. In the semiconductor package 100 according to the fourth embodiment, as shown in Fig. 10, the second control element SP2 of the control component SP is mounted on the organic layer OL. The second control element SP2 is electrically connected to the second wiring layer 8. In this configuration, part of the second wiring layer 8 can be used as part of a control circuit. This allows the area of ​​the control board SB to be reduced. Accordingly, the size of the semiconductor device 200 can be reduced. The operational effects of the semiconductor package 100 according to the present embodiment are described in detail in comparison with a semiconductor package 102 according to a second comparative example in Fig. 11. As shown in Fig. 11, in the semiconductor package 102 according to the second comparative example, the control component SP is mounted on a surface of the control board SB. Three first control elements SP1 of the control element are mounted on the control board SB. Thus, the control board SB has an area in which three first control elements SP1 can be mounted. In comparison, the control board SB in the semiconductor package 100 according to the present embodiment only needs to have one area in which two first control elements SP1 can be mounted, since the second control element SP2 is mounted on the organic layer OL. Accordingly, the area of ​​the control board SB can be reduced. Fifth embodiment With reference to Fig. 12, a configuration of the semiconductor package 100 according to a fifth embodiment is now described. The fifth embodiment has the same configuration and the same operating effects as the first embodiment, unless otherwise specified. Therefore, the same configuration as in the preceding first embodiment is indicated by the same reference numerals, and a description thereof is not repeated. As shown in Fig. 12, in the semiconductor housing 100 according to the fifth embodiment, the first wiring layer 6 extends to the outer surface of the sealing area 9. In particular, the first connection area 63 of the first wiring layer 6 extends to the outer surface of the sealing area 9. The first insulating layer 5 extends to the outer surface of the sealing area 9. The semiconductor housing 100 also includes a connecting element CC. The connecting element CC is attached to the first insulating layer 5 and the first connection area 63. The connecting element CC penetrates the first insulating layer 5 and the first connection area 63. The connecting element CC is, for example, a screw and a nut. The operational effects of the present embodiment will now be described. In the semiconductor package 100 according to the fifth embodiment, as shown in Fig. 12, the first wiring layer 6 extends to the outer surface of the sealing area 9. In this configuration, the connecting element CC can be attached to the first wiring layer 6. Thus, the first wiring layer 6 can be connected to external wiring via the connecting element CC. Accordingly, the semiconductor package 100 can be more easily connected to the external wiring than if the external wiring were directly soldered to the first wiring layer 6 or the second wiring layer 8.Furthermore, the semiconductor package 100 can be more easily connected to external wiring than if the external wiring is connected to a socket soldered to the first wiring layer 6 or the second wiring layer 8. Sixth embodiment With reference to Fig. 13, a configuration of the semiconductor package 100 according to a sixth embodiment is now described. The sixth embodiment has the same configuration and the same operating effects as the first embodiment, unless otherwise specified. Therefore, the same configuration as the preceding first embodiment is designated by the same reference numerals, and a description thereof is not repeated. As shown in Fig. 13, the heat spreader 4 in the semiconductor housing 100 according to the sixth embodiment comprises a first metal plate 46, an insulating substrate 47, and a second metal plate 48. The semiconductor element 1 and the conductive plate 2 are electrically connected to the first metal plate 46. The insulating substrate 47 is embedded between the second metal plate 48 and the first metal plate 46. The insulating substrate 47 is attached to both the first metal plate 46 and the second metal plate 48. The material of the first metal plate 46 and the second metal plate 48 is, for example, a metal with high conductivity, such as copper (Cu) and aluminum (Al). The insulating substrate 47 is, for example, a ceramic plate. The insulating substrate 47 has a higher thermal conductivity than a resin insulating layer RL described later (see Fig. 14). The operational effects of the present embodiment will now be described. In the semiconductor housing 100 according to the sixth embodiment, as shown in Fig. 13, the insulating plate is arranged between the second metal plate 48 and the first metal plate 46. In this configuration, the first metal plate 46 and the second metal plate 48 are insulated by the insulating substrate 47. Thus, when a heat sink HS (see Fig. 14), described later, is connected to the semiconductor housing 100, the semiconductor element 1 and the heat sink HS (see Fig. 14) can be insulated by the insulating substrate 47. Therefore, it is not necessary to arrange an insulating layer between the heat spreader 4 and the heat sink HS (see Fig. 14). Furthermore, the second metal plate 48 of the heat spreader 4 and the heat sink HS (see Fig. 14) can be joined, for example, by solder with high thermal conductivity.Accordingly, the heat dissipation of the semiconductor package is improved by 100%. Seventh embodiment With reference to Fig. 14, a configuration of the semiconductor package 100 and a semiconductor device 200 according to a seventh embodiment is now described. The seventh embodiment has the same configuration and the same operating effects as the fourth embodiment, unless otherwise specified. Therefore, the same configuration as the preceding fourth embodiment is designated by the same reference numerals, and a description thereof is not repeated. As shown in Fig. 14, the semiconductor device 200 according to the seventh embodiment comprises the semiconductor housing 100 described in the first to sixth embodiments, a heat sink HS, and a resin insulating layer RL. The resin insulating layer RL is arranged between the heat sink HS and the heat spreader 4. Thus, the semiconductor housing is connected to the heat sink HS by the resin insulating layer RL. In Fig. 14, the semiconductor device 200 includes the semiconductor housing 100 described in the fourth embodiment. The semiconductor housing 100 is attached to the heat sink HS by the resin insulating layer RL. The semiconductor housing 100 is insulated from the heat sink HS by the resin insulating layer RL. The heat sink HS has a base HS1 and a plurality of fins HS2. The base HS1 is connected to the heat spreader 4. The base HS1 is sandwiched between a plurality of fins HS2 and the heat spreader 4. With reference to Fig. 14, Fig. 15 to Fig. 16, a method for manufacturing a semiconductor device 200 according to the seventh embodiment is now described. As shown in Fig. 15, the first insulating layer 5 is arranged to cover the semiconductor element 1 and the conductive plate 2, and then the first wiring layer 6, the second insulating layer 7, the second wiring layer 8, and the organic layer OL are layered on top of each other. Subsequently, as shown in Fig. 16, the semiconductor element 1 and the conductive plate 2 are connected to the heat spreader 4 by the bonding material 3. Then, as shown in Fig. 14, the semiconductor element 1, the conductive plate 2, and the heat spreader 4 are sealed by the sealing area 9, and finally, the heat spreader 4 is attached to the heat sink HS by the resin insulating layer RL. The operational effects of the present embodiment will now be described. In the semiconductor device 200 according to the seventh embodiment, as shown in Fig. 14, the resin insulating layer RL is sandwiched between the heat sink HS and the heat spreader 4. In this configuration, the heat generated by the semiconductor element 1 of the semiconductor housing 100 is transferred to the heat sink HS via the heat spreader 4 and the resin insulating layer RL. Thus, the heat generated by the semiconductor element 1 is dissipated from the heat sink HS. Accordingly, the heat dissipation of the semiconductor device 200 is improved. Eighth embodiment With reference to Fig. 17, a configuration of the semiconductor device 200 according to an eighth embodiment is now described. The eighth embodiment has the same configuration and the same operating effects as the sixth embodiment, unless otherwise stated. Therefore, the same configuration as the preceding sixth embodiment is designated by the same reference numerals, and a description thereof is not repeated. As shown in Fig. 17, the semiconductor device 200 according to the eighth embodiment comprises the semiconductor housing 100 described in the sixth embodiment, a heat sink HS, and a conductive metal bonding material ML. The conductive metal bonding material ML is embedded between the heat sink HS and the second metal plate 48 of the heat spreader 4. Thus, the semiconductor housing 100 is connected to the heat sink HS by the conductive metal bonding material ML. The conductive metal bonding material ML comprises, for example, solder, silver (Ag), and copper (Cu). The conductive metal bonding material ML is conductive. The conductive metal bonding material ML has a higher electrical conductivity than the resin insulating layer RL (see Fig. 14). The conductive metal bonding material ML has a higher thermal conductivity than the resin insulating layer RL (see Fig. 14). The operational effects of the present embodiment will now be described. In the semiconductor device 200 according to the eighth embodiment, as shown in Fig. 17, the conductive metal bonding material ML is embedded between the heat sink HS and the second metal plate 48 of the heat spreader 4. In this configuration, the heat generated by the semiconductor element 1 of the semiconductor housing 100 is transferred to the heat sink HS via the heat spreader 4 and the conductive metal bonding material ML. Thus, the heat generated by the semiconductor element 1 is dissipated from the heat sink HS. Accordingly, the heat dissipation of the semiconductor device 200 is improved. The conductive metal bonding material ML has a higher thermal conductivity than the resin insulating layer RL (see Fig. 14).With this configuration, the heat dissipation of the semiconductor device 200 is improved compared to the case where the heat spreader 4 and the heat sink HS are connected by the resin insulating layer RL. Ninth embodiment With reference to Fig. 18, a configuration of the semiconductor device 200 according to a ninth embodiment is now described. The ninth embodiment has the same configuration and the same operating effects as the fourth embodiment, unless otherwise stated. Therefore, the same configuration as the preceding fourth embodiment is designated with the same reference numerals, and a description of it is not repeated. As shown in Figures 18 and 19, the semiconductor device 200 according to the ninth embodiment comprises the semiconductor housing 100 and the heat sink HS described in the first to sixth embodiments. The heat sink HS is connected to the heat spreader 4 on a side opposite the semiconductor element 1 with respect to the heat spreader 4. The heat spreader 4 and the heat sink HS are sealed by the sealing area 9. Thus, the heat spreader 4 and the heat sink HS are sealed together. The sealing area 9 seals the first surface 41 and the side surface 43 of the heat spreader 4. In the present embodiment, the heat spreader 4 and the heat sink HS are connected to each other before being sealed by the sealing area 9. The heat spreader 4 and the heat sink HS are sealed by injection molding using a mold, with the resin insulating layer RL sandwiched between the heat spreader 4 and the heat sink HS. As shown in Fig. 19, the heat spreader 4 and the heat sink HS can be pre-connected by the resin insulating layer RL. Alternatively, the heat spreader 4 and the heat sink HS can also be connected and integrated by an insulating substrate made of ceramic or similar material. The operational effects of the present embodiment will now be described. In the semiconductor device 200 according to the ninth embodiment, as shown in Fig. 18, the heat spreader 4 and the heat sink HS are sealed by the sealing area 9. In this configuration, the heat spreader 4 and the heat sink HS can be sealed simultaneously by the sealing area 9. As shown in Figs. 14, 15 to 16, it is therefore not necessary to connect the heat sink HS to the heat spreader 4 after the heat spreader 4 has been sealed by the sealing area 9. The manufacturing steps of the semiconductor device 200 can therefore be simplified. Tenth embodiment In the present embodiment, the semiconductor device according to the preceding seventh to ninth embodiments is used for a power converter device. Although the present invention is not limited to a specific power converter device, a case in which the present invention is applied to a three-phase inverter is described as the tenth embodiment. Fig. 20 is a block diagram showing a configuration of a power converter system in which the power converter device is used according to the present embodiment. The power converter system shown in Fig. 20 comprises a power source 110, a power converter device 300, and a load 400. The power source 110 is a DC power source and supplies direct current to the power converter device 300. The power source 110 can be configured with a plurality of power sources, such as a DC system, solar cells, a storage battery, and can be configured with a rectifier circuit or an AC / DC converter connected to an AC system. The power source 110 can be configured with a DC / DC converter that converts the DC power supplied by a DC system into a predetermined power output. The power converter device 300 is a three-phase inverter connected between the power source 110 and the load 400. It converts direct current (DC) power supplied by the power source 110 into alternating current (AC) power and supplies the AC power to the load 400. As shown in Fig. 20, the power converter device 300 comprises a main converter circuit 201 for converting DC power into AC power and outputting the AC power, and a control circuit 203 for outputting a control signal to the main converter circuit 201 for controlling the main converter circuit 201. The Last 400 is a three-phase motor driven by the alternating current supplied by the power converter 300. The Last 400 is not limited to specific applications and is a motor that can be attached to a variety of electrical devices, such as hybrid cars, electric cars, rail vehicles, elevators, or air conditioners. The details of the power converter device 300 are described below. The main converter circuit 201 contains switching elements and freewheeling diodes (not shown), and the switching elements perform switching operations to convert direct current power supplied by the power source 110 into alternating current power and to supply the alternating current power to the load 400. The main converter circuit 201 can have a plurality of specific circuit configurations. The main converter circuit 201 according to the present embodiment can be a two-stage, three-phase full-bridge circuit and comprise six switching elements and six freewheeling diodes connected antiparallel to the respective switching elements. At least one of the switching elements and one of the freewheeling diodes of the main converter circuit 201 is a switching element or a freewheeling diode of the semiconductor device 200 corresponding to the semiconductor device according to one of the preceding seventh to ninth embodiments. Six switching elements are connected in series in pairs to form upper and lower arms, and the upper and lower arms configure each phase (U-phase, V-phase, W-phase) of the full-bridge circuit. The output terminals of the upper and lower arms, i.e., three output terminals of the main converter circuit 201, are connected to the load 400. Although the main converter circuit 201 includes a control circuit (not shown) for controlling each switching element, the control circuit may be contained within the semiconductor device 200 or a control circuit may be provided separately from the semiconductor device 200. The control circuit generates a control signal for controlling a switching element of the main converter circuit 201 and supplies the control signal to the control electrode of the switching element of the main converter circuit 201. In particular, a control signal for switching on a switching element and a control signal for switching off a switching element are output to the control electrode of each switching element, in accordance with a control signal from the control circuit 203 described later. When the switching element remains switched on, the control signal is a voltage signal (ON signal) that is equal to or higher than a threshold voltage of the switching element, and when a switching element remains switched off, the control signal is a voltage signal (OFF signal) that is equal to or lower than a threshold voltage of the switching element. The control circuit 203 controls the switching elements of the main converter circuit 201 so that a desired power is delivered to the load 400. Specifically, the time (ON time) for which each switching element of the main converter circuit 201 is to be switched on is calculated based on the power to be delivered to the load 400. For example, the main converter circuit 201 can be controlled by a PWM controller that modulates the switch-on time of the switching elements as a function of a voltage to be output. A control command (control signal) is then issued to the control circuit of the main converter circuit 201, so that at any given time an ON signal is issued to a switching element to be switched on and an OFF signal is issued to a switching element to be switched off. The control circuit outputs an ON signal or an OFF signal as a control signal to the control electrode of each switching element in accordance with the control signal. With the power converter device according to the present embodiment, a reduction in inductance can be achieved, since the semiconductor device according to the seventh to ninth embodiments is used as semiconductor device 200, which forms the main converter circuit 201. In the present embodiment, the present invention is applied to a two-stage, three-phase inverter. However, the present invention is not limited thereto and can be applied to a plurality of power conversion devices. In the present embodiment, the present invention is applied to a two-stage power conversion device, but it can also be applied to a three-stage or multi-stage power conversion device or to a single-phase inverter when a single-phase load is supplied with current. The present invention is applicable to a DC / DC converter or an AC / DC converter when current is supplied to a DC load or the like. The energy converter device to which the present invention is applied is not limited to the case in which the load is a motor and can, for example, be used as an energy source device for electric discharge machines, laser processing machines or induction heating stoves or wireless charging systems, or it can be used as an energy conditioner for solar power generation systems and energy storage systems. Reference symbol list 1 Semiconductor element 2 Conductive plate 3 Bonding material 4 Heat spreader 5 First insulating layer 6 First wiring layer 7 Second insulating layer 8 Second wiring layer 9 Sealing area 46 First metal plate 47 Insulating substrate 48 Second metal plate 61 First layer area 62 Second layer area 100 Semiconductor package 110 Power source 200 Semiconductor device 201 Main converter circuit 203 Control circuit 300 Power converter device 400 Load HS Heat sink ML Conductive metal bonding material OL Organic layer OP1 First opening OP2 Second opening RL Insulating resin layer TH1 First through hole TH1a First through area TH1b Second through area TH2 Second through hole TH3 Third through hole SB Control board SP Control component SP1 First control element SP2 Second control element.

Claims

Semiconductor package (100) comprising: - a semiconductor element (1); - a first insulating layer (5) covering the semiconductor element (1) and having a first through-hole (TH1) and a second through-hole (TH2); - a first wiring layer (6) comprising a first layer region (61) covering the first insulating layer (5) and electrically connected to the semiconductor element (1) through the first through-hole (TH1); - a second insulating layer (7) covering the first insulating layer (5) and the first wiring layer (6) and having a third through-hole (TH3) connected to the second through-hole (TH2); and - a second wiring layer (8) comprising a second layer region (81) covering the second insulating layer (7) and electrically connected to the semiconductor element (1) through the second through-hole (TH2) and the third through-hole (TH3).wherein the second layer region (81) of the second wiring layer (8) has a region that lies above the first layer region (61) of the first wiring layer (6), wherein the second insulating layer (7) is arranged between them, wherein the first wiring layer (6) has a first connection region (63), the second wiring layer (8) has a second connection region (83), the first connection region (63) and the second connection region (83) each have an exposed region on one side that is opposite to the semiconductor element (1) with respect to the first insulating layer (5), and a direction of current flowing through the first layer region (61) of the first wiring layer (6) to a direction of current flowing opposite to that flowing through the region of the second layer region (81) that is superimposed on the first layer region (61) of the first wiring layer with the second insulating layer (7) arranged between them. Semiconductor package (100) according to claim 1, wherein the first wiring layer (6) and the second wiring layer (8) each have an area equal to or larger than the area of ​​the semiconductor element (1). Semiconductor package (100) according to claim 1 or 2, further comprising an organic layer (OL) superimposed on the second wiring layer (8), wherein the first wiring layer (6) and the second wiring layer (8) are partially exposed by the organic layer (OL). Semiconductor package (100) comprising: - a semiconductor element (1); - a first insulating layer (5) covering the semiconductor element (1) and having a first through-hole (TH1) and a second through-hole (TH2); - a first wiring layer (6) comprising a first layer area (61) covering the first insulating layer (5) and electrically connected to the semiconductor element (1) through the first through-hole (TH1); - a second insulating layer (7) covering the first insulating layer (5) and the first wiring layer (6) and having a third through-hole (TH3) connected to the second through-hole (TH2);and a second wiring layer (8) having a second layer area (81) covering the second insulating layer (7) and electrically connected to the semiconductor element (1) through the second through-hole (TH2) and the third through-hole (TH3), wherein the second layer area (81) of the second wiring layer (8) has an area that lies above the first layer area (61) of the first wiring layer (6), with the second insulating layer (7) positioned between them; an organic layer (OL) superimposed on the second wiring layer (8), wherein the first wiring layer (6) and the second wiring layer (8) are partially exposed by the organic layer (OL); a control board (SB) electrically connected to the first wiring layer (6);and a control component (SP), wherein the control component (SP) comprises a first control element (SP1) and a second control element (SP2), the first control element (SP1) being mounted on the control board (SB), the second control element (SP2) being mounted on the organic layer (OL) and electrically connected to the second wiring layer (8), and a direction of current flowing through the first layer region (61) of the first wiring layer (6) to a direction of current flowing opposite through the region of the second layer region (81) which superimposes the first layer region (61) of the first wiring layer with the second insulating layer (7) arranged between them. Semiconductor package (100) according to one of claims 1 to 4, which further comprises: - a conductive plate (2);and a heat spreader (4) having a first surface (41), wherein the semiconductor element (1) and the conductive plate (2) are connected to the first surface (41), the first wiring layer (6) having a first wiring area (6a) and a second wiring area (6b), the first through-hole (TH1) having a first through-hole (TH1a) overlapping the semiconductor element (1) and a second through-hole (TH1b) overlapping the conductive plate (2), wherein the first wiring area (6a) is electrically connected to the semiconductor element (1) through the first through-hole (TH1a), the second wiring area (6b) is electrically connected to the conductive plate (2) through the second through-hole (TH1b), and the first wiring area (6a) and the second wiring area (6b) are connected through the semiconductor element (1), the conductive plate (2), and the heat spreader (4). are.; Semiconductor housing (100) according to claim 5, wherein the heat spreader (4) comprises a first metal plate (46) with which the semiconductor element (1) and the conductive plate (2) are electrically connected, an insulating substrate (47) and a second metal plate (48), and the insulating substrate (47) is arranged sandwich-like between the second metal plate (48) and the first metal plate (46). Semiconductor housing (100) according to claim 5 or 6, which further comprises a sealing area (9), wherein the sealing area (9) seals the semiconductor element (1) and the conductive plate (2) between the first surface (41) and the first insulating layer (5). Semiconductor housing (100) according to claim 7, wherein the first insulating layer (5) has a first opening (OP1) that penetrates the first insulating layer (5), the first opening (OP1) is spaced apart from the semiconductor element (1) and the conductive plate (2), and the sealing area (9) fills the first opening (OP1). Semiconductor housing (100) according to claim 8, wherein the second insulating layer (7) has a second opening (OP2) which penetrates the second insulating layer (7) and is connected to the first opening (OP1), and the sealing area (9) fills the first opening (OP1) and the second opening (OP2). Semiconductor housing (100) according to one of claims 7 to 9, wherein the first wiring layer (6) extends beyond an outer circumference of the sealing area (9). Semiconductor device (200) comprising: - the semiconductor housing (100) according to any one of claims 5 to 10; - a heat sink (HS); and - a resin insulating layer (RL), wherein the resin insulating layer (RL) is arranged between the heat sink (HS) and the heat spreader (4). Semiconductor device (200) comprising: - the semiconductor housing (100) according to any one of claims 7 to 10; and - a heat sink (HS), wherein the heat sink (HS) is connected to the heat spreader (4) on a side opposite the semiconductor element (1) with respect to the heat spreader (4), and the heat spreader (4) and the heat sink (HS) are sealed by the sealing area (9). Semiconductor device (200) comprising: - the semiconductor housing (100) according to claim 6; - a heat sink (HS); and - a conductive metal bonding material (ML), wherein the conductive metal bonding material (ML) is arranged between the heat sink (HS) and the second metal plate (48) of the heat spreader (4). Power converter device (300) comprising: - a main converter circuit (201) comprising the semiconductor device (200) according to any one of claims 11 to 13, wherein the main converter circuit (201) converts the input power and outputs the converted power; and - a control circuit (203) for outputting a control signal to the main converter circuit (201) for controlling the main converter circuit (201).

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