Semiconductor module

Abstract

Semiconductor module comprising: a conductive substrate (2) with a front side (201) facing a first side in a thickness direction and a back side (202) facing away from the front side (201) in the thickness direction; a semiconductor element (10) electrically bonded to the front side (201) and having a switching function; a control terminal for controlling the semiconductor element; and a sealing resin (8) with a resin front side (81) facing the same side as the front side (201) and a resin back side (82) facing a side opposite the resin front side (81), wherein the sealing resin (8) covers the conductive substrate, the semiconductor element, and part of the control terminal; a control terminal carrier (5) provided between the front side (201) and the control terminal, which has an insulating layer (51); and a resin element bonded to the sealing resin (8).wherein the control terminal protrudes from the resin front face (81) and extends along the thickness direction, wherein the semiconductor module has at least one first power supply terminal and one second power supply terminal, wherein the conductive substrate (2) has a first conductive section (2A) and a second conductive section (2B) spaced apart from each other in a first direction perpendicular to the thickness direction, such that the first conductive section (2A) is offset to one side of the first direction and the second conductive section (2B) is offset to the other side of the first direction, wherein the at least one semiconductor element (10) has a first semiconductor element (10A) electrically bonded to the first conductive section (2A) and a second semiconductor element (10B) electrically bonded to the second conductive section (2B),wherein the at least one first power supply terminal has a first input terminal (41) offset to one side of the first direction relative to the first semiconductor element (10A) and connected to the first conductive section (2A), and a second input terminal (42) offset to one side of the first direction relative to the first semiconductor element (10A) and connected to the second semiconductor element (10B), wherein the second power supply terminal is an output terminal (44) that outputs a second power supply voltage, offset to the other side of the first direction relative to the second semiconductor element (10B) and connected to the second conductive section (2B), wherein the control terminal has a first control terminal (46A-46E) for controlling the first semiconductor element (10A) and a second control terminal (47A-47D) for controlling the second semiconductor element (10B),wherein on the first conductive section (2A) the first control terminal (46A-46E) is arranged between the first semiconductor element (10A) and the first and second input terminals (41; 42) as viewed from a second direction perpendicular to the thickness direction and the first direction, wherein on the second conductive section (2B) the second control terminal (47A-47D) is arranged between the second semiconductor element (10B) and the output terminal (44) as viewed from the second direction, wherein the control terminal carrier (5) comprises the insulating layer, a first metal layer stacked on one surface of the insulating layer on one side of the thickness direction, and a second metal layer stacked on another surface of the insulating layer on another side of the thickness direction and bonded to the conductive substrate to face the front (201),wherein the control connection is bonded to the first metal layer via a conductive bonding element, wherein the control connection has a conductive tubular holder (451) which is bonded to the first metal layer, and a metal pin (452) which is pressed into the holder (451) and extends in the thickness direction, wherein a part of the holder (451) on one side of the thickness direction is exposed by the sealing resin (8), and wherein the resin element covers a part of the holder (451) that is exposed by the sealing resin (8) and a part of the metal pin (452).

Description

TECHNICAL AREA

[0001] The present disclosure relates to a semiconductor module. background

[0002] Semiconductor modules with power switching elements such as metal-oxide-semiconductor field-effect transistors (MOSFETs) or insulated-gate bipolar transistors (IGBTs) are known. Such semiconductor modules are used in various electronic devices, e.g., in industrial equipment, household appliances, information terminals, and automotive equipment. Patent document 1 discloses a conventional semiconductor module (power module). The semiconductor module described in patent document 1 contains a semiconductor element and a support substrate (ceramic substrate). The semiconductor element is, for example, a silicon (Si) IGBT. The support substrate carries the semiconductor element. The support substrate consists of an insulating base element and conductor layers stacked on the respective surfaces of the base element. The base element can be made of ceramic, for example. Each of the conductor layers can be made of copper (Cu), for example, and the semiconductor element is connected to one of the conductor layers. State of the Art Document Patent document

[0003] Patent Document 1: JP-A-2015-220382 Summary of the invention: Problem to be solved by the invention

[0004] In recent years, the demand for energy-efficient, sophisticated, and smaller electronic devices has increased. To meet this demand, performance must be improved and the size of semiconductor modules on electronic devices reduced.

[0005] The present disclosure was conceived in view of the aforementioned circumstances, and one objective is to provide a semiconductor device with a module configuration that contributes to improving performance and reducing size. Means to solve the problem

[0006] A semiconductor module of the present disclosure comprises: a conductive substrate with a front face oriented towards one side of a thickness direction and a back face oriented away from the front face in the thickness direction; a semiconductor element electrically bonded to the front face and having a switching function; a control terminal for controlling the semiconductor element; and a sealing resin with a resin front face oriented towards the same side as the front face and a resin back face oriented towards a side opposite the resin front face, the sealing resin covering the conductive substrate, the semiconductor element, and part of the control terminal. The control terminal projects from the resin front face and extends along the thickness direction. Advantages of the invention

[0007] According to the configuration described above, it is possible to provide a semiconductor module configuration that preferably serves to improve performance and reduce size. List of characters Fig. Figure 1 is a perspective view showing a semiconductor module according to a first embodiment. Fig. 2 is a perspective view that Fig. 1 corresponds, but without a sealing resin, a resin element and a resin filling section. Fig. Figure 3 is a perspective view that Fig. 2 corresponds, but without a conducting element. Fig. Figure 4 is a top view showing the semiconductor module according to the first embodiment. Fig. 5 is a top view, which Fig. 4 corresponds, but shows the sealing resin, the resin element and the resin filling section with imaginary lines. Fig. 6 is a partially enlarged view showing part of Fig. Figure 5 shows, but without the imaginary lines of the sealing resin, the resin element and the resin filling section. Fig. 7 is a partially enlarged view showing part of Fig. 6 shows. Fig. 8 is a top view, which Fig. 5 corresponds, but shows part of the guiding element with an imaginary line. Fig. Figure 9 is a front view showing the semiconductor module according to the first embodiment. Fig. Figure 10 is a view from below showing the semiconductor module according to the first embodiment. Fig. Figure 11 is a left side view showing the semiconductor module according to the first embodiment. Fig. Figure 12 is a right side view showing the semiconductor module according to the first embodiment. Fig. 13 is a cross-sectional view along line XIII-XIII of Fig. 5. Fig. 14 is a cross-sectional view along line XIV-XIV of Fig. 5. Fig. 15 is a partially enlarged view showing part of Fig. 14 shows. Fig. 16 is a cross-sectional view along line XVI-XVI of Fig. 5. Fig. 17 is a cross-sectional view along line XVII-XVII of Fig. 5. Fig. 18 is a cross-sectional view along line XVIII-XVIII of Fig. 5. Fig. 19 is a cross-sectional view along the XIX-XIX line of Fig. 5. Fig. shows an example of the circuit arrangement of the semiconductor module according to the first embodiment. Fig. Figure 21 is a top view showing a step of a process for manufacturing the semiconductor module according to the first embodiment. Fig. Figure 22 is a schematic cross-sectional view showing one step of the process for manufacturing the semiconductor module according to the first embodiment. Fig. Figure 23 is a top view showing one step of the process for manufacturing the semiconductor module according to the first embodiment. Fig. Figure 24 is a cutaway end view illustrating a step of the manufacturing process according to the first embodiment and corresponds to the cross-sectional view of Fig. 13. Fig. Figure 25 is a partially enlarged cross-sectional view showing a step of the process for manufacturing the semiconductor module according to the first embodiment and an enlarged view of part of the cross-section in Fig. 13 corresponds to this. Fig. Figure 26 is a partially enlarged cross-sectional view showing a step of the process for manufacturing the semiconductor module according to the first embodiment and an enlarged view of part of the cross-section in Fig. 14 corresponds to this. Fig. Figure 27 is a partially enlarged cross-sectional view showing a step of the process for manufacturing the semiconductor module according to the first embodiment and an enlarged view of part of the cross-section in Fig. 14 corresponds to this. Fig. Figure 28 is a partially enlarged cross-sectional view showing a step of the process for manufacturing the semiconductor module according to the first embodiment and an enlarged view of part of the cross-section in Fig. 13 corresponds to this. Fig. Figure 29 is a partially enlarged cross-sectional view showing a step of the process for manufacturing the semiconductor module according to the first embodiment and an enlarged view of part of the cross-section in Fig. 14 corresponds to this. Fig. Figure 30 is a front view showing a semiconductor module according to a second embodiment. Fig. Figure 31 is a right side view showing the semiconductor module according to the second embodiment. Fig. Figure 32 is a cross-sectional view similar to Fig. 18 and shows the semiconductor module according to the second embodiment. Fig. Figure 33 is a front view showing a semiconductor module according to a third embodiment. Fig. Figure 34 is a right side view showing the semiconductor module according to the third embodiment. Fig. Figure 35 is a cross-sectional view similar to Fig. 18 and shows the semiconductor module according to the third embodiment. Fig. Figure 36 is a perspective view showing a semiconductor module according to a fourth embodiment. Fig. Figure 37 is a right side view showing the semiconductor module according to the fourth embodiment. Fig. 38 is a top view similar to Fig. 5 and shows a semiconductor module according to a fifth embodiment. Fig. 39 is a partially enlarged view showing part of Fig. Figure 38 shows, but without the imaginary lines of the sealing resin, the resin element and the resin filling section. Fig. 40 is a partially enlarged view showing part of Fig. shows. Fig. 41 is a top view similar to Fig. 5 and shows a semiconductor module according to a sixth embodiment. Fig. 42 is a cross-sectional view along the XLII-XLII line of Fig. 41. embodiment of the invention

[0008] Preferred embodiments of a semiconductor module according to the present disclosure are described below with reference to the drawings. Identical or similar elements are identified by the same reference numerals, and redundant descriptions are omitted.

[0009] Fig. 1 to Fig. Figure 20 shows a semiconductor module A1 according to a first embodiment. The semiconductor module A1 comprises: a plurality of semiconductor elements 10, a conductive substrate 2, a support substrate 3, a plurality of input terminals 41 to 43, a plurality of output terminals 44, a plurality of control terminals 45, a control terminal carrier 5, a conductive element 6, a first conductive bonding element 71, a second conductive bonding element 72, a plurality of wires 731 to 735, a sealing resin 8, resin elements 87 and resin-filled sections 88.

[0010] Fig. Figure 1 is a perspective view showing the semiconductor module A1. Fig. 2 is a perspective view that Fig. 1 corresponds, but without the sealing resin 8, the resin elements 87 and the resin filling sections 88. Fig. 3 is a perspective view accordingly Fig. 2, but without the conducting element 6. Fig. Figure 4 is a top view showing the semiconductor module A1. Fig. 5 is a top view, which Fig. 4 corresponds, but shows the sealing resin 8, the resin elements 87 and the resin filling sections 88 with imaginary lines. Fig. 6 is a partially enlarged view showing part of Fig. 5 shows. In Fig. The imaginary lines of the sealing resin 8, the resin filling section 87 and the resin filling sections 88 are not shown in Figure 6. Fig. 7 is a partially enlarged view showing part of Fig. 6 shows. Fig. 8 is a top view, which Fig. 5 corresponds, but shows part of the conducting element 6 (a second conducting element 62, which is described below) with an imaginary line. Fig. Figure 9 is a front view of the semiconductor module A1. Fig. Figure 10 is a bottom view of semiconductor module A1. Fig. Figure 11 is a left side view of semiconductor module A1. Fig. This is a right side view of the semiconductor module A1. Fig. 13 is a cross-sectional view along line XIII-XIII of Fig. 5. Fig. 14 is a cross-sectional view along line XIV-XIV of Fig. 5. Fig. 15 is a partially enlarged view showing part of Fig. 14 shows. Fig. 16 is a cross-sectional view along line XVI-XVI of Fig. 5. Fig. 17 is a cross-sectional view along line XVII-XVII of Fig. 5. Fig. 18 is a cross-sectional view along line XVIII-XVIII of Fig. 5. Fig. 19 is a cross-sectional view along the XIX-XIX line of Fig. 5. In Fig. 2, Fig. 3, Fig. 7, Fig. 14 and Fig. 18. Wires 731 to 735 are not shown. Fig. Figure 20 shows an example of the circuit arrangement of the semiconductor module A1. The circuit diagram of Fig. Figure 20 shows only one of a plurality of first semiconductor elements 10A (described below) and only one of a plurality of second semiconductor elements 10B (described below), and the remaining first semiconductor elements 10A and the second semiconductor elements 10B are omitted.

[0011] For the sake of simplicity, reference is made to three mutually perpendicular directions, i.e., the x, y, and z directions. The z direction corresponds, for example, to the thickness direction of the semiconductor module A1. The x direction corresponds to the horizontal direction in the top view (see Fig. 4) on the semiconductor module A1. The y-direction corresponds to the vertical direction in the top view (see Fig. 4) on the semiconductor module A1. A first side (first sense) of the x-direction is defined as the x1 direction and the other side (second sense) as the x2 direction. Similarly, a first side (first sense) of the y-direction is defined as the y1 direction and the other side (second sense) as the y2 direction. A first side (first sense) of the z-direction is defined as the z1 direction and the other side (second sense) as the z2 direction. In the following description, a "top view" is a view in the z-direction. The z-direction is an example of the "thickness direction," the x-direction is an example of a "first direction," and the y-direction is an example of a "second direction."

[0012] The semiconductor elements 10 form the functional core of the semiconductor module A1. The semiconductor elements 10 are made of a semiconductor material that, for example, mainly contains silicon carbide (SiC). The semiconductor material is not limited to SiC, but can also be silicon (Si), gallium arsenide (GaAs), or gallium nitride (GaN). Each of the semiconductor elements 10 has a switching functional unit Q1 (see Fig. ), which consists, for example, of a metal-oxide-semiconductor field-effect transistor (MOSFET). The switching functional unit Q1 is not limited to a MOSFET, but can also be another transistor, e.g., a field-effect transistor such as a metal-insulator-semiconductor FET or a bipolar transistor such as an IGBT. The semiconductor elements 10 are the same elements. The semiconductor elements 10 are, for example, n-channel MOSFETs, but can also be p-channel MOSFETs.

[0013] As in Fig. As shown in Figure 15, each of the semiconductor elements 10 has a front face 101 and a back face 102. The front face 101 and the back face 102 of each semiconductor element 10 are spaced apart from each other in the z-direction. The front face 101 points in the z2 direction, and the back face 102 points in the z1 direction.

[0014] The semiconductor elements 10 comprise a plurality of first semiconductor elements 10A and a plurality of second semiconductor elements 10B. In the present embodiment, the semiconductor module A1 comprises three first semiconductor elements 10A and three second semiconductor elements 10B. However, the number of first semiconductor elements 10A and the number of second semiconductor elements 10B are not limited and can be changed depending on the power required for the semiconductor module A1. In the Fig. In the example shown, three first semiconductor elements 10A and three second semiconductor elements 10B are provided. The number of first semiconductor elements 10A and the number of second semiconductor elements 10B can each be one, two, or at least four. The number of first semiconductor elements 10A and the number of second semiconductor elements 10B can be the same or different. The number of first semiconductor elements 10A and the number of second semiconductor elements 10B are determined depending on the current capacitance of the semiconductor module A1.

[0015] As in Fig. As shown in Figure 20, the semiconductor module A1 can be configured as a half-bridge circuit. In this case, the first semiconductor elements 10A form an upper arm of the semiconductor module A1, and the second semiconductor elements 10B form a lower arm of the semiconductor module A1. In the upper arm, the first semiconductor elements 10A are connected in parallel to each other, and in the lower arm, the second semiconductor elements 10B are connected in parallel to each other. Each of the first semiconductor elements 10A and each of the second semiconductor elements 10B are connected in series, forming a bridge layer.

[0016] As in the Fig. 8 and Fig. As shown in Figure 16, for example, the first semiconductor elements 10A are mounted on the conductive substrate 2. In the Fig. In the example shown in Figure 8, the first semiconductor elements 10A are aligned in the y-direction and spaced apart from each other. The first semiconductor elements 10A are electrically connected to the conductive substrate 2 (a first conductive section 2A described below) via the second conductive bonding element 72. When the first semiconductor elements 10A are connected to the first conductive section 2A, the back faces 102 of the elements point towards the first conductive section 2A.

[0017] As in Fig. 8 and Fig. As shown in Figure 17, the second semiconductor elements 10B are, for example, mounted on the conductive substrate 2. In the Fig. In the example shown in Figure 8, the second semiconductor elements 10B are aligned in the y-direction and spaced apart from each other. The second semiconductor elements 10B are electrically connected to the conductive substrate 2 (a second conductive section 2B described below) via the second conductive bonding element 72. When the second semiconductor elements 10B are connected to the second conductive section 2B, the element back faces 102 point towards the second conductive section 2B. As shown in Figure 8, the second semiconductor elements 10B are oriented in the y-direction and spaced apart. Fig. As can be seen in Figure 8, the first semiconductor elements 10A and the second semiconductor elements 10B overlap in the x-direction, but they do not necessarily have to overlap.

[0018] Each of the semiconductor elements 10 (the first semiconductor elements 10A and the second semiconductor elements 10B) has a first front-side electrode 11, a second front-side electrode 12, and a back-side electrode 15. The configurations of the first front-side electrode 11, the second front-side electrode 12, and the back-side electrode 15 described below are the same for all semiconductor elements 10. The first front-side electrode 11 and the second front-side electrode 12 are located on the front side 101 of the element. The first front-side electrode 11 and the second front-side electrode 12 are insulated from each other by an insulating film (not shown). The back-side electrode 15 is located on the back side 102 of the element.

[0019] The first front electrode 11 is, for example, a gate electrode to which a control signal (e.g., gate voltage) is applied to control the semiconductor element 10. In the semiconductor element 10, the second back electrode 12 is, for example, a source electrode through which a source current flows. The back electrode 15 is, for example, a drain electrode through which a drain current flows. The back electrode 15 almost completely covers the back of the element 102. The back electrode 15 can be formed by silver coating.

[0020] Each of the semiconductor elements 10 switches between a connected and a disconnected state depending on a control signal (gate voltage) that is input to the first front electrode 11 (gate electrode) via the switching function unit Q1. The process of switching between the connected and disconnected states is called a switching operation. In the connected state, a current flows from the back electrode 15 (drain electrode) to the second front electrode 12 (source electrode). In the disconnected state, no current flows. In other words, each of the semiconductor elements 10 performs a switching operation via the switching function unit Q1. The semiconductor module A1 converts a first supply voltage (DC voltage), which is, for example,The voltage supplied between input terminal 41 and the two input terminals 42 and 43 is converted into a second supply voltage (AC voltage) by the switching functional units Q1 of the semiconductor elements 10 and outputs the second supply voltage at output terminal 44. Input terminals 41 to 43 and output terminal 44 are power supply terminals that process the supply voltage. Input terminals 41 to 43 are the first power supply terminals that receive the first voltage. Output terminal 44 is the second power supply terminal that outputs the second voltage.

[0021] Some (in the example of Fig. 8 two) of the semiconductor elements 10 each have, in addition to the switching function unit Q1, a diode function unit D1 (see Fig. 20). In semiconductor module A1, one of the first semiconductor elements contains 10A (i.e., the first semiconductor element 10A that is in Fig. 8 is offset furthest in the y2 direction) and one of the second semiconductor elements 10B (i.e. the second semiconductor element 10B that is in Fig. 8 (where it is furthest in the y1 direction) each contains a diode functional unit D1 in addition to the switching functional unit Q1. The function and role of the diode functional unit D1 is not limited to a specific function and role; an example of the diode functional unit D1 could be a temperature sensing diode. In Fig. 20, the diode D2 is, for example, a parasitic diode element of the switching function unit Q1.

[0022] As in Fig. As shown in Figure 8, each of the semiconductor elements 10 having the diode functional unit D1 has a third front-side electrode 13, a fourth front-side electrode 14, and a fifth front-side electrode 16, in addition to the first front-side electrode 11, the second front-side electrode 12, and the back-side electrode 15. The configurations of the third front-side electrode 13, the fourth front-side electrode 14, and the fifth front-side electrode 16, which are described below, are the same for all semiconductor elements 10 having the diode functional unit D1. The third front-side electrode 13, the fourth front-side electrode 14, and the fifth front-side electrode 16 are formed on the element front 101. In each of the semiconductor elements 10 having the diode functional unit D1, the third front-side electrode 13 and the fourth front-side electrode 14 are electrically connected to the diode functional unit D1.The fifth front-side electrode 16 is, for example, a source sense electrode through which a source current of the switching function unit Q1 flows.

[0023] As in Fig. As shown in Figure 7, each of the first semiconductor elements 10A has a first side 191, a second side 192, a third side 193 and a fourth side 194 in the top view. Fig. Figure 7 shows the first semiconductor element 10A, which is arranged centrally in the y-direction below the first semiconductor elements 10A aligned in the y-direction. Similarly, each of the other first semiconductor elements 10A has a first side 191, a second side 192, a third side 193, and a fourth side 194. The first side 191 and the second side 192 extend in the y-direction. The first side 191 is an edge that lies in the x2-direction in the top view, and the second side 192 is an edge that lies in the x1-direction in the top view. The third side 193 and the fourth side 194 extend in the x-direction. The third side 193 is an edge that lies in the y2-direction in the top view, and the fourth side 194 is an edge that lies in the y1-direction in the top view.Since each of the first semiconductor elements 10A has a rectangular shape in plan view, the four corners formed by the first side 191, the second side 192, the third side 193, and the fourth side 194 are generally right angles in plan view. As shown in . Fig. As shown in Figure 7, the four corners do not overlap with the conducting element 6 in the top view (first conducting elements 61 and a second conducting element 62, which are described below). The third side 193 and the fourth side 194 are longer than the first side 191 and the second side 192.

[0024] The conductive substrate 2 is also referred to as the leadframe. The conductive substrate 2 supports the semiconductor elements 10. The conductive substrate 2 is connected to the support substrate 3 via the first conductive bonding element 71. In plan view, the conductive substrate 2 has, for example, a rectangular shape. The conductive substrate 2, together with the conductive element 6, forms the path of a main circuit current switched by the semiconductor elements 10.

[0025] The conductive substrate 2 has a first conductive section 2A and a second conductive section 2B. The first conductive section 2A and the second conductive section 2B are plate-shaped elements made of metal. The metal is, for example, copper (Cu) or a Cu alloy. The first conductive section 2A and the second conductive section 2B, together with the input terminals 41 to 43 and the output terminals 44, form a conductive path to the semiconductor elements 10. As shown in the Fig. 13 to Fig. As shown in Figure 18, the first conductive section 2A and the second conductive section 2B are connected to the substrate 3 via the first conductive bonding element 71. The first semiconductor elements 10A are connected to the first conductive section 2A via the second conductive bonding element 72. The second semiconductor elements 10B are connected to the second conductive section 2B via the second conductive bonding element 72. As shown in the Fig. 3, Fig. 8, Fig. 13 and Fig. As shown in Figure 14, the first conducting section 2A and the second conducting section 2B are spaced apart in the x-direction. In the example shown in these figures, the first conducting section 2A is offset relative to the second conducting section 2B in the x2-direction. In plan view, the first conducting section 2A and the second conducting section 2B have, for example, a rectangular shape. Viewed in the x-direction, the first conducting section 2A and the second conducting section 2B overlap. The first conducting section 2A and the second conducting section 2B can each have a dimension of 15 mm to 25 mm (preferably about 20 mm) in the x-direction, a dimension of 30 mm to 40 mm (preferably about 35 mm) in the y-direction, and a dimension of 1.5 mm to 3.0 mm (preferably about 2.0 mm) in the z-direction.

[0026] The conductive substrate 2 has a front 201 and a back 202. As shown in the Fig. 13, Fig. 14 and Fig. 16 to Fig. As shown in Figure 18, the front face 201 and the back face 202 are spaced apart in the z-direction. The front face 201 points in the z2 direction, and the back face 202 in the z1 direction. The front face 201 is a combination of the top surface of the first conductive section 2A and the top surface of the second conductive section 2B. The back face 202 is a combination of the bottom surface of the first conductive section 2A and the bottom surface of the second conductive section 2B. The back face 202 faces the support substrate 3 and is bonded (connected) to it. As shown in the Fig. 5, Fig. 8 and Fig. As shown in Figure 13, the front surface 201 is provided with a multitude of recessed sections 201a. The recessed sections 201a are recessed in the z-direction from the front surface 201. The degree of recession (depth) of each recessed section 201a is, for example, greater than 0 µm and less than or equal to 100 µm. The recessed sections 201a are formed, for example, during the shaping process described below. The recessed sections 201a include those formed in the front surface 201 of the first conductive section 2A and those formed in the front surface 201 of the second conductive section 2B. Two recessed sections 201a formed in the front surface 201 of the first conductive section 2A are spaced apart in the y-direction and overlap each other in the y-direction.Two recessed sections 201a, formed in the front face 201 of the second conducting section 2B, are spaced apart from each other in the y-direction and overlap each other when viewed in the y-direction.

[0027] The conductive substrate 2 (each, the first conductive section 2A and the second conductive section 2B) comprises a base element 21, a front-side bonding layer 22, and a back-side bonding layer 23, stacked on top of each other. The base element 21 is a plate-shaped metal element. The metal is copper or a copper alloy. The front-side bonding layer 22 is formed on the top side of the base element 21. The front-side bonding layer 22 is the surface layer of the conductive substrate 2 in the z2 direction. The top side of the front-side bonding layer 22 corresponds to the front 201 of the conductive substrate 2. The front-side bonding layer 22 is, for example, an silver coating. The back-side bonding layer 23 is formed on the bottom side of the base element 21. The back-side bonding layer 23 is the surface layer of the conductive substrate 2 in the z1 direction.The underside of the backside bonding layer 23 corresponds to the backside 202 of the conductive substrate 2. The backside bonding layer 23 is, for example, an Ag coating, as is the frontside bonding layer 22.

[0028] The support substrate 3 carries the conductive substrate 2. The support substrate 3 is, for example, a directly bonded copper substrate (DBC). The support substrate 3 has an insulating layer 31, a first metal layer 32, a first bonding layer 321, and a second metal layer 33.

[0029] The insulating layer 31 is, for example, a ceramic with excellent thermal conductivity. The ceramic can be made of aluminum nitride (AlN). The insulating layer 31 is not limited to ceramic, but can also be formed, for example, from an insulating resin sheet. The insulating layer 31 has, for example, a rectangular shape when viewed from above.

[0030] The first metal layer 32 is formed on the upper surface (facing in the z2 direction) of the insulating layer 31. The material of the first metal layer 32 contains, for example, copper. The material can contain aluminum instead of copper. The first metal layer 32 has a first section 32A and a second section 32B. The first section 32A and the second section 32B are spaced apart from each other in the x direction. The first section 32A is offset in the x2 direction relative to the second section 32B. The first section 32A is bonded to the first conductive section 2A and carries the first conductive section 2A. The second section 32B is bonded to the second conductive section 2B and carries the second conductive section 2B. In plan view, the first section 32A and the second section 32B each have, for example, a rectangular shape.

[0031] The first bonding layer 321 is formed on the top surface of the first metal layer 32 (both of the first section 32A and the second section 32B). The first bonding layer 321 is, for example, an Ag coating. The first bonding layer 321 serves to improve the solid-state diffusion bonding with the first conductive bonding element 71.

[0032] The second metal layer 33 is formed on the lower (z1-direction) surface of the insulating layer 31. The second metal layer 33 is made of the same material as the first metal layer 32. In the Fig. In the example shown in Figure 10, the lower surface (the bottom surface 302 described below) of the second metal layer 33 is exposed by the sealing resin 8. The lower surface need not be exposed by the sealing resin 8, but rather covered by it. The second metal layer 33 may overlap with the first section 32A and the second section 32B in the top view.

[0033] As in the Fig. 13 to Fig. As shown in Figure 18, the support substrate 3 has a bearing surface 301 and a base surface 302. The bearing surface 301 and the base surface 302 are spaced apart from each other in the z-direction. The bearing surface 301 points in the z2 direction, the base surface 302 in the z1 direction. As shown in Fig. As shown in Figure 10, the bottom surface 302 is exposed by the sealing resin 8. The bearing surface 301 is the top surface of the first bonding layer 321, i.e., a combination of the top surface of the first section 32A and the top surface of the second section 32B. The bearing surface 301 faces and is bonded to the conductive substrate 2. The bottom surface 302 is the lower surface of the second metal layer 33. A heat-dissipating element (e.g., a heat sink) or similar component, not shown in the figure, can be attached to the bottom surface 302. The dimension of the support substrate 3 in the z-direction (distance in the z-direction from the bearing surface 301 to the bottom surface 302) is, for example, 0.7 mm to 2.0 mm.

[0034] The input terminals 41 to 43 and the output terminals 44 are each a plate-shaped metal plate. The metal plate is made, for example, of copper or a copper alloy. In the Fig. 1 to Fig. 5, Fig. 8 and Fig. In the example shown in Figure 10, the semiconductor module A1 has three input terminals 41 to 43 and two output terminals 44.

[0035] The supply voltage is applied to the three input terminals 41 to 43. In the present embodiment, input terminal 41 is a positive electrode (P terminal), and the two input terminals 42 and 43 are negative electrodes (N terminals). Alternatively, input terminal 41 can be a negative terminal (N terminal), and the two input terminals 42 and 43 can be positive terminals (P terminals). In this case, the wiring in the housing can be adapted to the change in polarity of the individual terminals. The three input terminals 41 to 43 and the two output terminals 44 each have a section covered with the sealing resin 8 and a section exposed by a resin side face of the sealing resin 8.

[0036] As in Fig. As shown in Figure 14, the input terminal 41 is formed integrally with the first conductive section 2A. In contrast to this configuration, the input terminal 41 can be separate from and electrically bonded to the first conductive section 2A. As shown in Fig. As shown in Figure 8, the input terminal 41 is offset in the x2 direction relative to the first semiconductor elements 10A and the first conductive section 2A (conductive substrate 2). The input terminal 41 is electrically connected to the first conductive section 2A and is electrically connected via the first conductive section 2A to the back electrodes 15 (drain electrodes) of the first semiconductor elements 10A. The input terminal 41 is an example of a "first input terminal".

[0037] The input port 41 has an input-side bonding surface 411 and input-side side surfaces 412. The input-side bonding surface 411 points in the z2 direction and extends in the x2 direction. Each of the input-side side surfaces 412 is located at the edge of the input-side bonding surface 411 in the z-direction and points in a direction that intersects the input-side bonding surface 411. In the present embodiment, the input-side side surfaces 412 have a pointed surface 413 and a pair of side surfaces 414. The pointed surface 413 is located at the end of the input port 41 in the x2 direction and points in the x2 direction. The two side surfaces 414 are located at the respective ends of the input port 41 in the y direction and point in the y1 and y2 directions, respectively. Of the input-side side surfaces 412, at least the tip surface 413 or the pair of side surfaces 414 has an input-side processing mark.The input-side editing marker is formed by cutting a leadframe, as described below.

[0038] As in Fig. As shown in Figure 8, the two input terminals 42 and 43 are spaced apart from the first conductive section 2A. The two input terminals 42 and 43 are connected to the second conductive element 62. As shown in Fig. As shown in Figure 8, for example, the two input terminals 42 and 43 are offset in the x2 direction relative to the first semiconductor elements 10A and the first conductive section 2A (conductive substrate 2). The two input terminals 42 and 43 are electrically connected to the second conductive element 62 and are electrically connected via the second conductive element 62 to the second front electrodes 12 (source electrodes) of the second semiconductor elements 10B. Input terminal 42 is an example of a "second input terminal," and input terminal 43 is an example of a "third input terminal."

[0039] The input port 42 has an input-side bonding surface 421 and input-side side surfaces 422, and the input port 43 has an input-side bonding surface 431 and input-side side surfaces 432. The input-side bonding surfaces 421 and 431 are oriented in the z2 direction and extend in the x2 direction. Each of the input-side side surfaces 422 is located at the edge of the input-side bonding surface 421 in the z direction and points in a direction that intersects the input-side bonding surface 421. Each of the input-side side surfaces 432 is located at the edge of the input-side bonding surface 431 in the z direction and points in a direction that intersects the input-side bonding surface 431. In the present embodiment, the inlet-side side surfaces 422 have a tip surface 423 and a pair of side surfaces 424.The pointed surface 423 is located at the end of the inlet port 42 in the x2 direction and points in the x2 direction. The two side surfaces 424 are located at the respective ends of the inlet port 42 in the y direction and point in the y1 and y2 directions, respectively. Of the inlet-side side surfaces 422, at least the pointed surface 423 or the pair of side surfaces 424 has an inlet-side machining mark. The inlet-side machining mark is formed by cutting a leadframe, as described below. The inlet-side side surfaces 432 have a pointed surface 433 and a pair of side surfaces 434. The pointed surface 433 is located at the end of the inlet port 43 in the x2 direction and points in the x2 direction. The two lateral surfaces 434 are located at the respective ends of the input port 43 in the y-direction and point in the y1-direction and y2-direction, respectively.Of the entry-side side faces 432, at least the tip face 433 or the pair of side faces 434 has an entry-side machining mark. The entry-side machining mark is formed by cutting a leadframe, as described below.

[0040] As in the Fig. 1 to Fig. 5, Fig. 8 and Fig. As shown in Figure 10, the three input terminals 41 to 43 of the semiconductor module A1 protrude from the sealing resin 8 in the x2 direction. The three input terminals 41 to 43 are spaced apart from each other. The two input terminals 42 and 43 are arranged opposite each other, with input terminal 41 lying between them in the y direction. Input terminal 42 is offset relative to input terminal 41 in the y2 direction, and input terminal 43 is offset relative to input terminal 41 in the y1 direction. The three input terminals 41 to 43 overlap in the y direction.

[0041] As from the Fig. 8 and Fig. As can be seen in Figure 14, the two output terminals 44 are formed integrally with the second conductive section 2B. In contrast to this configuration, the output terminals 44 can be separate from the second conductive section 2B and electrically bonded to it. As shown in Fig. As shown in Figure 8, for example, the two output terminals 44 are offset in the x1 direction relative to the second semiconductor elements 10B and the second conductive section 2B (conductive substrate 2). The output terminals 44 are electrically connected to the second conductive section 2B and, via the second conductive section 2B, electrically connected to the back electrodes 15 (drain electrodes) of the second semiconductor elements 10B. The two output terminals 44 are examples of a "first output terminal" and a "second output terminal".

[0042] The output terminals 44 each have an output-side bonding surface 441 and output-side side surfaces 442. The output-side bonding surface 441 is oriented in the z2 direction and extends in the x1 direction. Each of the output-side side surfaces 442 is located at the edge of the output-side bonding surface 441 in the z direction and points in a direction that intersects the output-side bonding surface 441. In the present embodiment, the output-side side surfaces 442 have a pointed surface 443 and a pair of side surfaces 444. The pointed surface 443 is located at the end of the output terminal 44 in the x1 direction and points in the x1 direction. The two side surfaces 444 are located at the respective ends of the output terminal 44 in the y direction and point in the y1 and y2 directions, respectively.Of the output-side side faces 442, at least the tip face 443 or the pair of side faces 444 has an output-side machining mark. The output-side machining mark is formed by cutting a leadframe, as described below. The number of output ports 44 is not limited to two, but can be one, three, or more. If the number of output ports 44 is one, it is desirable that the output port 44 be connected to the middle section of the second conductive section 2B in the y-direction.

[0043] The control terminals 45 are pin-shaped terminals for controlling the semiconductor elements 10. The control terminals 45 have a plurality of first control terminals 46A to 46E and a plurality of second control terminals 47A to 47D. The first control terminals 46A to 46E are used to control the first semiconductor elements 10A. The second control terminals 47A to 47D are used to control the second semiconductor elements 10B.

[0044] The first control connections, 46A to 46E, are arranged at intervals in the y-direction. As shown in the Fig. 8 and Fig. As shown in Figure 14, the first control connections 46A to 46E are carried by the first conductive section 2A via the control connection carriers 5 (a first carrier section 5A is described further below). As shown in the Fig. 5 and Fig. As shown in Figure 8, the first control terminals 46A to 46E are located between the first semiconductor elements 10A and the three input terminals 41 to 43 in the x-direction.

[0045] The first control terminal 46A is a terminal (gate terminal) used to input a control signal for the first semiconductor elements 10A. The first control terminal 46A receives the control signal to control the first semiconductor elements 10A (e.g., the application of a gate voltage).

[0046] The first control terminal 46B is a terminal (source detection terminal) used to detect a source signal for the first semiconductor elements 10A. The voltage applied to the second front electrodes 12 (source electrodes) of the first semiconductor elements 10A (corresponding to a source current) is detected by the first control terminal 46B.

[0047] The first control terminals 46C and 46D are terminals that are electrically connected to the diode functional unit D1. The first control terminal 46C is electrically connected to the third front-side electrode 13 of the first semiconductor element 10A that has the diode functional unit D1, and the first control terminal 46D is electrically connected to the fourth front-side electrode 14 of the first semiconductor element 10A that has the diode functional unit D1.

[0048] The first control terminal 46E is a terminal (drain detection terminal) used to detect a drain signal for the first semiconductor elements 10A. The voltage applied to the back electrodes 15 (drain electrodes) of the first semiconductor elements 10A (corresponding to a drain current) is detected by the first control terminal 46E.

[0049] The second control terminals 47A to 47D are arranged at intervals in the y-direction. As shown in the Fig. 5 and Fig. As shown in Figure 18, the second control terminals 47A to 47D are held by the second conductive section 2B over the control terminal carriers 5 (a second carrier section 5B is described below). As shown in the Fig. 5 and Fig. As shown in Figure 8, the second control terminals 47A to 47D are located between the second semiconductor elements 10B and the two output terminals 44 in the x-direction.

[0050] The control terminals 45 (the first control terminals 46A to 46E and the second control terminals 47A to 47D) each have a holder 451 and a metal pin 452.

[0051] Holder 451 is made of a conductive material. As in Fig. As shown in Figure 15, the holder 451 is connected to the control connection carrier 5 (a first metal layer 52, described below) via a conductive bonding element 459. The holder 451 has a tubular section, a flanged section at the upper end, and a flanged section at the lower end. The flanged section at the upper end is joined to the upper end of the tubular section, and the flanged section at the lower end is joined to the lower end of the tubular section. The metal pin 452 is inserted at least through the flanged section at the upper end and the tubular section of the holder 451. The upper surface of the flanged section at the upper end is exposed by the sealing resin 8 (a second projecting section 852 is described below) and covered by the resin element 87.

[0052] The metal pin 452 is a rod-shaped element extending in the z-direction. The metal pin 452 is supported by pressing it into the holder 451. The metal pin 452 is electrically connected to the control terminal carrier 5 (a first metal layer 52, described below) at least via the holder 451. As in the example in Fig. As shown in Figure 15, the metal pin 452 is electrically connected to the control terminal carrier 5 via the conductive bonding element 459 when the lower end (end in z1 direction) of the metal pin 452 is in contact with the conductive bonding element 459 inside the insertion hole of the holder 451.

[0053] The control connector carrier 5 carries the control connections 45. The control connector carrier 5 is provided between the front face 201 (conductive substrate 2) and the control connections 45.

[0054] The control terminal carrier 5 has a first carrier section 5A and a second carrier section 5B. The first carrier section 5A is arranged on the first conductive section 2A of the conductive substrate 2 and carries the first control terminals 46A to 46E below the control terminals 45. As shown in Fig. As shown in Figure 15, the first support section 5A is connected to the first conductive section 2A via a bonding element 59. The bonding element 59 can be conductive or insulating. The bonding element 59 can, for example, be solder. The second support section 5B is arranged on the second conductive section 2B of the conductive substrate 2 and carries the second control terminals 47A to 47D of the control terminals 45. The second support section 5B is connected to the second conductive section 2B via the bonding element 59.

[0055] The control interface carrier 5 (first carrier section 5A and second carrier section 5B) can, for example, be a DBC substrate. The carrier sections of the control interface carrier 5 each have an insulating layer 51, a first metal layer 52, and a second metal layer 53, which are stacked on top of each other.

[0056] The insulating layer 51 is, for example, ceramic. In a top view, the insulating layer 51 has, for example, a rectangular shape.

[0057] As in Fig. As shown in Figure 15, the first metal layer 52 is formed, for example, on the top side of the insulating layer 51. The control terminals 45 are applied to the first metal layer 52. The first metal layer 52 is, for example, copper or a copper alloy. As shown in Fig. As shown in Figure 8, the first metal layer 52 has a first section 521, a second section 522, a third section 523, a fourth section 524, and a fifth section 525. The first section 521, the second section 522, the third section 523, the fourth section 524, and the fifth section 525 are spaced apart and insulated from each other.

[0058] A multitude of wires 731 are bonded to the first section 521, such that the first section 521 is electrically bonded via the wires 731 to the first front-end electrodes 11 (gate electrodes) of the semiconductor elements 10. As in Fig. As shown in Figure 8, the first control terminal 46A is bonded to the first section 521 of the first carrier section 5A, and the second control terminal 47A is bonded to the first section 521 of the second carrier section 5B.

[0059] A multitude of wires 732 are bonded to the second section 522, such that the second section 522 is electrically bonded via the wires 732 to the second front electrodes 12 (source electrodes) of the semiconductor elements 10. As shown in Fig. As shown in Figure 8, the first control terminal 46B is connected to the second section 522 of the first support section 5A, and the second control terminal 47B is connected to the second part 522 of the second support section 5B.

[0060] A wire 733 is bonded to the third section 523, such that the third section 523 is electrically bonded via the wire 733 to the third front electrode 13 of the semiconductor element 10, which has the diode functional unit D1. As shown in Fig. As shown in Figure 8, the first control terminal 46C is bonded to the third section 523 of the first carrier section 5A, and the second control terminal 47C is bonded to the third section 523 of the second carrier section 5B.

[0061] A wire 734 is bonded to the fourth section 524, so that the fourth section 524 is electrically connected via the wire 734 to the fourth front electrode 14 of the semiconductor element 10, which has the diode functional unit D1. As shown in Fig. As shown in Figure 8, the first control terminal 46D is bonded to the fourth section 524 of the first carrier section 5A, and the second control terminal 47D is bonded to the fourth section 524 of the second carrier section 5B.

[0062] A 735 wire is bonded to the fifth section 525 of the first carrier section 5A, and the fifth section 525 is electrically bonded to the first conductive section 2A. The fifth section 525 of the second carrier section 5B is not electrically connected to any other components. As shown in Fig. As shown in Figure 8, the first control terminal 46E is bonded to the fifth section 525 of the first carrier section 5A.

[0063] As in Fig. As shown in Figure 15, the second metal layer 53 is formed, for example, on the lower surface of the insulating layer 51. As in Fig. As shown in Figure 15, the second metal layer 53 of the first support section 5A is bonded to the first conductive section 2A via the bonding element 59. The second metal layer 53 of the second support section 5B is connected to the second conductive section 2B via the bonding element 59.

[0064] The conductive element 6, together with the conductive substrate 2, forms the path of a main circuit current switched by the semiconductor elements 10. The conductive element 6 is separated from the front face 201 (conductive substrate 2) in the z2 direction and overlaps with the front face 201 in the top view. In the present embodiment, the conductive element 6 is a plate-shaped metal element. The metal is, for example, copper or a copper alloy. More precisely, the conductive element 6 is a plate-shaped metal element that is bent. Alternatively, the conductive element 6 can also be a metal foil. In the present embodiment, the conductive element 6 has a plurality of first conductive elements 61 and a second conductive element 62. The main circuit current has a first main circuit current and a second main circuit current.The first main circuit current flows via a path between the input terminal 41 and the output terminals 44. The second main circuit current flows via a path between the output terminals 44 and the input terminals 42, 43.

[0065] The first conductive elements 61 are connected to the second front-side electrodes 12 (source electrodes) of the first semiconductor elements 10A and the second conductive section 2B, such that the second front-side electrodes 12 of the first semiconductor elements 10A are electrically connected to the second conductive section 2B. The first conductive elements 61 and the second back-side electrodes 12 (see Fig. 8) The first semiconductor elements 10A, as well as the first conductive elements 61 and the second conductive section 2B, are bonded together via the conductive bonding element 69. The conductive bonding element 69 can be solder, a metal paste, or a sintered metal. As shown in Fig. As shown in Figure 8, each of the first conducting elements 61 has a band shape that extends along the x-direction in the top view.

[0066] In the present embodiment, each of the first conductive elements 61 has a rectangular section connecting the first semiconductor element 10A and the second conductive section 2B, and the rectangular section is provided with an opening 61h, as shown, for example, in Fig. Figure 6 shows the opening 61h. The opening 61h can be a through hole in the z-direction, preferably formed in the center of the rectangular section in the top view. The opening 61h is shaped such that, when a flowable resin material is injected to form a sealing resin, the resin material can easily flow between the top (in the z2 direction) and the bottom (in the z1 direction) near the first conductive element 61. In the top view, the opening 61h can be perfectly circular or have another shape, e.g., an oval or rectangular shape. Each of the first conductive elements 61 is not limited to the configuration described above and need not necessarily be provided with an opening 61h.

[0067] In the present embodiment, the number of first conductive elements 61 is three to correspond to the number of first semiconductor elements 10A. Alternatively, a single first conductive element 61 can be used that is common to all first semiconductor elements 10A, without this depending on the number of first semiconductor elements 10A.

[0068] The second conductive element 62 electrically connects the second front electrodes 12 of the second semiconductor elements 10B to the input terminals 42 and 43. The second conductive element 62 can have a maximum dimension of 25 mm to 40 mm (preferably about 32 mm) in the x-direction and a maximum dimension of 30 mm to 45 mm (preferably about 38 mm) in the y-direction. As shown in Fig. As shown in Figure 6, the second conductive element 62 has a first wiring section 621, a second wiring section 622, a third wiring section 623 and a fourth wiring section 624.

[0069] The first wiring section 621 is connected to the input terminal 42. The first wiring section 621 and the input terminal 42 are bonded to the conductive bonding element 69. The first wiring section 621 has a ribbon shape that extends in the x-direction in the plan view.

[0070] The second wiring section 622 is connected to the input terminal 43. The second wiring section 622 and the input terminal 43 are bonded to the conductive bonding element 69. The second wiring section 622 has a ribbon shape that extends in the x-direction in the plan view. The first wiring section 621 and the second wiring section 622 are spaced apart from each other in the y-direction and are substantially parallel to each other. The second wiring section 622 is offset in the y1-direction relative to the first wiring section 621.

[0071] The third wiring section 623 is joined with the first wiring section 621 and the second wiring section 622. In plan view, the third wiring section 623 has a band shape extending in the y-direction. As shown from Fig. As can be seen in Figure 6, the third wiring section 623 overlaps with the second semiconductor elements 10B in the top view. As shown in Figure 6. Fig. As shown in Figure 17, the third wiring section 623 is connected to the second semiconductor elements 10B. The third wiring section 623 has a plurality of recessed areas 623a. As shown in Fig. As shown in Figure 17, the recessed areas 623a are recessed in the z1 direction relative to the other areas of the third wiring section 623. The recessed areas 623a of the third wiring section 623 are bonded to the second semiconductor elements 10B. The recessed areas 623a of the third wiring section 623 and the second front-side electrodes 12 (see Figure 17) are shown in Figure 17. Fig. 8) The second semiconductor elements 10B are bonded to the conductive bonding element 69.

[0072] The fourth wiring section 624 is connected to the first wiring section 621 and the second wiring section 622. The fourth wiring section 624 is also connected to the third wiring section 623. The fourth wiring section 624 is offset in the x2 direction relative to the third wiring section 623. As can be seen from Fig. As can be seen in Figure 6, the fourth wiring section 624 overlaps with the first semiconductor elements 10A in the top view. The fourth wiring section 624 has a first band section 625 and a plurality of second band sections 626.

[0073] The first ribbon section 625 is part of the fourth wiring section 624, which has a ribbon shape in plan view and is spaced x-direction from the third wiring section 623. The first ribbon section 625 is joined with the first wiring section 621 and the second wiring section 622. The first ribbon section 625 overlaps the first semiconductor elements 10A in plan view. The first ribbon section 625 has a plurality of projecting regions 625a. As shown in Fig. As shown in Figure 16, the protruding areas 625a project in the z2 direction relative to the other areas of the first band section 625. As shown in Fig. As shown in Figure 6, the projecting areas 625a overlap with the first semiconductor elements 10A in the top view. Since the first strip section 625 has the projecting areas 625a, areas (surfaces) for bonding the first conductive elements 61 are provided on the first semiconductor elements 10A, as shown in Figure 6. Fig. 16 shown. This prevents the first tape section 625 from coming into contact with the first conductive elements 61.

[0074] Each of the second ribbon sections 626 is connected to the first ribbon section 625 and the third wiring section 623. Each of the second ribbon sections 626 has a ribbon shape that extends in the x-direction in the plan view. The second ribbon sections 626 are spaced apart from each other in the y-direction and are substantially parallel to each other. In the plan view, a first end of each ribbon section 626 is connected to a portion of the first ribbon section 625 located between two first semiconductor elements 10A adjacent in the y-direction, and the other end of each ribbon section 626 is connected to a portion of the third wiring section 623 located between two second semiconductor elements 10B adjacent in the y-direction.

[0075] The first strip section 625 has a first edge 627 and a second edge 628. As in Fig. As shown in Figure 7, the first edge 627 is offset in the x1 direction relative to the first side 191 in the top view and extends in the y direction at least from the third side 193 to the fourth side 194. Therefore, two corners 171 and 172 of each first semiconductor element 10A do not overlap with the second conducting element 62 in the x2 direction in the top view. The two corners are corner 171, formed by the first side 191 and the third side 193, and corner 172, formed by the first side 191 and the fourth side 194. Accordingly, in each of the first semiconductor elements 10A, portions of the two sides flanking corners 171 and 172 are visible in the top view (especially when viewed as in Figure 7). Fig. 7 considered; the same applies below). As in Fig. As shown in Figure 7, the second edge 628 is offset in the x2 direction relative to the second side 192 in the plan view and extends in the y direction at least from the third side 193 to the fourth side 194. Therefore, two corners 173 and 174 of each first semiconductor element 10A do not overlap with the second conducting element 62 in the x1 direction in the plan view. The two corners are corner 173, formed by the second side 192 and the third side 193, and corner 174, formed by the second side 192 and the fourth side 194. Accordingly, in each of the first semiconductor elements 10A, portions of the two sides flanking corners 173 and 174 are visible in the plan view.

[0076] For corners 171, 172, 173, and 174, it is sufficient if each of the visible sections of the two sides flanking corners 171, 172, 173, and 174 has a length greater than 0 µm and no more than 200 µm in plan view. Furthermore, the length of the visible sections of the two sides flanking corners 171, 172, 173, and 174 should be no less than 5 µm and no more than 150 µm in plan view. If the length of each of the visible sections of the two sides flanking corners 171, 172, 173, and 174 is no less than 2 µm, it is possible to detect the corners of each of the first semiconductor elements 10A. If the length of each of the visible sections of the two sides is not less than 5 µm, it is possible to reliably detect the corners of each of the first 10A semiconductor elements.If the length of each of the visible sections of the two sides is greater than 200 µm, the bonding areas (bonding surfaces) between the first conductive elements 61 and the first semiconductor elements 10A will be smaller than necessary, which is undesirable. Preferably, the upper limit of the length of each of the visible sections of the two sides should not exceed 150 µm, as this prevents the bonding area between the first conductive elements 61 and the first semiconductor elements 10A from becoming too small.

[0077] As in Fig. As shown in Figure 6, the conductive element 6 (first conductive element 61 and second conductive element 62) has first sections 601. The first sections 601 are areas that overlap with the semiconductor elements 10 (first semiconductor elements 10A and second semiconductor elements 10B) in the top view. On the second conductive element 62, parts of the fourth wiring section 624 (areas that overlap with the first semiconductor elements 10A in the top view) and parts of the third wiring section 623 (areas that overlap with the second semiconductor elements 10B in the top view) form the first sections 601.

[0078] As in Fig. 6 and Fig. As shown in Figure 8, the front electrodes 11, 13, 14, and 16 of one of the first semiconductor elements 10A (the first semiconductor element 10A with the diode functional unit D1) are aligned along the y-direction at the end of the first semiconductor element 10A in the x2-direction. In the top view, the first conducting elements 61 and the second conducting element 62 do not overlap with the front electrodes 11, 13, 14, and 16 of the first semiconductor element 10A or with its corners 171 and 172 in the x2-direction. Furthermore, in the top view, the first conducting elements 61 and the second conducting element 62 do not overlap with at least one of the corners 173 and 174 of the first semiconductor element 10A in the x1-direction (opposite to the side on which the front electrodes are arranged). At least three of the four corners 171, 172, 173 and 174 of the semiconductor element 10A are visible in the top view.In this way, it can be verified that the first semiconductor elements 10A are correctly mounted when the first semiconductor elements 10A, the conductive elements 61, and the second conductive element 62 are mounted on the conductive substrate 2. In the top view, the four corners 171, 172, 173, and 174 of each of the first semiconductor elements 10A can all be seen. Note that the front electrodes 11, 13, 14, and 16 of the first semiconductor element 10A are examples of "one-sided front electrodes."

[0079] As in Fig. As shown in Figure 6, each of the second semiconductor elements 10B has a rectangular shape in plan view, similar to the first semiconductor elements 10A, and four corners 181, 182, 183, and 184, corresponding to the four corners 171, 172, 173, and 174 of each first semiconductor element 10A. The top-view relationship described above between the four corners 171, 172, 173, and 174 of each first semiconductor element 10A and the first and second conducting elements 61 and 62 also applies to the top-view relationship between the four corners 181, 182, 183, and 184 of each second semiconductor element 10B and the second conducting element 62.

[0080] As in Fig. As shown in Figure 5, the second conducting element 62 has first sections 62A and second sections 62B. The first sections 62A overlap in plan view with the front face 201 of the conducting substrate 2 (the front face 201 of either the first conducting section 2A or the second conducting section 2B) and do not overlap in plan view with either of the semiconductor elements 10. The second sections 62B overlap in plan view with the front face 201 and also overlap in plan view with the semiconductor elements 10. Fig. Figure 5 shows the first sections 62A with a diagonally rising hatching to the right and the second sections 62B with a diagonally falling hatching to the right. The first sections 62A have openings 63. As shown in the Fig. 5 and Fig. As shown in Figure 13, the openings 63 are partially cut away in the top view. In the present embodiment, the openings 63 are located at positions that, in the top view, overlap with the front face 201 of the first conductive section 2A (conductive substrate 2) and do not overlap with the semiconductor elements 10. The openings 63 are through holes, e.g., extending through in the z-direction. The openings 63 include one opening in the first wiring section 621 and one opening in the second wiring section 622. In the top view, the openings 63 are located near at least two of the four corners of the conductive substrate 2. For example, one of the openings 63 is located in a region of the first wiring section 621 in the x2-direction, and the other is located in a region of the second wiring section 622 in the x2-direction. The planar shape of each opening 63 is not to be understood as limiting.The openings 63 can be, for example, holes, as described in the present embodiment, or notches, in contrast to the present embodiment. The openings 63 can be produced, for example, by electroforming. In this case, the second conductive element 62 has openings 63 in areas that are not electroplated with a metal, instead of the openings 63 that are created by removing parts of the second conductive element 62.

[0081] The second conductive element 62 is provided with openings 625h in rectangular sections, which overlap with the first semiconductor elements 10A in plan view. In the present embodiment, it is advantageous that the openings 625h are configured such that they overlap with the centers of the first semiconductor elements 10A in plan view. The openings 625h are through holes (see Fig. 6), which are formed, for example, in the aforementioned areas 625a of the first strip section 625 (fourth wiring section 624). The openings 625h serve to make the bonding state (connection state) visually verifiable from above when connecting the first conductive elements 61 and the first semiconductor elements 10A.

[0082] The second conductive element 62 is provided with openings 623h in rectangular sections, which overlap with the second semiconductor elements 10B in plan view. In the present embodiment, it is advantageous that the openings 623h are configured to overlap with the centers of the second semiconductor elements 10B in plan view. The openings 623h are through holes, which are formed, for example, in the recessed areas 623a of the third wiring section 623. The openings 623h are used when the second conductive element 62 is positioned relative to the conductive substrate 2. In plan view, each of the two types of openings 623h and 625h can have a perfectly circular shape or another shape, such as an oval or rectangular shape.

[0083] The second conductive element 62 is not limited to the configuration described above and may not include the fourth wiring section 624. However, the second conductive element 62 is preferably provided with the fourth wiring section 624 in order to reduce the induction value due to the current flowing through the second conductive element 62.

[0084] The first conductive bonding element 71 is provided between the conductive substrate 2 and the support substrate 3 to electrically connect the conductive substrate 2 and the support substrate 3. The first conductive bonding element 71 has a conductive bonding section that electrically connects the first conductive section 2A to the first section 32A, and a conductive bonding section that electrically connects the second conductive section 2B to the second section 32B. As shown in Fig. As shown in Figure 15, the first conductive bonding element 71 has a first base layer 711, a first layer 712 and a second layer 713 stacked on top of each other.

[0085] As in Fig. As shown in Figure 15, it is preferred that a side surface of the first conductive bonding element 71 and a side surface of the first metal layer 32, which is the uppermost layer of the support substrate 3, are flush with each other. Preferably, the side surface of the first metal layer 32 is positioned slightly further inward in the top view than the side surface of the first conductive bonding element 71. That is, in the top view, the bonding is carried out such that the side surface of the first metal layer 32 does not extend outward from the side surface of the first conductive bonding element 71. If the side surface of the first metal layer 32 extends further outward in the top view than the side surface of the first conductive bonding element 71, the creepage distance between the first metal layer 32 and the second metal layer 33 becomes undesirably small.In the top view, the side surface of the first metal layer 32 is arranged further outwards than a side surface of the base element 21 on the conductive substrate 2.

[0086] The first base layer 711 is made of a metal, e.g., aluminum or an aluminum alloy. The first base layer 711 is made of a sheet material. The Young's modulus of elasticity of aluminum (Al), the material of the first base layer 711, is 70.3 GPa.

[0087] The first layer 712 is formed on the top side of the first base layer 711. The first layer 712 is located between the first base layer 711 and the conductive substrate 2 (between the first conductive section 2A and the second conductive section 2B, respectively). The first layer 712 is, for example, an Ag coating. The first layer 712 is bonded to the respective backside bonding layer 23 of the first conductive section 2A and the second conductive section 2B, for example, by solid-state diffusion of metal. In other words, the first layer 712 and the backside bonding layer 23 of the first conductive section 2A and the second conductive section 2B are bonded by solid-state diffusion. This results in the first layer 712 and the backside bonding layer 23 being bonded in direct contact with each other at the bonding interface (connection point).In the present disclosure, “A and B are bonded by solid-phase diffusion” means that A and B are attached to each other in direct contact at the bonding interfaces as a result of solid-phase diffusion bonding, with A and B forming a solid-phase diffusion layer. Under ideal conditions, the bonding interface may not be clearly visible in solid-phase diffusion bonding due to the diffusion of the metallic elements. However, if an inclusion, such as an oxide film, has formed on the surface layers of A and B, or if a gap exists between A and B, the inclusion or gap may be present at the bonding interface.

[0088] The second layer 713 is formed on the lower surface of the first base layer 711. The second layer 713 is located between the first base layer 711 and the support substrate 3 (specifically, the first section 32A and the second section 32B). The second layer 713 is, for example, an Ag coating. The second layer 713 is bonded to the first bonding layer 321, which is formed on both the first section 32A and the second section 32B, by solid-state diffusion of metal. In other words, the second layer 713 and the first bonding layer 321 are bonded to each other by solid-state diffusion in direct contact at the bonding interface. The elastic modulus (Young's modulus) of silver (Ag), the material of the first layer 712 and the second layer 713, is 82.7 GPa.

[0089] Since the first base layer 711, the first layer 712, and the second layer 713 of the first conductive bonding element 71 are made of the materials described above, the elastic modulus (Young's modulus) of the first base layer 711 is smaller than the elastic modulus (Young's modulus) of the first layer 712 and the second layer 713. The thickness (dimension in the z-direction) of the first base layer 711 is greater than the thickness of the first layer 712 and the second layer 713.

[0090] In the first conductive bonding element 71, an end face of the first base layer 711, which is made of Al or an Al alloy, is not coated with Ag, so that the end face of the first base layer 711 is exposed. The end face of the first base layer 711 can also be coated with Ag. To reduce the manufacturing costs of the first conductive bonding element 71, it is advantageous to produce the first conductive bonding element 71 by applying an Ag coating to both surfaces of a large layer material and subsequently cutting the Ag-coated layer material. In this context, it is preferred that the end face of the first base layer 711 is not coated with Ag.

[0091] The second conductive bonding element 72 is provided between the conductive substrate 2 and the semiconductor elements 10 to electrically connect the conductive substrate 2 and the semiconductor elements 10. The second conductive bonding element 72 has a conductive bonding section that electrically connects the first semiconductor elements 10A to the first conductive section 2A, and a conductive bonding section that electrically connects the second semiconductor elements 10B to the second conductive section 2B. As shown in Fig. As shown in Figure 15, the second conducting base element 72 has a second base layer 721, a third layer 722 and a fourth layer 723 stacked on top of each other.

[0092] The second base layer 721 is made of a metal, such as aluminum or an aluminum alloy. The second base layer 721 is made of a layered material.

[0093] The third layer 722 is formed on the upper surface of the second base layer 721. The third layer 722 is positioned between the second base layer 721 and the semiconductor elements 10. The third layer 722 is, for example, an Ag coating. The third layer 722 is bonded to the back electrodes 15 of the semiconductor elements 10, for example, by solid-state diffusion of metal. In other words, the third layer 722 and the back electrodes 15 are bonded to each other at the bonding interface by solid-state diffusion.

[0094] The fourth layer 723 is formed on the lower surface of the second base layer 721. The fourth layer 723 is located between the second base layer 721 and the conductive substrate 2 (between the first conductive section 2A and the second conductive section 2B, respectively). The fourth layer 723 is, for example, an Ag coating. The fourth layer 723 is bonded to the respective front-side bonding layers 22 of the first conductive section 2A and the second conductive section 2B, for example, by solid-state diffusion of metal. In other words, the fourth layer 723 and the front-side bonding layers 22 are bonded to each other at the bonding interfaces by solid-state diffusion.

[0095] Since the second base layer 721, the third layer 722, and the fourth layer 723 in the second conductive bonding element 72 are formed from the materials described above, the elastic modulus (Young's modulus) of the second base layer 721 is smaller than the elastic modulus (Young's modulus) of the third layer 722 and the fourth layer 723. The thickness (dimension in the z-direction) of the second base layer 721 is greater than the thickness of the third layer 722 and the fourth layer 723.

[0096] In the second conductive bonding element 72, an end face of the second base layer 721, which is made of Al or an Al alloy, is not coated with Ag, so that the end face of the second base layer 721 is exposed. The end face of the second base layer 721 can also be coated with Ag. To reduce the manufacturing costs of the second conductive bonding element 72, it is advantageous to produce the second conductive bonding element 72 by forming an Ag coating on both surfaces of a large layer material and subsequently cutting the Ag-coated layer material. In this context, it is preferred that the end face of the second base layer 721 is not coated with Ag.

[0097] Wires 731 to 735 each electrically connect two separate elements. Wires 731 to 735 are, for example, bond wires. The material of each of the wires 731 to 735 contains, for example, gold (Au), aluminum (Al), or copper (Cu).

[0098] As in Fig. As shown in Figure 8, the wires 731 are each connected to the first front-side electrode 11 (gate electrode) of a semiconductor element 10 and to a first section 521 (first metal layer 52) of the control terminal carrier 5, thus establishing an electrical connection. As shown in Fig. As shown in Figure 8, the plurality of wires 731 comprises a plurality of first wires 731a and a plurality of second wires 731b. The first wires 731a are each connected to the first front-end electrode 11 (gate electrode) of one of the first semiconductor elements 10A and to the first section 521 (first metal layer 52) of the first support section 5A. Consequently, the first control terminal 46A is electrically connected via the first wires 731a to the first front-end electrodes 11 (gate electrodes) of the first semiconductor elements 10A. The second wires 731b are each connected to the first front-end electrode 11 (gate electrode) of one of the second semiconductor elements 10B and to the first section 521 (first metal layer 52) of the second support section 5B. Consequently, the second control terminal 47A is electrically connected to the first front electrodes 11 (gate electrodes) of the second semiconductor elements 10B via the second wires 731b.

[0099] As in Fig. As shown in Figure 8, the wires 732 are each connected to the second front-side electrode 12 (source electrode) of a semiconductor element 10 and to a second section 522 (first metal layer 52) of the control terminal carrier 5, thus establishing an electrical connection. As with each of the semiconductor elements 10 that have the diode functional units D1, the wire 732 is bonded to the fifth front-side electrode 16 (source sensing electrode) instead of the second front-side electrode 12 (source electrode).

[0100] As in Fig. As shown in Figure 8, the wires 733 are each connected to the third front electrode 13 of one of the semiconductor elements 10 which have the diode functional units D1, and to a third section 523 (first metal layer 52) of the control terminal carrier 5, thus establishing an electrical connection.

[0101] As in Fig. As shown in Figure 8, the wires 734 are each connected to the fourth front electrode 14 of one of the semiconductor elements 10 which have the diode functional units D1 and to a fourth section 524 (first metal layer 52) of the control terminal carrier 5 and establish an electrical connection.

[0102] As in Fig. As shown in Figure 8, the wire 735 is connected to the front 201 of the first conductive section 2A (conducting substrate 2) and the fifth section 525 (first metal layer 52) of the first carrier section 5A (control terminal carrier 5) and establishes an electrical connection.

[0103] The sealing resin 8 covers the semiconductor elements 10, the conductive substrate 2, the support substrate 3 (except for the bottom surface 302), parts of the input terminals 41 to 43, parts of the output terminals 44, parts of the control terminals 45, the control terminal carrier 5, the conductive element 6, and the wires 731 to 735. The sealing resin 8 is, for example, a black epoxy resin. The sealing resin 8 can be produced by the molding process described below. The sealing resin 8 can have dimensions of approximately 35 mm to 60 mm in the x-direction, approximately 35 mm to 50 mm in the y-direction, and approximately 4 mm to 15 mm in the z-direction. Each of these dimensions is the size of the largest section along one of the directions. The sealing resin 8 has a resin front 81, a resin back 82 and a multitude of resin side surfaces 831 to 834.

[0104] As in the Fig. 9, Fig. 11 and Fig. As shown in Figure 12, for example, the resin front 81 and the resin back 82 are spaced apart from each other in the z-direction. The resin front 81 points in the z2 direction and the resin back 82 in the z1 direction. The control connections 45 (the first control connections 46A to 46E and the second control connections 47A to 47D) protrude from the resin front 81. As shown in Fig. As shown in Figure 10, the resin back surface 82 has a frame shape in plan view that surrounds the bottom surface 302 of the support substrate 3 (lower surface of the second metal layer 33). The bottom surface 302 of the support substrate 3 is free from the resin back surface 82 and is, for example, flush with the resin back surface 82. The resin side surfaces 831 to 834 are joined to the resin front surface 81 and the resin back surface 82 and are flanked by these surfaces in the z-direction. As shown in Fig. As shown, the resin-side surface 831 and the resin-side surface 832 are spaced apart from each other in the x-direction. The resin-side surface 831 faces in the x1 direction and the resin-side surface 832 faces in the x2 direction. The two output ports 44 protrude from the resin-side surface 831, and the three input ports 41 to 43 protrude from the resin-side surface 832. As shown in Fig. As shown in Figure 4, for example, resin side surface 833 and resin side surface 834 are spaced apart from each other in the y-direction. Resin side surface 833 points in the y1-direction and resin side surface 834 points in the y2-direction.

[0105] As in Fig. As shown in Figure 4, the resin side surface 832 is provided with a plurality of recessed sections 832a. The recessed sections 832a are recessed in the x-direction in plan view. The recessed sections 832a have a section formed between the inlet port 41 and the inlet port 42, and a section formed between the inlet port 41 and the inlet port 43 in plan view. The recessed sections 832a are provided to increase the creepage distance between the inlet port 41 and the inlet port 42 along the resin side surface 832, and to increase the creepage distance between the inlet port 41 and the inlet port 43 along the resin side surface 832.

[0106] As in the Fig. 13 and Fig. As shown in Figure 14, the sealing resin 8 has a plurality of first projections 851, a plurality of second projections 852 and resin cavities 86.

[0107] The first projections 851 extend in the z-direction from the resin front surface 81. In plan view, the first projections 851 are located near the four corners of the sealing resin 8. The tips (ends in the z2-direction) of each of the first projections 851 are provided with a first projecting end surface 851a. The first projecting end surfaces 851a of the first projections 851 are substantially parallel to the resin front surface 81 and lie in the same plane (xy-plane). The first projections 851 each have, for example, the shape of a hollow truncated cone with a base. The first projections 851 are used for a device that utilizes a power supply generated by the semiconductor module A1 and act as spacers when the semiconductor module A1 is mounted, for example, on a control board of the device. The first projections 851 each have a recessed section 851b and an inner wall surface 851c, which is formed in the recessed section 851b.It is sufficient if the first projections 851 are pier-shaped, preferably column-shaped. Preferably, each of the recessed sections 851b is column-shaped, and each of the inner wall surfaces 851c has a single perfect circular shape in plan view. Each of the first projections 851 is an example of a "projection," and each of the first projecting end faces 851a is an example of a "projecting end face."

[0108] The semiconductor module A1 can be mechanically mounted on a control board or similar, e.g., by screwing. In this case, the threads of the internal screws can be formed in the inner wall surfaces 851c of the recessed sections 851b in the first projections 851. It is also possible to embed an insert nut in the recessed section 851b of each of the first projections 851.

[0109] As in Fig. As shown in Figure 14, for example, the second projections 852 protrude from the resin front face 81 in the z-direction. In plan view, the second projections 852 overlap with the control connections 45. The metal pins 452 of the control connections 45 protrude from the second projections 852. A portion of each holder 451 (the upper surface of each flange section at its top end) is exposed at the upper end face of each second projection 852. Each of the second projections 852 has the shape of a truncated cone. The resin elements 87 are attached to the second projections 852.

[0110] As in Fig. As shown in Figure 13, each of the resin cavities 86 extends from the resin face 81 to the recessed section 201a formed in the z-direction of the front face 201 of the conductive substrate 2. Each of the resin cavities 86 is shaped to taper, such that its cross-sectional area decreases along the z-direction from the resin face 81 to the recessed section 201a. A resin cavity edge 861 of each of the resin cavities 86, which is in contact with the front face 201, and a recess edge 201b of each of the recessed sections 201a, which is in contact with the front face 201, coincide with each other. The resin cavities 86 are sections formed in a shaping process described below, in which the sealing resin 8 is not formed during the shaping process.

[0111] The resin elements 87 are attached to the second projections 852 of the sealing resin 8. The resin elements 87 cover parts of the control connections 45, i.e., parts (tops of the flange sections at the upper end) of the holders 451 that are exposed by the sealing resin 8, and parts of the metal pins 452. The resin elements 87 are, for example, made of epoxy resin like the sealing resin 8, but can also be made of a different material than the sealing resin 8.

[0112] The resin filling sections 88 are intended for the resin cavities 86 in order to fill the resin cavities 86. The resin filling sections 88 are, for example, made of epoxy resin like the sealing resin 8, but can also be made of a different material than the sealing resin 8.

[0113] The following describes a method for manufacturing the semiconductor module A1 with reference to the Fig. 21 to Fig. 29 described. Fig. Figure 21 is a top view showing one step of the process for manufacturing the semiconductor module A1. Fig. Figure 22 is a schematic cross-sectional view showing one step of the process for manufacturing the semiconductor module A1. Fig. Figure 23 is a top view showing one step of the process for manufacturing the semiconductor module A1. Fig. Figure 24 is a cutaway end view showing one step of the process for manufacturing the semiconductor module A1. Fig. 24 corresponds to the one in Fig. 13 shown cross-section. Fig. 25 and Fig. Figures 28 are each a partially enlarged cross-sectional view illustrating a step in the process for manufacturing semiconductor module A1, and correspond to an enlarged view of part of the cross-section in Fig. 13. Each of the Fig. 26, Fig. 27 and Fig. Figure 29 is a partially enlarged cross-sectional view illustrating a step in the process for manufacturing semiconductor module A1, and corresponds to an enlarged view of part of the cross-section in Fig. 14.

[0114] First, a plurality of semiconductor elements 10, a conductive substrate 2, a support substrate 3, a plurality of input terminals 41 to 43, and a plurality of output terminals 44 are prepared. The configurations of the semiconductor elements 10, the conductive substrate 2, and the support substrate 3 are as described above. During their fabrication, the semiconductor elements 10, the conductive substrate 2, and the support substrate 3 are manufactured separately and are not connected to each other. As in Fig. As shown in Figure 21, the conductive substrate 2, the input terminals 41 to 43, and the output terminals 44 are interconnected and can be formed from the same conductor frame. As shown in Fig. As shown in Figure 21, there is no recessed section 201a formed in the front face 201 of the conductive substrate 2.

[0115] Next, as in Fig. Figure 22 shows the conductive substrate 2 being placed on the support substrate 3 via a first conductive bonding element 71, and the semiconductor elements 10 being placed on the conductive substrate 2 via a second conductive bonding element 72. Heat is then applied while the underside of the support substrate 3 and the tops of the semiconductor elements 10 are held in place (see the thick arrows in Figure 22). Fig. 22). Consequently, the semiconductor elements 10 and the conductive substrate 2 are connected to each other by solid-phase diffusion, and the conductive substrate 2 and the support substrate 3 are connected to each other by solid-phase diffusion. More precisely, the following elements are connected to each other by solid-phase diffusion: a first bonding layer 321 (support substrate 3) on a first metal layer 32 and a second layer 713 (first conductive bonding element 71); a first layer 712 (first conductive bonding element 71) and a backside bonding layer 23 (conductive substrate 2); a fourth layer 723 (second conductive bonding element 72) and a frontside bonding layer 22 (conductive substrate 2); and a third layer 722 (second conductive bonding element 72) and backside electrodes 15 of the semiconductor elements 10.Regarding the conditions of solid-state diffusion, the thermal temperature during bonding can range from 200°C to 350°C, and the pressure applied during bonding (holding force) can range from 1 MPa to 100 MPa. It is assumed that solid-state diffusion bonding takes place in the atmosphere, but bonding can also be performed in a vacuum. Consequently, the conductive substrate 2 is bonded to the support substrate 3 via the first conductive bonding element 71, and the semiconductor elements 10 are bonded to the conductive substrate 2 via the second conductive bonding element 72. It should be noted that the connection between the conductive substrate 2 and the support substrate 3, as well as the connection between the conductive substrate 2 and the semiconductor elements 10, can be performed separately and not simultaneously. However, it is preferred to perform the bonding simultaneously to improve manufacturing efficiency.

[0116] In the case that the semiconductor elements 10 are placed on the conductive substrate 2 via the second conductive connecting element 72, individual second conductive connecting elements 72, corresponding to the respective semiconductor elements 10, can be arranged as shown in the Fig. 16 and Fig. 17 shown, provided for. Alternatively, it is possible to provide a single second conductive bonding element 72, which connects the three in Fig. 16 semiconductor elements shown corresponds to 10.

[0117] Next, as in Fig. Figure 23 shows the bonding of a control terminal carrier 5, the bonding of several holders 451 of a plurality of control terminals 45, the bonding of several wires 731 to 735, the bonding of a plurality of first conductive elements 61, and the bonding of a second conductive element 62. The bonding of these elements can take place in any suitable sequence.

[0118] A sealing resin 8 is then formed. The sealing resin 8 is formed, for example, by casting. As in Fig. Figure 24 shows a mold 91 for a molding process, equipped with pressure pins 911 as pressure elements. The tips of the pressure pins 911 are in contact with the front surface 201 of the conductive substrate 2. At this point, the pressure exerted by the pressure pins 911 on the front surface 201 forms recessed sections 201a in the front surface 201. The degree of recession (depth) of the recessed sections 201a varies depending on the strength of the pressure or similar factors. The pressure pins 911, which are in contact with the front surface 201 of a first conductive section 2A, are inserted through openings 63 of the second conductive section 62. Then, a flowable resin material is injected successively into a cavity 919 of the mold 91 via a resin flow channel and a resin inlet (both not shown here). The injected flowable resin material solidifies and forms the sealing resin 8.The sealing resin 8 thus formed has first projections 851, second projections 852 and resin cavities 86, all of which are located at the top, as in the . Fig. 25 and Fig. 26 are shown and described. As in Fig. As shown in Figure 25, a resin cavity edge 861 of each of the resin cavities 86 that is in contact with the front face 201 and a depression edge 201b of each of the depression sections 201a that is in contact with the front face 201 coincide. As shown in Fig. As shown in Figure 26, the top of each holder 451 is exposed by a second projection 852 and is flush with the top of the second projection 852. As can be seen from the Fig. 24 and Fig. As can be seen in Figure 25, the resin cavities 86 are formed by the pressure pins 911, since the flowable resin material does not fill them. The pressure pins 911 can be movable. In this case, the pressure pins 911 are preferably provided in holes in the mold 91 and elastically mounted. The pressure elements do not necessarily have to be pin-shaped, but can also be in the form of a block.

[0119] The mold 91 is then opened and a molded body is removed, containing the conductor frame including the conductive substrate 2 and the sealing resin 8. The sealing resin 8 is then separated from the resin that has solidified at the resin flow channel and the resin inlet. In this process, one or more resin separation marks are formed at either a first or a second position on a resin side face 831 of the sealing resin 8 in the x1 direction. As in Fig. As shown in Figure 1, the first position can correspond to at least one of two positions, each located near a corresponding end of the resin side surface 831 in the y-direction, or to at least one of the edges of the corresponding ends. If the parting line is formed on one of the edges of the respective ends, it can be formed on a surface along the edge (chamfered portion in the top view). Such a chamfered surface can be a portion of the resin side surface 831 of the sealing resin 8 in the x1-direction. The second position is located between the two outlet connections 44 at the Fig. The resin side surface 831 shown in Figure 1. The resin separation mark corresponds to the position of a resin inlet of the mold 91 and is formed by separating the sealing resin 8 from the resin that has solidified at the resin inlet. To avoid uneven resin flow, the resin should preferably be injected from the central position of the mold in the y-direction. In this case, a resin separation mark is formed between the two outlet ports 44.

[0120] Then, as in Fig. As shown in Figure 27, the metal pins 452 of the control connections 45 are pressed into the respective holders 451. In particular, the metal pins 452, whose cross-section is each slightly larger than the inner diameter of a tubular section (see Figure 27), are pressed into the respective holders 451. Fig. 26) Each of the holders 451 is inserted with pressure. This mechanically fixes the holders 451 and the metal pins 452 and electrically connects them. The holders 451 and the metal pins 452 can be electrically connected, for example, with solder. Then the resin elements 87 and the resin-filled sections 88 are installed as described in the Fig. 28 and Fig. 29 shown in the molded form. The resin elements 87 and the resin filling sections 88 can be produced by casting.

[0121] The conductor frame is then cut accordingly to separate output terminals 41 to 43 and output terminal 44. For each of the in Fig. The area near the connecting section (in 21) can be seen at the input terminals 41 to 43 and output terminals 44 shown. Fig. 21 (section indicated by a dashed line) between the terminal and the outer frame section of the conductor frame are cut out using a die or similar tool. At this point, the input terminals 41 to 43 are provided with pointed surfaces 413, 423, and 433, respectively, which have input-side machining marks. Each of the output terminals 44 is provided with a pointed surface 443, which has an output-side machining mark. If the conductor frame has tie bars that connect terminals adjacent in the y-direction, the tie bars can be cut using a die or similar tool. In this case, machining marks are formed for each terminal on two y-direction-facing side faces. The Fig. 1 to Fig. The semiconductor module A1 shown in Figure 20 is manufactured in the steps described above.

[0122] The semiconductor module A1 is mounted, for example, on a circuit board for control purposes. The metal pins 452 are inserted into the pin holes of the circuit board on which the semiconductor module A1 is mounted and are connected to the terminals near the pin holes. The input terminals 41, 42, and 43 have input-side bonding pads 411, 421, and 431, respectively, which point in one direction (z2 direction) of the z-direction. Each of the output terminals 44 has an output-side bonding pad 441 that points in one direction (z2 direction) of the z-direction. The input-side bonding pads 411, 421, 431, and the output-side bonding pads 441 are connected, for example, with solder to the terminals of the circuit board on which the semiconductor module A1 is mounted.

[0123] The current path from the input terminal 41 to the output terminals 44 in the semiconductor module A1 in the present embodiment is described below. The first main circuit current flows along a path that includes the input terminal 41, the first conductive section 2A, the first semiconductor elements 10A, the first conductive elements 61, the second conductive section 2B, and the output terminals 44. The first main circuit current flows in the x-direction between the second counter electrodes 12 of the first semiconductor elements 10A and the second conductive section 2B via the first conductive elements 61. In the second conductive section 2B, the first main circuit current flows along the x-direction and in a direction slightly deviating from the x-direction between the sections to which the first conductive elements 61 are connected and the output terminals 44.

[0124] The path of a current from the output terminals 44 to the input terminals 42 and 43 is described below. The second main circuit current flows along a path that includes the output terminals 44, the second conductive section 2B, the second semiconductor elements 10B, the second conductive element 62, the input terminal 42, and the input terminal 43. The second conductive element 62, which forms the path of the second main circuit current, has the third wiring section 623 extending in the y-direction, and the first and second wiring sections 621 and 622, respectively, joined to the ends of the third wiring section 623 so that they extend in the x2-direction. Thus, the second main circuit current flows through the third wiring section 623, as well as the first wiring section 621 and the second wiring section 622.Furthermore, the path of the second main circuit current includes the two second band sections 626, which are arranged between the first wiring section 621 and the second wiring section 622 such that they extend in the x-direction, as well as the first band section 625, which is arranged between the first wiring section 621 and the second wiring section 622 such that it extends in the y-direction. Thus, the second main circuit current flows through the first wiring section 621 and the second wiring section 622.

[0125] The second main circuit current flows between the input terminals 42, 43 and the second front electrodes 12 of the second semiconductor elements 10B along a path that includes the first wiring section 621, the second wiring section 622, the third wiring section 623, the two second band sections 626, and the first band section 625 in the second conductive element 62. In the first wiring section 621, the second wiring section 622, and the two second band sections 626, the second main circuit current flows in the x-direction. The direction in which the first main circuit current flows is opposite to the direction in which the second main circuit current flows.

[0126] The direction in which the first main circuit current flows in the first conducting elements 61 is the x-direction, and the direction in which the second main circuit current flows in the first wiring section 621, the second wiring section 622 and the two second band sections 626 in the second conducting element 62 is also the x-direction.

[0127] The following describes the functionality and advantages of the A1 semiconductor module.

[0128] Semiconductor module A1 comprises the conductive substrate 2, input terminals 41 to 43, output terminals 44, and the conductive element 6. The conductive substrate 2 has the first conductive section 2A, to which the first semiconductor elements 10A are bonded, and the second conductive section 2B, to which the second semiconductor elements 10B are bonded. Input terminal 41 is connected to the first conductive section 2A and electrically connected to the first semiconductor elements 10A via the first conductive section 2A. Input terminal 42 and input terminal 43 are electrically connected to the second semiconductor elements 10B via the second conductive element 62 (conductive element 6). Output terminals 44 are connected to the second conductive section 2B and electrically connected to the second semiconductor elements 10B via the second conductive section 2B.The conductive element 6 comprises the first conductive elements 61, which electrically connect the first semiconductor elements 10A and the second conductive section 2B, and the second conductive element 62, which electrically connects the second semiconductor elements 10B and the input terminals 42 and 43. The input terminals 41 to 43 are offset in the x2 direction relative to the conductive substrate 2, and the output terminals 44 are offset in the x1 direction relative to the conductive substrate 2. The two input terminals 42 and 43 are arranged opposite each other, with the input terminal 41 located between them in the y direction. Suppose a semiconductor module has a different configuration than semiconductor module A1, such that there is no input terminal 43 and the input terminals 41 and 42 are arranged next to each other in the y direction.In this case, fluctuations can occur in the current path running from input terminal 41 to output terminals 44 via the first semiconductor elements 10A, as well as in the current path running from output terminals 44 to input terminals 42 via the second semiconductor elements 10B. Therefore, semiconductor module A1 includes the two input terminals 42 and 43, which flank input terminal 41. This reduces fluctuations in the current path running from input terminal 41 to output terminals 44 via the first semiconductor elements 10A, and in the current path running from output terminals 44 to input terminals 42 and 43 via the second semiconductor elements 10B. This reduces the parasitic inductance of semiconductor module A1.In other words, the semiconductor module A1 has a package configuration that preferably contributes to the reduction of parasitic inductance components.

[0129] In the semiconductor module A1, an upper arm current path and a lower arm current path intersect in the top view. The upper arm current path is the current path that runs from the input terminal 41 to the output terminals 44 via the first conductive section 2A, the first semiconductor elements 10A, the first conductive elements 61, and the second conductive section 2B. In the present embodiment, the upper arm current path extends, as shown in Fig. 5, as can be seen, from the side of the x2 direction to the side of the x1 direction. The underarm current path is the current path that runs from the output terminals 44 to the input terminal 42 via the second semiconductor elements 10B and the second conductive element 62. In the present embodiment, the underarm current path extends, as shown in Fig. 5, from the side of the x1 direction to the side of the x2 direction. In this configuration, the magnetic field generated by the current in the upper arm current path and the magnetic field generated by the current in the lower arm current path cancel each other out, thus reducing parasitic inductance components. In particular, the conductive element 6 (each of the first conductive elements 61 and the second conductive element 62) in the semiconductor module A1 is made of a metal plate-like element, so that an area where the upper arm current path and the lower arm current path intersect in the top view can be appropriately provided. In other words, the semiconductor module A1 has a package configuration that preferably contributes to reducing parasitic inductance components.

[0130] In semiconductor module A1, the second conductive element 62, which forms the forearm current path, has the first wiring section 621, the second wiring section 622, the third wiring section 623, and the fourth wiring section 624. The first wiring section 621 and the second wiring section 622 extend in the x-direction and are connected to the input terminal 42 and the input terminal 43, respectively, which are arranged opposite each other, with the input terminal 41 located between them in the y-direction. The third wiring section 623 is joined to the first wiring section 621 and the second wiring section 622, extends in the y-direction, and is connected to the second semiconductor elements 10B. The fourth wiring section 624 is joined with the first wiring section 621 and the second wiring section 622 and overlaps in the top view with the first semiconductor elements 10A.The second conductive element 62, which includes the first wiring section 621, the second wiring section 622, the third wiring section 623, and the fourth wiring section 624, is spaced in the z-direction from the front face 201 (conductive substrate 2) and overlaps a large area of ​​the front face 201 in plan view. This configuration can adequately reduce fluctuations in the current path running from the output terminals 44 to the input terminals 42 and 43 via the second semiconductor elements 10B and is therefore suitable for reducing parasitic inductance components.

[0131] The first semiconductor elements 10A and the second semiconductor elements 10B overlap in the x-direction. This configuration avoids an increase in the y-direction of the conductive substrate 2 (first conductive section 2A and second conductive section 2B) on which the first semiconductor elements 10A and the second semiconductor elements 10B are arranged, and thus allows the size of the semiconductor module A1 to be reduced.

[0132] The fourth wiring section 624 of the second conductive element 62 comprises the first ribbon section 625 and the second ribbon sections 626. The first ribbon section 625 is joined with the first wiring section 621 and the second wiring section 622, extends in the y-direction, and overlaps the first semiconductor elements 10A in plan view. The second ribbon sections 626 are each connected to the first ribbon section 625 and the third wiring section 623 and have a ribbon shape extending in the x-direction in plan view. The second ribbon sections 626 are spaced apart from each other in the y-direction and are substantially parallel to each other.In the top view, one end of each band section 626 is connected to a portion of the first band section 625 located between two adjacent first semiconductor elements 10A in the y-direction, and the other end of each band section 626 is connected to a portion of the third wiring section 623 located between two adjacent second semiconductor elements 10B in the y-direction. With this configuration, the size of the fourth wiring section 624 (second conductive element 62) can be increased in the top view. This is better suited to reducing parasitic inductance components.

[0133] The first strip section 625 has the projecting areas 625a, which project in the z2 direction relative to the other areas. The projecting areas 625a overlap with the first semiconductor elements 10A in the top view. The configuration in which the first strip section 625 has the projecting areas 625a prevents the first strip section 625 from making impermissible contact with the first conductive elements 61, which are connected to the first semiconductor elements 10A.

[0134] In the third wiring section 623, the recessed areas 623a are recessed in the z1 direction relative to the other areas. The recessed areas 623a are connected to the respective second semiconductor elements 10B. In this configuration, the size of the third wiring section 623 (second conductive element 62) can be increased in the top view, and at the same time, the third wiring section 623 (second conductive element 62) and the second semiconductor elements 10B can be electrically connected to each other in a suitable manner.

[0135] The semiconductor module A1 has the conductive element 6 (first conductive element 61 and second conductive element 62) with the configuration described above, as well as the first control terminals 46A to 46E and the second control terminals 47A to 47D for controlling the first semiconductor elements 10A and the second semiconductor elements 10B. The first control terminals 46A to 46E and the second control terminals 47A to 47D are located on the front face 201 of the conductive substrate 2 and extend along the z-direction. The semiconductor module A1 with this configuration can be smaller in plan view and is therefore suitable for reducing the plan view size while simultaneously reducing parasitic inductance components.

[0136] The first control terminals 46A to 46E are supported by the first conductive section 2A and are offset in the x2 direction relative to the first semiconductor elements 10A. The second control terminals 47A to 47D are supported by the second conductive section 2B and are offset in the xl direction relative to the second semiconductor elements 10B. The first control terminals 46A to 46E are spaced apart in the y direction, and the second control terminals 47A to 47D are also spaced apart in the y direction. Thus, the first control terminals 46A to 46E and the second control terminals 47A to 47D are located in a region corresponding to the first semiconductor elements 10A, which form the upper arm circle, and in a region corresponding to the second semiconductor elements 10B, which form the lower arm circle, respectively.The semiconductor module A1 according to this configuration is even better suited for miniaturization while simultaneously reducing parasitic inductance components.

[0137] The first semiconductor elements 10A and the second semiconductor elements 10B each have a first front-side electrode 11 (gate electrode) pointing in the z2 direction. The first control terminal 46A is connected to the first front-side electrodes 11 (gate electrodes) of the first semiconductor elements 10A via the first wires 731a. The second control terminal 47A is connected to the first front-side electrodes 11 (gate electrodes) of the second semiconductor elements 10B via the second wires 731b. This makes it possible to supply a control signal to the first front-side electrodes 11 of the first semiconductor elements 10A (second semiconductor elements 10B), which have a switching function, in a suitable manner via the first control terminal 46A (second control terminal 47A) and the first wires 731a (second wires 731b).

[0138] When the semiconductor module A1 is mounted on a printed circuit board (PCB), the metal pins 452 are inserted into the pin holes of the PCB on which the semiconductor module A1 is mounted and connected to terminals near the pin holes. The input terminals 41, 42, and 43 have input-side bonding pads 411, 421, and 431, respectively, which point in one direction (z2 direction) of the z-direction. The output-side bonding pads 441 of the output terminals 44 are oriented towards the first side (z2 direction) of the z-direction. The input-side bonding pads 411, 421, 431, and the output-side bonding pads 441 are connected, for example, with solder to the terminals of the PCB on which the semiconductor module A1 is mounted.In this configuration, the power system circuit board, to which the input terminals 41 to 43 and the output terminals 44 are connected, and the control system circuit board, to which the metal pins 452 are connected, can be arranged separately in the z-direction. This results in the following improvements. First, the degree of freedom for arranging a signal terminal on the semiconductor module A1 is improved. Second, the degree of freedom regarding the routing and length of a signal wire on the semiconductor module A1 is improved. Third, the degree of freedom for a user to arrange a circuit board is improved when using the semiconductor module A1.

[0139] In semiconductor module A1, the control terminals 45 protrude from the resin front 81 and extend in the z-direction. In a configuration different from semiconductor module A1, the control terminals 45 can be arranged to extend along a plane (xy-plane) perpendicular to the z-direction. With this configuration, there is a limit to the size reduction possible in the top view. Accordingly, the control terminals 45 can be arranged, as in semiconductor module A1, to extend along the z-direction, thus reducing the size of semiconductor module A1 in the top view. In other words, semiconductor module A1 has a package configuration that is advantageous for miniaturization in the top view.

[0140] In the semiconductor module A1 of the present embodiment, the control terminal carrier 5 is provided between the control terminals 45 and the front surface 201 (conductive substrate 2). The control terminal carrier 5 has the insulating layer 51, and the control terminals 45 are supported by the conductive substrate 2 via the control terminal carrier 5. The configuration with the control terminal carrier 5 can support the control terminals 45 on the conductive substrate 2 in a suitable manner while simultaneously isolating them from the conductive substrate 2.

[0141] The control terminal carrier 5 has a layered structure in which the insulating layer 51, the first metal layer 52, and the second metal layer 53 are stacked on top of each other. The control terminals 45 are bonded to the first metal layer 52, which forms the top surface of the control terminal carrier 5, via the conductive bonding element 459. Depending on the configuration, the control terminals 45 can be electrically connected to the control terminal carrier 5 (first metal layer 52), using an existing layered structure (e.g., a DBC substrate) as the control terminal carrier 5.

[0142] Each of the semiconductor elements 10 has a front face 101 oriented in the z2 direction and a back face 102 oriented in the z1 direction. A first front face electrode 11 (gate electrode) is provided on the front face 101. The first front face electrode 11 of each of the semiconductor elements 10 and the first metal layer 52 (first section 521) are connected by an electrically conductive wire 731. This makes it possible to input a control signal for controlling the semiconductor elements 10 with switching function at the first front face electrodes 11 via the control terminals 45, the first metal layer 52, and the wires 731.

[0143] The control ports 45 each have a holder 451 and a metal pin 452. The holder 451 is made of a conductive material and has a tubular section. The metal pin 452 is a rod-shaped element that extends in the z-direction and is pressed into the holder 451. A portion (the top of the flange section at the upper end) of the holder 451 is exposed by the sealing resin 8. In this configuration, the sealing resin 8 is shaped (by casting) such that the holder 451 is covered with the sealing resin 8 except for a portion (the upper end face) of the holder 451, leaving the upper end face exposed. This allows the metal pin 452 to be inserted into the holder 451 after the sealing resin 8 has been shaped.Accordingly, with the configuration in which the control terminals 45 have the holders 451 and the metal pins 452, it is possible to avoid the complex shape of mold 91 for a forming process. For this reason, this configuration is suitable for the efficient manufacture of the semiconductor module A1.

[0144] The semiconductor module A1 of the present embodiment contains the resin elements 87, which are bonded to the sealing resin 8. The resin elements 87 cover portions (upper surfaces of the flange sections at the top end) of the holders 451 that are exposed by the sealing resin 8, as well as portions of the metal pins 452. This prevents foreign matter from entering the connection sections between the holders 451 and the metal pins 452. The semiconductor module A1 with the configuration described above is preferred with regard to durability and reliability.

[0145] The sealing resin 8 has secondary projections 852 that protrude from the resin face 81. These secondary projections 852 surround the respective control terminals 45 in plan view. The metal pins 452 of the control terminals 45 protrude from the secondary projections 852. The resin elements 87 are attached to the secondary projections 852. In this configuration, the creepage distance between adjacent control terminals 45 along the resin face 81 can be increased. This is advantageous for increasing the tensile strength (withstanding stress) of the adjacent control terminals 45.

[0146] The conductive substrate 2 has a first conductive section 2A and a second conductive section 2B, spaced apart in the x-direction. The first conductive section 2A is offset in the x2-direction relative to the second conductive section 2B. The semiconductor elements 10 have first semiconductor elements 10A connected to the first conductive section 2A and second semiconductor elements 10B connected to the second conductive section 2B. The control terminals 45 include first control terminals 46A to 46E and second control terminals 47A to 47D. First control terminals 46A to 46E are supported by the first conductive section 2A and are arranged in the x-direction between the first semiconductor elements 10A and the input terminals 41, 42, etc. The second control terminals 47A to 47D are arranged between the second semiconductor elements 10B and the output terminals 44 in the x-direction.In this configuration, the control terminals 45 (the first control terminals 46A to 46E and the second control terminals 47A to 47D) are conveniently arranged in a region corresponding to the first semiconductor elements 10A that form the upper arm circle and in a region corresponding to the second semiconductor elements 10B that form the lower arm circle. This configuration is advantageous for miniaturizing the semiconductor module A1.

[0147] The sealing resin 8 has first projections 851 that protrude from the resin front surface 81. The tip end of each of the first projections 851 is provided with a first projecting end surface 851a. The first projecting end surfaces 851a of the first projections 851 are substantially parallel to the resin front surface 81 and lie in the same plane (xy-plane). With this configuration, it is possible to provide a predetermined gap between the surface of a control board on which the semiconductor module A1 is mounted and the resin front surface 81 in a device that uses a power supply generated by the semiconductor module A1. In this way, the functional components do not come into impermissible contact with the sealing resin 8 even when they are mounted on a surface of the control board facing the semiconductor module A1.

[0148] The semiconductor module A1 comprises the conductive substrate 2 to which the semiconductor elements 10 are bonded. In this configuration, the heat generated by the excitation of the semiconductor elements 10 is transferred from the semiconductor elements 10 to the conductive substrate 2 and diffused to it. The semiconductor module A1 thus has a package configuration that preferably serves to improve the heat dissipation of the semiconductor elements 10.

[0149] In semiconductor module A1, the conductive substrate 2 and the support substrate 3 are connected via the first conductive bonding element 71. The first conductive bonding element 71 has a first layer 712 and a second layer 713. The first layer 712 is bonded to the conductive substrate 2 by solid-state diffusion of metal and is in direct contact with the conductive substrate 2 at the bonding interface. The second layer 713 is bonded to the support substrate 3 by solid-state diffusion of metal and is in direct contact with the support substrate 3 at the bonding interface. This configuration can increase the bond strength (connection strength) between the conductive substrate 2 and the support substrate 3 compared to the case where the conductive substrate 2 and the support substrate 3 are bonded by a bonding material such as solder.Accordingly, the semiconductor module A1 has a housing configuration that preferably prevents detachment between the conductive substrate 2 and the support substrate 3.

[0150] In semiconductor module A1, the semiconductor elements 10 and the conductive substrate 2 are connected to each other via the second conductive bonding element 72. The second conductive bonding element 72 has a third layer 722 and a fourth layer 723. The third layer 722 is bonded to the semiconductor elements 10 (backside electrodes 15) by solid-state diffusion of metal and is in direct contact with the semiconductor elements 10 at the bonding interface. The fourth layer 723 is bonded to the conductive substrate 2 by solid-state diffusion of metal and is in direct contact with the conductive substrate 2 at the bonding interface. This configuration can increase the bond strength between the semiconductor elements 10 and the conductive substrate 2 compared to the case where the semiconductor elements 10 and the conductive substrate 2 are connected by a bonding material such as solder.Accordingly, the semiconductor module A1 has a housing configuration that preferably prevents detachment between the semiconductor elements 10 and the conductive substrate 2.

[0151] In the semiconductor module A1 of the present embodiment, the elastic modulus (Young's modulus) of the first base layer 711 in the first conductive bonding element 71 is smaller than the elastic modulus (Young's modulus) of the material of the first layer 712 and the second layer 713. When the first conductive bonding element 71 is bonded to the conductive substrate 2 and the support substrate 3 by solid-phase diffusion, mechanical stress is mitigated by the relatively soft first base layer 711, and the bonding interface (connection transition section) is thereby smoothed. This results in a stronger bond between the first layer 712 and the conductive substrate 2, as well as between the second layer 713 and the support substrate 3, by solid-phase diffusion.

[0152] In the present embodiment, the first base layer 711 is thicker than the first layer 712 and the second layer 713. Accordingly, during bonding by solid-state diffusion, the compressive force acting on the interface between the first layer 712 and the conductive substrate 2 (backside bonding layer 23) and on the interface between the second layer 713 and the support substrate 3 (first bonding layer 321) is more uniform. As a result, the first layer 712 and the conductive substrate 2, as well as the second layer 713 and the support substrate 3, can be brought into a more conductive bonding state.

[0153] The material of the first layer 712 and the second layer 713 each contains silver. This composition suppresses oxidation of the first layer 712 and the second layer 713 during solid-phase diffusion bonding with the first conductive bonding element 71, thus enabling excellent solid-phase diffusion bonding. The backside bonding layer 23 and the first bonding layer 321, which are bonded to the first layer 712 and the second layer 713 respectively, also contain silver, thereby enabling improved solid-phase diffusion bonding.

[0154] In the present embodiment, the elastic modulus (Young's modulus) of the second base layer 721 in the second conductive connecting element 72 is smaller than the elastic modulus (Young's modulus) of the material of the third layer 722 and the fourth layer 723. When the second conductive connecting element 72 is connected to the semiconductor elements 10 (backside electrodes 15) and the conductive substrate 2 by solid-phase diffusion, the stress is reduced by the relatively soft second base layer 721, and the connection interface is thereby smoothed. This results in a stronger bond between the third layer 722 and the semiconductor elements 10 (backside electrodes 15), as well as between the fourth layer 723 and the conductive substrate 2, by solid-phase diffusion.

[0155] In the present embodiment, the second base layer 721 is thicker than the third layer 722 and the fourth layer 723. Accordingly, during bonding by solid-phase diffusion, the compressive force acting on the interface between the third layer 722 and the semiconductor elements 10 (backside electrode 15) and on the interface between the fourth layer 723 and the conductive substrate 2 (frontside bonding layers 22) is more uniform. This allows the third layer 722 and the semiconductor elements 10 (backside electrodes 15), as well as the fourth layer 723 and the conductive substrate 2, to be brought into a more conductive bonding state.

[0156] The material of the third layer 722 and the fourth layer 723 each contains silver. This composition suppresses oxidation of the third layer 722 and the fourth layer 723 during solid-phase diffusion bonding with the second conductive bonding element 72, thus enabling excellent solid-phase diffusion bonding. The backside electrode 15 and the frontside bonding layers 22, which are bonded to the third layer 722 and the fourth layer 723 respectively, also contain silver, further enhancing solid-phase diffusion bonding.

[0157] The first conductive bonding element 71 has a configuration in which the first layer 712 and the second layer 713, which are Ag coating layers, are formed on the surfaces (both surfaces) of the first base layer 711, which is made of an Al-containing layer material. Similarly, the second conductive bonding element 72 has a configuration in which the third layer 722 and the fourth layer 723, which are Ag coating layers, are formed on the surfaces (both surfaces) of the second base layer 721, which is made of an Al-containing layer material. With this configuration, the first conductive bonding element 71 and the second conductive bonding element 72 can be easily prepared.

[0158] In semiconductor module A1, the second conductive element 62 is formed with openings 63. In plan view, the openings 63 overlap with the front face 201 (conductive substrate 2) and do not overlap with the semiconductor elements 10. This configuration allows the pressure pins 911 of mold 91 to be inserted into the openings 63 during a forming step (the sealing resin formation step 8) in the semiconductor module A1 manufacturing process. This enables the pressure pins 911 to press the conductive substrate 2 without affecting the second conductive element 62, thus preventing deformation of the support substrate 3 to which the conductive substrate 2 is bonded. Such deformation would, for example, cause the outer surfaces of the support substrate 3 to be positioned higher in the y-direction than its center in the y-direction.If the support substrate 3 warps, the bond strength between the conductive substrate 2 and the support substrate 3 can be reduced. Furthermore, during the molding process, some of the sealing resin 8 may form on the base surface 302 due to resin leakage, leading to bond failure of any heat-dissipating element (e.g., a heat sink) that may be bonded to the base surface 302. Accordingly, the semiconductor module A1 has a housing configuration that preferably improves the bond strength between the conductive substrate 2 and the support substrate 3 by suppressing deformation of the support substrate 3, and also preferably prevents the sealing resin 8 from leaking out at an unintended location.

[0159] The conductive substrate 2 has a first conductive section 2A, to which the first semiconductor elements 10A are bonded, and a second conductive section 2B, to which the second semiconductor elements 10B are bonded. The first conductive section 2A and the second conductive section 2B are spaced apart in the x-direction, and the first conductive section 2A is offset in the x2-direction relative to the second conductive section 2B. The second conductive element 62 is connected to the second semiconductor elements 10B and the input terminals 42 and 43, and the openings 63 in the second conductive element 62 overlap with the front face 201 of the first conductive section 2A in the top view.In this configuration, the pressure pins 911 of the mold 91 can press the conductive substrate 2 without being obstructed by the second conductive element 62 during the formation (during the molding process) of the sealing resin 8, even if the second conductive element 62 is large in plan view. The parasitic resistance components of the second conductive element 62 (conducting element 6), which forms the path of the main circuit current, can preferably be suppressed by enlarging the second conductive element 62 in plan view.

[0160] The second conductive element 62 comprises the first wiring section 621, the second wiring section 622, the third wiring section 623, and the fourth wiring section 624. The first wiring section 621 and the second wiring section 622 extend in the x-direction and are connected to the input terminal 42 and the input terminal 43, respectively, which are arranged opposite each other, with the input terminal 41 located between them in the y-direction. The third wiring section 623 is joined to the first wiring section 621 and the second wiring section 622, extends in the y-direction, and is connected to the second semiconductor elements 10B. The openings 63 are formed in the regions of the first wiring section 621 and the second wiring section 622 that are offset in the x2-direction.The openings 63 are located near two corners of the conductive substrate 2 (first conductive section 2A) on the respective outer surfaces of the conductive substrate 2 in the y-direction. Similarly, the openings 63 are located near two corners of the support substrate 3, which carries the conductive substrate 2 (first conductive section 2A), on the respective outer surfaces of the support substrate 3 in the y-direction. Due to the configuration described above, the second conductive element 62 can be relatively large in plan view, and during the formation of the sealing resin 8 (molding process), areas near the two corners of the conductive substrate 2 (first conductive section 2A) on the respective outer surfaces of the conductive substrate 2 in the y-direction can be pressed together with the pressure pins 911 of the mold 91 inserted into the openings 63.As described above, the deformation of the support substrate 3, to which the conductive substrate 2 is bonded, occurs such that the outer surfaces of the support substrate 3 are positioned higher in the y-direction than its center in the y-direction. However, the configuration described above can effectively suppress the deformation of the support substrate 3 during the forming process.

[0161] In the present embodiment, the conductive element 6 (the first conductive element 61 and the second conductive element 62) is a metal plate-like element. This facilitates the formation of the openings 63 in the second conductive element 62. Furthermore, the conductive element 6 (first conductive element 61 and second conductive element 62), being a metal plate-like element, can be easily adapted to various shapes and sizes and increases the reliability of a bonding section with another component by ensuring a sufficient bonding area (bonding surface) with the other component.

[0162] Parts of the front surface 201 of the conductive substrate 2 (first conductive section 2A) overlap with the openings 63 in plan view and are provided with the recessed sections 201a. The recessed sections 201a are markings left by the pressure pins 911, which exert a pressing force on the front surface 201 during the forming process. In the present embodiment, it is possible to arrange the second conductive element 62 and the openings 63 formed therein such that, during the forming process, corresponding parts of the conductive substrate 2 (first conductive section 2A) can be pressed together with the pressure pins 911 without impairing functional elements such as the semiconductor elements 10.

[0163] The sealing resin 8 is shaped such that the resin cavities 86 extend from the resin face 81 to the recessed sections 201a. Each resin cavity 86 is tapered such that its cross-sectional area decreases from the resin face 81 to the recessed section 201a. The resin cavities 86 are formed during the molding process (when the sealing resin 8 is shaped). After casting, the surfaces of the recessed sections 201a in the front face 201 of the conductive substrate 2 are exposed by the sealing resin 8. In the present embodiment, resin-filling sections 88 are provided for the resin cavities 86 to fill them. This configuration prevents foreign matter (such as moisture) from penetrating the recessed sections 201a exposed by the sealing resin 8. The semiconductor module A1 with the configuration described above is preferred in terms of durability and reliability.

[0164] In the present embodiment, the openings 63 in the second conductive element 62 (conducting element 6) are through holes that penetrate in the z-direction. This configuration can prevent a deflection of the current path caused by the formation of the openings 63 in the second conductive element 62 (conducting element 6), which forms the path of a main circuit current.

[0165] Semiconductor module A1 contains conductive element 6. Conductive element 6 forms the path of a main circuit current switched through semiconductor elements 10. Conductive element 6 has first conductive elements 61, which are connected to the first semiconductor elements 10A, and a second conductive element 62, which is connected to the second semiconductor elements 10B. Conductive element 6 (first conductive element 61 and second conductive element 62) is a metal plate-like element. The main circuit current described above can assume a relatively high value. In this case, it is advantageous to suppress the parasitic resistance components in conductive element 6, which forms the path of the main circuit current, in order to reduce the power consumption of semiconductor module A1.Accordingly, in semiconductor module A1, as described above, the conductive element 6 is a metal plate-like element instead of a bond wire in order to suppress the parasitic resistance components of the conductive element 6. In other words, semiconductor module A1 has a package configuration that is preferably designed to suppress the parasitic resistance components.

[0166] In semiconductor module A1, each of the first semiconductor elements 10A has a rectangular shape in plan view, and the four corners of each of the first semiconductor elements 10A in plan view do not overlap with the second conductive element 62. With this configuration, it is possible to perform a visual inspection during the manufacturing process of semiconductor module A1 before the sealing resin 8 is formed, in order to check whether the first semiconductor elements 10A are properly bonded. In other words, semiconductor module A1 allows for visual control of the bonding condition of the first semiconductor elements 10A during the manufacturing process (e.g., in the step described in the diagram). Fig. (Step 23 shown). In this way, it can be determined whether the first semiconductor elements 10A are properly bonded. For example, it is possible to measure the respective distances to the four corners of each first semiconductor element 10A using a laser distance measurement method and determine that the first semiconductor element 10A is properly bonded if there is a small difference between the distances to the four corners. As described above, the semiconductor module A1 can be visually inspected during the manufacturing process and therefore has a package configuration that contributes to improved reliability. For visual inspection, it is sufficient if at least three of the four corners of each of the first semiconductor elements 10A are visible in the top view. For this reason, it is sufficient if three corners of the first semiconductor elements 10A each do not overlap with the second conductive element 62. Similarly, overlap as shown in Fig. Figure 5 shows that four corners of each of the second semiconductor elements 10B are not bonded to the second conductive element 62. Accordingly, it is possible to perform a visual inspection during the manufacturing process of the semiconductor module A1, before the sealing resin 8 is formed, to check that the second semiconductor elements 10B are properly bonded. This visual inspection can be automated, employing image acquisition and image processing.

[0167] The second conductive element 62 comprises the first wiring section 621, the second wiring section 622, the third wiring section 623, and the fourth wiring section 624. The first wiring section 621 and the second wiring section 622 extend in the x-direction and are connected to the input terminal 42 and the input terminal 43, respectively, which are arranged opposite each other, with the input terminal 41 located between them in the y-direction. The third wiring section 623 is joined with the first wiring section 621 and the second wiring section 622, extends in the y-direction, and is connected to the second semiconductor elements 10B. The fourth wiring section 624 is joined with the first wiring section 621 and the second wiring section 622.The fourth wiring section 624 is offset in the x2 direction relative to the third wiring section 623 and overlaps with the first semiconductor elements 10A in the top view. The second conductive element 62, which includes the first wiring section 621, the second wiring section 622, the third wiring section 623, and the fourth wiring section 624, overlaps a large area of ​​the front face 201 in the top view and is relatively large in the top view. Increasing the size of the second conductive element 62 in the top view is advantageous for suppressing the parasitic resistance components of the second conductive element 62 (conducting element 6), which forms the path of the main circuit current.

[0168] Each of the first semiconductor elements 10A has, in plan view, a first side 191, a second side 192, a third side 193, and a fourth side 194. The first side 191 and the second side 192 extend in the y-direction. The first side 191 is an edge that lies in the x2-direction in plan view, and the second side 192 is an edge that lies in the xl-direction in plan view. The third side 193 and the fourth side 194 extend in the x-direction. The third side 193 is an edge that lies in the y2-direction in plan view, and the fourth side 194 is an edge that lies in the y1-direction in plan view. Since each of the first semiconductor elements 10A has a rectangular shape in plan view, the four corners formed by the first side 191, the second side 192, the third side 193 and the fourth side 194 are generally right angles in plan view.The fourth wiring section 624 (the first ribbon section 625) of the second conducting element 62 has a first edge 627 and a second edge 628. The first edge 627 is an edge of the fourth wiring section 624 that lies in the x2 direction and is offset in the xl direction relative to the first side 191 in the plan view. The first edge 627 extends at least from the third side 193 to the fourth side 194 in the y direction. Therefore, two corners 171 and 172 of each first semiconductor element 10A do not overlap with the second conducting element 62 in the x2 direction in the plan view. The second edge 628 is an edge of the fourth wiring section 624 (first ribbon section 625) that lies in the xl direction and is offset in the x2 direction relative to the second side 192 in the plan view. The second edge 628 extends at least from the third side 193 to the fourth side 194 in the y-direction.Therefore, two corners 173 and 174 of each first semiconductor element 10A in the xl direction do not overlap with the second conductive element 62 in the top view. In this configuration, the four corners of each of the first semiconductor elements 10A do not overlap with the second conductive element 62 in the top view, while the size of the second conductive element 62 in the top view is increased by providing the fourth wiring section 624 with areas that overlap with the first semiconductor elements 10A in the top view. This makes it possible to effectively suppress the parasitic resistance components of the second conductive element 62 (conducting element 6) and to perform a visual inspection to verify the bonding condition of the first semiconductor elements 10A during the manufacturing process of the semiconductor module A1.

[0169] The fourth wiring section 624 (first strip section 625) has the projecting areas 625a, which project in the z2 direction relative to the other areas. The projecting areas 625a overlap with the first semiconductor elements 10A in the top view. According to the configuration in which the fourth wiring section 624 has the projecting areas 625a, the fourth wiring section 624 is prevented from making an impermissible contact with the first conductive elements 61, which are connected to the first semiconductor elements 10A.

[0170] In the third wiring section 623, the recessed areas 623a are recessed in the z1 direction relative to the other areas. The recessed areas 623a are connected to the respective second semiconductor elements 10B. In this configuration, the size of the third wiring section 623 (second conductive element 62) can be increased in the top view, and at the same time, the third wiring section 623 (second conductive element 62) and the second semiconductor elements 10B can be electrically connected to each other in a suitable manner.

[0171] The first semiconductor elements 10A and the second semiconductor elements 10B overlap in the x-direction. This configuration avoids an increase in the y-direction of the conductive substrate 2 (first conductive section 2A and second conductive section 2B) on which the first semiconductor elements 10A and the second semiconductor elements 10B are arranged, and thus allows the size of the semiconductor module A1 to be reduced.

[0172] The semiconductor module A1 comprises the conductive substrate 2, the two input terminals 41, 42 (or the two input terminals 41, 43), the output terminals 44, and the conductive element 6. The conductive substrate 2 has the first conductive section 2A and the second conductive section 2B, which are aligned in the x-direction in the top view. The first semiconductor elements 10A are electrically connected to the first conductive section 2A. The second semiconductor elements 10B are electrically connected to the second conductive section 2B. The first semiconductor elements 10A and the second semiconductor elements 10B are spaced apart in the y-direction. The two input terminals 41, 42 (or the two input terminals 41, 43) are offset in the x2 direction relative to the first conductive section 2A. The input terminal 41 is a positive electrode connected to the first conductive section 2A.The input terminal 42 (or input terminal 43) is a negative electrode. The output terminals 44 are offset in the xl direction relative to the second conductive section 2B. The conductive element 6 has the first conductive elements 61, which are connected to the first semiconductor elements 10A and the second conductive section 2B, and the second conductive element 62, which is connected to the second semiconductor elements 10B and the input terminal 42 (or input terminal 43). According to this configuration, the path of the main circuit current switched by the semiconductor elements 10 (the first semiconductor elements 10A and the second semiconductor elements 10B) runs along the x-direction in the top view, and the axis of symmetry (see auxiliary line L1 in ). Fig. 5) In the planar structure of the semiconductor module A1, the axis of symmetry runs along the y-direction in the top view. In other words, the axis of symmetry and the path of the main circuit current are perpendicular to each other. This reduces the difference in the current path to the first semiconductor elements 10A and the second semiconductor elements 10B with respect to the main circuit current supplied by the two input terminals 41, 42 (or the two input terminals 41, 43) and output by the output terminals 44. This makes it possible to suppress fluctuations in the parasitic inductance components and current fluctuations in the semiconductor module A1. Accordingly, the semiconductor module A1 has a package configuration that preferably serves to balance the parasitic inductance components in the path of the main circuit current and to equalize the current to the semiconductor elements 10.

[0173] The first semiconductor elements 10A and the second semiconductor elements 10B are spaced apart in the x-direction. The first semiconductor elements 10A and the second semiconductor elements 10B are aligned along the y-direction. Accordingly, the direction in which the semiconductor elements 10 are aligned is perpendicular to the direction in which the first main circuit current or the second main circuit current flows. In this way, when several circuit elements are connected in parallel, as in the present embodiment, the difference in the length of the path of the first main circuit current between the first three semiconductor elements 10A can be reduced. In this way, the parasitic resistance components in the conductive element 6, which forms the path of the main circuit current, can be suppressed.

[0174] The region in which the first main circuit current flows and the region in which the second main circuit current flows overlap in plan view. In other words, the second conductive element 62, which connects the output terminals 44 to the input terminals 42, 43 (negative electrode terminals) for the second main circuit current, is located above the region of the first main circuit current (the first conductive section 2A, the first conductive elements 61, and the second conductive section 2B). The direction in which the first main circuit current flows is opposite to the direction in which the second main circuit current flows. In the arrangement described above, the magnetic field generated by the first main circuit current and the magnetic field generated by the second main circuit current cancel each other out, thus reducing the inductance.

[0175] The semiconductor module A1 of the present embodiment has two input terminals 42 and 43. The input terminals 42 and 43 are negative electrodes and flank the input terminal 41 in the y-direction. The two input terminals 42 and 43 are connected to the second conductive element 62. This configuration can further reduce fluctuations in the path of a current flowing from the output terminals 44 to the input terminals 42 and 43 via the second semiconductor elements 10B and the second conductive element 62.

[0176] In semiconductor module A1, the second conductive element 62 comprises the first wiring section 621, the second wiring section 622, the third wiring section 623, and the fourth wiring section 624. The first wiring section 621 and the second wiring section 622 extend in the x-direction and are connected to the input terminal 42 and the input terminal 43, respectively, which are arranged opposite each other, with the input terminal 41 located between them in the y-direction. The third wiring section 623 is joined to the first wiring section 621 and the second wiring section 622, extends in the y-direction, and is connected to the second semiconductor elements 10B.The fourth wiring section 624 is offset in the x2 direction relative to the third wiring section 623 and is connected to the first wiring section 621, the second wiring section 622, and the third wiring section 623. The second conductive element 62, which includes the first wiring section 621, the second wiring section 622, the third wiring section 623, and the fourth wiring section 624, overlaps a large area of ​​the front face 201 in plan view and is relatively large in plan view. This configuration can suitably reduce variations in the path of a current flowing from the output terminals 44 to the input terminals 42 and 43 via the second semiconductor elements 10B and the second conductive element 62.Accordingly, the semiconductor module A1 of the present embodiment is better suited to compensate for the parasitic inductance components in the path of the main circuit current (second conducting element 62) and to balance the amount of current to the semiconductor elements 10B.

[0177] The fourth wiring section 624 is joined with the first wiring section 621 and the second wiring section 622 and overlaps with the first semiconductor elements 10A in plan view. The fourth wiring section 624 (first strip section 625) has the projecting areas 625a, which protrude in the z2 direction relative to the other areas. The projecting areas 625a overlap with the first semiconductor elements 10A in plan view. This configuration increases the size of the fourth wiring section 624 (second conductive element 62) in plan view and prevents the fourth wiring section 624 from having an impermissible contact with the first conductive elements 61, which are bonded to the first semiconductor elements 10A.

[0178] The first semiconductor elements 10A and the second semiconductor elements 10B overlap in the x-direction. This configuration avoids an increase in the y-direction of the conductive substrate 2 (first conductive section 2A and second conductive section 2B) on which the first semiconductor elements 10A and the second semiconductor elements 10B are arranged, and thus allows the size of the semiconductor module A1 to be reduced.

[0179] In the Fig. 30 to Fig. Figure 32 shows a semiconductor module according to a second embodiment. A semiconductor module A2 of the present embodiment differs from the semiconductor module A1 of the first embodiment in the configuration of the sealing resin 8.

[0180] In the present embodiment, the sealing resin 8 does not contain any second projections 852. As in Fig. As shown in Figure 32, the resin front face 81 of the sealing resin 8 is flush with the top surface of the flange section at the upper end of each of the holders 451. Therefore, a portion (the top surface of the flange section at the upper end) of each holder 451 is exposed by the sealing resin 8. A plastic element 87 is provided on the upper surface of the flange section at the upper end of each holder 451 and on a region of the resin front face 81 that surrounds the upper surface of the upper flange section of the holder 451. The resin elements 87 cover portions of the control connections 45, i.e., portions (top surfaces of the flange sections at the upper end) of the holders 451 that are exposed by the sealing resin 8, and portions of the metal pins 452.

[0181] The semiconductor module A2 of the present embodiment has the same advantages as the semiconductor module A1 of the first embodiment.

[0182] In the Fig. 33 to Fig. Figure 35 shows a semiconductor module according to a third embodiment. A semiconductor module A3 of the present embodiment differs from the semiconductor module A2 of the second embodiment by the configurations of the resin elements 87.

[0183] In the present embodiment, the sealing resin 8 does not include any second projections 852, and the resin front face 81 of the sealing resin 8 is flush with the top surface of the flange section at the upper end of each holder 451, as shown in Fig. 35 shown. This exposes part (the top of the flange section at the upper end) of each holder 451 from the sealing resin 8, as in the case of the one shown in Fig. 32 of the semiconductor module A2 shown. On the other hand, in the present embodiment, a resin element 87 is provided on the upper surfaces of the flange sections at the upper end of the holders 451 in the second control terminals 47A to 47D and on the associated areas of the resin front surface 81. Furthermore, another resin element 87 is provided on the upper surfaces of the flange sections at the upper end of the holders 451 at the first control terminals 46A to 46E and on the associated areas of the resin front surface 81. In the semiconductor module A2 (see Fig. 32) The plurality of resin elements 87 are provided in accordance with the holders 451 of the control ports 45. In the present embodiment, however, a single resin element 87 is provided in accordance with the first control ports 46A to 46E, and another single resin element 87 is provided in accordance with the second control ports 47A to 47D. At the first control ports 46A to 46E, the single resin element 87 covers parts (the top surfaces of the flange sections at the upper end) of the holders 451 that are exposed by the sealing resin 8 and also covers parts of the metal pins 452. At the second control ports 47A to 47D, the other single resin element 87 covers parts (the top surfaces of the flange sections at the upper end) of the holders 451 that are exposed by the sealing resin 8 and also covers parts of the metal pins 452.

[0184] The semiconductor module A3 of the present embodiment has the same advantages as the semiconductor module A1 of the first embodiment.

[0185] Fig. 36 and Fig. Figure 37 shows a semiconductor module according to a fourth embodiment. A semiconductor module A4 of the present embodiment differs from the semiconductor module A1 of the first embodiment in the configuration of the metal pin 452 of each of the control terminals 45.

[0186] In the present embodiment, the metal pin 452 of each of the control terminals 45 (first control terminals 46A to 46E and second control terminals 47A to 47D) has a cushioning element 452a. The cushioning element 452a absorbs a shock caused by vibrations and is exposed by the sealing resin 8. In the Fig. 36 and Fig. In the example shown in Figure 37, the cushioning element 452a is provided at a position of the metal pin 452 which is located in a longitudinal direction of the metal pin 452 near the resin element 87, and is configured as an essentially U-shaped bent element in a plane including the z-direction.

[0187] The semiconductor module A4 of the present embodiment also has the same advantages as the semiconductor module A1 of the first embodiment. In semiconductor module A4, each of the metal pins 452 (each of the control terminals 45) has a cushioning element 452a. Even if semiconductor module A4 is intended for an electronic device (e.g., a vehicle) that can generate relatively strong vibrations, the cushioning elements 452a absorb the shocks caused by the vibrations and thus prevent damage to the metal pins 452 (control terminals 45). It should be noted that each of the cushioning elements 452a is not limited to the specific configuration shown in the figure. Instead, each of the cushioning elements 452a can be an L-shaped element provided on the middle part of a metal pin 452.

[0188] Fig. 38 to Fig. Figure 40 shows a semiconductor module according to a fifth embodiment. A semiconductor module A5 of the present embodiment differs from the semiconductor module A1 of the first embodiment in the configuration of the second conductive element 62.

[0189] The present embodiment differs from the first embodiment in the area occupied by the fourth wiring section 624 of the second conductive element 62. In particular, the dimension of the first band section 625 in the x-direction is larger than that of the semiconductor module A1. As shown in the Fig. 39 and Fig. As shown in Figure 40, the second edge 628 of the first band section 625 is offset in the xl direction compared to the second edge 628 of the semiconductor module A1. As shown in Fig. As shown in Figure 40, the second edge 628 in the top view is offset in the xl-direction relative to the second sides 192 of the first semiconductor elements 10A. Thus, two corners of each first semiconductor element 10A overlap in the xl-direction with the second conductive element 62 (first band section 625) in the top view.

[0190] The semiconductor module A5 of the present embodiment has the same advantages as the semiconductor module A1 of the first embodiment. In addition, in semiconductor module A5, the first band section 625 (second conductive element 62) of the fourth wiring section 624 can be larger in the top view. This is better suited to reducing parasitic inductance components.

[0191] In the Fig. 41 and Fig. Figure 42 shows a semiconductor module according to a sixth embodiment. A semiconductor module A6 of the present embodiment differs from the semiconductor module A1 of the first embodiment mainly in the configuration of the second conductive element 62.

[0192] Unlike the first embodiment, the second conductive element 62 of the semiconductor module A6 does not have openings 63. The mold 91, which is used in the manufacture of the semiconductor module A6 for shaping the sealing resin 8 (by casting), is not provided with the pressure pins 911. Accordingly, as in Fig.As shown in Figure 42, the sealing resin 8 is not formed with the resin cavities 86, and the front face 201 of the conductive substrate 2 (first conductive section 2A and second conductive section 2B) is not formed with the recessed sections 201a. Since the sealing resin 8 is not formed with the resin cavities 86, the semiconductor module A6 of the present embodiment does not have resin-filling sections 88, which are used to fill the resin cavities 86 in the first embodiment.

[0193] The semiconductor module A6 of the present embodiment has the same advantages as the semiconductor module A1 of the first embodiment.

[0194] The semiconductor module according to the present disclosure is not limited to the embodiments mentioned above. Various modifications can be made to the specific configurations of the elements of the semiconductor module according to the present disclosure.

[0195] The present disclosure also includes the configurations defined in the following sections. Clause 1.

[0196] A semiconductor module comprising: a conductive substrate with a front side facing a first side of a thickness direction, and with a back side facing away from the front side in the thickness direction; at least one semiconductor element that is electrically bonded to the front side and has a switching function; at least one control terminal for controlling the at least one semiconductor element; and a sealing resin having a resin front facing the same side as the front and a resin back facing a side opposite the resin front, wherein the sealing resin covers the conductive substrate covering at least one semiconductor element and part of the at least one control terminal, the control connection protrudes from the front of the resin and extends along the thickness direction. Clause 2.

[0197] The semiconductor module according to clause 1, wherein the sealing resin has a resin side surface which is connected to the resin front and the resin back and which is flanked by the resin front and the resin back in the thickness direction, wherein the semiconductor module is provided with at least one power supply terminal that protrudes from the resin side surface, is electrically connected to the semiconductor element and processes a power supply voltage, and wherein the power supply connection has a bonding surface that points to one side of the thickness direction. Clause 3.

[0198] Semiconductor module according to clause 2, wherein the at least one power input terminal has a first power input terminal which receives a first power input voltage and a second power input terminal which outputs a second power input voltage. Clause 4.

[0199] Semiconductor module according to one of clauses 1 to 3, further comprising: a control connector carrier provided between the front face and the control connector and comprising an insulating layer. Clause 5.

[0200] Semiconductor module according to clause 4, wherein the control terminal carrier comprises the insulating layer, a first metal layer stacked on a surface of the insulating layer to one side of the thickness direction, and a second metal layer stacked on another surface of the insulating layer to another side of the thickness direction and bonded to the conductive substrate to be facing the front. Clause 6.

[0201] Semiconductor module according to clause 5, wherein the control terminal is bonded to the first metal layer via a conductive bonding element. Clause 7.

[0202] Semiconductor module according to clause 6, further comprising: a conductive wire, wherein the semiconductor element has an element front facing the same side as the front, an element back facing the element front, and a gate electrode on the element front, and where the conductive wire is connected to the gate electrode and the first metal layer. Clause 8.

[0203] Semiconductor module according to clause 6 or 7, wherein the control terminal has a conductive tubular holder bonded to the first metal layer and a metal pin pressed into the holder and extending in the thickness direction. Clause 9.

[0204] Semiconductor module according to clause 8, wherein part of the holder is exposed to the sealing resin on one side of the thickness direction. Clause 10.

[0205] Semiconductor module according to clause 9, further comprising: a resin element bonded with the sealing resin, the resin element covers part of the holder that is exposed by the sealing resin and part of the metal pin. Clause 11.

[0206] The semiconductor module according to clause 3, wherein the conducting substrate has a first conducting section and a second conducting section spaced apart from each other in a first direction perpendicular to the thickness direction, such that the first conducting section is offset to one side of the first direction and the second conducting section is offset to the other side of the first direction, wherein the at least one first power supply terminal has a first input terminal which is offset to one side of the first direction relative to a first semiconductor element and is connected to the first conductive section, and a second input terminal which is offset to one side of the first direction relative to the first semiconductor element and is connected to a second semiconductor element, wherein the second power input terminal is an output terminal that is offset to the other side of the first direction relative to the second semiconductor element and is connected to the second conductive section, wherein the at least one control terminal has a first control terminal for controlling the first semiconductor element and a second control terminal for controlling the second semiconductor element, wherein the first control terminal is carried by the first conductive section and is provided between the first semiconductor element and both the first input terminal and the second input terminal in the first direction, and wherein the second control terminal is carried by the second conductive section and is provided between the second semiconductor element and the output terminal in the first direction. Clause 12.

[0207] Semiconductor module according to clause 11, further comprising: a plurality of the first semiconductor elements arranged at intervals in a second direction perpendicular to the thickness direction and to the first direction; a multitude of first control connections arranged at intervals in the second direction; a plurality of the second semiconductor elements, arranged at intervals in the second direction; and a multitude of secondary control connections arranged at intervals in the second direction. Clause 13.

[0208] Semiconductor module according to one of clauses 1 to 12, wherein the sealing resin has a plurality of projections, each of which projects from the resin front and has a projecting end face formed at a pointed end thereof, and wherein the projecting end faces of the plurality of projections lie parallel to the resin front and in the same plane as the resin front. Clause 14.

[0209] Semiconductor module according to one of clauses 1 to 13, wherein the at least one control terminal has a cushioning element for absorbing a shock caused by vibrations. Clause 15.

[0210] Semiconductor module according to clause 14, wherein the cushioning element is exposed from the sealing resin. Clause 16.

[0211] A semiconductor module comprising: a conductive substrate with a front side facing a first side of a thickness direction, and with a back side facing away from the front side in the thickness direction; a semiconductor element that is electrically bonded to the front side and has a switching function; a control terminal for controlling the at least one semiconductor element; and a sealing resin having a resin front facing the same side as the front and a resin back facing a side opposite the resin front, wherein the sealing resin covers the conductive substrate covering at least one semiconductor element and part of the at least one control terminal, the control connection protrudes from the front of the resin and extends along the thickness direction. Clause 17.

[0212] Semiconductor module according to clause 16, further comprising: a control terminal carrier provided between the front face and the control terminal and comprising an insulating layer. Clause 18.

[0213] Semiconductor module according to clause 17, wherein the control terminal carrier comprises the insulating layer, a first metal layer stacked on a surface of the insulating layer to one side of the thickness direction, and a second metal layer stacked on another surface of the insulating layer to another side of the thickness direction and connected to the conductive substrate to be facing the front. Clause 19.

[0214] Semiconductor module according to clause 18, wherein the control terminal is connected to the first metal layer via a conductive connecting element. Clause 20.

[0215] Semiconductor module according to clause 19, wherein the semiconductor element has an element front facing the same side as the front, an element back facing the element front, and a gate electrode on the element front, and wherein the gate electrode and the first metal layer are connected by a conductive wire. Clause 21.

[0216] Semiconductor module according to clause 19 or 20, wherein the control terminal has a conductive tubular holder connected to the first metal layer and a metal pin pressed into the holder and extending in the thickness direction. Clause 22.

[0217] Semiconductor module according to clause 21, wherein part of the holder is exposed from one side of the thickness direction by the sealing resin. Clause 23.

[0218] Semiconductor module according to clause 22, further comprising: a resin element bonded with the sealing resin, the resin element covers part of the holder that is exposed by the sealing resin and part of the metal pin. Clause 24.

[0219] Semiconductor module according to one of clauses 16 to 23, wherein the conducting substrate has a first conducting section and a second conducting section spaced apart from each other in the thickness direction, wherein the first conducting section is offset to one side of a first direction perpendicular to the thickness direction, and wherein the second conducting section is offset to the other side of the first direction, and wherein the at least one semiconductor element comprises a first semiconductor element electrically bonded to the first conductive section and a second semiconductor element electrically bonded to the second conductive section, the semiconductor module further features: a first input terminal that is offset to one side of the first direction relative to the first semiconductor element and connected to the first conductive section; a second input terminal that is offset to one side of the first direction relative to the first semiconductor element and is connected to the second semiconductor element; and an output terminal that is offset to the other side of the first direction relative to the second semiconductor element and connected to the second conductive section, wherein the at least one control terminal has a first control terminal for controlling the first semiconductor element and a second control terminal for controlling the second semiconductor element, wherein the first control terminal is carried by the first conductive section and is provided between the first semiconductor element and both the first input terminal and the second input terminal in the first direction, and wherein the second control terminal is carried by the second conductive section and is provided between the second semiconductor element and the output terminal in the first direction. Clause 25.

[0220] Semiconductor module according to clause 24, further comprising: a plurality of the first semiconductor elements arranged at intervals in a second direction perpendicular to the thickness direction and to the first direction; a multitude of first control connections arranged at intervals in the second direction; a plurality of the second semiconductor elements, arranged at intervals in the second direction; and a multitude of secondary control connections arranged at intervals in the second direction. Clause 26.

[0221] Semiconductor module according to one of clauses 16 to 25, wherein the sealing resin has a plurality of projections, each of which projects from the resin front and has a projecting end face formed at a pointed end thereof, and wherein the projecting end faces of the plurality of projections lie parallel to the resin front and in the same plane as the resin front. Clause 27.

[0222] Semiconductor module according to one of clauses 16 to 26, wherein the at least one control terminal has a cushioning element for absorbing a shock caused by vibrations. Clause 28.

[0223] Semiconductor module according to clause 27, wherein the cushioning element is exposed from the sealing resin. Reference symbol list A1, A2, A3, A4, A5, A6 semiconductor module 10 At least one semiconductor element 10A First semiconductor element 10B Second semiconductor element 101 Element front 102 Element back 11 First front electrode (gate electrode) 12 Second front electrode (source electrode) 13 Third front electrode 14 Fourth front electrode 15 Backside electrode (drain electrode) 16 Fifth front electrode 171, 172, 173, 174 Corner 181, 182, 183, 184 Corner 191 First page 192 Second page 193 Third page 194 Fourth page 2 Conductive substrate 2A First conductive section 2B Second Leading Section 201 Front 201a In-depth section 201b Recess edge 202 Back 21 Basic element 22 Front side bonding layer 23 Backside bonding layer 3 Carrier substrate 301 Contact surface 302 floor area 31 Insulation layer 32 First metal layer 32A First Section 32B Second Section 321 First bonding layer 33 Second metal layer 41 First input connection 411 Entrance-side bonding surface 412 Entrance-side side surface 413 Peak area 414 Side surface 42 Second input connection 421 Entrance-side bonding surface 422 Entrance-side side surface 423 Peak area 424 Side surface 43 Third input port 431 Entrance-side bonding surface 432 Entrance-side side surface 433 peak area 434 Side surface 44 Output port 441 Outward-side bonding surface 442 Exit-side side surface 443 peak area 444 Side surface 45 At least one control connection 451 holders 452 Metal pin 452a Upholstery element 459 Conductive bonding element 46A, 46B, 46C, 46D, 46E First control connection 47A, 47B, 47C, 47D Second control connection 5 control connector carriers 51 Insulating layer 52 First metal layer 521 First Section 522 Second Section 523 Third Section 524 Fourth Section 525 Fifth Section 53 Second metal layer 59 Bonding element 6. Conducting element 601 First Section 61 First guiding element 61h opening 62 Second guiding element 62A First Section 62B Second Section 621 First wiring section 622 Second wiring section 623 Third wiring section 623a Recessed area 623h: Opening 624 Fourth wiring section 625 First section of the tape 625a Foreground area 625h opening 626 Second section 627 First Edge 628 Second edge 63 Opening 69 Conductive bonding element 71 First conductive bonding element 711 First Base Layer 712 First Shift 713 Second shift 72 Second conductive bonding element 721 Second base layer 722 Third Shift 723 Fourth Shift 731 wire 731a First wire 731b Second wire 732, 733, 734, 735 wire 8 Sealing resin 81 Resin front 82 Resin back 831, 832 Resin side surface 832a Deepened section 833, 834 Resin side surface 851 First lead 851a First projecting end face 851b Deepened Section 851c Interior wall area 852 Second lead 86 resin cavity 861 Resin cavity edge 87 resin element 88 Resin filling section 91 Form 911 Pushpin QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2015220382 A

[0003]

Claims

[1] A semiconductor module comprising: a conductive substrate with a front side facing a first side of a thickness direction, and with a back side facing away from the front side in the thickness direction; a semiconductor element that is electrically bonded to the front side and has a switching function; a control terminal for controlling the semiconductor element; and a sealing resin having a resin front facing the same side as the front and a resin back facing a side opposite the resin front, wherein the sealing resin covers the conductive substrate, the semiconductor element and part of the control terminal, the control connection protrudes from the front of the resin and extends along the thickness direction. [2] Semiconductor module according to claim 1, wherein the sealing resin has a resin side surface which is connected to the resin front and the resin back and which is flanked by the resin front and the resin back in the thickness direction, wherein the semiconductor module is provided with a power supply connection that protrudes from the resin side surface, is electrically connected to the semiconductor element and processes a power supply voltage, and wherein the power supply connection has a bonding surface that points to one side of the thickness direction. [3] Semiconductor module according to claim 2, wherein the at least one power supply terminal has at least a first power supply terminal which receives a first power supply voltage and a second power supply terminal which outputs a second power supply voltage. [4] Semiconductor module according to one of claims 1 to 3, further comprising: a control terminal carrier which is provided between the front side and the control terminal and which has an insulating layer. [5] Semiconductor module according to claim 4, wherein the control terminal carrier comprises the insulating layer, a first metal layer stacked on a surface of the insulating layer in one direction of the thickness, and a second metal layer stacked on another surface of the insulating layer in another direction of the thickness and bonded to the conductive substrate to face the front. [6] Semiconductor module according to claim 5, wherein the control terminal is bonded to the first metal layer via a conductive bonding element. [7] Semiconductor module according to claim 6, wherein the semiconductor element has an element front facing the same side as the front, an element back facing the element front, and a gate electrode on the element front, and wherein the gate electrode and the first metal layer are connected by a conductive wire. [8] Semiconductor module according to claim 6 or 7, wherein the control terminal has a conductive tubular holder bonded to the first metal layer and a metal pin pressed into the holder and extending in the thickness direction. [9] Semiconductor module according to claim 8, wherein a part of the holder is exposed to the sealing resin on one side of the thickness direction. [10] Semiconductor module according to claim 9, further comprising: a resin element bonded with the sealing resin, wherein the resin element covers a part of the holder exposed by the sealing resin and a part of the metal pin. [11] Semiconductor module according to claim 3, wherein the conducting substrate has a first conducting section and a second conducting section spaced apart from each other in a first direction perpendicular to the thickness direction, such that the first conducting section is offset to one side of the first direction and the second conducting section is offset to the other side of the first direction, wherein the at least one semiconductor element comprises a first semiconductor element electrically bonded to the first conductive section and a second semiconductor element electrically bonded to the second conductive section, wherein the at least one first power supply terminal has a first input terminal which is offset to one side of the first direction relative to the first semiconductor element and is connected to the first conductive section, and a second input terminal which is offset to one side of the first direction relative to the first semiconductor element and is connected to the second semiconductor element, wherein the second power input terminal is an output terminal that is offset to the other side of the first direction relative to the second semiconductor element and is connected to the second conductive section, wherein the at least one control terminal has a first control terminal for controlling the first semiconductor element and a second control terminal for controlling the second semiconductor element, wherein the first control terminal is carried by the first conductive section and is provided between the first semiconductor element and both the first input terminal and the second input terminal in the first direction, and wherein the second control terminal is carried by the second conductive section and is provided between the second semiconductor element and the output terminal in the first direction. [12] Semiconductor module according to claim 11, further comprising: a plurality of the first semiconductor elements arranged at intervals in a second direction perpendicular to the thickness direction and to the first direction; a multitude of first control connections arranged at intervals in the second direction; a plurality of the second semiconductor elements, arranged at intervals in the second direction; and a multitude of secondary control connections arranged at intervals in the second direction. [13] Semiconductor module according to any one of claims 1 to 12, wherein the sealing resin has a plurality of projections, each of which projects from the resin front and has a projecting end face formed at a pointed end thereof, and wherein the projecting end faces of the plurality of projections lie parallel to the resin front and in the same plane as the resin front. [14] Semiconductor module according to any one of claims 1 to 13, wherein the control connector has a cushioning element for absorbing a shock caused by vibrations. [15] Semiconductor module according to claim 14, wherein the cushioning element is exposed from the sealing resin.