Semiconductor device and method for manufacturing the same

Abstract

Semiconductor device (100) comprising: a substrate (104); and a fin field effect transistor, FinFET, (102) on the substrate (104), the FinFET (102) comprising: a fin (110) made of a semiconductor material on the substrate (104), a source (120) in the fin (110), the source (120) having a first conductivity type; a body (124) in the fin (110) adjacent to the source (120), the body (124) having a second conductivity type opposite the first conductivity type; a drain drift region (128) in the fin (110), the drain drift region (128) being adjacent to the body (124) opposite the source (120), the drain drift region (128) having the first conductivity type, the drain drift region (128) being wider than the body (124), and the drain drift region (128) having an enhanced portion (136) of the drain drift region (128), the enhanced portion (136) of the drain drift region (128) having a higher average net dopant concentration of the first conductivity type than a remainder of the drain drift region (128); a first charge equilibrium region (148) in the fin (110) laterally adjacent and contiguous to the enhanced portion (136) of the drain drift region (128), the first charge equilibrium region (148) having the second conductivity type; a second charge equilibrium region (150) in the fin (110) adjacent and contiguous to the enhanced portion (136) of the drain drift region (128), opposite the first charge equilibrium region (148), the second charge equilibrium region (150) having the second conductivity type; a drain contact region (132) in the fin (110) adjacent to the drain drift region (128), opposite the body (124), the drain contact region (132) having the first conductivity type; a gate dielectric layer (166) on the body (124) over a top surface (114) of the fin (110) and extending onto two side surfaces of the body (124); and a gate (170) over the gate dielectric layer (166), the gate (170) extending over the top surface (114) of the fin (110) and extending over the two side surfaces of the body (124).

Description

[0001] This disclosure relates to the field of semiconductor devices. In particular, but not exclusively, this disclosure relates to fin field-effect transistors (FinFETs) in semiconductor devices. BACKGROUND

[0002] Fin field-effect transistors (FinFETs) are a type of field-effect transistor in which the body is contained within a fin of semiconductor material. The gate surrounds the body on at least three sides of the fin. FinFETs are generally used in "low-voltage" circuits, such as logic circuits, where the operating potential at the drains is lower than the breakdown potential of the gate dielectric layer between the gate and the body. Forming FinFETs that can operate with drain potentials above the breakdown potential of the gate dielectric has been challenging. US 2015 / 0 206 975 A1 discloses a FIN-type semiconductor device and a fabrication method. Furthermore, US 2014 / 0 183 629 A1 discloses a semiconductor device comprising a transistor formed in a semiconductor substrate having a first main surface.Furthermore, US 2018 / 0 254 340 A1 relates to structures and methods for a tunnel field-effect transistor (TFET). Furthermore, US 2017 / 0 365 665 A1 discloses that an n-type drift layer is successively epitaxially grown on a front side of an n+-type SiC substrate, which becomes a drain region. - -type, a p-type base layer and an n+-type source layer. SUMMARY

[0003] The present disclosure presents a semiconductor device including an extended-drain FinFET, hereinafter the FinFET. The FinFET includes a drain drift region between a drain contact region of the FinFET and a body of the FinFET. The drain drift region includes an enhanced portion of the drain drift region between the drain contact region and the body. The FinFET further includes a first charge balance region and a second charge balance region laterally adjacent and on opposite sides of the enhanced portion of the drain drift region. The enhanced portion of the drain drift region and the drain contact region have a first conductivity type. The body, the first charge balance region, and the second charge balance region have a second opposite conductivity type. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A to Fig. 1G are perspective and cross-sectional views of a semiconductor device including an extended drain FinFET, illustrated in stages of an exemplary method of formation. Fig. 2A to Fig. 2G are perspective and cross-sectional views of a semiconductor device including an extended drain FinFET, illustrated in stages of another exemplary method of formation. DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

[0004] A semiconductor device includes a FinFET having a fin made of a semiconductor material on a substrate of the semiconductor device. The FinFET includes a drain contact region having a first conductivity type in the fin and a body having a second conductivity type, opposite the first conductivity type, in the fin. The FinFET further includes a drain drift region having the first conductivity type in the fin between the drain contact region and the body. The drain drift region includes an enhanced portion of the drain drift region having the first conductivity type between the drain contact region and the body.The enhanced portion of the drain drift region has a higher average net dopant concentration of the first conductivity type than the rest of the drain drift region, wherein in the enhanced portion of the drain drift region, the average net dopant concentration of the first conductivity type represents an average dopant concentration of the first conductivity type minus an average dopant concentration of the second conductivity type. The terms "dopants of the first conductivity type" and "dopants of the second conductivity type" are to be understood as meaning dopants that provide a first conductivity type and dopants that provide a second conductivity type, respectively, in a semiconductor material.For example, in a case where the first conductivity type is n-type and the second conductivity type is p-type, phosphorus, arsenic, and antimony are dopants of the first conductivity type because they provide n-type conductivity in the semiconductor material, and boron, gallium, and indium are dopants of the second conductivity type because they provide p-type conductivity in the semiconductor material. The FinFET also includes a first charge equilibrium region and a second charge equilibrium region. The first charge equilibrium region is laterally adjacent and contiguous to the enhanced portion of the drain drift region between the body and the drain contact region. The second charge equilibrium region is laterally adjacent and contiguous to the enhanced portion of the drain drift region between the body and the drain contact region, opposite the first charge equilibrium region.The terms "lateral" and "laterally (adverb)" in the examples disclosed herein refer to directions parallel to a top surface of the fin. The first charge equilibrium region and the second charge equilibrium region each have the second conductivity type. The body has a body width that is a maximum lateral dimension of the fin through the body in a direction perpendicular to current flow during operation of the FinFET. The drift region has a drain width that is a maximum lateral dimension of the fin through the drain drift region in a direction perpendicular to current flow during operation of the FinFET. The drain width is greater than the body width. The FinFET may include one or more fins configured in parallel, each having a drain contact region, a body and a drain drift region with an enhanced portion of the drain drift region, and first and second charge equilibrium regions.The improved portion of the drain drift region can advantageously concentrate the current flow between the first charge equilibrium region and the second charge equilibrium region during operation of the FinFET, providing lower resistance for the FinFET. The first charge equilibrium region and the second charge equilibrium region can advantageously enable a higher operating potential applied to the drain contact region compared to a similar FinFET that does not have the charge equilibrium regions.

[0005] It should be noted that terms such as above, above, below, and below may be used in this disclosure. These terms are not to be construed as limiting the position or orientation of any structure or element, but are intended to indicate spatial relationships between structures or elements.

[0006] Fig. 1A to Fig. 1G are perspective and cross-sectional views of a semiconductor device 100 including an extended-drain FinFET 102, hereinafter FinFET 102, illustrated in stages of an exemplary method of formation. Referring to Fig. 1A, the semiconductor device 100 may be implemented, for example, as a discrete semiconductor device, integrated circuit, microelectronic sensor, MEMS (micro-electrical mechanical system) device, electro-optical device, or MOMS (micro-optical mechanical system) device. The semiconductor device 100 is formed on a substrate 104. The substrate 104 may be implemented, for example, as a semiconductor wafer, such as a silicon wafer or silicon-on-insulator (SOI) wafer. Alternatively, the substrate 104 may be implemented as a dielectric substrate, such as a sapphire wafer. The substrate 104 may include regions for additional semiconductor devices (not shown) similar to the semiconductor device 100. In this example, a semiconductor material 106 is disposed on the substrate 104.For example, semiconductor material 106 may primarily be single-crystal silicon with dopants or may be another semiconductor material such as silicon with germanium or silicon with carbon. In versions of this example in which substrate 104 is implemented as a semiconductor wafer, semiconductor material 106 may continue continuously through substrate 104.

[0007] A fin mask 108 is formed over the semiconductor material 106 to cover an area for a first fin 110 of the FinFET 102 and a second fin 112 of the FinFET 102. The fin mask 108 may include a photoresist and an anti-reflective material and is formed by a photolithography process. The fin mask 108 may also include a hard mask material, such as silicon dioxide, patterned by a reactive ion etch (RIE) process.

[0008] The semiconductor material 106 is removed where it was exposed by the fin mask 108, leaving the semiconductor material 106 beneath the fin mask 108 to form the first fin 110 and the second fin 112. The semiconductor material 106 may be removed from the substrate 104 by an RIE process using halogen radicals, such as fluorine radicals. The first fin 110 and the second fin 112 have a top surface 114; the semiconductor material 106 extends to the top surface 114.

[0009] The fin mask 108 is removed after the first fin 110 and the second fin 112 are formed. The photoresist in the fin mask 108 can be removed by a plasma process using oxygen radicals, such as an ashing process, followed by a wet cleaning process using an aqueous solution of ammonium hydroxide and hydrogen peroxide. Alternatively, the photoresist in the fin mask 108 can be removed by a wet etching process using an aqueous mixture of sulfuric acid and hydrogen peroxide, followed by the wet cleaning process of the aqueous solution of ammonium hydroxide and hydrogen peroxide. The hard mask material in the fin mask 108 can be removed by an RIE process or by a buffered aqueous solution of dilute hydrofluoric acid.

[0010] Referring to Fig. 1B, a recess oxide 116 may be formed on the substrate 104 around the first fin 110 and the second fin 112. The recess oxide 116 includes a dielectric material, such as silicon dioxide. The recess oxide 116 may be formed by forming the dielectric material over the substrate, removing the dielectric material over the first fin 110 and the second fin 112, and then recessing the dielectric material under the top surface 114, thereby exposing the first fin 110 and the second fin 112. The first fin 110 extends above the substrate 104 to a fin height 118, which may be, for example, 300 nanometers to 800 nanometers.

[0011] Dopants of the first conductivity type, in this example n-type dopants such as phosphorus, are introduced into the first fin 110 to form a first source 120 and into the second fin 112 to form a second source 122. Dopants of the second conductivity type, in this example p-type dopants such as boron, are introduced into the first fin 110 to form a first body 124 and into the second fin 112 to form a second body 126 in the second fin 112. Dopants of the first conductivity type, such as phosphorus in this example, are introduced into the first fin 110 to form a first drain drift region 128 and into the second fin 112 to form a second drain drift region 130. The first drain drift zone 128 and the second drain drift zone 130 may, for example, have average concentrations of the dopants of the first conductivity type of 1×10 16 cm -3 up to 4×10 16 cm -3to enable operation of the FinFET 102 with a desired drain potential. Dopants of the first conductivity type, such as phosphorus and arsenic in this example, are introduced into the first fin 110 to form a first drain contact region 132, and into the second fin 112 to form a second drain contact region 134. The first drain contact region 132 and the second drain contact region 134 may have average concentrations of the dopants of the first conductivity type above 1×10 19 cm -3 to provide low-resistance connections to the first drain drift zone 128 and the second drain drift zone 130 and to subsequently formed improved portions 136 and 138 of the drain drift zones 128 and 130, which in Fig. 1E. In this example, the first drain contact region 132 and the second drain contact region 134 may continue continuously, as shown in Fig. 1B, which may advantageously provide lower resistance connections to the first drain drift region 128 and the second drain drift region 130 and to the subsequently formed enhanced portions 136 and 138 of the drain drift regions 128 and 130, compared to a similar FinFET with segmented drain contact regions.

[0012] A drain length 140, which represents a lateral dimension between the first body 124 and the first drain contact region 132 along the top surface 114 of the first fin 110 in a direction parallel to the current flow during operation of the FinFET 102, may be selected to enable operation of the FinFET 102 with the desired drain potential. The drain length 140 may, for example, be 200 nanometers to 1 micrometer. In one specific example, a value of 800 nanometers for the drain length 140 may enable operation of the FinFET 102 with a drain potential of 20 volts.

[0013] The first body 124 has a body width 142, which represents a maximum lateral dimension of the first body 124 in a direction perpendicular to the current flow during operation of the FinFET 102. The direction of the body width 142 is perpendicular to the direction of the drain length 140. Furthermore, the first drain drift zone 128 has a drain width 144, which represents a maximum lateral dimension of the first drain drift zone 128 in the direction perpendicular to the current flow during operation of the FinFET 102. The direction of the drain width 144 is perpendicular to the direction of the drain length 140. The drain width 144 is greater than the body width 142. The body width 142 can be, for example, 100 nanometers to 300 nanometers. The drain width 144 can be, for example, 300 nanometers to 600 nanometers. For example, the drain width 144 can be 200 nanometers to 300 nanometers larger than the body width 142.

[0014] Referring to Fig. 1C, a charge balance mask 146 is formed over the semiconductor device 100. The charge balance mask 146 exposes the first fin 110 in a region for a first charge balance zone 148 and in a region for a second charge balance zone 150, and exposes the second fin 112 in a region for a third charge balance zone 152 and in a region for a fourth charge balance zone 154. The region for the first charge balance zone 148 and the region for the second charge balance zone 150 are located on opposite sides of the first drain drift zone 128. Likewise, the region for the third charge balance zone 152 and the region for the fourth charge balance zone 154 are located on opposite sides of the second drain drift zone 130.The charge balance mask 146 may include photoresist and anti-reflection material, such as a bottom anti-reflection coat (BARC), and may be formed by a photolithographic process.

[0015] Dopants of the second conductivity type 156, for example boron in this example, are implanted into the first fin 110 and the second fin 112 where they have been exposed by the charge equilibrium mask 146, namely in the areas for the charge equilibrium zones 148, 150, 152 and 154. Dopants of the second conductivity type 156 can be implanted in a total dose of 5×10 11 cm -2 up to 1×10 13 cm -2 The dopants of the second conductivity type 156 may be implanted with more than one implantation energy to vertically distribute the dopants of the second conductivity type 156 in the first fin 110 and the second fin 112.

[0016] The charge balance mask 146 is removed after the second conductivity type dopants 156 are implanted. The photoresist and anti-reflective material in the charge balance mask 146 can be removed by a plasma process using oxygen radicals, such as an ashing process.

[0017] Referring to Fig. 1D, a drift zone mask 158 is formed over the semiconductor device 100. The drift zone mask 158 exposes the first fin 110 in an area for a first enhanced portion 136 in the first drain drift zone 128 of Fig. 1B and exposes the second fin 112 in an area for a second improved section 138 in the second drain drift zone 130 of Fig. 1B. The area for the first improved portion 136 of the first drain drift zone 128 lies between the area for the first charge equilibrium zone 148 and the area for the second charge equilibrium zone 150. Likewise, the area for the second improved portion 138 of the second drain drift zone 130 lies between the area for the third charge equilibrium zone 152 and the area for the fourth charge equilibrium zone 154. The drift zone mask 158 may have a composition similar to that of the charge equilibrium mask 146 of Fig. 1C and are formed by a similar process.

[0018] Dopants of the first conductivity type 160, for example phosphorus in this example, are implanted into the first fin 110 and the second fin 112 where they have been exposed by the drift zone mask 158, namely in the areas for the enhanced portions 136 and 138 of the drain drift zones 128 and 130. The dopants of the first conductivity type 160 may be implanted with a total dose that is 65 percent to 150 percent of the total dose of the dopants of the second conductivity type 156, disclosed with reference to Fig. 1C, to achieve a desired charge balance during operation of the FinFET 102. The first conductivity type dopants 160 may be implanted with more than one implantation energy to vertically distribute the first conductivity type dopants 160 in the first fin 110 and the second fin 112.

[0019] The drift zone mask 158 is removed after the first conductivity type dopants 160 are implanted. The drift zone mask 158 can be removed by a process similar to that used to remove the charge balance mask 146.

[0020] In an alternative version of this example, the implanted areas of the first enhanced portion 136 and the second enhanced portion 138 of the first drain drift region 128 and the second drain drift region 130 may extend to the first body 124 and the second body 126, respectively, of Fig. 1B. In another alternative version, the implanted areas of the first enhanced portion 136 and the second enhanced portion 138 of the first drain drift region 128 and the second drain drift region 130 may extend to the first drain contact region 132 and the second drain contact region 134, respectively, of Fig. 1B. In a further alternative version, the dopants of the first conductivity type 160 may be arranged after the dopants of the second conductivity type 156 of Fig. 1C can be implanted.

[0021] Referring to Fig. 1E, the substrate 104 is heated by an annealing process 162 which heats the dopants of the first conductivity type 160 from Fig. 1D to form the first enhanced portion 136 in the first drain drift region 128 and to form the second enhanced portion 138 of the second drain drift region 130 in the second drain drift region 130. The annealing process 162 also activates the second conductivity type dopants 156 of Fig. 1C, to form the first charge equilibrium region 148 and the second charge equilibrium region 150 in the first fin 110 and to form the third charge equilibrium region 152 and the fourth charge equilibrium region 154 in the second fin 112. The enhanced portions 136 and 138 of the drain drift regions 128 and 130 may have average net dopant concentrations of the first conductivity type of 1×10 16 cm -3 up to 4×10 16 cm -3 have.

[0022] The charge equilibrium zones 148, 150, 152, and 154 may have average net dopant concentrations of the second conductivity type in the enhanced portions 136 and 138 of the drain-drift zones 128 and 130 of 65 percent to 150 percent of the average net dopant concentrations of the first conductivity type, wherein the average net dopant concentrations of the first conductivity type in the charge equilibrium zones 148, 150, 152, and 154 are the average dopant concentrations of the second conductivity type minus the average dopant concentrations of the first conductivity type. The annealing process 162 may be implemented, for example, as a rapid thermal anneal, a spike anneal, or a flash lamp anneal.A rapid thermal anneal can heat the substrate 104 to 1000°C to 1150°C for 5 seconds to 60 seconds and can be implemented in a fast thermal processor using an incandescent lamp. A peak anneal can heat the substrate 104 to 1100°C to 1250°C for 100 milliseconds to 5 seconds and can be implemented using an arc flash lamp. A flash lamp anneal can heat the substrate 104 to 1200°C to 1350°C for 50 microseconds to 1 millisecond and can be implemented using a flash lamp or a scanning laser.

[0023] Forming the enhanced portions 136 and 138 of the drain drift regions 128 and 130 by implanting first conductivity type dopants 160 without overlapping implants of second conductivity type dopants 156, as disclosed in this example, may provide uniform average dopant concentrations in the enhanced portions 136 and 138 of the drain drift regions 128 and 130, advantageously providing uniform performance of the FinFET 102.Likewise, forming the charge equilibrium regions 148, 150, 152, and 154 by implanting second conductivity type dopants 156 without overlapping implants of first conductivity type dopants 160, as disclosed in this example, may provide uniform average dopant concentrations in the charge equilibrium regions 148, 150, 152, and 154, advantageously providing even greater uniform performance of the FinFET 102.

[0024] The first charge balance region 148 is adjacent to the first enhanced portion 136 of the first drain drift region 128 between the first body 124 and the first drain contact region 132, and the second charge balance region 150 is adjacent to the first enhanced portion 136 of the first drain drift region 128 between the first body 124 and the first drain contact region 132 on a side of the first enhanced portion 136 of the first drain drift region 128 opposite the first charge balance region 148.Likewise, the third charge equilibrium region 152 is adjacent to the second enhanced portion 138 of the second drain drift region 130 between the second body 126 and the second drain contact region 134, and the fourth charge equilibrium region 154 is adjacent to the second enhanced portion 138 of the second drain drift region 130 between the second body 126 and the second drain contact region 134 on a side of the second enhanced portion 138 of the second drain drift region 130 opposite the third charge equilibrium region 152. In this example, the second charge equilibrium region 150 may continue continuously within the third charge equilibrium region 152.

[0025] Disposing the first charge balance region 148 and the second charge balance region 150 adjacent to the first enhanced portion 136 of the first drain drift region 128 and on opposite sides, as well as the third charge balance region 152 and the fourth charge balance region 154, with respect to the second enhanced portion 138 of the second drain drift region 130 may advantageously enable a higher operating potential to be applied to the first drain contact region 132 compared to a similar FinFET that does not include the charge balance regions.

[0026] Fig. 1F and Fig. 1G are cutaway views of the semiconductor device 100 along the Fig. 1E, showing further stages of formation. Referring to Fig. 1F, a field plate dielectric layer 164 is formed over the substrate 104 extending from near the first body 124 and from near the second body 126 of Fig. 1E, in Fig. 1F, extends to the first drain contact zone 132 and the second drain contact zone 134 and at least partially overlaps the first improved portion 136 of the first drain drift zone 128 and at least partially overlaps the second improved portion 138 of the second drain drift zone 130 of Fig. 1E, in Fig. 1F. The field plate dielectric layer 164 may also at least partially cover the first charge equilibrium zone 148 of Fig. 1E, in Fig. 1F, and the second charge equilibrium zone 150, the third charge equilibrium zone 152 and the fourth charge equilibrium zone 154 of Fig. 1E, in Fig. 1F. The field plate dielectric layer 164 may comprise silicon dioxide or a silicon dioxide-based dielectric material and may be formed, for example, by a chemical vapor deposition (CVD) process or a plasma-enhanced chemical vapor deposition (PECVD) process. A thickness of the field plate dielectric layer 164 may depend on the desired drain potential of the FinFET 102. By way of example, the thickness of the field plate dielectric layer 164 may be 30 nanometers for a desired drain potential of 5 volts and 120 nanometers for a desired drain potential of 20 volts. The field plate dielectric layer 164 may be patterned by a wet etch process to provide a tapered profile proximate the first body 124 and second body 126.

[0027] On the first body 124 and on the second body 126 of Fig. 1E, in Fig. 1F, a gate dielectric layer 166 is formed on the top surface 114 of the first fin 110 and the second fin 112 and further extends to lateral surfaces of the first body 124 and the second body 126, wherein the lateral surfaces extend from the top surface 114 to the recess oxide 116. The gate dielectric layer 166 may comprise silicon dioxide, nitrided silicon dioxide, hafnium oxide, zirconium oxide, tantalum oxide, or another dielectric material suitable for a gate dielectric of a FinFET. The gate dielectric layer 166 may be formed by a thermal oxidation process, a CVD process, a nitriding process, or a combination thereof. The gate dielectric layer 166 may, for example, have a thickness of 2 nanometers to 12 nanometers.

[0028] A field plate 168 is formed over the field plate dielectric layer 164, and a gate 170 is formed over the gate dielectric layer 166. In this example, the field plate 168 may continue continuously into the gate 170. The gate 170 extends over the top surface 114 of the first fin 110 and the second fin 112, overlapping the first body 124 and the second body 126, and over the side surfaces of the first body 124 and the second body 126. The field plate 168 and the gate 170 may comprise polycrystalline silicon, commonly referred to as polysilicon, and may include a layer of metal silicide on the polysilicon. Alternatively, the field plate 168 and the gate 170 may comprise metallic gate materials such as titanium, titanium nitride, tantalum, or tantalum nitride.The field plate 168 and gate 170 may be formed by forming a conductive layer of polysilicon or gate metals over the field plate dielectric layer 164 and the gate dielectric layer 166, forming a combined field plate / gate mask over the conductive layer, and removing the conductive layer where exposed by the combined field plate / gate mask.

[0029] The field plate 168 may advantageously reduce an electric field in the first enhanced portion 136 of the first drain drift region 128 and the second enhanced portion 138 of the second drain drift region 130 during operation of the FinFET 102. Simultaneously forming the field plate 168 and the gate 170, as disclosed in this example, may advantageously reduce the manufacturing complexity and cost of the semiconductor device 100.

[0030] Referring to Fig. 1G, a drain terminal 172 is formed on the first drain contact region 132 and on the second drain contact region 134 of Fig. 1F formed in Fig. 1G. In this example, the drain terminal 172 is through-hole. The source terminals 174 are formed on the first source 120 and the second source 122. The drain terminal 172 and the source terminals 174 are electrically conductive and may be formed simultaneously. A pre-metal dielectric (PMD) layer (not shown) may be formed over the FinFET 102 prior to forming the drain terminal 172 and the source terminals 174. The drain terminal 172 and the source terminals 174 may be formed by forming contact holes through the PMD layer and forming one or more layers of conductive material such as titanium, titanium nitride, and tungsten on the PMD layer that extend into the contact holes and make electrical connections to the first drain contact region 132, the second drain contact region 134, the first source 120, and the second source 122.The conductive material layers are then removed from the PMD layer, leaving the conductive material layers in the contact holes to provide the drain terminal 172 and the source terminals 174. The drain terminal 172 and the source terminals 174 represent nodes for electrically connecting the FinFET 102 to other components, such as active components or input / output terminals, in the semiconductor device 100.

[0031] Fig. 2A to Fig. 2G are perspective and cross-sectional views of a semiconductor device 200 having an extended drain FinFET 202, hereinafter FinFET 202, illustrated in stages of another exemplary method of formation. Referring to Fig. 2A, the semiconductor device 200 may be implemented like any of the examples described with reference to the semiconductor device 100 of Fig. 1A. In this example, the formation of semiconductor device 200 begins with acquiring a substrate 204. Substrate 204 may be implemented, for example, as a silicon wafer or SOI wafer. Substrate 204 may include regions for additional semiconductor devices (not shown) similar to semiconductor device 200.

[0032] A recess oxide 216 is formed over the substrate 204. The recess oxide 216 may comprise one or more layers of silicon dioxide or silicon dioxide with a few percent by weight hydrogen content and may be formed by thermal oxidation of silicon or by a low-pressure chemical vapor deposition (LPCVD) process. The recess oxide 216 may be formed by forming the one or more layers of silicon dioxide and simultaneously patterning the one or more layers with a fin mask 208.

[0033] The fin mask 208 is formed over the recess oxide 216. The fin mask 208 may include one or more layers of epitaxial mask material such as silicon dioxide, silicon nitride, or silicon-doped boron nitride (Si xBN) with 1 atomic percent to 30 atomic percent silicon, or a combination thereof. The silicon-doped boron nitride can be formed using a PECVD process with diborane (B2H6), silane (SiH4), and ammonia (NH3), an atomic layer deposition (ALD) process with boron trichloride (BCl3), dichlorosilane (SiH2Cl2), and ammonia, or a metal organic chemical vapor deposition (MOCVD) process.The fin mask 208 may be formed by forming the one or more layers of epitaxial mask material over the one or more layers of silicon dioxide for the recess oxide 216, forming a hard mask over the one or more layers of silicon nitride or silicon-doped boron nitride exposing the regions for the first fin 210 and the second fin 212, followed by etching the one or more layers of silicon nitride or silicon-doped boron nitride for the fin mask 208 and the one or more layers of silicon dioxide for the recess oxide 216 using a fluorine radical RIE process to simultaneously form the fin mask 208 and the recess oxide 216. Incorporating the silicon-doped boron nitride into the fin mask 208 may provide etch selectivity for underlying materials such as silicon and silicon dioxide.The fin mask 208 exposes areas for a first fin 210 and a second fin 212 of the FinFET 202.

[0034] The first fin 210 and the second fin 212 are simultaneously formed from a semiconductor material 206 on the substrate 204, where it was exposed by the fin mask 208 and the recess oxide 216, through an epitaxial process. In this example, the semiconductor material 206 of the first fin 210 and the second fin 212 may have a different composition than the substrate 204. For example, the substrate 204 may primarily comprise single-crystal silicon with substantially no germanium or carbon. In versions of this example where the FinFET 202 is a p-channel FinFET 202, the semiconductor material 206 of the first fin 210 and the second fin 212 may comprise silicon-germanium to provide higher hole mobility compared to silicon.In versions of this example where the FinFET 202 is an n-channel FinFET 202, the semiconductor material 206 of the first fin 210 and the second fin 212 may comprise silicon-carbon to provide higher electron mobility compared to silicon. This example describes the FinFET 202 as a p-channel FinFET 202. A corresponding n-channel FinFET 202 may be formed by appropriately changing the conductivity types of dopants used to form the FinFET 202.

[0035] The semiconductor material 206 extends to a top surface 214 of the first fin 210 and the second fin 212. The first fin 210 and the second fin 212 may have dimensions as shown in relation to the first fin 110 and the second fin 112 of Fig. 1B and Fig. 1B. In an alternative version of this example, the epitaxial process may continue until the semiconductor material 206 extends above a top surface of the fin mask 208, and the semiconductor material 206 above the top surface of the fin mask 208 may be removed by a back etch process or a chemical mechanical polishing (CMP) process.

[0036] After the first fin 210 and the second fin 212 are formed, the fin mask 208 is removed, leaving the recess oxide 216 in place. Silicon nitride and silicon-doped boron nitride in the fin mask 208 can be removed by a plasma etching process using fluorine radicals.

[0037] Referring to Fig. 2B, dopants of the first conductivity type, p-type dopants such as boron and optionally gallium or indium in this example, are introduced into the substrate 204 to form a first source 220 in the first fin 210 and a second source 222 in the second fin 212. Dopants of the second conductivity type, p-type dopants such as phosphorus and optionally arsenic or antimony in this example, are introduced into the substrate 204 to form a first body 224 in the first fin 210 and a second body 226 in the second fin 212. Dopants of the first conductivity type, such as boron in this example, are introduced into the substrate 204 to form a first drain drift region 228 in the first fin 210 and a second drain drift region 230 in the second fin 212.The first drain drift region 228 and the second drain drift region 230 may have average concentrations of the first conductivity type dopants of 1×10. 16 cm -3 up to 4×10 16 cm -3 as with reference to Fig. 1B. Dopants of the first conductivity type, such as boron and optionally gallium or indium in this example, are introduced into the first drain drift region 228 to form a first drain contact region 232 in the first fin 210, and into the second drain drift region 230 to form a second drain contact region 234 in the second fin 212. The first drain contact region 232 and the second drain contact region 234 may have average concentrations of the dopants of the first conductivity type above 1×10 19 cm -3 as with reference to Fig. 1B. In this example, the first drain contact region 232 and the second drain contact region 234 are segmented, which may advantageously reduce current crowding in the FinFET 202 during operation of the semiconductor device 200.

[0038] Referring to Fig. 2C, a drift zone mask 258 is formed over the substrate 204. The drift zone mask 258 exposes the substrate 204 in an area suitable for a first enhanced portion 236 of the first drain drift zone 228, in Fig. 2E, over the first fin 210 in the first drain drift zone 228 of Fig. 2B, and which is for a second improved portion 238 of the second drain drift zone 230, in Fig. 2E, via the second fin 212 in the drain drift zone 230 of Fig. 2B. The drift zone mask 258 may have a composition similar to the drift zone mask 158 of Fig. 1D and may be formed by a similar process to that used to form the drift zone mask 158. Forming the drift zone mask 258 to expose the substrate 204 continuously across the first fin 210 and the second fin 212 may advantageously provide greater process latitude for the process used to form the drift zone mask 258 compared to a mask with discrete exposed regions. The region exposed by the drift zone mask 258 may be different from the first body 224 and second body 226 of Fig. 2B to the first drain contact zone 232 and second drain contact zone 234 of Fig. 2B, as shown in Fig. 2C. Alternatively, the area exposed by the drift zone mask 258 may be recessed by the first body 224 and second body 226 or may be recessed by the first drain contact region 232 and second drain contact region 234.

[0039] Dopants of the first conductivity type 260, for example boron in this example, are implanted into the first fin 210 and the second fin 212, where they have been exposed by the drift zone mask 258. The dopants of the first conductivity type 260 can be implanted in a total dose of 5×10 11 cm -2 up to 3×10 12 cm -2 The dopants of the first conductivity type 260 may be implanted with more than one implantation energy to vertically distribute the dopants of the first conductivity type 260 in the first fin 210 and the second fin 212.

[0040] The drift zone mask 258 is removed after the dopants of the first conductivity type 260 are implanted. The drift zone mask 258 may be removed by a process as described with respect to the removal of the drift zone mask 158 from Fig. 1D revealed.

[0041] Referring to Fig. 2D, a charge balance mask 246 is formed over the substrate 204. The charge balance mask 246 places the substrate 204 in an area for a first charge balance zone 248, in Fig. 2E, and in an area for a second charge equilibrium zone 250, in Fig. 2E, in the first fin 210 and in an area for a third charge equilibrium zone 252, in Fig. 2E, and in an area for a fourth charge equilibrium zone 254, in Fig. 2E, in the second fin 212. The area for the first charge equilibrium region 248 and the area for the second charge equilibrium region 250 are located on opposite sides of the first drain drift region 228 of Fig. 2E. Likewise, the third charge equilibrium region 252 and the fourth charge equilibrium region 254 are located on opposite sides of the second drain drift region 230 of Fig. 2E. In this example, the charge balance mask 246 may expose the regions for the second charge balance zone 250 and the region for the third charge balance zone 252 in a single overlapping exposure zone, which may advantageously provide greater process latitude for the process used to form the charge balance mask 246 compared to a mask with discrete exposed regions. The charge balance mask 246 may have a composition similar to the drift zone mask 258 of Fig. 2C and may be formed by a similar process to that used to form the drift zone mask 258.

[0042] Dopants of the second conductivity type 256, for example phosphorus in this example, are implanted into the first fin 210 and the second fin 212 where they have been exposed by the charge balance mask 246, namely in the areas for the charge balance zones 248, 250, 252 and 254. In this example, the dopants of the second conductivity type 256 may be implanted with a total dose that is 165 percent to 250 percent of the total dose of the dopants of the first conductivity type 260 of Fig. 2C so as to counterdope the first conductivity type dopants 260 to provide an average net dopant density in the charge equilibrium regions 248, 250, 252, and 254 that is 65 percent to 150 percent of the average net dopant density in the first enhanced portion 236 of the first drain drift region 228 and the second enhanced portion 238 of the second drain drift region 230. The second conductivity type dopants 256 may be implanted with more than one implantation energy to vertically distribute the second conductivity type dopants 256 in the first fin 210 and the second fin 212.

[0043] The charge balance mask 246 is removed after the dopants of the second conductivity type 256 are implanted. The charge balance mask 246 may be removed by a process as described with respect to the removal of the drift zone mask 258 from Fig. 2C revealed.

[0044] In an alternative version of this example, the dopants of the first conductivity type 260 may be arranged after the dopants of the second conductivity type 256 of Fig. 2C can be implanted.

[0045] Referring to Fig. 2E, the substrate 204 is heated by an annealing process 262 which heats the dopants of the first conductivity type 260 from Fig. 2C and the dopants of the second conductivity type 256 of Fig. 2D activated. In this example, the activated dopants of the first conductivity type 260 form the first enhanced portion 236 of the first drain drift zone 228 in the first drain drift zone 228 and form the second enhanced portion 238 of the second drain drift zone 230 in the second drain drift zone 230 and extend into the first charge equilibrium zone 248 and the second charge equilibrium zone 250 and extend into the third charge equilibrium zone 252 and the fourth charge equilibrium zone 254. The activated dopants of the second conductivity type 256 counter-dope the activated dopants of the first conductivity type 260 to form the first charge equilibrium zone 248 and the second charge equilibrium zone 250 in the first fin 210 and the third charge equilibrium zone 252 and the fourth charge equilibrium zone 254 in the second fin 212.The annealing process 262 may be implemented, for example, as rapid thermal annealing, tip annealing, or flash lamp annealing.

[0046] The first charge balance region 248 is adjacent to and borders the first enhanced portion 236 of the first drain drift region 228 between the first body 224 and the first drain contact region 232, and the second charge balance region 250 is adjacent to and borders the first enhanced portion 236 of the first drain drift region 228 between the first body 224 and the first drain contact region 232 on a side of the first enhanced portion 236 of the first drain drift region 228 opposite the first charge balance region 248.Likewise, the third charge balance region 252 is adjacent to and borders the second enhanced portion 238 of the second drain drift region 230 between the second body 226 and the second drain contact region 234, and the fourth charge balance region 254 is adjacent to and borders the second enhanced portion 238 of the second drain drift region 230 between the second body 226 and the second drain contact region 234 on a side of the second enhanced portion 238 of the second drain drift region 230 opposite the third charge balance region 252.Disposing the first charge balance region 248 and the second charge balance region 250 adjacent to the first enhanced portion 236 of the first drain drift region 228 and on opposite sides, as well as the third charge balance region 252 and the fourth charge balance region 254, with respect to the second enhanced portion 238 of the second drain drift region 230 may advantageously enable a higher operating potential to be applied to the first drain contact region 232 compared to a similar FinFET that does not include the charge balance regions.

[0047] Fig. 2F and Fig. 2G are cutaway views of the semiconductor device 200 along the Fig. 2E, showing further stages of formation. Referring to Fig. 2F, a field plate dielectric layer 264 is formed over the substrate 204, extending from near the first body 224 to the first drain contact region 232 and extending from near the second body 226 to the second drain contact region 234 and at least partially covering the first enhanced portion 236 of the first drain drift region 228 and at least partially covering the second enhanced portion 238 of the second drain drift region 230 of Fig. 2E, in Fig. 2F. The field plate dielectric layer 264 may also at least partially cover the first charge equilibrium zone 248 of Fig. 2E, in Fig. 2F, and the second charge equilibrium zone 250, the third charge equilibrium zone 252 and the fourth charge equilibrium zone 254 of Fig. 2E, in Fig. 2F. The field plate dielectric layer 264 may have properties similar to the field plate dielectric layer 164 of Fig. 1F and can be formed by similar processes.

[0048] A field plate 268 is formed over the field plate dielectric layer 264. The field plate 268 may comprise polysilicon with a layer of metal silicide on the polysilicon or may comprise other electrically conductive materials such as aluminum, copper, titanium, titanium nitride, tantalum, or tantalum nitride. The field plate 268 may be formed by forming a layer of field plate material over the field plate dielectric layer 264, forming a field plate mask over the layer of field plate material, and removing the layer of field plate material where exposed by the field plate mask.

[0049] Referring to Fig. 2G, a gate dielectric layer 266 is formed on the first body 224 and on the second body 226. The gate dielectric layer 266 extends onto the top surface 214 of the first fin 210 and the second fin 212, across the first body 224 and the second body 226, and onto two lateral surfaces of each of the first body 224 and the second body 226, wherein the lateral surfaces extend from the top surface 214 to the recess oxide 216. The gate dielectric layer 266 may comprise any of the materials and may be formed by any of the processes described with respect to the gate dielectric layer 166 of Fig. 1F. The gate dielectric layer 266 may, for example, have a thickness of 2 nanometers to 12 nanometers.

[0050] A gate 270 is formed over the gate dielectric layer 266. The gate 270 extends over the top surface 214 on the first body 224 and the second body 226 and over the side surfaces of the first body 224 and the second body 226. In this example, the field plate 268 may be separate from the gate 270. The gate 270 may comprise any of the materials and may be formed by any of the processes described with respect to the gate 170 of Fig. 1F are disclosed.

[0051] The field plate 268 may, in this example, be biased independently of the gate 270 to advantageously maintain an electric field in the first enhanced portion 236 of the first drain drift region 228 and in the second enhanced portion 238 of the second drain drift region 230 of Fig. 2E, in Fig.2G, during operation of the FinFET 202. The arrangement of the field plate 268 separate from the gate 270 can enable the FinFET 202 to operate at a higher potential than a comparable FinFET with a gate and field plate in continuous continuation.

[0052] Various features of the examples disclosed herein may be combined in other embodiments of exemplary semiconductor devices. For example, in FinFET 102, drain contact regions 132 and 134 may be segmented. In FinFET 202, drain contact regions 232 and 234 may be continuous. In FinFET 102, gate 170 and field plate 168 may be separated. In FinFET 202, gate 270 and field plate 268 may be continuous. In FinFET 102, fins 110 and 112 may be formed by an epitaxial process. In FinFET 202, fins 210 and 212 may be formed by an etching process. In FinFET 102, charge balance regions 148, 150, 152, and 154 may be counterdoped. In the FinFET 202, the charge equilibrium regions 248, 250, 252 and 254 may be implanted with dopants of one conductivity type.In FinFET 102 and FinFET 202, enhanced portions 136 and 138 of drain drift regions 128 and 130 and enhanced portions 236 and 238 of drain drift regions 228 and 230 may be counterdoped. FinFET 102 may be a p-channel FinFET. FinFET 202 may be an n-channel FinFET.

Claims

[1] A semiconductor device (100) comprising: a substrate (104); and a fin field effect transistor, FinFET, (102) on the substrate (104), the FinFET (102) comprising: a fin (110) made of a semiconductor material on the substrate (104), a source (120) in the fin (110), the source (120) having a first conductivity type; a body (124) in the fin (110) adjacent to the source (120), the body (124) having a second conductivity type opposite the first conductivity type; a drain drift region (128) in the fin (110), the drain drift region (128) being adjacent to the body (124) opposite the source (120), the drain drift region (128) having the first conductivity type, the drain drift region (128) being wider than the body (124), and the drain drift region (128) having an enhanced portion (136) of the drain drift region (128), the enhanced portion (136) of the drain drift region (128) having a higher average net dopant concentration of the first conductivity type than a remainder of the drain drift region (128); a first charge equilibrium region (148) in the fin (110) laterally adjacent and contiguous to the enhanced portion (136) of the drain drift region (128), the first charge equilibrium region (148) having the second conductivity type; a second charge equilibrium region (150) in the fin (110) adjacent and contiguous to the enhanced portion (136) of the drain drift region (128), opposite the first charge equilibrium region (148), the second charge equilibrium region (150) having the second conductivity type; a drain contact region (132) in the fin (110) adjacent to the drain drift region (128), opposite the body (124), the drain contact region (132) having the first conductivity type; a gate dielectric layer (166) on the body (124) over a top surface (114) of the fin (110) and extending onto two side surfaces of the body (124); and a gate (170) over the gate dielectric layer (166), the gate (170) extending over the top surface (114) of the fin (110) and extending over the two side surfaces of the body (124). [2] The semiconductor device of claim 1, wherein the enhanced portion (136) of the drain drift region (128) has an average net dopant concentration of the first conductivity type of 1×10 16 cm -3 up to 4×10 16 cm -3 has. [3] The semiconductor device of claim 1, wherein the first charge balance region (148) and the second charge balance region (150) each have an average net dopant concentration of the second conductivity type of 65 percent to 150 percent of an average net dopant concentration of the first conductivity type in the enhanced portion (136) of the drain drift region (128). [4] The semiconductor device of claim 1, wherein the enhanced portion (136) of the drain drift region (128) has a length of 200 nanometers to 1 micrometer between the body (124) and the drain contact region (132). [5] The semiconductor device of claim 1, wherein the body (124) is 100 nanometers to 300 nanometers wide. [6] The semiconductor device of claim 1, wherein the enhanced portion (136) of the drain drift region (128) is 200 nanometers to 400 nanometers wider than the body (124). [7] The semiconductor device of claim 1, wherein the fin (110) extends 300 nanometers to 800 nanometers above the substrate (104). [8] The semiconductor device of claim 1, wherein the FinFET (102) further comprises a field plate (168) at least partially overlapping the enhanced portion (136) of the drain drift region (128). [9] A semiconductor device according to claim 8, wherein the field plate (168) continues continuously in the gate (170). [10] A semiconductor device according to claim 1, wherein: the fin (110) is a first fin; the source (120) is a first source; the body (124) is a first body; the drain drift region (128) is a first drain drift region; the improved portion (136) of the first drain drift region (128) is a first improved portion of the first drain drift region (128); the drain contact zone (132) is a first drain contact zone; and the FinFET (102) further comprises: a second fin (112) of the semiconductor material on the substrate (104); a second source (122) in the second fin (112), the second source (122) having the first conductivity type; a second body (126) in the second fin (112) adjacent to the second source (122), the second body (126) having the second conductivity type; and a second drain drift region (130) in the second fin (112), the drain drift region (128) being adjacent to the second body (126) opposite the second source (122), the second drain drift region (130) having the first conductivity type, the second drain drift region (130) being wider than the second body (126), the second drain drift region (130) having a second enhanced portion (138) of the second drain drift region (130), the second enhanced portion (138) of the second drain drift region (130) having a higher average net dopant concentration of the first conductivity type than a remainder of the second drain drift region (130); a third charge equilibrium region (152) in the fin (110), laterally adjacent and contiguous to the second enhanced portion (138) of the second drain drift region (130), the third charge equilibrium region (152) having the second conductivity type; a fourth charge equilibrium region (154) in the fin (110), laterally adjacent and contiguous to the second enhanced portion (138) of the second drain-drift region (130), opposite the third charge equilibrium region (152), the fourth charge equilibrium region (154) having the second conductivity type; and a second drain contact region (134) in the second fin (112) adjacent to the second enhanced portion (138) of the second drain drift region (134), opposite the second body (126), the second drain contact region (154) having the first conductivity type; wherein the gate dielectric layer (166) extends onto the second body (126), over a top surface (114) of the second fin (112) and extends onto two lateral surfaces of the second body (126); and the gate (170) extends over the upper surface (114) of the second fin (112), over the second body (126) and over the two lateral surfaces of the second body (126). [11] The semiconductor device according to claim 10, wherein the second drain contact region (134) continuously continues the first drain contact region (132). [12] A method of forming a semiconductor device (100, 200), comprising: Providing a substrate (104, 204); Forming a fin (210) from a semiconductor material on the substrate (104, 204); Forming a source (220) in the fin (210), the source (220) having a first conductivity type; forming a body (224) in the fin (210) adjacent to the body (224), the body (224) having a second conductivity type opposite the first conductivity type; Forming a drain drift region (228) in the fin (210), the drain drift region (228) having the first conductivity type and the drain drift region (228) being wider than the body (224); Forming a drain contact region (232) in the drain drift region (228), the drain contact region (232) having the first conductivity type; Forming an improved portion (236) of the drain drift region (228) in the drain drift region (228) between the body (224) and the drain contact region (232), wherein the improved portion (236) of the drain drift region (228) has the first conductivity type and the improved portion (236) of the drain drift region (228) has a higher average net dopant concentration of the first conductivity type than a remainder of the drain drift region (228); Forming a first charge equilibrium region (248) in the fin (210) adjacent the enhanced portion (236) of the drain drift region (228) between the body (224) and the drain contact region (232), the first charge equilibrium region (248) having the second conductivity type; Forming a second charge equilibrium region (250) in the fin (210) adjacent to the enhanced portion (236) of the drain drift region (228) between the body (224) and the drain contact region (232), opposite the first charge equilibrium region (248), the second charge equilibrium region (250) having the second conductivity type; Forming a gate dielectric layer (266) on the body (224) over a top surface (214) of the fin (210) and extending onto two side surfaces of the body; and Image of a gate (270) over the gate dielectric layer (266), wherein the gate (270) extends over the top surface (214) of the fin (210) on the body (224) and extends over the two side surfaces of the body (224). [13] The method of claim 12, wherein forming the improved portion (236) of the drain drift region (228) comprises implanting dopants of the first conductivity type into the drain drift region (228) with a total dose of 5×10 11 cm -2 up to 3×10 12 cm -2 contains. [14] The method of claim 12, wherein forming the first charge balance region (248) and the second charge balance region (250) includes implanting dopants of the second conductivity type into the fin (210) at a total dose of 65 percent to 150 percent of a total dose of dopants of the first conductivity type implanted into the drain drift region (228) to form the enhanced portion (236) of the drain drift region (228). [15] The method of claim 12, wherein the enhanced portion (236) of the drain drift region (228) is formed to have a length of 200 nanometers to 1 micrometer between the body (224) and the drain contact region (232). [16] The method of claim 12, wherein the body (224) is formed to be 100 nanometers to 300 nanometers wide. [17] The method of claim 12, wherein the enhanced portion (236) of the drain drift region (228) is formed to be 200 nanometers to 400 nanometers wider than the body (224). [18] The method of claim 12, wherein the fin (210) is formed to extend 300 nanometers to 800 nanometers across the substrate (204). [19] The method of claim 12, wherein: the fin (210) is a first fin; the source (220) is a first source; the body (224) is a first body; the drain drift region (228) is a first drain drift region; the drain contact zone (232) is a first drain contact zone; and the improved portion (236) of the first drain drift region is a first improved portion of the first drain drift region; and which also includes: Forming a second fin (212) from the semiconductor material on the substrate (204); Forming a second source (222) in the second fin (212), the second source (222) having the first conductivity type; Forming a second body (226) in the second fin (212) adjacent to the second source (222), the second body (226) having the second conductivity type; Forming a second drain drift region (230) in the second fin (212), the second drain drift region (230) being adjacent to the second body (226) opposite the second source (222), the second drain drift region (230) having the first conductivity type, and the second drain drift region (230) being wider than the second body (226); Forming a second drain contact region (234) in the second drain drift region (230), the second drain contact region (234) having the first conductivity type; Forming a second enhanced portion (238) of the drain drift region (128) in the second drain drift region (230) adjacent to the second body (226), opposite the second source (222), wherein the second enhanced portion (238) of the drain drift region (128) has the first conductivity type and the second enhanced portion (238) of the second drain drift region (230) has a higher average net dopant concentration of the first conductivity type than a remainder of the second drain drift region (230); Forming a third charge equilibrium region (252) in the second fin (212) adjacent to the second enhanced portion (238) of the drain drift region (128) between the second body (226) and the second drain contact region (234), the third charge equilibrium region (252) having the second conductivity type; Forming a fourth charge equilibrium region (254) in the second fin (212) adjacent to the second enhanced portion (238) of the drain drift region (128) between the second body (226) and the second drain contact region (234), opposite the third charge equilibrium region (252), the fourth charge equilibrium region (254) having the second conductivity type; Forming the gate dielectric layer (266) to extend onto the second body (226), over a top surface (214) of the second fin (212) on the second body (226), and to extend onto two side surfaces of the second body (226); and Forming the gate (270) so that it extends over the top surface (214) of the second fin (212) and extends over the two side surfaces of the second body (226). [20] The method of claim 19, wherein the second drain contact region (234) is formed to continuously continue the first drain contact region (132).

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