Method for manufacturing a semiconductor component

Abstract

Method for manufacturing a semiconductor device (1), comprising the steps: a step of providing a semiconductor layer (10) which has a main area and which includes an active region (3) and a non-active region (4) which is a different region than the active region; a step of forming a FET structure having a gate electrode (20), a source region (17) or an emitter region and a drain region (40) or a collector region in the active region (3); a step of forming a first insulating layer (61) having contact holes (61b) in the active region (3) on the semiconductor layer (10); a step of forming a first metal film on the first insulating layer (61) which has a section embedded in the contact hole (61b); a step of forming a first main surface electrode (50) located in the non-active region (4) and electrically connected to the gate electrode (20) of the FET structure, and forming a second main surface electrode (55) located in the active region (3) and electrically connected inside the contact holes (61b) to the source region (17) or the emitter region of the FET structure by removing part of the first metal film; a step of forming a second insulating layer (63) covering part of the first main surface electrode (50) and part of the second main surface electrode (55); a step of forming an end insulating layer (65) covering an outer circumferential section of the semiconductor layer (10), wherein the step of forming the end insulating layer (65) is carried out simultaneously with the step of forming the second insulating layer (63), a step of forming a second metal film on the second insulating layer (63), the first main surface electrode (50) and the second main surface electrode (55), which are exposed opposite the second insulating layer (63); a step of forming a first pad (70) which, when viewed from a top view, overlaps the first main surface electrode (50) and the second main surface electrode (55) and is electrically connected to the first main surface electrode (50), and of forming a second pad (75) which, when viewed from a top view, overlaps the second main surface electrode (55) and is electrically connected to the second main surface electrode (55), by removing part of the second metal film; a step of forming a third insulating layer (66) on the first pad (70), the second pad (75) and the second insulating film (63); and a step of exposing part of the first pad (70) and part of the second pad (75) by removing part of the third insulating layer (66), wherein the step of forming the second insulating layer (63) includes a step of forming the second insulating layer (63) in such a way that it has a through hole (63a) which selectively exposes a part of the first main surface electrode (50), and wherein the first pad (70) is electrically connected to the first main surface electrode (50) via the through hole (63a).

Description

Technical field

[0001] The present invention relates to a method for manufacturing a semiconductor component. State of the art

[0002] Patent literature 1 discloses a prior art relating to a semiconductor component having a SiC substrate. List of citations from patent literature

[0003] Patent literature 1: US 2015 / 0 295 079 A1 Another semiconductor component manufacturing process is known from document US 2014 / 0 001 539 A1. Overview of the invention Technical problem

[0004] A preferred embodiment provides a semiconductor component that is capable of relaxing design rules that result from or are derived from an electrode. Solution to the problem

[0005] According to the invention, a method for manufacturing a semiconductor component according to claim 1 is provided. The method is implemented, among other things, by a step that prepares or provides a semiconductor layer containing SiC, having a first main surface on one side and a second main surface on the other side, and including a vertical transistor; by a step that forms a first electrode and a second electrode spaced apart on the first main surface; and by a step that forms a first electrode pad at a position opposite the first electrode of the semiconductor layer, such that it overlaps at least partially with the first electrode in a top view and is electrically connected to the first electrode, wherein in the step of forming the first electrode pad, that first electrode pad is formed oris formed in such a way that it overlaps with part of the second electrode.

[0006] Furthermore, a semiconductor component is disclosed, comprising: a semiconductor layer having a main surface, a switching component formed in the semiconductor layer, a first electrode arranged on the main surface and electrically connected to the switching component, a second electrode arranged on the main surface at a distance or interval from the first electrode and electrically connected to the switching component, a first terminal electrode having a section overlapping the first electrode in a top view and a section overlapping the second electrode and electrically connected to the first electrode, and a second terminal electrode having a section overlapping the second electrode in a top view and electrically connected to the second electrode.

[0007] Furthermore, a semiconductor component is disclosed, comprising: a semiconductor layer having a main surface, a main component formed in the semiconductor layer generating a main current, a sensing component formed in the semiconductor layer in a region distinct from the main component generating a monitoring current that monitors the main current, a first electrode arranged on the main surface and electrically connected to the main component, a second electrode arranged on the main surface at a distance from the first electrode and electrically connected to the main component, a third electrode arranged on the main surface at a distance from the first and second electrodes and electrically connected to the sensing component, and a first terminal electrode.which is electrically connected to the first electrode, to a second terminal electrode which is electrically connected to the second electrode, and to a third terminal electrode which has a section that overlaps with the third electrode in a top view, and a section that overlaps with the second electrode and is electrically connected to the third electrode.

[0008] Furthermore, a semiconductor component is disclosed, comprising: a semiconductor layer having a main surface, a switching component formed in the semiconductor layer, a diode formed in the semiconductor layer in a different region than the switching component, a first electrode arranged on the main surface and electrically connected to the switching component, a second electrode arranged on the main surface at a distance from the first electrode and electrically connected to the switching component, a first terminal electrode electrically connected to the first electrode, a second terminal electrode electrically connected to the second electrode, and a polar terminal electrode having a section that overlaps the diode in a top view and a sectionwhich overlaps with the second electrode and is electrically connected to the diode.

[0009] Furthermore, a semiconductor component is disclosed, comprising: a semiconductor layer containing SiC and having a first principal surface on one side and a second principal surface on the other side, a vertical transistor formed in the semiconductor layer, a first electrode arranged on the first principal surface, a second electrode arranged on the first principal surface at a distance from the first electrode, a first electrode pad arranged on the side opposite the semiconductor layer with respect to the first electrode, such that it overlaps at least partially with the first electrode in a top view and is electrically connected to the first electrode, and a second electrode arranged on the second principal surface, wherein the first electrode pad overlaps a portion of the second electrode in a top view.

[0010] The aforementioned as well as further tasks, features and effects of the present invention will become clearer through the description of the preferred embodiments, which are described with reference to the accompanying drawings. Brief description of the drawings Fig. Figure 1 is a cross-sectional view showing a main section of a semiconductor component according to a first preferred embodiment. Fig. 2 is a cross-sectional view showing another main section of the Fig. 1 shows the semiconductor component shown. Fig. 3 a top view of the in Fig. 1 Semiconductor component shown. Fig. 4. A top view from a position along line IV-IV, which is in Fig. 2 is shown. Fig. 5 is a top view from a position along a line VV that is in Fig. 2 is shown. Fig. 6 is a top view from a position along a line VI-VI, which is in Fig. 2 is shown. Fig. 7 is a top view, in which, compared to the top view of the Fig. 3 a protective insulating layer is removed. Fig. Figure 8 is a top view showing a layout example of a through-hole for a gate pad. Fig. Figure 9 is a top view showing another layout example of the through-hole for the gate pad. Fig. Figure 10 is a top view showing another layout example of a main surface gate electrode and a main surface source electrode. Fig. Figure 11 is a top view showing yet another layout example of the main surface gate electrode and the main surface source electrode. Fig. 12 is an enlarged cross-sectional view showing an outer circumferential section of the in Fig. 2 shows the semiconductor component shown. Fig. 13A is a cross-sectional view showing an example of a method for producing the in Fig. 2 shows the semiconductor component shown. Fig. 13B is a cross-sectional view, taken one step after that of the Fig. 13A is shown. Fig. 13C is a cross-sectional view, one step after that of the Fig. 13B shows. Fig. 13D is a cross-sectional view, one step after that of the Fig. 13C shows. Fig. 13E is a cross-sectional view, one step after that of the Fig. 13D shows. Fig. Figure 14 is an enlarged cross-sectional view, which is a modified example of the outer circumferential section of the in Fig. 2 shows the semiconductor component shown. Fig. Figure 15 is a cross-sectional view of a semiconductor component according to a second preferred embodiment. Fig. 16 is a top view of the in Fig. 15 semiconductor components shown. Fig. 17 is a top view, in which the opposite side is in Fig. In the top view shown in 16, a protective insulating layer has been removed. Fig. 18 is a top view from a position along the line XVIII-XVIII, which is in Fig. 15 is shown. Fig. Figure 19 is a top view, a modified example of the one in Fig. 15 shows the semiconductor component shown. Fig. 20 is a top view of an upper surface of an electrode of the in Fig. 19 semiconductor components shown. Fig. Figure 21 is a cross-sectional view of a semiconductor component according to a third preferred embodiment. Fig. 22 is a top view of the in Fig. 21 semiconductor component shown. Fig. 23 is a top view, in which the opposite side is in Fig. In the top view shown in 22, a protective insulating layer has been removed. Fig. 24 is a top view from a position along a line XXIV-XXIV, which is in Fig. 21 is shown. Fig. 25 is a top view, which is a modified example of the one in Fig. 21 shows the semiconductor component shown. Fig. 26 is a top view of an upper surface of an electrode of the in Fig. 25 semiconductor components shown. Fig. 27 is a top view, which is another modified example of the in Fig. 21 shows the semiconductor component shown. Fig. 28 is a top view of an upper surface of an electrode of the in Fig. 27 semiconductor components shown. Fig. Figure 29 is a front view of an example of a semiconductor package according to a fourth preferred embodiment. Fig. 30 is a rear view, an example of the in Fig. The semiconductor package shown in section 29 is shown. Fig. 31 is a front view of another example of the in Fig. 29 semiconductor packages shown. Fig. Figure 32 is a cross-sectional view of a semiconductor device having a configuration in which a plating layer or layers are formed to cover a gate pad or a source pad. Description of embodiments

[0011] Each of the preferred embodiments described below represents a comprehensive or specific example. Numerical values, shapes, materials, constituent devices, arrangement positions and connection forms of the constituents, steps, sequence of steps, etc., described in connection with the preferred embodiments below are examples and are not intended to limit the present invention. Of the constituents of the preferred embodiments below, one constituent not specified in an independent claim is described as an optional constituent.

[0012] The attached drawings are schematic views and are not necessarily exact. For example, the scales, dimensions, etc., of the accompanying drawings do not always necessarily correspond. In the accompanying drawings, arrangements that are essentially the same are marked with the same reference symbols, and redundant descriptions are omitted or simplified.

[0013] In this description, terms that represent a relationship between components, such as vertical, horizontal, etc., terms that represent the shapes of components, such as rectangular, etc., and numerical ranges are not expressions that convey only a strict meaning, but rather expressions intended to encompass essentially equivalent ranges. For example, in a polygonal shape or a polygonal column shape, the corners or apex may be rounded.

[0014] In this description, the terms "upper" / "above" and "lower" / "below" do not indicate an upper direction (vertically upwards) or a lower direction (vertically downwards) with respect to absolute spatial perception or recognition, but are defined by a relative positional relationship based on the sequence of laminations in a laminated configuration. For example, descriptions are provided in which a first principal surface of the semiconductor layer is considered an upper surface (above) and a second principal surface is considered a lower surface (below). In the actual use of a semiconductor device (vertical transistor), the first principal surface may be a lower surface (below) and the second principal surface an upper surface (above).It is understood that the semiconductor component (vertical transistor) can be used in an orientation in which the first principal surface and the second principal surface are inclined or aligned perpendicular to a horizontal plane.

[0015] The terms “upper” / “above” and “lower” / “below” are not only used in a case where two components are arranged in such a way that they are separated from each other in an upward / downward direction over another component, but also in a case where two components are arranged in the upward / downward direction in such a way that they are close to or adhere to each other.

[0016] In this description and the accompanying drawings, the x-axis, y-axis, and z-axis represent three axes of a three-dimensional orthogonal coordinate system. In this description, a "laminated direction" or "lamination direction" means a direction orthogonal to the main face of the semiconductor layer. In this description, "in a top view" refers to a view from a direction perpendicular to the first main face of the semiconductor layer.

[0017] Fig. Figure 1 is a cross-sectional view of a vertical transistor contained in a semiconductor device according to the first preferred embodiment. Fig. 1. For the sake of clarity in the drawing, no hatching is shown to indicate the cross-section of a semiconductor layer 10. With reference to Fig. 1 is a semiconductor component, an example of a switching component, and includes a vertical transistor 2 (switching component / switching element). The vertical transistor 2 is, for example, a vertical MISFET (metal-insulator-semiconductor field-effect transistor).

[0018] Semiconductor component 1 comprises semiconductor layer 10, a gate electrode 20, a source electrode 30, and a drain electrode 40. Semiconductor layer 10 is formed in a rectangular parallelepiped chip shape. Semiconductor layer 10 has a first main surface 11 on one side and a second main surface 12 on the other side. Semiconductor layer 10 contains SiC (silicon carbide) as a major component. More precisely, semiconductor layer 10 is an n-type (first conductivity type) SiC semiconductor layer, which has a SiC monocrystal.

[0019] The SiC monocrystal can be a 4H-SiC monocrystal. The first principal surface 11 can be a silicon plane ((0001) plane) where silicon of a SiC crystal is exposed. The second principal surface 12 can be a carbon plane ((000-1) plane) where carbon of a SiC crystal is exposed. The semiconductor layer 10 can have an off-angle inclined at an angle of within 10° with respect to a [11-20] direction relative to a (0001) plane of the 4H-SiC monocrystal. The off-angle may be not less than 0° and not greater than 4°.

[0020] The off angle can be greater than 0° and less than 4°. The off angle can be 2° or 4°. The off angle can be set within a range of 2° ± 0.2° or within a range of 4° ± 0.4°. The x-axis direction can be [11-20], and the y-axis direction can be [1-100]. It is understood that the x-axis direction can be [1-100], and the y-axis direction can be [11-20].

[0021] The semiconductor layer 10 has a laminated structure comprising an n-type semiconductor substrate 13 and an n-type epitaxial layer 14. The semiconductor substrate 13 contains a SiC monocrystal. A lower surface of the semiconductor substrate 13 is the second principal surface 12. The epitaxial layer 14 is laminated onto an upper surface of the semiconductor substrate 13. The epitaxial layer 14 is an n-type SiC semiconductor layer containing a SiC monocrystal. An upper surface of the epitaxial layer 14 is the first principal surface 11.

[0022] The n-type impurity concentration of the semiconductor substrate 13 may not be less than 1.0 × 10 18 cm -3 and not larger than 1.0 × 10 21 cm -3In this description, "impurity concentration" means a peak value of the impurity concentration. An n-type impurity concentration of the epitaxial layer 14 is preferably lower than the n-type impurity concentration of the semiconductor substrate 13. The n-type impurity concentration of the epitaxial layer 14 is optionally not less than 1.0 × 10⁻⁶ 15 cm -3 and not larger than 1.0 × 10 17 cm -3 The semiconductor substrate 13 is defined as a drain region of n + -type provided. The epitaxial layer 14 is designed as a drain-drift region of n - -Type provided.

[0023] The thickness of the semiconductor substrate 13 may be no less than 1 µm and no less than 1000 µm. The thickness of the semiconductor substrate 13 may be no less than 5 µm, no less than 25 µm, no less than 50 µm, or no less than 100 µm. The thickness of the semiconductor substrate 13 may be no greater than 700 µm, no greater than 500 µm, no greater than 400 µm, no greater than 300 µm, no greater than 250 µm, no greater than 200 µm, no greater than 150 µm, or no greater than 100 µm. In the vertical transistor 2, a current flows in the laminated direction (i.e., the thickness direction) of the semiconductor layer 10. Therefore, the semiconductor substrate 13 is reduced in thickness, and a current channel can be shortened as a result, in order to reduce a resistance value.

[0024] The thickness of the epitaxial layer 14 may be no less than 1 µm and no greater than 100 µm. The thickness of the epitaxial layer 14 may be no less than 5 µm, no less than 10 µm, and / or no greater than 50 µm. The thickness of the epitaxial layer 14 may be no greater than 40 µm, no greater than 30 µm, no greater than 20 µm, no greater than 15 µm, or no greater than 10 µm. The thickness of the epitaxial layer 14 is preferably less than the thickness of the semiconductor substrate 13.

[0025] With reference to Fig. The semiconductor device 1 comprises a p-type body region 16 (second conductivity type), a plurality of trench-gate structures 21, a plurality of trench-source structures 31, an n-type source region 17, and a p-type contact region 18. The body region 16 is a p-type semiconductor region. -The type is provided in a surface layer section of the first main surface 11 of the semiconductor layer 10. The body region 16 is formed in a surface layer section of the epitaxial layer 14. A p-type impurity concentration of the body region 16 may be no less than 1.0 × 10 16 cm -3 and not larger than 1.0 × 10 19 cm -3 .

[0026] The multitude of trench-gate structures 21 are arranged in an array-like manner on the first main surface 11 at a distance in the x-axis direction in a top view and are each formed in a band shape extending in the y-axis direction. The multitude of trench-gate structures 21 are formed such that they penetrate the body region 16 starting from the first main surface 11. The multitude of trench-gate structures 21 are formed inside the epitaxial layer 14 at a distance from the semiconductor substrate 13 on the side of the first main surface 11.

[0027] Each of the trench-gate structures 21 includes a gate trench 22, a gate insulating layer 23, and a gate electrode 20. The gate trench 22 is formed by a trench in the first main surface 11 in the direction of the side of the second main surface 12. The gate trench 22 has a rectangular cross-sectional shape in an xz section and is formed as a recessed or offset section (depression or groove section) that extends in a band shape in the y-axis direction.

[0028] The gate trench 22 can have a length on the order of one or more millimeters in a longitudinal direction (y-axis direction). The length of the gate trench 22 may be no less than 1 mm and no greater than 10 mm. The length of the gate trench 22 may be no less than 2 mm and no greater than 5 mm. The total extension of one or more gate trenches 22 per unit area may be no less than 0.5 µm / µm 2 and not larger than 0.75 µm / µm 2 .

[0029] The gate insulating layer 23 is formed as a film along a side wall 22a and a bottom wall 22b of the gate trench 22. The gate insulating layer 23 delineates a recessed space in the interior of the gate trench 22. The gate insulating layer 23 can contain at least one type of silicon oxide, impurity-free silicon, silicon nitride, aluminum oxide, aluminum nitride, and aluminum oxynitride.

[0030] The thickness of the gate insulating layer 23 is not less than 0.01 µm and not greater than 0.5 µm. The thickness of the gate insulating layer 23 can be uniform or vary depending on the location. The gate insulating layer 23 comprises a sidewall section 23a, which covers the sidewall 22a of the gate trench 22, and a bottomwall section 23b, which covers the bottomwall 22b of the gate trench 22. The thickness of the bottomwall section 23b can be greater than the thickness of the sidewall section 23a.

[0031] The thickness of the bottom wall section 23b may be not less than 0.01 µm and not greater than 0.2 µm. The thickness of the side wall section 23a may be not less than 0.05 µm and not greater than 0.5 µm, or vice versa. The gate insulating layer 23 may include a covering section that covers the main area 11 outside the gate trench 22. The thickness of the covering section may exceed the thickness of the side wall section 23a.

[0032] The gate electrode 20 is embedded in the gate groove 22 via the gate insulating layer 23. The gate electrode 20 is embedded in a recess that is delimited by the gate insulating layer 23. The gate electrode 20 can contain at least one of a non-metallic conductor and one of a metal. The gate electrode 20 can contain at least one type of conductive polysilicon, titanium, nickel, copper, aluminum, silver, gold, tungsten, and titanium nitride (conductive metal nitride).

[0033] The aspect ratio of the trench-gate structure 21 is not less than 0.25 and not greater than 15.0. The aspect ratio of the trench-gate structure 21 is defined as the ratio of its depth (length in the z-axis direction) to its width (length in the x-axis direction). The aspect ratio of the gate trench 22 is the same as the aspect ratio of the trench-gate structure 21.

[0034] The width of the trench-gate structure 21 may be no less than 0.2 µm and no greater than 2.0 µm. For example, the width of the trench-gate structure 21 could be approximately 0.4 µm. The depth of the trench-gate structure 21 may be no less than 0.5 µm and no greater than 3.0 µm. For example, the depth of the trench-gate structure 21 could be approximately 1.0 µm.

[0035] The multitude of trench-source structures 31 are each formed in a region of the first main surface 11 between the multitude of trench-gate structures 21 that are adjacent to each other. The multitude of trench-source structures 31 are each formed in a band shape that extends in the y-axis direction. Thus, the multitude of trench-source structures 31, together with the multitude of trench-gate structures 21, are arranged in an array-like, alternating and repeating pattern in the x-axis direction. Fig. Figure 1 shows only one area where a trench-gate structure 21 is arranged or held between two trench-source structures 31. The multitude of trench-source structures 31 form a striped structure in a plan view (see the one described below). Fig. 5), together with the multitude of trench-gate structures 21.

[0036] The trench-source structures 31 can each be formed at a distance from an adjacent trench-gate structure 21 of a value not less than 0.3 µm and not greater than 1.0 µm. The multitude of trench-source structures 31 are formed such that they penetrate the body region 16 starting from the first principal surface 11 in order to delimit the body region 16, which extends between the trench-source structures 31 and the multitude of trench-gate structures 21 in the y-axis direction. The multitude of trench-source structures 31 are formed inside the epitaxial layer 14 at a distance from the semiconductor substrate 13 on the side of the first principal surface 11. The multitude of trench-source structures 31 are formed deeper than the multitude of trench-gate structures 21.

[0037] The trench-source structure 31 comprises a source trench 32, a barrier layer 33, the source electrode 30, and a deep basin region 15. The source trench 32 is formed by a trench extending into the first main surface 11 towards the side of the second main surface 12. In an xz-section, the source trench 32 has a rectangular cross-sectional shape and is formed as a recessed section (depression section) that extends in a band shape along the y-axis. The source trench 32 is deeper than the gate trench 22. That is, a bottom wall 32b of the source trench 32 is positioned further towards the side of the second main surface 12 than the bottom wall 22b of the gate trench 22.

[0038] The source electrode 30 is embedded in the source trench 32. The source electrode 30 can contain at least one non-metallic conductor and one metal. The source electrode 30 can contain at least one type of conductive polysilicon, titanium, nickel, copper, aluminum, silver, gold, tungsten, and titanium nitride (conductive metal nitride). The source electrode 30 can contain n-type polysilicon doped with an n-type impurity, or it can contain p-type polysilicon doped with a p-type impurity. The source electrode 30 can be formed from the same material as the gate electrode 20. In this case, the source electrode 30 can be formed in the same step as the gate electrode 20.

[0039] The barrier layer 33 is arranged between a wall surface of the source trench 32 and the source electrode 30. In this embodiment, the barrier layer 33 covers a side wall 32a and the bottom wall 32b of the source trench 32 like a film and delineates a recessed space within the source trench 32. That is, the source electrode 30 is embedded in the recessed space delineated by the barrier layer 33.

[0040] The barrier layer 33 is formed from a material different from that of the source electrode 30m. The barrier layer 33 has a potential barrier that is higher than the potential barrier between the source electrode 30 and the semiconductor layer 10 (more precisely, the deep well region 15 described below). The barrier layer 33 can be a conductive barrier layer. In this case, the barrier layer 33 can contain at least one type of conductive polysilicon, tungsten, platinum, nickel, cobalt, and molybdenum.

[0041] The barrier layer 33 is preferably an insulating barrier layer. In this case, the barrier layer 33 can contain at least one type of silicon oxide, impurity-free silicon, silicon nitride, aluminum oxide, aluminum nitride, and aluminum oxynitride. The barrier layer 33 can be formed from the same material as the gate insulating layer 23. In this case, the barrier layer 33 can have the same film thickness as the gate insulating layer 23. If, for example, the gate insulating layer 23 and the barrier layer 33 are formed from silicon oxide, the gate insulating layer 23 and the barrier layer 33 can be formed simultaneously by a heat oxidation treatment process.

[0042] The deep well region 15 is formed in a region of the semiconductor layer 10 along the trench-source structure 31. The deep well region 15 is referred to as a withstand voltage holding region and is a p-type semiconductor region. The deep well region 15 can harbor a p-type impurity concentration of not less than 1.0 × 10⁻⁶ 17 cm -3 and of no more than 1.0 × 10 19 cm -3 The p-type impurity concentration in the deep-well region 15 preferably exceeds the n-type impurity concentration in the epitaxial layer 14. The p-type impurity concentration in the deep-well region 15 can be equal to the p-type impurity concentration in the body region 16. The p-type impurity concentration in the deep-well region 15 can be lower than the p-type impurity concentration in the body region 16.

[0043] The deep basin region 15 comprises a side wall section 15a, which covers the side wall 32a of the source trench 32, and a bottom wall section 15b, which covers the bottom wall 32b of the source trench 32. The side wall section 15a is electrically connected to the body region 16. The bottom wall section 15b is formed inside the epitaxial layer 14 at a distance from the semiconductor substrate 13. The thickness (length in the z-axis direction) of the bottom wall section 15b is preferably not less than the thickness (length in the x-axis direction) of the side wall section 15a. At least a portion of the bottom wall section 15b may be formed inside the semiconductor substrate 13.

[0044] The length ratio of the trench-source structure 31 is greater than that of the trench-gate structure 21. The length ratio of the trench-source structure 31 is preferably not less than 0.5 and not greater than 18.0. The length ratio of the trench-source structure 31 is preferably not less than 1.5 and not greater than 4.0. The length ratio of the trench-source structure 31 is defined by the ratio of the depth (length in the z-axis direction) of the trench-source structure 31 to the width (length in the x-axis direction) of the trench-source structure 31.

[0045] The width of the trench-source structure 31 is the sum of the width of the source trench 32 and the widths of the side wall sections 15a of the deep basin region 15 on both sides of the source trench 32. The depth of the trench-source structure 31 is the sum of the depth of the source trench 32 and the thickness of the bottom wall section 15b of the deep basin region 15.

[0046] The width of the trench-source structure 31 may be no less than 0.6 µm and no greater than 2.4 µm. For example, the width of the trench-source structure 31 is approximately 0.8 µm. The depth of the trench-source structure 31 may be no less than 1.5 µm and no greater than 11 µm. For example, the depth of the trench-source structure 31 is approximately 2.5 µm. The trench-source structure 31 is enlarged with respect to depth, and the stress retention effects due to a super junction (SJ) structure can be improved as a result.

[0047] Source region 17 is a semiconductor region of n +-type, which is formed in a surface layer section of the first main surface 11 of the semiconductor layer 10. The source region 17 is formed on the body region 16 (a surface layer section of the body region 16) and is connected to the body region 16. The source region 17 is formed in a region along the gate groove 22. The source region 17 covers the gate insulating layer 23 and is opposite the gate electrode 20 via the gate insulating layer 23.

[0048] Source region 17 is formed in a band shape extending along the y-axis in a top view. The width (length along the x-axis) of source region 17 may be no less than 0.2 µm and no greater than 0.6 µm. For example, the width of source region 17 could be approximately 0.4 µm. The n-type impurity concentration in source region 17 may be no less than 1.0 × 10⁻⁶ 18 cm -3 and not larger than 1.0 × 10 21 cm-3 .

[0049] Contact region 18 is a semiconductor region of p + -Type, which is formed in the surface layer section of the first main surface 11 of the semiconductor layer 10. The contact region 18 is formed on the body region 16 (a surface layer section of the body region 16) and is connected to the body region 16. The contact region 18 is also connected to the source region 17. The contact region 18 is formed in a region along the source trench 32. The contact region 18 covers the barrier layer 33 and is opposite the source electrode 30 via the barrier layer 33.

[0050] The contact region 18 is formed in a band shape that extends in the y-axis direction in a top view. The width (length in the x-axis direction) of contact region 18 is not less than 0.1 µm and not greater than 0.4 µm. For example, the width of contact region 18 could be approximately 0.2 µm. The p-type impurity concentration in contact region 18 is not less than 1.0 × 10⁻⁶. 18 cm -3 and not larger than 1.0 × 10 21 cm -3 .

[0051] The semiconductor device 1 includes a drain electrode 40, which covers the second main surface 12 of the semiconductor layer 10. The drain electrode 40 is electrically connected to the semiconductor substrate 13 on the second main surface 12. The drain electrode 40 can contain at least one type of titanium, nickel, copper, aluminum, gold, and silver. The drain electrode 40 can have a four-layer structure, with a Ti layer, a Ni layer, an Au layer, and an Ag layer laminated in that order starting from the second main surface 12.

[0052] The drain electrode 40 can have a four-layer structure containing a Ti layer, an AlCu layer, a Ni layer, and an Au layer, laminated in that order starting from the second main surface 12. The AlCu layer is an alloy layer of aluminum and copper. The drain electrode 40 can also have a four-layer structure with a Ti layer, an AlSiCu layer, a Ni layer, and an Au layer, laminated in that order starting from the second main surface 12. The AlSiCu layer is an alloy layer of aluminum, silicon, and copper. Finally, the drain electrode 40 can have a single-layer structure consisting of a TiN layer instead of the Ti layer, or a laminated structure containing a Ti layer and a TiN layer.

[0053] The vertical transistor 2 is switched between an on state, in which a drain current flows, and an off state, in which no drain current flows, depending on a gate voltage applied to the gate electrode 20. The gate voltage can be no less than 10 V and no greater than 50 V. For example, the gate voltage can be 30 V. A source voltage applied to the source electrode 30 can be a reference voltage, acting as a reference for circuit operation, such as a ground voltage (0 V). A drain voltage applied to the drain electrode 40 is a voltage that is not less than the source voltage. For example, the drain voltage can be no less than 0 V and no greater than 10,000 V. The drain voltage can be no less than 1,000 V.

[0054] When the gate voltage is applied to the gate electrode 20, a channel is opened at a section of body region 16 in contact with the gate insulating layer 23. - -type formed. This creates a current channel from the source electrode 30 to the drain electrode 40, using the contact region 18, the source region 17, the body region 16 (channel), the epitaxial layer 14 and the semiconductor substrate 13.

[0055] The drain electrode 40 has a higher potential than the source electrode 30. Therefore, the drain current flows from the drain electrode 40 to the source electrode 30, via the semiconductor substrate 13, the epitaxial layer 14, the body region 16 (channel), the source region 17, and the contact region 18. Consequently, the drain current flows along the thickness direction of the semiconductor device 1.

[0056] The deep-well region 15 forms a pn junction between the deep-well region 15 and the epitaxial layer 14. In the switched-on state of the vertical transistor 2, the source voltage is applied to the deep-well region 15 via the source electrode 30, and a drain voltage, higher than the source voltage, is applied to the epitaxial layer 14 via the drain electrode 40. That is, in the switched-on state of the vertical transistor 2, a reverse bias voltage is applied to the pn junction, and a depletion layer spreads from the pn junction towards the drain electrode 40.

[0057] This allows the vertical transistor 2 to be improved with respect to its withstand voltage. According to the deep well region 15, which has a higher p-type impurity concentration than the n-type impurity concentration of the epitaxial layer 14, the depletion layer can be suitably extended or widened starting from an interface portion between the deep well region 15 and the epitaxial layer 14.

[0058] In this embodiment, a trench-gate structure is used. However, a planar gate structure can also be used. Furthermore, in the preferred embodiment, a trench-source structure is formed. However, a configuration without a trench-source structure can also be used. Additionally, although a so-called strip cell structure is used in the preferred embodiment, a mesh or grid cell structure can be used.

[0059] In preferred embodiments of the present description, a FET structure (transistor structure) is defined as a structure having three regions: the source region, the drain region, and the gate region. A voltage is applied to the gate region to generate an electric field in the channel region, thereby controlling a current between the source region and the drain region. In this sense, the FET structure is a concept that, in addition to a MOSFET, a MISFET, etc., includes a junction-type FET.

[0060] This means that the FET structure is a concept that also incorporates an IGBT (bipolar transistor with insulated gate) which has an "emitter region" and a "collector region" corresponding to the "source region" and the "drain region," respectively. In preferred embodiments, the FET structure is formed by the body region 16, the source region 17, the gate electrode 20, the epitaxial layer 14, etc.

[0061] In preferred embodiments of the present description, the active region is a region (delimited region) of the semiconductor device in which the FET structure is formed. In a semiconductor device, the active region can be a single region or it can be a plurality of regions that are separated or subdivided from one another. Furthermore, where a diode structure such as a Schottky barrier diode is formed within a region containing the FET structure, a region containing both the FET structure and the diode structure is defined as the active region. Furthermore, where a region containing the diode structure is adjacent to a region containing the FET structure, both the region containing the diode structure and the region containing the FET structure are defined as the active region.

[0062] In preferred embodiments of this description, the non-active region is different from the active region. Examples of the non-active region include a region directly below a gate wiring section, an outer circumferential withstand voltage structure section, a region directly below a PN diode structure for a temperature sensor, etc. In preferred embodiments of this description, a current-sensing FET structure is defined as the non-active region.

[0063] Next, an overall structure of the semiconductor component 1 (in particular a pad structure for supplying a predetermined voltage to the gate electrode 20 and the source electrode 30) is described. Fig. 2 is a cross-sectional view showing another main section of the Fig. Semiconductor component 1 is shown. Fig. 2 is a precise arrangement of the in Fig. Semiconductor layer 10 shown in 1 is not shown. Fig. Figure 2 omits a hatching pattern that shows a cross-section of semiconductor layer 10. Fig. Figure 2 shows a cross-section along a line II-II in Fig. 3. Fig. Figure 3 is a top view of the semiconductor component 1, which is located in Fig. 1 is shown. Fig. Figure 3 shows an outer edge 70b of a gate pad 70 (wide section 72), an outer edge 75a of a source pad 75 and an inner edge 75b of the source pad 75, indicated by dashed lines.

[0064] Fig. Figure 4 is a top view of the semiconductor device 1 onto a plane parallel to a front surface of a substrate, viewed from a position along line IV-IV in Fig. 2. Fig. Figure 4 is a drawing showing a planar shape of a principal surface gate electrode 50 and a planar shape of a principal surface source electrode 55. More precisely, Fig. 4 a top view when the semiconductor component 1 is viewed from the positive side of the z-axis through the gate pad 70 and the source pad 75, which are shown in Fig. 3 is shown.

[0065] Fig. Figure 5 is a top view of the semiconductor component 1 on a plane parallel to the front surface of the substrate, viewed from the position of line VV in Fig. 2. Fig. Figure 5 is a drawing showing a top view of the arrangement or provision of the gate electrode 20 and the source electrode 30. More precisely, it is Fig. 5 a top view when the semiconductor component 1 is viewed from the positive side of the z-axis through the main surface gate electrode 50, the main surface source electrode 55, an insulating layer 60, the gate pad 70 and the source pad 75 (see also Fig. 3 and Fig. 4).

[0066] Fig. Figure 6 is a top view of a plane parallel to the front surface of the substrate, viewed from the position of line VI-VI in Fig. 2. In Fig. Figure 6 shows an upper insulating layer 63 and an end insulating layer 65, indicated by white sections. Fig. 6 are a column section 71 of the main surface gate electrode 50 and the source pad 75, which are exposed opposite a gap or a gap or a transition between the upper insulating layer 63 and the final insulating layer 65, shown by hatched sections.

[0067] In Fig. 6 The gate pad 70 (wide section 72) as well as an outer edge 75a and an inner edge 75b of an upper part of the source pad 75 are shown by dashed lines. Fig. 7 is a top view, in which, compared to the top view of the Fig. 3. A protective insulating layer 66 is removed. 3. Fig. Figure 7 is a drawing showing the plane shapes of Gate Pad 70 and Source Pad 75. In other words, Fig. 7 a top view showing the protective insulating layer 66 in Fig. 3 is away.

[0068] With reference to Fig. 2 and on Fig. 3. The semiconductor component 1 is a semiconductor chip whose planar shape is rectangular. The length of one side of the semiconductor component 1 may be no less than 1 mm and no greater than 10 mm. The length of one side of the semiconductor component 1 may be no less than 2 mm and no greater than 5 mm. The semiconductor component 1 includes the main plane gate electrode 50, the main plane source electrode 55, the insulating layer 60, the gate pad 70, the source pad 75, and the protective insulating layer 66.

[0069] With reference to Fig. 1 and Fig. Figure 5 of the semiconductor device 1 comprises a plurality of gate electrodes 20 and a plurality of source electrodes 30 embedded in the first main surface 11. The plurality of gate electrodes 20 and the plurality of source electrodes 30 are each formed in a long and elongated shape, respectively, extending along the y-axis direction. In a top view, the plurality of gate electrodes 20 and the plurality of source electrodes 30 are arranged in an alternating array-like fashion along the x-axis direction to form a striped structure. Fig. Figure 5 schematically represents the number of gate electrodes (20) and source electrodes (30), to the point where they can be counted. In reality, however, the number of gate electrodes (20) and source electrodes (30) is significantly larger than the numbers shown.

[0070] The semiconductor device 1 comprises a plurality of gate finger sections 20b, which are electrically connected to the plurality of gate electrodes 20. The plurality of gate finger sections 20b are arranged at both end sections in the y-axis direction of the semiconductor layer 10 and form an elongated shape extending along the x-axis direction. The plurality of gate finger sections 20b are each connected to both or corresponding ends of the plurality of gate electrodes 20 in the y-axis direction.

[0071] The number of gate finger sections 20b is arbitrary. Therefore, a single gate finger section 20b can be connected to only one end of the plurality of gate electrodes 20 in the y-axis direction. The plurality of gate electrodes 20 can be separated or spaced apart from each other at a central section in the y-axis direction. In this case, the semiconductor device 1 can include a gate finger section 20b that, in a top view, is located on an inner section of the semiconductor layer 10. The gate finger section 20b on the inner section can extend in the x-axis direction in a region between the plurality of gate electrodes 20 that are adjacent to each other in the y-axis direction. Furthermore, the gate finger section 20b on the inner section can be electrically connected to the plurality of gate electrodes 20 that are adjacent to each other in the y-axis direction.

[0072] The semiconductor device 1 includes the main-area gate electrode 50 as an example of the first electrode, which is electrically connected to the plurality of gate electrodes 20. The main-area gate electrode 50 is positioned above the plurality of gate electrodes 20 (on the positive side in the z-axis direction) and is electrically connected to the plurality of gate electrodes 20. The main-area gate electrode 50 can have an area not greater than 20% of the area of ​​the semiconductor layer 10 (first main area 11) in a top view. Preferably, the main-area gate electrode 50 has an area not greater than 10% of the area of ​​the semiconductor layer 10 (first main area 11) in a top view.

[0073] With reference to Fig. 4. The main surface gate electrode 50 can be shown in plan view in the shape of the letter H. More precisely, the main surface gate electrode 50 includes an electricity receiving section 50a, an electricity supply section 50b, and a connecting section 50c. The electricity receiving section 50a is a section positioned directly below the gate pad 70, which will be described later, and is connected to the column section 71 of the gate pad 70. A section of the main surface gate electrode 50 that overlaps with the column section 71 of the gate pad 70 in a plan view corresponds to the electricity receiving section 50a.

[0074] The power supply sections 50b are arranged at the two end sections in the y-axis direction and form an elongated shape extending in the x-axis direction. The power supply section 50b is connected to the gate finger section 20b by means of a via conductor (not shown) that penetrates a lower insulating layer 61, as will be described later.

[0075] The connecting section 50c connects the electricity receiving section 50a and the electricity supply section 50b. The connecting section 50c is formed in an elongated shape extending in the y-axis direction. In the Fig. In the example shown in section 4, the connecting section 50c is led out opposite the electricity receiving section 50a towards the positive side and also towards the negative side in the y-axis direction and extends to the electricity supply section 50b.

[0076] The main surface gate electrode 50 can contain a non-metallic conductor or a metal. The main surface gate electrode 50 is preferably made of an aluminum-based metal material. Examples of aluminum-based metal materials for the main surface gate electrode 50 include aluminum, an aluminum-silicon (Al-Si) alloy, an aluminum-copper (Al-Cu) alloy, etc. It is understood that the main surface gate electrode 50 can also be made of conductive polysilicon, tungsten, titanium, nickel, copper, silver, gold, titanium nitride (metal nitride), etc. The main surface gate electrode 50 can be made of the same material as the gate electrode 20.

[0077] The main-area gate electrode 50 can have a laminated structure containing multiple metal layers. For example, the main-area gate electrode 50 can have a base layer and a metal layer laminated in that order, starting from the side of the semiconductor layer 10. The base layer can be formed from a barrier metal such as titanium. The metal layer can be formed from an aluminum-based metal material deposited on top of the base layer. The semiconductor device 1 can have a plating layer covering a front surface of the main-area gate electrode 50.

[0078] The semiconductor device 1 includes the main-area source electrode 55 as an example of the second electrode, which is electrically connected to the plurality of source electrodes 30. The main-area source electrode 55 is an electrode that is positioned above the plurality of source electrodes 30 (the positive side in the z-axis direction) and is electrically connected to the plurality of source electrodes 30. With reference to Fig. 1 the main surface source electrode 55 is directly connected to the upper surfaces of the plurality of source electrodes 30.

[0079] The main surface source electrode 55 is arranged in a top view at a distance from the main surface gate electrode 50. The main surface source electrode 55 can be formed in substantially an entire region, except for a region of the first main surface 11 where the main surface gate electrode 50 is arranged, and a region on the perimeter of the region where the main surface gate electrode 50 is arranged, in a top view.

[0080] The main surface source electrode 55 has a larger area in a top view than the main surface gate electrode 50. The main surface source electrode 55 has an area that is not less than 50% of the area of ​​the semiconductor layer 10 (first main surface 11) in a top view. The main surface source electrode 55 preferably has an area that is not less than 70% of the area of ​​the semiconductor layer 10 (first main surface 11) in a top view.

[0081] The main surface source electrode 55 can contain a non-metallic conductor or a metal. The main surface gate electrode 50 or the main surface source electrode 55 is preferably made of an aluminum-based metal material. Examples of aluminum-based metal materials for the main surface gate electrode 50 or the main surface source electrode 55 include aluminum, an aluminum-silicon (Al-Si)-based alloy, an aluminum-copper (Al-Cu)-based alloy, etc.

[0082] It is understood that the main surface gate electrode 50 or the main surface source electrode 55 can be made of conductive polysilicon, tungsten, titanium, nickel, copper, silver, gold, titanium nitride (metal nitride), etc. The main surface source electrode 55 can be made of the same material as the main surface gate electrode 50. In this case, the main surface source electrode 55 can be formed using the same process as the main surface gate electrode 50.

[0083] The main surface source electrode 55 can have a laminated structure containing multiple metal layers. The main surface source electrode 55 can have a base layer and a metal layer laminated in that order, starting from the side of the semiconductor layer 10. The base layer can be formed from a barrier metal such as titanium. The metal layer can be formed from an aluminum-based metal material deposited on top of the base layer. The semiconductor device 1 can include a plating layer covering the front surface of the main surface source electrode 55.

[0084] In this embodiment, the main-area gate electrode 50 contains tungsten, and the main-area source electrode 55 also contains tungsten. That is, the active region 3 is covered by the main-area source electrode 55, which contains tungsten, a material with relatively high hardness. This allows the active region 3 to be protected by the main-area source electrode 55. Furthermore, damage to the FET structure due to stresses or strains, such as wire bonding, etc., in the active region 3 can be suppressed. This structure has been found to be particularly effective in a case where wire bonding is performed on the source pad 75 using a copper wire with relatively high hardness, as described below.

[0085] In another configuration example, a section of the main-area gate electrode 50 embedded in a through-hole (gate contact hole) can be made of tungsten, and a section of the main-area gate electrode 50 distinct from the through-hole (gate contact hole) can be made of an aluminum-based metal material. This section of the main-area gate electrode 50 distinct from the through-hole (gate contact hole) is formed on the lower insulating layer 61, which is described below. The tungsten can be a pure metal or a tungsten alloy. Furthermore, the tungsten can be formed over a barrier film, such as titanium / titanium nitride, etc.

[0086] Furthermore, a section of the main surface source electrode 55 embedded in a source contact hole 61b can be made of tungsten, and a section of the main surface source electrode 55 outside the source contact hole 61b can be made of an aluminum-based metal material. That section of the main surface source electrode 55 outside ("other") the through-hole (gate contact hole) is a section formed on the lower insulating layer 61, which will be described later. The tungsten can be a pure metal or a tungsten alloy. Furthermore, tungsten can be formed over a barrier film such as titanium / titanium nitride, etc.

[0087] In semiconductor device 1, the main surface source electrode 55 is located in a region containing the center position of the semiconductor layer 10 in a plan view, and the main surface gate electrode 50 is located in a region that avoids or bypasses the main surface source electrode 55. However, the main surface gate electrode 50 and the main surface source electrode 55 can be arranged in any configuration and are not limited to the distribution described above. For example, the main surface gate electrode 50 can be located in a region containing the center position of the semiconductor layer 10 in a plan view, and the main surface source electrode 55 can be arranged such that it surrounds a perimeter of the main surface gate electrode 50 in a plan view.

[0088] With reference to Fig. Figure 2 includes the insulating layer 60, the lower insulating layer 61, the upper insulating layer 63 as an example of a first insulating layer (first insulator), and the end or edge insulating layer 65. The lower insulating layer 61 is an intermediate insulating film and is provided on the first main surface 11. More precisely, the lower insulating layer 61 collectively covers the multitude of trench-gate structures 21. With reference to Fig. 1 The lower insulating layer 61 is designed to prevent the main surface source electrode 55 from coming into contact with the gate electrode 20.

[0089] The lower insulating layer 61 has a plurality of source contact holes 61b. A portion of the main surface source electrode 55 is embedded in the plurality of source contact holes 61b and is electrically connected to the plurality of source electrodes 30 inside the plurality of source contact holes 61b. Furthermore, the main surface source electrode 55 is electrically connected to the source region 17 and the contact region 18 inside the plurality of source contact holes 61b.

[0090] Although not shown, the lower insulating layer 61 includes at least one (or several in this embodiment) through-hole (gate contact hole) to expose the power supply section 50b. Part of the power supply section 50b (see Fig. 4) The main surface gate electrode 50 is embedded in the plurality of through holes (gate contact holes) and is electrically connected to the gate finger section 20b (see Fig. 5) connected inside the multitude of through holes (gate contact holes). This electrically connects the main surface gate electrode 50 to the gate electrode 20.

[0091] The plurality of through holes (gate contact holes) are preferably formed at the same time as the plurality of source contact holes 61b. In this case, the material and structure of the main surface gate electrode 50 (electricity supply section 50b), which is embedded in the plurality of through holes (gate contact holes), are the same as those of the main surface source electrode 55, which is embedded in the plurality of source contact holes 61b.

[0092] The upper insulating layer 63 covers part of the main-area gate electrode 50 and part of the main-area source electrode 55. The upper insulating layer 63 is arranged between the gate pad 70, which is described below, and the main-area source electrode 55, such that the gate pad 70 is not in contact with the main-area source electrode 55. Furthermore, the upper insulating layer 63 is arranged between the source pad 75, which is described later, and the main-area gate electrode 50, such that the source pad 75 is not in contact with the main-area gate electrode 50.

[0093] The upper insulating layer 63 has a through-hole 64 that covers the connecting section 50c of the main surface gate electrode 50 and selectively exposes the electricity receiving section 50a. More precisely, the upper insulating layer 63 exposes a portion of an upper surface 52 of the electricity receiving section 50a via the through-hole 64. In this embodiment, a single through-hole 64 is formed in a section of the upper insulating layer 63 that is opposite a substantially central position of the gate pad 70.

[0094] The gate pad 70 is connected only to the upper surface 52 of the electricity receiving section 50a via the through-hole 64. The plane shape of the through-hole 64 (plane shape of the column section 71, which will be described later) can be square or rectangular. The length of one side of the through-hole 64 in a top view is not less than 5 µm and not greater than 50 µm. As an example, the plane shape of the through-hole 64 is a square of approximately 20 µm × 20 µm.

[0095] The through-hole 64 can be provided in various layouts. Another layout example of the through-hole is described below. Fig. Figure 8 is a top view showing a layout example of the through-hole 64 for the gate pad 70. Fig. Figure 8 does not show the protective insulating layer 66. Referring to Fig. 8. The through-hole 64 can be arranged near an edge section of the gate pad 70. In this case, a bonding wire 303g (shown in dashed lines) is preferably connected to the gate pad 70 such that it does not overlap the through-hole 64 (column section 71) in a top view. According to this structure, a load, pressure, or stress exerted on the through-hole 64 (column section 71) during wire bonding can be suppressed.

[0096] Fig. Figure 9 is a top view showing another layout example of through hole 64 for gate pad 70. Referring to Fig. 9. The upper insulating layer 63 can have a plurality of through-holes 64 for a single gate pad 70. In this case, the plurality of through-holes 64 (column sections 71) are formed in a region where the gate pad 70 and the main-area gate electrode 50 overlap in a top view. This allows the gate pad 70 and the main-area gate electrode 50 to be reliably guided and connected. The bond wire 303g (shown by dashed lines) is preferably connected such that it does not overlap with at least some of the through-holes 64 (column sections 71).

[0097] With renewed reference to Fig. 2 The upper insulating layer 63 is arranged between the gate pad 70 and the main surface source electrode 55, viewed in the z-axis direction. This insulates the gate pad 70 from the main surface source electrode 55 by the upper insulating layer 63. The upper insulating layer 63 is formed by etching (pattern formation), and a side surface 63a of the upper insulating layer 63 is thereby formed in a plane that extends vertically (in the z-axis direction) with respect to the first main surface 11. Here, "vertical" essentially means vertical and is not to be understood in a strict sense.

[0098] The terminal insulating layer 65 covers an outer circumferential section (circumferential edge section) of the semiconductor device 1 (semiconductor layer 10). The terminal insulating layer 65 covers the entire outer circumferential section (circumferential edge section) of the semiconductor device 1 (semiconductor layer 10). The terminal insulating layer 65 covers the power supply section 50b of the main area gate electrode 50. Part of the terminal insulating layer 65 rests on the lower insulating layer 61 and the main area source electrode 55.

[0099] The lower insulating layer 61, the upper insulating layer 63, and the final insulating layer 65 may contain an inorganic insulating material. This inorganic insulating material may contain silicon dioxide, silicon nitride, etc. Silicon dioxide includes PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. The lower insulating layer 61, the upper insulating layer 63, and the final insulating layer 65 may also contain an organic insulating material. This organic insulating material may contain polyimide, PBO (polybenzoxazole), etc.

[0100] The lower insulating layer 61, the upper insulating layer 63, and the final insulating layer 65 can be made of the same insulating material or of different insulating materials. For example, the lower insulating layer 61, the upper insulating layer 63, and the final insulating layer 65 can all be made of silicon dioxide. It is understood that the upper insulating layer 63 and the final insulating layer 65 can be made of silicon nitride, while the lower insulating layer 61 is made of silicon dioxide.

[0101] Both the upper insulating layer 63 and the final insulating layer 65 can have a thickness of not less than 3 µm and not more than 20 µm. The upper insulating layer 63 and the final insulating layer 65 preferably have a thickness of not less than 5 µm and not more than 15 µm. The upper insulating layer 63 and the final insulating layer 65 preferably have a thickness of not less than 5 µm and not more than 10 µm.

[0102] The semiconductor device 1 includes the gate pad 70 as an example of the first electrode pad (first terminal electrode), which is electrically connected to the main-area gate electrode 50. The gate pad 70 overlaps the main-area gate electrode 50 in a top view and is electrically connected to it. More precisely, the gate pad 70 is arranged such that the electricity receiving section 50a of the main-area gate electrode 50 is positioned inside the gate pad 70 in a top view. That is, the gate pad 70 completely covers the electricity receiving section 50a of the main-area gate electrode 50.

[0103] With reference to Fig. 2 The gate pad 70 includes the column section 71 as an example of the lower conductive layer and the wide section 72 as an example of the upper conductive layer. The column section 71 is located on the main surface gate electrode 50. More precisely, the column section 71 is connected to the upper surface 52 of the electricity receiving section 50a and is formed in a column shape that extends along the normal (z-axis) direction to the upper surface 52. The height of the column section 71 is equal to the thickness of a section of the upper insulating layer 63 positioned on the electricity receiving section 50a. The column section 71 is positioned at a distance from a circumferential edge of the electricity receiving section 50a in a top view.That is, a side surface 74 of the column section 71, which points towards the y-axis direction, is positioned inside with respect to a side surface 53 of the main surface gate electrode 50, which points in the y-axis direction.

[0104] The wide section 72 is located at the upper end of the column section 71 and connects the electricity receiving section 50a and the column section 71. The wide section 72 is a section in which the upper end of the column section 71 is extended or enlarged in size. That is, the wide section 72 has a larger surface area in plan view than the column section 71. The wide section 72 is designed such that the column section 71 is positioned within the wide section 72 in plan view. The size and shape of the wide section 72 correspond to or are adapted to those of the gate pad 70 in plan view.

[0105] The wide section 72 is shaped such that, in a top view, it extends further outwards towards the outside than the electricity receiving section 50a. In this embodiment, the wide section 72 is formed in an umbrella shape, extending further outwards from the electricity receiving section 50a than the main surface gate electrode 50, specifically in a direction (x-axis direction) that is orthogonal to the direction (y-axis direction) in which the main surface gate electrode 50 extends. In this embodiment, the wide section 72 extends in an umbrella shape towards both the negative and positive sides in the x-axis direction.

[0106] This results in the width of the wide section 72 in the x-axis direction being greater than the width of the main surface gate electrode 50 in the x-axis direction. That is, the gate pad 70 has an overlapping or intersecting section that crosses or overlaps at least one side (two sides in this embodiment) of the main surface gate electrode 50 in a top view. A section of an upper surface 73 of the wide section 72, which overlaps the column section 71 in a top view, is recessed or set back towards the main surface gate electrode 50.

[0107] The upper surface 73 of the wide section 72 is used for electrically connecting the semiconductor component 1 to other circuits. For example, the upper surface 73 of the wide section 72 is electrically connected to a power circuit that supplies a gate voltage. A metal wire can be connected to the upper surface 73 of the wide section 72 by wire bonding. The metal wire can contain at least one type of aluminum, copper, and gold. In this embodiment, an aluminum wire is wedge-bonded to the gate pad 70 (upper surface 73 of the wide section 72). A metal plate can be connected to the upper surface 73 of the wide section 72 by soldering instead of wire bonding.

[0108] The gate pad 70 has an area not greater than 20% of the area of ​​the semiconductor layer 10 (first principal area 11) in a top view. Preferably, the gate pad 70 has an area not greater than 10% of the area of ​​the semiconductor layer 10 (first principal area 11) in a top view. The wide section 72 (area of ​​the gate pad 70) has an area greater than the area of ​​the electricity receiving section 50a (i.e., the column section 71) in a top view. The wide section 72 is optionally not less than 200 times and not greater than 40,000 times the area of ​​the electricity receiving section 50a. Preferably, the wide section 72 is not less than 400 times larger in area than the electricity receiving section 50a. As an example, the wide section 72 can be about 2500 times larger in area than the electricity receiving section 50a.

[0109] To properly perform wire bonding, the wide section 72 (gate pad 70) must be larger than a specified size. The wide section 72 preferably has an area not less than 800 µm × 800 µm and not greater than 1 mm × 1 mm in plan view. In this case, the wide section 72 can be square in plan view. The metal wire bonding can then be set or carried out in any desired direction. It is understood that the wide section 72 can also be square with an area larger than 1 mm × 1 mm in plan view. Furthermore, the wide section 72 can be rectangular with an area not less than 400 µm × 800 µm.

[0110] Column section 71 and wide section 72 can be made of the same conductive material. Column section 71 and wide section 72 can be made of an aluminum-based metal material. It is understood that column section 71 and wide section 72 can be made of titanium, nickel, copper, silver, gold, tungsten, etc. Column section 71 and wide section 72 can be made of conductive materials that differ from each other.

[0111] The height of the gate pad 70 is not less than a few dozen micrometers and not greater than a few hundred micrometers (that is, not less than 20 µm and greater than 1000 µm). The height of the gate pad 70 (length in the z-axis direction) is calculated as the sum of the height of the column section 71 (length in the z-axis direction) and the thickness of the wide section 72 (length in the z-axis direction). Fig. Figure 2 shows an example where the height of column section 71 is equal to the thickness of wide section 72. However, the height of column section 71 can be greater than the thickness of wide section 72, or it can be less than the thickness of wide section 72.

[0112] The semiconductor device 1 includes the source pad 75 as an example of the second electrode pad (second terminal electrode), which is electrically connected to the main surface source electrode 55. The source pad 75 overlaps the main surface source electrode 55 in a top view and is electrically connected to it. The source pad 75 is provided on the main surface source electrode 55. That is, the source pad 75 covers an upper surface 56 of the main surface source electrode 55. If one considers a normal line direction (z-axis direction) of the upper surface 56 of the main surface source electrode 55 as a thickness direction, the source pad 75 is formed in a plate shape that extends along the upper surface 56.

[0113] The source pad 75 is arranged in a region that includes the center position of the semiconductor layer 10 (first principal surface 11) in the top view. The source pad 75 is arranged in a region that avoids or bypasses the gate pad 70. In this embodiment, the gate pad 70 is arranged in a region that includes the center position of the semiconductor layer 10 (first principal surface 11), and the source pad 75 is arranged to surround a perimeter of the gate pad 70n.

[0114] An end section 79 of the source pad 75 on the negative side in the x-axis direction rides on or rests on the upper insulating layer 63, specifically above the main surface source electrode 55. A side surface 77 of the source pad 75 is positioned on the upper insulating layer 63. The source pad 75 has an area that is smaller than the area of ​​the main surface source electrode 55 in a top view. The source pad 75 has an area that is larger than the area of ​​the gate pad 70 in a top view. The source pad 75 has an area that is not less than 50% of the area of ​​the semiconductor layer 10 (first main surface 11) in a top view. The source pad 75 preferably has an area that is not less than 70% of the area of ​​the semiconductor layer 10 (first main surface 11) in a top view.

[0115] The source pad 75 is positioned at a distance from the gate pad 70 in the top view and forms a gap or gap section that exposes the upper insulating layer 63 between the source pad 75 and the gate pad 70 above the main surface source electrode 55m. The gap section is delimited by a section of the side surface of the gate pad 70, which is positioned above the main surface source electrode 55, and by a section of the side surface 77 of the source pad 75, which is positioned above the main surface source electrode 55.

[0116] It is therefore possible to suppress a short circuit caused by contact between the gate pad 70 and the source pad 75 above the main surface source electrode 55, and it is also possible to form the source pad 75 stably. In this embodiment, the side surface 77 of the source pad 75 is formed in a plane that extends vertically or substantially vertically with respect to the first main surface 11. However, the side surface 77 need not necessarily be flat or planar, but can be a curved surface or a surface with irregularities.

[0117] An upper surface 76 of the source pad 75 is used for electrically connecting the semiconductor component 1 to other circuits. For example, the upper surface 76 of the source pad 75 is connected to a power circuit that provides or supplies a source voltage. A metal wire can be connected to the upper surface 76 of the source pad 75 by wire bonding. The metal wire can contain at least one type of aluminum, copper, and gold. In this embodiment, for example, an aluminum wire is wedge-bonded to the source pad 75. A metal plate can be connected to the source pad 75 by soldering instead of wire bonding.

[0118] Source Pad 75 is made of a conductive material. It can be made of an aluminum-based metal. It is understood that Source Pad 75 can also be made of titanium, nickel, copper, silver, gold, tungsten, etc. Source Pad 75 can be made of the same material as Gate Pad 70. In this case, Source Pad 75 can be formed using the same process as Gate Pad 70. It is understood that Source Pad 75 can also be made of a different material than Gate Pad 70.

[0119] The gate pad 70 is preferably formed in the same step as the source pad 75. In this case, the structure and material of the gate pad 70 are the same as those of the source pad 75. If the source pad 75 is wire-bonded using an aluminum wire, the source pad 75 is preferably made of an aluminum-based material. In this case, the gate pad 70 is also made of an aluminum-based material, just like the source pad 75.

[0120] If the Source-Pad 75 is soldered to a metal plate, a plating layer can be formed on the front surface of the Source-Pad 75. In this case, the Source-Pad 75 can be made of an aluminum-based metal material. Furthermore, the plating layer can contain at least one nickel plating or one gold plating. The plating layer can have a single-layer structure consisting of a nickel plating, or it can have a laminated structure containing a nickel plating and a gold plating, laminated from the side of the Source-Pad 75 in that order.

[0121] In this case, the gate pad 70 can be arranged similarly to the source pad 75. That is, the plating layer is formed on the front surface of the gate pad 70. In this case, the gate pad 70 can be made of an aluminum-based metal material. Furthermore, the plating layer can contain at least one nickel plating or one gold plating. The plating layer can have a single-layer structure consisting of nickel plating, or it can have a laminated structure containing nickel plating and gold plating, laminated in that order starting from the side of the gate pad 70.

[0122] If the source pad 75 is connected to a metal plate by a sintered element such as Ag, the plating layer can be formed on the front surface of the source pad 75. In this case, the source pad 75 can be made of an aluminum-based metal material. Furthermore, the plating layer can contain at least one nickel plating, one palladium plating, and one gold plating. For example, the plating layer can have a laminated structure containing nickel plating, palladium plating, and gold plating, laminated in that order starting from the side of the source pad 75.

[0123] In this case, the gate pad 70 can be similar in arrangement to the source pad 75. That is, the plating layer can be formed on the front surface of the gate pad 70. In this case, the gate pad 70 can be made of an aluminum-based metal material. Furthermore, the plating layer can contain at least one nickel plating, one palladium plating, and one gold plating. For example, the plating layer can have a laminated structure containing a nickel plating, a palladium plating, and a gold plating, laminated in that order starting from the side of the gate pad 70.

[0124] An example is shown here in which the gate pad 70 and the source pad 75 contain an aluminum-based material. However, the gate pad 70 and the source pad 75 can be made of a metallic material such as copper and nickel instead of the aluminum-based material. That is, the gate pad 70 can contain the column section 71 and the wide section 72, which are made of a metallic material such as copper and nickel.

[0125] The main surface gate electrode 50, the main surface source electrode 55, the gate pad 70 and the source pad 75 can be formed in various types of layouts in addition to the above description. Fig. Figure 10 is a top view showing another layout example of gate pad 70 and electricity receiving section 50a. In other words, Fig. Figure 10 shows a further layout example of the main surface gate electrode 50 and the main surface source electrode 55. With reference to Fig. 10 the electricity receiving section 50a of the main surface gate electrode 50 can be arranged on an outermost circumferential section (circumferential edge section) of the semiconductor component 1 (chip, semiconductor layer 10).

[0126] The wide section 72 can be formed in an umbrella shape that extends only towards the positive side in the x-axis direction. That is, the gate pad 70 has an overlapping or crossing section that intersects at least one side (a single side in this embodiment) of the main surface gate electrode 50 in a top view. In the Fig. In the layout example shown in Figure 10, the main surface source electrode 55 is formed in a rectangular shape in a top view, and the main surface gate electrode 50 is formed in a rectangular ring shape surrounding the main surface source electrode 55 when viewed in a top view.

[0127] Fig. Figure 11 is a top view showing yet another layout example of the main surface gate electrode 50 and the main surface source electrode 55. Fig. Figure 11 shows an example where the main surface gate electrode 50 also has a section extending from the electricity receiving section 50a in the x-axis direction, as in the layout example of Fig. 10. Accordingly, the arrangement or distribution of the main surface gate electrode 50 and the main surface source electrode 55, as well as the arrangement or distribution of the gate pad 70 in relation to the main surface gate electrode 50 and the main surface source electrode 55, can assume different types of configurations.

[0128] With renewed reference to the Fig. 2, Fig. 3, Fig. 4 to Fig. 5 includes the semiconductor component 1, the active region 3, and the inactive region 4. In Fig. 3 and in Fig. In Figure 5, active region 3 is shown by a region surrounded by alternating long and short dashed lines. Active region 3 is the region where the FET structure is formed and is a main region through which a drain current of the vertical transistor 2 flows. Active region 3 essentially coincides with a region covered by the main-area source electrode 55. Non-active region 4 is distinct from active region 3. Non-active region 4 comprises a region where the main-area gate electrode 50 is located and a withstand-voltage structure region on its outer periphery (at the periphery edge).

[0129] In a semiconductor device, a gate pad 70 of a defined size is generally required for wire bonding a metal wire. If a main-area gate electrode 50 is formed to be essentially the same size as the gate pad 70, the main-area source electrode 55 will be relatively small. An active region 3 is essentially the same size as the main-area source electrode 55. Therefore, if the main-area gate electrode 50 is made large, the size of the main-area source electrode 55 is correspondingly reduced, and the active region 3 becomes smaller. As a result, the semiconductor layer 10 is no longer used efficiently, which has the detrimental effect of reducing the size and cost of the semiconductor device.

[0130] In contrast, semiconductor device 1 features a main-area gate electrode 50 and a gate pad 70 (wide section 72) that intersects the active region 3 at multiple levels. This structure shifts the wire bonding target from the main-area gate electrode 50 to the gate pad 70. This allows the size of the main-area gate electrode 50 to be reduced, while the size of the active region 3 can be increased. In other words, the design constraints of semiconductor device 1, which are derived from the main-area gate electrode 50, are relaxed by means of the gate pad 70, thus increasing the design freedom.

[0131] More precisely, a portion of the gate pad 70 (wide section 72) overlaps the main surface source electrode 55 in a top view. Even more precisely, the gate pad 70 has a width, viewed along the y-axis, that is greater than the width of the main surface gate electrode 50 in a top view, and overlaps with a portion of the main surface source electrode 55. This allows the area of ​​the main surface gate electrode 50 to be reduced and the area of ​​the active region 3 to be increased. Furthermore, the gate pad 70 can be formed in a size larger than a specified size, while avoiding design rules derived from the main surface gate electrode 50. Therefore, the limited region of the semiconductor layer 10 can be efficiently utilized to realize the semiconductor device 1, which is capable of easily reducing size and cost.

[0132] With reference to Fig. Figure 3 of the semiconductor device 1 includes the protective insulating layer 66 as an example of the second insulating layer (second insulator) formed on the upper insulating layer 63. The protective insulating layer 66 covers a boundary section 80 (gap section) between the gate pad 70 and the source pad 75. That is, the protective insulating layer 66 includes a section that covers the upper insulating layer 63 within the boundary section 80 between the gate pad 70 and the source pad 75 above the main surface source electrode 55. The protective insulating layer 66 has a section that is opposite the main surface source electrode 55, extending across the upper insulating layer 63 inside the boundary section 80.

[0133] The boundary section 80 is formed in a rectangular ring shape in a top view. Therefore, the protective insulating layer 66 is formed in a rectangular ring shape over a section covering the boundary section 80. Furthermore, the protective insulating layer 66 covers the entire outer circumferential section (circumferential edge section) of the semiconductor device 1 (first main surface 11). The protective insulating layer 66 may contain an organic insulating material. The protective insulating layer 66 may contain polyimide, PBO, etc.

[0134] Fig. Figure 12 is an enlarged cross-sectional view showing an outer circumferential section (circumferential edge section) of the semiconductor device 1 (first principal surface 11), and is a drawing showing region XII of the Fig. 2 shows with greater accuracy. With reference to Fig. In the outer circumferential section (circumferential edge section) of the semiconductor device 1 (first main surface 11), an end section of the end insulating layer 65 is located on the positive side in the x-axis direction on the main surface source electrode 55, such that it is positioned on or above the main surface source electrode 55. An end section of the source pad 75 on the negative side in the x-axis direction is positioned on the end section of the end insulating layer 65 on the positive side in the x-axis direction. The protective insulating layer 66 covers the end section of the end insulating layer 65 on the positive side in the x-axis direction and the end section of the source pad 75 on the negative side in the x-axis direction.

[0135] In an environment exhibiting at least one of high voltage, high temperature, and high humidity, migration of impurities within a module gel and water ingress into the module gel, etc., can occur. If deterioration of the structure of the outer circumferential section (circumferential edge section) of semiconductor layer 10 is observed due to the influence of temperature cycles and humidity, the substance (element) can penetrate the component from the deteriorated area, potentially causing problems such as short circuits, electrical discharges, malfunctions, etc.

[0136] In the semiconductor device 1, the outer circumferential section (circumferential edge section) of the semiconductor layer 10 is covered in a predetermined pattern by the lower insulating layer 61, the protective insulating layer 66, and the final insulating layer 65 (upper insulating layer 63). Compared to a case where the outer circumferential section (circumferential edge section) of the semiconductor layer 10 is covered by the lower insulating layer 61 and the protective insulating layer 66, deterioration of the outer circumferential section (circumferential edge section) is therefore suppressed. That is, the ingress of water, etc., starting from a deteriorated point as a starting point is suppressed, thus increasing the reliability of the semiconductor device 1.

[0137] The Fig. Figures 13A to 13E are each a cross-sectional view showing individual steps of a process for fabricating the semiconductor device 1. The following mainly describes a process for fabricating an upper arrangement of the semiconductor layer 10. A publicly known method is used in a process for forming the trench-gate structure 21, the trench-source structure 31, and each of the semiconductor regions (each well region) in the semiconductor layer 10.

[0138] First, with reference to Fig. 13A The lower insulating layer 61, which has the plurality of source contact holes 61b, is formed on the first main surface 11 of the semiconductor layer 10. One step of forming the lower insulating layer 61 includes, for example, a step in which an insulating film such as silicon dioxide is formed by a plasma-CVD (chemical vapor deposition) process, and a step in which part of the insulating film (silicon dioxide) is removed after film formation by a photolithographic process and an etching process. This achieves pattern formation of the insulating film to form the lower insulating layer 61 with a predetermined pattern.

[0139] Next, with reference to Fig. 13B the main surface gate electrode 50 and the main surface source electrode 55 are formed at a distance from each other on the lower insulating layer 61m. One step of forming the main surface gate electrode 50 and the main surface source electrode 55 includes, for example, a step in which a metal film is formed over an entire area of ​​the first main surface 11 by a vapor deposition process or a sputtering process to cover the lower insulating layer 61, and a step in which part of the metal film is removed after film formation by a photolithographic process and an etching process.

[0140] This achieves pattern formation of the metal film to form the main surface gate electrode 50 with a predetermined pattern and the main surface source electrode 55 with a predetermined pattern. The main surface gate electrode 50 and the main surface source electrode 55 can be formed by different steps, namely by repeating the metal film formation using a different material and a different pattern formation step.

[0141] Next, with reference to Fig. 13C forms the upper insulating layer 63 with the through-hole 64 and the final insulating layer 65 on the lower insulating layer 61. One step of forming the upper insulating layer 63 and the final insulating layer 65 includes, for example, a step that forms an insulating film such as silicon dioxide by means of a plasma CVD process, and a step in which part of the insulating film (silicon dioxide) is removed after film formation by means of a photolithographic process and an etching process.

[0142] The upper insulating layer 63 and the final insulating layer 65 can be formed from an organic insulating material (for example, a photosensitive resin material such as polyimide). In this case, one step of forming the upper insulating layer 63 and the final insulating layer 65 includes, for example, a step in which a liquid-type photosensitive resin material, which is to be a base for each of the insulating layers, is coated onto the upper surface 52 of the main surface gate electrode 50 and the upper surface 56 of the main surface source electrode 55 by a spin coating process, and a step in which the photosensitive resin material is cured by exposure after coating, and subsequently, after curing, the photosensitive resin material is removed by development (for example, a wet etching process).

[0143] Next, with reference to Fig. 13D a metal film 78 is formed over the entire area of ​​the first main surface 11 to cover the upper insulating layer 63. The metal film 78 is formed, for example, by a vapor deposition process or a sputtering process.

[0144] Next, with reference to Fig. 13E A portion of the metal film 78 is removed after film formation by a photolithographic process and an etching process. This achieves pattern formation on the metal film 78 to form the gate pad 70 with a predetermined pattern and the source pad 75 with a predetermined pattern. The gate pad 70 and the source pad 75 can be formed by a different step or steps, namely by repeating a step of metal film formation using a different material and a different pattern formation step.

[0145] Next, the liquid-type organic insulating material (photosensitive resin material), which is to form the basis of the protective insulating layer 66, is coated onto the upper surface of the semiconductor layer 10 by means of a spin coating process, in a state that is in Fig. Figure 13E is shown. Next, the photosensitive resin material is cured after coating by exposure to light, and after curing, the photosensitive resin material is removed by development (for example, a wet etching process). This forms the protective insulating layer 66 with a predetermined pattern.

[0146] Next, a drain electrode 40, covering the second main surface 12, is formed. The drain electrode 40 is formed (film formation) by, for example, a vapor deposition or sputtering process. Following this, the semiconductor layer 10 is cut by a dicing step using a dicing knife, a laser irradiation process, etc., and the semiconductor component 1 is cut out of the semiconductor layer 10. The semiconductor component 1 is fabricated by these steps, including the one described above.

[0147] Fig. Figure 14 is a cross-sectional view showing a modified example of the structure of the outer circumferential section (circumferential edge section) of the semiconductor device 1 (semiconductor layer 10). Fig. Figure 12 shows a configuration example where the protective insulating layer 66 sits on or rests on the source pad 75. However, the protective insulating layer 66 can be separated or spaced from the source pad 75 such that the final insulating layer 65 is exposed to a region between the protective insulating layer 66 and the source pad 75. In this case, the final insulating layer 65 can be an inorganic insulating film. Furthermore, the source pad 75 can be an aluminum-based metal. In this case, a bond wire can be bonded to the source pad 75.

[0148] If the metal plate is bonded to the Source-Pad 75 by soldering, a nickel / gold plating layer or a nickel / palladium / gold plating layer can be laminated onto the Source-Pad 75. The dashed section of the Fig. Figure 14 shows a plating layer where the plating layer is laminated onto the source pad 75. According to the arrangement of the Fig. 14. The plating layer can be formed stably, compared to the arrangement of the Fig. 12.

[0149] Accordingly, semiconductor component 1 includes the vertical transistor 2. Semiconductor component 1 includes semiconductor layer 10, main-area gate electrode 50, main-area source electrode 55, gate pad 70, and drain electrode 40. Semiconductor layer 10 contains SiC as a major component and has the first main-area 11 and the second main-area 12 on the side opposite the first main-area 11. The main-area gate electrode 50 covers part of the first main-area 11.

[0150] The main surface source electrode 55 covers a portion of the first main surface 11 at a distance or interval from the main surface gate electrode 50. The gate pad 70 is located on the side opposite the semiconductor layer 10 with respect to the main surface gate electrode 50, such that it at least partially overlaps the main surface gate electrode 50 in a top view and is electrically connected to it. The gate pad 70 also covers a portion of the main surface source electrode 55 in a top view.

[0151] Furthermore, from another perspective, the semiconductor component 1 comprises the semiconductor layer 10, the vertical transistor 2 (switching component), the main-area gate electrode 50 (first electrode), the main-area source electrode 55 (second electrode), the gate pad 70 (first terminal electrode), the source pad 75 (second terminal electrode), and the drain electrode 40. The semiconductor layer 10 has the first main-area 11 (main surface). The vertical transistor 2 is formed within the semiconductor layer 10. The main-area gate electrode 50 is located on the first main-area 11 and is electrically connected to the vertical transistor 2.

[0152] The main surface source electrode 55 is located on the first main surface 11 at a distance from the main surface gate electrode 50 and is electrically connected to the vertical transistor 2. The gate pad 70 has a section that overlaps with the main surface gate electrode 50 in a top view and a section that overlaps with the main surface source electrode 55, and is electrically connected to the main surface gate electrode 50. The source pad 75 has a section that overlaps with the main surface source electrode 55 in a top view and is electrically connected to the main surface source electrode 55. The drain electrode 40 is electrically connected to the second main surface 12.

[0153] Assuming that, instead of the gate pad 70 according to the present embodiment, the main-area gate electrode 50 is used as an electrode pad for wire bonding (i.e., in the case of a conventional arrangement), a main-area gate electrode 50 of the same size as the gate pad 70 is required. A region of the semiconductor layer 10 covered by the main-area gate electrode 50 becomes the inactive region 4. Therefore, the area that can be used as the active region 3 is reduced. As a result, the efficient use of the semiconductor layer 10 is prevented, which has a detrimental effect on reducing the size and cost of the semiconductor device.

[0154] In contrast, according to the semiconductor device 1, the gate pad 70 is formed, which overlaps the main-area gate electrode 50 and the main-area source electrode 55 in a top view. According to this structure, the design rules of the main-area gate electrode 50 are relaxed by means of the gate pad 70, and the area of ​​the main-area gate electrode 50 can be reduced. Therefore, the active region 3 can be enlarged. Furthermore, according to this structure, the gate pad 70, to which a wire bond is provided, can be formed in a size larger than a specified dimension, while avoiding restrictions on the design rules resulting from the main-area gate electrode 50.

[0155] This means that in semiconductor device 1, design rules derived from the main-area gate electrode 50, etc., are relaxed to improve the design freedom. According to this arrangement, the need to increase the chip size to expand the active region 3 is eliminated. That is, while avoiding an increase in chip size, the active region 3 can be expanded. This allows semiconductor layer 10 to be used effectively to provide semiconductor device 1, which is capable of reducing size and cost.

[0156] The vertical transistor 2 can contain a source, a gate, and a drain. More precisely, the vertical transistor 2 can contain the source region 17, which is formed on the front surface of the semiconductor layer 10 on the side of the first main surface 11; the gate insulating layer 23 (gate insulating film), which covers the source region 17; the gate electrode 20, which is located opposite the source region 17 across the gate insulating layer 23; and the drain region, which is formed inside the semiconductor layer 10. In the structure described above, the main surface gate electrode 50 is electrically connected to the gate electrode 20, the main surface source electrode 55 is electrically connected to the source region 17, and the drain electrode 40 is electrically connected to the drain region.

[0157] The semiconductor device 1 can include the upper insulating layer 63, which is positioned in a direction perpendicular to the first main surface 11 between the gate pad 70 and the main surface source electrode 55. According to this structure, the upper insulating layer 63 is able to be arranged in such a way that the gate pad 70 overlaps a portion of the main surface source electrode 55 in a top view. The side surface 63a of the upper insulating layer 63 can be located within a plane extending in a direction perpendicular to the first main surface 11. According to this structure, the upper insulating layer 63 can be formed by an etching process.

[0158] When the source pad 75 is electrically connected to the main surface source electrode 55, the end section 79 of the source pad 75 is preferably positioned on the upper insulating layer 63 on the side of the gate pad 70. According to this structure, the source pad 75 can be formed stably. More precisely, it is possible to easily adjust the shape of the source pad 75, etc.

[0159] The semiconductor device 1 can include the protective insulating layer 66, which covers the interface 80 (gap or gap) between the gate pad 70 and the source pad 75. According to this structure, the ingress of water, etc., into the interface 80 can be suppressed. This increases the reliability of the semiconductor device 1. In this case, a section of the protective insulating layer 66, positioned at the interface 80, can extend across the upper insulating layer 63 opposite the main surface source electrode 55.

[0160] A process for fabricating the semiconductor component 1 comprises a first step, a second step, and a third step. In the first step, the semiconductor layer 10 is prepared such that it contains SiC as a major component and has the first main surface 11 and the second main surface 12 on the side opposite the first main surface 11. The semiconductor layer 10 contains the vertical transistor 2. In the second step, the main surface gate electrode 50 and the main surface source electrode 55 are formed at a distance from each other on the first main surface 11.

[0161] In the third step, the gate pad 70 is formed in a region located on the side opposite the semiconductor layer 10 with respect to the main-area gate electrode 50, such that it is electrically connected to the main-area gate electrode 50. The gate pad 70 is formed so that it overlaps at least a portion of the main-area gate electrode 50 and also a portion of the main-area source electrode 55 in a top view. According to the manufacturing process, it is possible to produce and supply the semiconductor device 1, which is able to avoid an increase in chip size and also to expand the active region 3.

[0162] In the first preferred embodiment, an example is shown in which the wide section 72 is shaped in an umbrella shape towards both the negative side and the positive side in the x-axis direction (see Fig. 3, etc.). However, the wide section 72 can have an arrangement in which it spreads out in an umbrella shape only towards the positive side in the x-axis direction (see Fig. 10). In this arrangement as well, the gate pad 70 (wide section 72) is designed to overlap the active region 3 (main surface source electrode 55) in a top view.

[0163] In the first preferred embodiment, an example is shown in which the main surface gate electrode 50 extends from the electricity receiving section 50a in the y-axis direction (see Fig. 3, etc.). However, the main surface gate electrode 50 can have an arrangement in which, starting from the electricity receiving section 50a, it extends not only in the y-axis direction but also in the x-axis direction (see Fig. 11). In this arrangement as well, the gate pad 70 (wide section 72) is designed to overlap the active region 3 (main surface source electrode 55) in the top view.

[0164] Fig. Figure 15 is a cross-sectional view of a semiconductor component 101 according to the second preferred embodiment. Fig. 15 shows a cross-section along a line XV-XV in Fig. 16. Fig. Figure 16 is a top view of the semiconductor component 101 according to the second preferred embodiment. Fig. Figure 16 shows an outer edge 70b of a gate pad 70, an outer edge 75a of a source pad 75, an inner edge 75b of the source pad 75 and an outer edge 170b of a current sensing pad 170 by dashed lines.

[0165] Fig. 17 is a top view, in which the opposite side is in Fig. In the top view shown in 16, a protective insulating layer 66 has been removed. Fig. 17 is a main surface source electrode 55 shown by dashed lines. Fig. Figure 18 is a top view of an upper surface of an electrode of the semiconductor device 101 onto a plane parallel to a front surface of a substrate, viewed from a position of line XVIII-XVIII in Fig. 15. Fig. Figure 18 is a top view when the semiconductor component 101 is viewed from the positive side of a z-axis through the gate pad 70, the source pad 75 and the current sensing pad 170, as shown in Fig. 16 is shown.

[0166] Although this in Fig. 15, Fig. 16, Fig. 17 to Fig. As shown in Figure 18, the semiconductor component 101, like the first embodiment, includes a vertical transistor 2 that allows current to flow in one thickness direction of a semiconductor layer 10. The semiconductor component 101 (second preferred embodiment) differs from the semiconductor component 1 (first preferred embodiment) mainly in that it further comprises a current-sensing electrode and an electrode pad connected to the current-sensing electrode. In the semiconductor component 101, the current-sensing electrode is smaller than the electrode pad. A difference from the first preferred embodiment is described below, with common sections of the description being omitted or simplified.

[0167] With reference to Fig. 15, Fig. 16, Fig. 17 to Fig. Figure 18 of the semiconductor component 101 includes a main-area gate electrode 50 (first electrode), a main-area source electrode 55 (second electrode), and a current-sensing electrode 150 as an example of a third electrode. The main-area gate electrode 50 and the main-area source electrode 55 differ from each other in terms of arrangement, distribution, and shape compared to the first preferred embodiment, but are essentially the same. Therefore, the description of the main-area gate electrode 50 and the main-area source electrode 55 is omitted.

[0168] The current sensing electrode 150 is arranged in a top view at a distance from the main surface gate electrode 50 and the main surface source electrode 55. The current sensing electrode 150 can be arranged on an outer circumferential section (circumferential edge section) of the semiconductor layer 10 (first main surface 11) in a top view. The current sensing electrode 150 can be arranged in a region that includes a central position of the semiconductor layer 10 (first main surface 11) in a top view. The current sensing electrode 150 can be arranged in a region that is surrounded by the main surface source electrode 55 in a top view. That is, the main surface source electrode 55 can be arranged such that it surrounds a circumference of the current sensing electrode 150 in a top view.

[0169] The current sensing electrode 150 corresponds to a section in which a portion of the main surface source electrode 55 is separated or delimited according to the first preferred embodiment. Although not shown, a FET structure is formed below the current sensing electrode 150. The FET structure on the side of the current sensing electrode 150 is formed in a similar manner to the FET structure formed below the main surface source electrode 55 (see also Fig. 1 and Fig. 2).

[0170] In this embodiment, the FET structure includes a main cell region located below the main surface source electrode 55 and a current sensing cell region (sense cell region) located below the current sensing electrode 150. The main cell region conducts a drain current. The current sensing cell region is formed to sense or detect the drain current. In other words, the semiconductor device 101 includes the main cell region located at the first main surface 11 and the current sensing cell region located at a region different from the main cell region on the first main surface 11.

[0171] The FET structure is formed in both the main cell region and the current sensing cell region. The FET structure on the main cell region side is configured as a main FET structure (main component / element) for generating a drain current as a main current. The FET structure on the current sensing cell region side is configured as a sensing FET structure (sensing component / element) for generating a sensing current that detects the drain current. In this embodiment, the FET structure on the main cell region side and the FET structure on the current sensing cell region side have the same structure.

[0172] The main surface source electrode 55 is located in a region that overlaps with the main cell region (FET main structure) in a top view and is electrically connected to a source region 17 of the main cell region (FET main structure). The current sensing electrode 150 is located in a region that overlaps with the current sensing cell region (FET sensing structure) in a top view and is electrically connected to a source region 17 of the current sensing cell region (FET sensing structure).

[0173] In the vertical transistor 2 according to the semiconductor component 101, a drain current flows from a drain electrode 40 to a source region 17 on the side of the main cell region, and a sensing current flows from the drain electrode 40 to the source region 17 on the side of the sensing cell region. This causes the drain current to be taken out of the main surface source electrode 55, and the sensing current to be taken out of the current sensing electrode 150.

[0174] The FET sensing structure can be arranged to generate the sensing current in conjunction with the drain current, through on / off control synchronously with the main FET structure. This means that the same gate voltage can be applied to the main cell region and the current sensing cell region simultaneously. The main cell region has a larger area than the current sensing cell region. In this embodiment, the main cell region differs from the current sensing cell region only in its area. Therefore, a current flows in the current sensing cell region that is proportional to the area ratio of the main cell region to the current sensing cell region.

[0175] This means that the sensing current of the FET sensing structure can be smaller than the main current of the FET main structure. The main cell region may be no less than 100 times and no more than 10,000 times the area of ​​the current sensing cell region. In this case, the current flowing in the current sensing electrode 150 is no less than 1 / 10,000 and no more than 1 / 100 of the current (drain current) flowing in the main area source electrode 55.

[0176] Even if a relatively large drain current occurs due to certain factors, it is therefore possible to reduce the current flowing through the current sensing electrode 150. For example, the maximum current flowing through the current sensing electrode 150 can be suppressed or limited to approximately 1 A. Consequently, the current sensing electrode 150 can be used to appropriately detect an increase in current within a predetermined current sensing range.

[0177] The current sensing electrode 150 can contain a non-metallic conductor or a metal. The current sensing electrode 150 is preferably made of an aluminum-based metal material. Examples of aluminum-based metal materials for the current sensing electrode 150 include aluminum, an aluminum-silicon (Al-Si)-based alloy, an aluminum-copper (Al-Cu)-based alloy, etc. It is understood that the current sensing electrode 150 can also be made of conductive polysilicon, tungsten, titanium, nickel, copper, silver, gold, titanium nitride (metal nitride), etc. The current sensing electrode 150 can be made of the same material as the main surface gate electrode 50 and the main surface source electrode 55.

[0178] With reference to Fig. In 15, the current sensing electrode 150 is provided on a lower insulating layer 61, which has one or more source contact holes 61b. The current sensing electrode 150 is electrically connected to the source region 17 of the current sensing cell region via the source contact holes 61b.

[0179] The current sensing electrode 150 is smaller in a top view than the current sensing pad 170, which is described later. The current sensing electrode 150 can be square or rectangular. The length of one side of the current sensing electrode 150 is not less than 5 µm and not greater than 50 µm. For example, the current sensing electrode 150 can be square, with dimensions of approximately 20 µm × 20 µm. With reference to Fig. In this embodiment, the current sensing electrode 150 has the same size as an electricity receiving section 50a of the main surface gate electrode 50.

[0180] It is understood that the current sensing electrode 150 can be smaller than the current receiving section 50a. The current sensing electrode 150 can also be larger than the current receiving section 50a. The current sensing electrode 150 can have an area not greater than 20% of the area of ​​the semiconductor layer 10 (first principal area 11) in a top view. Preferably, the current sensing electrode 150 has an area not greater than 10% of the area of ​​the semiconductor layer 10 (first principal area 11).

[0181] With reference to Fig. 15, Fig. 16 to Fig. Figure 17 includes the semiconductor component 101 comprising the gate pad 70 (first electrode pad), the source pad 75 (second electrode pad), and the current sensing pad 170 as an example of the third electrode pad. The gate pad 70 and the source pad 75 differ from each other in terms of arrangement, distribution, and shape compared to those of the first preferred embodiment, but are essentially the same. A description of the gate pad 70 and the source pad 75 is omitted.

[0182] The current sensing pad 170 overlaps the current sensing electrode 150 in a top view and is electrically connected to the current sensing electrode 150. The current sensing pad 170 is positioned at a distance from the gate pad 70 and the source pad 75. The current sensing pad 170 can be located in a region that includes a center position of the semiconductor layer 10 (first principal surface 11) in a top view. The current sensing pad 170 can be located in a region surrounded by the source pad 75. That is, the source pad 75 can be positioned to surround a perimeter of the current sensing pad 170.

[0183] In this embodiment, the current sensing pad 170 is similar in arrangement to the gate pad 70. With reference to Fig. Figure 15 includes the current sensing pad 170, more precisely a column section 171 as an example of the lower conductive layer or conduction layer, and a wide section 172 as an example of the upper conductive layer or conduction layer. The column section 171 is provided on the current sensing electrode 150. The column section 171 is connected to an upper surface 152 of the current sensing electrode 150 and is formed in a column shape that extends in a normal direction (z-axis direction) with respect to the upper surface 152. The column section 171 is connected to the current sensing electrode 150 via a through-hole 164 provided in an upper insulating layer 63.

[0184] The height of column section 171 (length in the z-axis direction) is greater than the thickness of the upper insulating layer 63 (length in the z-axis direction). More precisely, the height of column section 171 is equal to the thickness of a section of the upper insulating layer 63 positioned on the current sensing electrode 150. A side surface 174 of column section 171 can be flush with a side surface 153 of the current sensing electrode 150. The side surface 174 of column section 171 can be positioned inside, or within, the current sensing electrode 150 with respect to the side surface 153 of the current sensing electrode 150.

[0185] The wide section 172 is located at the upper end of the column section 171. The wide section 172 is a section in which the upper end of the column section 171 widens or extends in size. That is, the wide section 172 has a surface area larger than that of the column section 171 in plan view. The wide section 172 is designed such that the column section 171 is positioned inside the wide section 172 in plan view. The size and shape of the wide section 172 are adapted to those of the current sensing pad 170 in plan view. A portion of the upper surface 173 of the wide section 172, which overlaps with the column section 171 in plan view, is recessed or set back towards the current sensing electrode 150.

[0186] The upper surface 173 of the wide section 172 is used to electrically connect the semiconductor device 101 and other circuits. For example, the upper surface 173 of the wide section 172 is connected to a control circuit that controls the semiconductor device 101 based on a detected current. A metal wire can be connected to the upper surface 173 of the wide section 172 by wire bonding. The metal wire can contain at least one type of aluminum, copper, and gold. In this embodiment, an aluminum wire is wedge-bonded to the current-sensing pad 170 (upper surface 173 of the wide section 172). A metal plate can be connected to the upper surface 173 of the wide section 172 by soldering instead of wire bonding.

[0187] The current sensing pad 170 has an area not greater than 20% of the area of ​​the semiconductor layer 10 (first principal surface 11) in the top view. Preferably, the current sensing pad 170 has an area not greater than 10% of the area of ​​the semiconductor layer 10 (first principal surface 11) in the top view. The wide section 172 (i.e., the current sensing pad 170) has a larger area than the current sensing electrode 150 in the top view. The area of ​​the wide section 172 may be no less than 200 times and no more than 40,000 times the area of ​​the current sensing electrode 150. The area of ​​the wide section 172 may also be no less than 400 times larger than the area of ​​the current sensing electrode 150. For example, the area of ​​the wide section 172 could be approximately 2,500 times larger than the area of ​​the current sensing electrode 150.

[0188] To properly perform a wire bond, the wide section 172 (current sensing pad 170) must be larger than a specified size. The wide section 172 preferably has an area not less than 800 µm × 800 µm and not greater than 1 mm × 1 mm in a top view. In this case, the wide section 172 can be square in a top view. In this case, a connection of the metal wire can be made in any given direction.

[0189] It is understood that the wide section 172 can be formed in a square shape larger than 1 mm × 1 mm in a top view. Furthermore, the wide section 172 can be formed in a rectangular shape not smaller than 400 µm × 800 µm in a top view. In this embodiment, the wide section 172 has the same size as the wide section 72 of the gate pad 70. It is understood that the size of the wide section 172 can be smaller than or larger than the size of the wide section 72.

[0190] Column section 171 and wide section 172 can be made of the same conductive material. Column section 171 and wide section 172 can be made of an aluminum-based metal. It is understood that column section 171 and wide section 172 can be made of titanium, nickel, copper, silver, gold, tungsten, etc. Column section 171 and wide section 172 can be made of different conductive materials. The current sensing pad 170 can be made of the same material as gate pad 70 and source pad 75. This allows the current sensing pad 170, gate pad 70, and source pad 75 to be formed in the same step.

[0191] The height of the current sensing pad 170 (length in the z-axis direction) is the sum of the height of the column section 171 (length in the z-axis direction) and the thickness of the wide section 172 (length in the z-axis direction). For example, the height of the current sensing pad 170 may be no less than a few dozen micrometers and no greater than a few hundred micrometers (that is, no less than 20 µm and no less than 1000 µm). Fig. Figure 15 shows an example where the height of the column section 171 is equal to the thickness of the wide section 172. However, the height of the column section 171 can be greater than the thickness of the wide section 172, or it can be less than the thickness of the wide section 172.

[0192] With reference to Fig. In figure 15, the semiconductor component 101 includes an active region 103 and a non-active region 104. The active region 103 is a main region in which a drain current of the vertical transistor 2 flows. More precisely, the active region 103 is a region that, in a top view, overlaps with the main surface source electrode 55 and does not contain a region that overlaps with the main surface gate electrode 50 (in Fig. (15 not shown) and overlaps the current sensing electrode 150. That is, the active region 103 contains a main cell region in which a FET main structure is formed, but does not contain any region other than the main cell region.

[0193] The non-active region 104 is a different region from the active region 103 and is a region in which no drain current of the vertical transistor 2 flows. More precisely, the non-active region 104 is a region that, in a top view, overlaps with the main-area gate electrode 50 and the current-sensing electrode 150, and does not contain a region that overlaps with the main-area source electrode 55. That is, the non-active region 104 includes the current-sensing cell region in which the FET sensing structure is formed, but does not include the main cell region. With reference to Fig. 15 includes the inactive region 104 and a current sensing region 102. The current sensing region 102 includes a region that overlaps with the current sensing electrode 150 in a top view (i.e., the current sensing cell region).

[0194] The semiconductor device 101 incorporates a current sensing pad 170 (wide section 172) that intersects the active region 103 at multiple levels, forming the current sensing electrode 150. According to this structure, a wire bond target changes from the current sensing electrode 150 to the current sensing pad 170. This allows the current sensing electrode 150 to be reduced in size, thereby increasing the size of the active region 103. In other words, in the semiconductor device 101, design rules derived from the current sensing electrode 150 are relaxed by means of the current sensing pad 170 to improve or increase the design freedom.

[0195] More precisely, the current sensing pad 170 has a width greater than that of the current sensing electrode 150 in both the x-axis and y-axis directions, and overlaps with a portion of the main surface source electrode 55 in a top view. This allows the current sensing pad 170 to be formed with a larger size than a specified dimension while avoiding design constraints derived from the current sensing electrode 150. Furthermore, the area of ​​the main surface gate electrode 50 can be reduced, and the area of ​​the active region 103 can be increased. Therefore, the limited area of ​​the semiconductor layer 10 can be efficiently used to provide the semiconductor device 101, which is capable of easily reducing size and cost.

[0196] A configuration similar to the modified example applied to Gate Pad 70 can be applied to Current Sense Pad 170. For example, the configuration shown in Fig. 8 and in Fig. The arrangement shown in Figure 9 (the position and number of through holes, a positional relationship with a bond wire, etc.) is applied to the current sensing pad 170.

[0197] In this embodiment, the arrangement has been described in which the current sensing pad 170 overlaps the current sensing electrode 150 in a top view. However, the current sensing pad 170 may not overlap the current sensing electrode 150 in a top view. In this case, a connecting wiring section (not shown) can be provided that extends from the current sensing pad to a position above the current sensing electrode, such that it passes through the through-hole to the current sensing electrode 150. In this case, the main surface source electrode 55 can be located in a region below the current sensing pad and the connecting wiring section.

[0198] Accordingly, the semiconductor component 101 includes the vertical transistor 2. The semiconductor component 101 includes the active region 103, the inactive region 104, the main area gate electrode 50 (first electrode), the main area source electrode 55 (second electrode), the current sensing electrode 150 (third electrode), the gate pad 70 (first electrode pad), the source pad 75 (second electrode pad) and the current sensing pad 170 (third electrode pad).

[0199] The active region 103 is located in semiconductor layer 10. Active region 103 contains the main cell region, which carries a drain current. The inactive region 104 is located in a region distinct from active region 103, specifically in semiconductor layer 10. Inactive region 104 contains the current sensing cell region, which carries a sensing current to detect the drain current. The main area gate electrode 50 is positioned so that, in a top view, it overlaps a region other than the main cell region. The main area source electrode 55 is positioned so that, in a top view, it overlaps the main cell region, but at a distance from the main area gate electrode 50.

[0200] The gate pad 70 is located on the side opposite the semiconductor layer 10 with respect to the main surface gate electrode 50, such that in a top view it overlaps at least partially with the main surface gate electrode 50 and is electrically connected to it. In a top view, the gate pad 70 also overlaps a portion of the main surface source electrode 55. The source pad 75 is arranged at a distance from the gate pad 70. The source pad 75 is located on the side opposite the semiconductor layer 10 with respect to the main surface source electrode 55, such that in a top view it overlaps at least partially with the main surface source electrode 55 and is electrically connected to it.

[0201] The current sensing pad 170 is arranged at a distance from the gate pad 70 and the source pad 75 in a top view. The current sensing pad 170 is positioned on the side opposite the semiconductor layer 10 with respect to the current sensing electrode 150, such that in a top view it at least partially overlaps the current sensing electrode 150 and is electrically connected to it. In this embodiment, the current sensing pad 170 also overlaps a portion of the main surface source electrode 55 in a top view.

[0202] Assuming that, instead of the current sensing pad 170 according to the present preferred embodiment, the current sensing electrode 150 is used as an electrode pad for wire bonding, a current sensing electrode 150 of the same size as the current sensing pad 170 is required. Since a region of the semiconductor layer 10 covered by the current sensing electrode 150 becomes the inactive region 104, the area that can be used as the active region 103 is reduced. Therefore, the efficient use of the semiconductor layer 10 is prevented, which has a detrimental effect on reducing the size and cost of the semiconductor device.

[0203] In contrast, according to the semiconductor component 101, the current sensing pad 170 is formed, which overlaps with the current sensing electrode 150 and the main surface source electrode 55 in a top view. According to this structure, the design rules of the current sensing electrode 150 are relaxed by the current sensing pad 170, and the area of ​​the current sensing electrode 150 can be reduced. This allows the active region 103 to be enlarged. Furthermore, the current sensing pad 170, on which a wire bond is applied, can be formed with a size larger than a specified value, while avoiding restrictions on design rules derived from the current sensing electrode 150.

[0204] This means that in the semiconductor component 101, the design rules derived from the current sensing electrode 150, etc., are relaxed to increase or improve the design freedom. According to this arrangement, the need to increase the chip size to expand the active region 103 is eliminated. That is, while avoiding an increase in chip size, the active region 103 can be expanded. Consequently, the semiconductor layer 10 can be effectively used to provide the semiconductor component 101, which is capable of reducing size and cost.

[0205] The semiconductor device 101 is manufactured using the same manufacturing process as the process for manufacturing the semiconductor device 1. More precisely, the semiconductor device 101 is manufactured by modifying the pattern formation step of the main area gate electrode 50, the main area source electrode 55 and the current sensing electrode 150, the pattern formation step of the insulating layer 60 and the pattern formation step of the gate pad 70, the source pad 75 and the current sensing pad 170 in the process for manufacturing the semiconductor device 1, each compared to the corresponding steps in the semiconductor device 101.

[0206] Fig. Figure 19 is a top view of a semiconductor component 101a according to a modified example of the second preferred embodiment (a protective insulating layer 66 is not shown). Fig. Figure 20 is a top view of an upper surface of an electrode of the semiconductor component 101a according to the modified example of the second preferred embodiment. Fig. 19 and Fig. 20 correspond Fig. 17 or Fig. 18. In the second preferred embodiment, an example has been described in which the gate pad 70 has the wide section 72 and the current sensing pad 170 has the wide section 172. As described in Fig. 19 and in Fig. However, as shown in Figure 20, such a configuration can be used in which the gate pad 70 does not have the wide section 72 and the current sensing pad 170 has the wide section 172.

[0207] More precisely, in semiconductor device 101a, the gate pad 70a has the same size and shape as the main surface gate electrode 50A in a top view. That is, the main surface gate electrode 50A of semiconductor device 101a is larger in a top view than the current receiving section 50a of the main surface gate electrode 50 of semiconductor device 101. A current sensing electrode 150 and a current sensing pad 170 have a similar arrangement to that of semiconductor device 101. That is, semiconductor device 101a includes the current sensing electrode 150 as an example of the first electrode and includes the current sensing pad 170 as an example of the first electrode pad.

[0208] Accordingly, an arrangement (more precisely, the current sensing pad 170) is applied to the semiconductor component 101a in which only the current sensing electrode 150 is enlarged in terms of its area in the top view. That is, the current sensing electrode 150 of the semiconductor component 101a overlaps in a top view with part of a main surface source electrode 55 and is electrically connected to one of a plurality of source electrodes 30. In this case, the current sensing electrode is considered an example of a first electrode, and the current sensing pad 170 is considered an example of a first electrode pad.

[0209] Accordingly, the current sensing pad 170 is formed according to the semiconductor component 101a, overlapping the current sensing electrode 150 and the main surface source electrode 55 in a top view. According to this structure, the design rules of the current sensing electrode 150 are relaxed by means of the current sensing pad 170, and the area of ​​the current sensing electrode 150 can be reduced. This allows the active region 103 to be enlarged. Furthermore, according to this structure, the current sensing pad 170, to which a wire bond is applied, can be formed in a size larger than a specified dimension, while avoiding restrictions on the design rules derived from the current sensing electrode 150.

[0210] This means that in the semiconductor device 101a, design rules derived from the current sensing electrode 150, etc., are relaxed to increase the design freedom. According to this arrangement, the need to increase the chip size to extend the active region 103 is eliminated. That is, while avoiding an increase in chip size, the active region 103 can be extended. This allows the semiconductor layer 10 to be effectively used to provide the semiconductor device 101a, which is capable of reducing size and cost.

[0211] Fig. Figure 21 is a cross-sectional view of a semiconductor component 201 according to the third preferred embodiment. Fig. 21 shows a cross-section along a line XXI-XXI in Fig. 22. Fig. Figure 22 is a top view of the semiconductor component 201 according to the third preferred embodiment. Fig. 22 are an outer rim 70b of a gate pad 70, an outer rim 75a of a source pad 75, an inner rim 75b of the source pad 75, an outer rim 270a of an anode electrode pad 270 and an outer rim 275a of a cathode electrode pad 275 shown by dashed lines. Fig. 23 is a top view, in which, compared to the top view of Fig. 22 a protective insulating layer 66 is removed. In Fig. 23 is a main surface source electrode 55 shown by dashed lines.

[0212] Fig. Figure 24 is a top view of the semiconductor component 201 onto a plane parallel to a front surface of a substrate, viewed from a position along line XXIV-XXIV in Fig. 21. More precisely, Fig. 24 a top view when the semiconductor component 201 is viewed from the positive side of a z-axis through the gate pad 70, the source pad 75, the anode electrode pad 270 and the cathode electrode pad 275, which are in Fig. 23 are shown.

[0213] With reference to Fig. 21, Fig. 22, Fig. 23 to Fig. 24 The semiconductor device 201 (third preferred embodiment) differs from the semiconductor device 1 (first preferred embodiment) mainly in that it includes a diode 290 (first conductive layer). The main difference compared to the first preferred embodiment is described below, and generally applicable descriptions are omitted or simplified. More precisely, the semiconductor device 201 includes an insulating layer 260 covering part of a first principal area 11 of a semiconductor layer 10, and the diode 290 provided on the insulating layer 260.

[0214] In this embodiment, the diode 290 is a pn-type diode comprising polysilicon, a p-type semiconductor layer 291 formed within the polysilicon, and an n-type semiconductor layer 292 formed within the polysilicon. For example, the p-type semiconductor layer 291 is polysilicon doped with a p-type impurity, and the n-type semiconductor layer 292 is polysilicon doped with an n-type impurity. The n-type semiconductor layer 292 is connected to the p-type semiconductor layer 291, thereby forming a pn junction (pn-diode) together with the p-type semiconductor layer 291.

[0215] Diode 290 is used as a temperature sensor (temperature-sensitive diode) that detects the temperature of the semiconductor component 201 (semiconductor layer 10) by measuring the voltage between the p-type semiconductor layer 291 and the n-type semiconductor layer 292. That is, diode 290 can have a forward voltage characteristic, which exhibits a linear change in response to a change in temperature. The temperature of semiconductor layer 10 is indirectly determined from the voltage characteristics of diode 290.

[0216] The semiconductor component 201 comprises the gate pad 70, the source pad 75, the anode electrode pad 270 (first pole-terminal electrode), and the cathode electrode pad 275 (second pole-terminal electrode). The anode electrode pad 270 and the cathode electrode pad 275 are each represented as an example of a diode electrode pad (pole-terminal electrode). The gate pad 70 and the source pad 75 differ from each other in terms of their arrangement, distribution, and shape, or compared to those of the first embodiment, but they are essentially the same. A description of the gate pad 70 and the source pad 75 is omitted.

[0217] The anode electrode pad 270 is arranged in a region that overlaps the p-type semiconductor layer 291 in a top view, at a distance from the gate pad 70 and the source pad 75, and is electrically connected to the p-type semiconductor layer 291. In this embodiment, the anode electrode pad 270 has the same arrangement and configuration as the gate pad 70.

[0218] With reference to Fig. Figure 21 includes the anode electrode pad 270, more precisely a column section 271 as an example of the lower conductive layer and a wide section 272 as an example of the upper conductive layer. The column section 271 is provided on the p-type semiconductor layer 291. The column section 271 is connected to an upper surface of the p-type semiconductor layer 291 and is formed in a column shape that extends in a normal direction (z-axis direction) onto the upper surface of the p-type semiconductor layer 291.

[0219] The wide section 272 is located at the upper end of the column section 271. The wide section 272 is a section in which the upper end of the column section 271 is enlarged or extended in size. That is, in a plan view, the wide section 272 has an area larger than that of the column section 271. The wide section 272 is designed such that, in a plan view, the column section 271 is positioned inside the wide section 272. In a plan view, the size and shape of the wide section 272 are adapted to those of the anode electrode pad 270.

[0220] An upper surface 273 of the wide section 272 is used to electrically connect the semiconductor component 201 and other circuits. A metal wire can be connected to the upper surface 273 of the wide section 272 by wire bonding. The metal wire can contain at least one type of aluminum, copper, and gold. In this embodiment, an aluminum wire is wedge-bonded to the anode electrode pad 270 (upper surface 273 of the wide section 272).

[0221] To properly perform wire bonding, the wide section 272 (anode electrode pad 270) must be larger than a specified size. The plane shape and size of the wide section 272 can be the same as those of the wide section 72 of the gate pad 70. It is understood that the plane shape and / or size of the wide section 272 may differ from those of the wide section 72.

[0222] Column section 271 and wide section 272 can be formed from the same conductive material. Column section 271 and wide section 272 can be formed from an aluminum-based metal material. It is understood that column section 271 and wide section 272 can be formed from titanium, nickel, copper, silver, gold, tungsten, etc. Column section 271 and wide section 272 can be formed from conductive materials that differ from each other.

[0223] The height of the anode electrode pad 270 (length in the z-axis direction) is the sum of the height of the column section 271 (length in the z-axis direction) and the thickness of the wide section 272 (length in the z-axis direction). The height of the anode electrode pad 270, for example, may be no less than a few dozen micrometers and no greater than a few hundred micrometers (that is, no less than 20 µm and no less than 1000 µm). The height of the column section 271 may exceed the thickness of the wide section 272 or it may be less than the thickness of the wide section 272. It is understood that the height of the column section 271 may be equal to the thickness of the wide section 272.

[0224] The cathode electrode pad 275 is arranged in a region that overlaps the n-type semiconductor layer 292, at a distance from the gate pad 70, the source pad 75, and the anode electrode pad 270, and is electrically connected to the n-type semiconductor layer 292. In this embodiment, the cathode electrode pad 275 is similar in arrangement and design to the gate pad 70 and the anode electrode pad 270.

[0225] With reference to Fig. Figure 21 includes the cathode electrode pad 275, more precisely a column section 276 as an example of the lower conductive layer or conduction layer, and a wide section 277 as an example of the upper conductive layer or conduction layer. The column section 276 is provided on the n-type semiconductor layer 292. The column section 276 is connected to an upper surface of the n-type semiconductor layer 292 and is formed in a column shape that extends in a normal direction (z-axis direction) of the n-type semiconductor layer 292.

[0226] The wide section 277 is located at the upper end of the column section 276. The wide section 277 is a section in which the upper end of the column section 276 is extended in size. That is, in a plan view, the wide section 277 has an area larger than that of the column section 276. The wide section 277 is designed such that the column section 276 is positioned within the wide section 277 in a plan view.

[0227] In a top view, the size and shape of the wide section 277 are adapted to those of the cathode electrode pad 275. An upper surface 278 of the wide section 277 is used to electrically connect the semiconductor component 201 and other circuits. In this embodiment, the upper surface 278 of the wide section 277 is connected to a voltmeter, etc. A metal wire can be connected to the upper surface 278 of the wide section 277 by wire bonding.

[0228] The anode electrode pad 270 and the cathode electrode pad 275 can each have an area not greater than 20% of the area of ​​the semiconductor layer 10 (first principal area 11) in a top view. Preferably, the anode electrode pad 270 and the cathode electrode pad 275 can each have an area not greater than 10% of the area of ​​the semiconductor layer 10 (first principal area 11) in a top view.

[0229] The anode electrode pad 270 and / or the cathode electrode pad 275 can be arranged in an outer circumferential section (circumferential edge section) of the semiconductor layer 10 (first principal surface 11) in a top view. The anode electrode pad 270 and / or the cathode electrode pad 275 can be arranged in a region that includes a central position of the semiconductor layer 10 (first principal surface 11) in a top view.

[0230] The anode electrode pad 270 and / or the cathode electrode pad 275 can be arranged in a region surrounded by the source pad 75. That is, the source pad 75 can be formed such that it surrounds the anode electrode pad 270 and / or the cathode electrode pad 275.

[0231] The anode electrode pad 270 and the cathode electrode pad 275, for example, are formed from the same material as the gate pad 70 and the source pad 75. This allows the anode electrode pad 270, the cathode electrode pad 275, the gate pad 70, and the source pad 75 to be formed in the same step. The shape, material, etc., of the column section 276 and the wide section 277 belonging to the cathode electrode pad 275 can be the same as those of the column section 276 and the wide section 277 belonging to the anode electrode pad 270. A description of the shape, material, etc., of the column section 276 and the wide section 277 belonging to the cathode electrode pad 275 is omitted.

[0232] With reference to Fig. The semiconductor component 201 includes an active region 203 and a non-active region 204. The active region 203 is a main region in which a drain current of a vertical transistor 2 flows. The active region 203 is a region that overlaps with the main surface source electrode 55 in a top view.

[0233] In a top view, the inactive region 204 is a different region from the active region 203 and is a region that does not act as the vertical transistor 2 (a region where no drain current flows). The diode 290 is located in the inactive region 204. That is, in this embodiment, the anode electrode pad 270 and the cathode electrode pad 275 are located in a region that overlaps the inactive region 204, such that in a top view they overlap a portion of the active region 203.

[0234] In the semiconductor device 201, part of the anode electrode pad 270 (wide section 272) overlaps the main area source electrode 55 in a top view. This avoids design rules derived from the diode 290, and the anode electrode pad 270 can be larger than a specified size. Furthermore, the area of ​​the diode 290 can be reduced, and the area of ​​the active region 203 can be increased. Therefore, the limited area of ​​the semiconductor layer 10 can be used efficiently to realize the semiconductor device 201, which is capable of easily reducing size and cost.

[0235] Furthermore, in the semiconductor device 201, a portion of the cathode electrode pad 275 (wide section 277) overlaps with the main surface source electrode 55 in a top view. This allows the cathode electrode pad 275 to be formed with a larger size than specified, while avoiding the design constraints derived from the diode 290. Additionally, the area of ​​the diode 290 can be reduced, and the area of ​​the active region 203 can be increased. Therefore, the limited area of ​​the semiconductor layer 10 is used efficiently to realize the semiconductor device 201, which is capable of easily reducing size and cost.

[0236] Accordingly, the semiconductor device 201 includes the insulating layer 260, the diode 290, the anode electrode pad 270 (first pole terminal electrode), and the cathode electrode pad 275 (second pole terminal electrode). The insulating layer 260 covers part of the first main area 11. The diode 290 is arranged on the insulating layer 260. The diode 290 includes the p-type semiconductor layer 291 (first pole layer) and the n-type semiconductor layer 292 (second pole layer), which forms a pn junction with the p-type semiconductor layer.

[0237] The anode electrode pad 270 has a section that overlaps with the p-type semiconductor layer 291 in a top view and is electrically connected to the p-type semiconductor layer 291. The cathode electrode pad 275 has a section that overlaps with the n-type semiconductor layer 292 in a top view and is electrically connected to the n-type semiconductor layer 292. In this structure, the anode electrode pad 270 and / or the cathode electrode pad 275 overlap with a portion of the main surface source electrode 55 in a top view.

[0238] According to this structure, the anode electrode pad 270 and / or the cathode electrode pad 275 can be formed in a size larger than a specified dimension, while avoiding the design constraints derived from the diode 290. Furthermore, according to this structure, the area of ​​the diode 290 can be reduced, and the area of ​​the active region 203 can be increased. Therefore, the limited area of ​​the semiconductor layer 10 is effectively utilized to realize the semiconductor device 201, which is capable of easily reducing size and cost.

[0239] The semiconductor device 201 is manufactured using the same manufacturing process as the process for manufacturing semiconductor device 1. More precisely, the semiconductor device 201 is manufactured by changing a pattern formation step of the main area gate electrode 50 and the main area source electrode 55, a pattern formation step of the insulating layer 60, and a pattern formation step of the gate pad 70, the source pad 75, the anode electrode pad 270, and the cathode electrode pad 275, each compared to the corresponding steps in the semiconductor device 201.

[0240] Fig. Figure 25 is a top view (a protective insulating layer 66 is not shown) of a semiconductor component 201a according to a modified example of the third preferred embodiment. Fig. Figure 26 is a top view showing an upper surface of an electrode of the semiconductor device 201a according to the modified example of the third preferred embodiment. Fig. 25 and Fig. 26 correspond Fig. 23 or Fig. 24 of the third preferred embodiment. In Fig. 25 is a main surface source electrode 55 shown by dashed lines.

[0241] The example described for semiconductor component 201 is that the gate pad 70 has the wide section 72, the anode electrode pad 270 has the wide section 272, and the cathode electrode pad 275 has the wide section 277. As shown in Fig. 25 and Fig. However, as shown in Figure 26, a configuration can be applied in which the gate pad 70 does not have a wide section 72, in which the anode electrode pad 270 has the wide section 272, and in which the cathode electrode pad 275 has the wide section 277.

[0242] A gate pad 70a belonging to the semiconductor device 201a has the same size and shape as a main-area gate electrode 50A in a top view. That is, the main-area gate electrode 50A belonging to the semiconductor device 201a is larger than the electricity receiving section 50a of the main-area gate electrode 50 belonging to the semiconductor device 201, in a top view.

[0243] Accordingly, the semiconductor device 201a can also reduce the area of ​​a diode 290 and increase the area of ​​an active region 203. Therefore, the limited region of a semiconductor layer 10 is effectively used to realize the semiconductor device 201a, which is able to easily reduce the size and cost.

[0244] Fig. 27 and Fig. Figures 28 are each a drawing showing a semiconductor component 201b according to a further modified example of the third embodiment. Fig. Figure 27 is a top view (a protective insulating layer 66 is not shown) of the semiconductor component 201b. Fig. Figure 28 is a top view showing an upper surface of an electrode in the semiconductor device 201b. Fig. 27 is a main surface source electrode 55 shown by dashed lines. Fig. Figure 28 shows that a diode 290 is arranged on a main surface source electrode 55.

[0245] With reference to Fig. 27 and Fig. 28 includes the semiconductor component 201, as well as the semiconductor component 201b, the diode 290, an anode electrode pad 270 and a cathode electrode pad 275. In this embodiment, the diode 290 is arranged in a top view in the vicinity of a central section of a chip (in the vicinity of a central section of a first main surface 11).

[0246] In this embodiment, the anode electrode pad 270 and the cathode electrode pad 275 are arranged on a circumferential edge of the chip (circumferential edge section of the first main surface 11) in a top view. The anode electrode pad 270 and / or the cathode electrode pad 275 (both in this embodiment) are arranged at a distance from the diode 290 so that they do not overlap the diode 290 in a top view. In this embodiment, the anode electrode pad 270 overlaps completely with the main surface source electrode 55 in a top view. Furthermore, the cathode electrode pad 275 overlaps completely with the main surface source electrode 55 in a top view.

[0247] The semiconductor device 201b comprises a first interconnect 250a, a first finger 250, a second interconnect 255a, and a second finger 255. The first interconnect 250a is positioned directly on a p-type semiconductor layer 291 of the diode 290. The first finger 250 is located between the anode electrode pad 270 and the first interconnect 250a, connecting the anode electrode pad 270 and the first interconnect 250a.

[0248] The first finger section 250 extends in a line (band shape) in a region that, in a top view, lies between the anode electrode pad 270 and the first connecting section 250a. In this embodiment, the first finger section 250 extends in an x-axis direction in a top view. At least a portion of the first finger section 250 overlaps the main surface source electrode 55 in the top view.

[0249] The second interconnect section 255a is positioned directly on an n-type semiconductor layer 292 of the diode 290. The second finger section 255 is located between the cathode electrode pad 275 and the second interconnect section 255a, connecting the cathode electrode pad 275 and the second interconnect section 255a. The second finger section 255 extends in a line (band shape) in a region that, in a top view, lies between the cathode electrode pad 275 and the second interconnect section 255a.

[0250] In this embodiment, the second finger section 255 is positioned at a distance in the y-axis direction from the first finger section 250 in a top view and extends in the x-axis direction. That is, the second finger section 255 extends parallel to the first finger section 250 in a top view. At least a portion of the second finger section 255 overlaps with the main surface source electrode 55 in a top view.

[0251] There is a tendency for the temperature to rise in a central section of the chip (semiconductor layer 10), unlike at or compared to a peripheral edge section of the chip (semiconductor layer 10). Therefore, if the diode 290, which functions as a temperature sensor, is provided, the diode 290 is preferably arranged in the top view at the central section of the chip (semiconductor layer 10). On the other hand, with regard to the arrangement and mounting of the wire bonding, etc., the electrode pad is preferably arranged at an end section (a peripheral edge section) of the chip, where there are few obstructions.

[0252] In a conventional case, a region directly below a plurality of electrode pads for a temperature sensor, which is arranged at an end section (a circumferential edge section) of a chip (semiconductor layer 10), and a region directly below a wiring from the electrode pads to the central section of the chip (semiconductor layer 10) are formed as a non-active region. In this respect, according to the structure of the semiconductor device 201b, in addition to a region directly below the anode electrode pad 270 and the cathode electrode pad 275, a region directly below the first finger section 250 and the second finger section 255 can be used as the active region 203.

[0253] Fig. 29 and Fig. Figure 30 each represents a drawing showing a semiconductor package 300 according to the fourth preferred embodiment. Fig. Figure 30 is a drawing showing an internal structure of the semiconductor package 300. Fig. 29 shows, namely when viewed from the opposite side to that of the Fig. 29.

[0254] The semiconductor package 300 is a TO (transistor outline) type semiconductor package. The semiconductor package 300 includes a main package body 301, a terminal 302d, a terminal 302g, a terminal 302s, a bond wire 303g, a bond wire 303s, and a semiconductor component 1. Hereinafter, the terminal 302d, the terminal 302g, and the terminal 302s may be collectively referred to simply as "terminals 302d to 302s".

[0255] The main body of the casing 301 is formed in a rectangular parallelepiped shape. The main body of the casing 301 is formed, for example, from an epoxy resin containing carbon and glass fibers, etc. Each of the terminals 302d to 302s projects from a bottom section of the main body of the casing 301 and is arranged sequentially in a line. The terminals 302d to 302s can be made of aluminum. The terminals 302d to 302s can be made of other metallic materials, such as copper, etc.

[0256] The semiconductor component 1 is housed inside the main body of the casing 301. That is, the main body of the casing 301 is designed as a sealing element to seal the semiconductor component 1. A gate pad 70, belonging to the semiconductor component 1, is electrically connected to the terminal 302g via the bond wire 303g, etc., inside the main body of the casing 301.

[0257] A source pad 75 belonging to the semiconductor component 1 is electrically connected to terminal 302s via bond wire 303s, etc. A drain electrode 40 belonging to the semiconductor component 1 is bonded to terminal 302d by soldering or via a sintered layer, etc. The sintered layer may contain silver, copper, etc. In this embodiment, the drain electrode 40 is bonded to a wide section of terminal 302d, which is positioned inside the main housing body 301.

[0258] The semiconductor package 300 can contain semiconductor component 101, 101a, 201, 201a, or 201b instead of semiconductor component 1. In this case, the semiconductor package 300 can furthermore have at least one different or additional terminal than terminals 302d to 302s. For example, if semiconductor component 101 is installed, the semiconductor package 300 can furthermore contain a terminal connected to a current sensing pad 170. Furthermore, if semiconductor component 201 is installed, the semiconductor package 300 can furthermore contain a terminal connected to an anode electrode pad 270 and a terminal connected to a cathode electrode pad 275.

[0259] Consequently, the semiconductor package 300 contains the semiconductor component 1, 101, 101a, 201, 201a, or 201b. As described above, the semiconductor layer 10 is used efficiently to reduce the size of semiconductor component 1 and the others. Therefore, the semiconductor package 300 can be easily reduced in size by reducing the size of semiconductor component 1, etc.

[0260] Furthermore, according to semiconductor component 1, etc., the active regions 3, 103, and 203 can be extended. Therefore, semiconductor package 300 can be improved or enlarged with respect to a permissible current value compared to a semiconductor package of the same size. An example of semiconductor package 300 is shown where semiconductor component 1, etc., is electrically connected to the terminal via a bond wire. However, in semiconductor package 300, semiconductor component 1, etc., can also be electrically connected to the terminal via a bonding material.

[0261] Fig. Figure 31 is a drawing showing a semiconductor package 400 according to the fourth preferred embodiment. With reference to Fig. 31 The semiconductor package 400 is a semiconductor package of the so-called DIP (Dual In-line Package) type. The semiconductor package 400 includes a main package body 401, a plurality of terminals 402, and a semiconductor component 1.

[0262] The main body of the casing 401 is formed in a rectangular parallelepiped shape. The main body of the casing 401 is made of an epoxy resin containing, for example, carbon, glass fibers, etc. A multitude of terminals 402 are arranged side by side in an array-like manner along one long side of the main body of the casing 401. The multitude of terminals 402 project outwards from the long side of the main body of the casing 401. The multitude of terminals 402 can be made of, for example, aluminum. The multitude of terminals 402 can be made of other metallic materials, such as copper, etc.

[0263] The semiconductor component 1 is housed inside the main housing body 401. That is, the main housing body 401 is designed as a sealing element for the semiconductor component 1. A gate pad 70, a source pad 75, and a drain electrode 40, belonging to the semiconductor component 1, are each electrically connected to corresponding terminals 402 via a bond wire, etc., inside the main housing body 401. The semiconductor housing 400 can contain a plurality of semiconductor components 1. That is, a plurality of semiconductor components 1 can be housed inside the main housing body 401.

[0264] It is understood that the semiconductor package 400 can contain at least one of the semiconductor components 101, 101a, 201, 201a, and 201b, either instead of or in addition to semiconductor component 1. When semiconductor component 101 is installed, a current sensing pad 170 is electrically connected to a corresponding terminal 402 via a bond wire, etc., inside the main body of the package 401. When semiconductor component 201 is installed, an anode electrode pad 270 and a cathode electrode pad 275 are also electrically connected to their corresponding terminals 402 via a bond wire, etc., inside the main body of the package 401.

[0265] Therefore, the semiconductor package 400 contains at least one of the semiconductor components 1, 101, 101a, 201, 201a, and 201b. As described above, the semiconductor component 1, etc., can be reduced in size by efficiently utilizing the semiconductor layer 10. Therefore, the semiconductor package 300 can be easily reduced in size by reducing the size of the semiconductor component 1, etc.

[0266] Furthermore, according to semiconductor component 1, etc., the active regions 3, 103, and 104 can be enlarged. Therefore, the semiconductor package 300 can be increased or reinforced with respect to a permissible current value compared to a semiconductor package of generally the same size. An example is shown for semiconductor package 400 where semiconductor component 1, etc., is electrically connected to the terminals via a bond wire. However, in semiconductor package 400, semiconductor component 1, etc., can also be electrically connected to the terminals via a bonding material.

[0267] Fig. Figure 32 is a cross-sectional view of a semiconductor device 501 according to a modified example. With reference to Fig. 32 can be an example of a metal layer, a plating layer 90 (metal plating layer) on an upper surface 73 of a gate pad 70 and an upper surface 76 of a source pad 75. Fig.Figure 32 shows, in addition to the plating layer 90, a bond wire 303g, a bond material 502 and a metal plate 503, as an example of connecting elements (bonding means) with an external terminal.

[0268] In the semiconductor component 501, the bond wire 303g is connected to the gate pad 70, and the bond material 502 is bonded to the source pad 75. The bond material 502 is positioned between the metal plate 503 and the source pad 75 to bond them together. The bond material 502 includes, for example, solder and a sintered metal element. The sintered metal element can contain silver, copper, etc.

[0269] The plating layer 90 is formed from a metal material that differs from the metal material forming the gate pad 70 and the source pad 75. For example, the plating layer 90 is a metal layer containing nickel as a major component. More precisely, the plating layer 90 is a metal layer composed entirely of nickel.

[0270] The plating layer 90 can have a two-layer structure, comprising a nickel layer and a palladium layer laminated onto the nickel layer (i.e., a NiPd layer). The plating layer 90 can also have a three-layer structure, comprising a nickel layer, a palladium layer laminated onto the nickel layer, and a gold (Au) layer laminated onto the palladium layer (i.e., a NiPdAu layer). It is understood that the plating layer 90 can have a laminated structure containing an additional metal layer instead of the gold (Au) layer. The NiPd and NiPdAu layers are favored applications, not only for bonding a bond wire but also for bonding an external terminal by silver sintering or soldering.

[0271] The plating layer 90 can be applied to the semiconductor components 101, 101a, 201, 201a and 201b. That is, the plating layer 90 can be provided on the respective upper surfaces of the current sensing pad 170, the anode electrode pad 270 and the cathode electrode pad 275.

[0272] The preferred embodiments have been described so far. These preferred embodiments can be further realized or implemented in other embodiments. For example, the configuration of the semiconductor package on which the semiconductor component 1, 101, 101a, 201, 201a, 201b, and 501 are mounted is not limited to the configurations of semiconductor package 300 and semiconductor package 400. The following package types can be used as the semiconductor package: SOP (Small Outline Package), QFN (Quad Flat Non-Lead Package), DFP (Dual Flat Package), QFP (Quad Flat Package), SIP (Single Inline Package), or SOJ (Small Outline J-Leaded Package). It is understood that various types of semiconductor packages can be used similarly to those described above.

[0273] In the first to fourth preferred embodiments, a case has been described in which the "first conductivity type" is the "n-type" and the "second conductivity type" is the "p-type". However, the "first conductivity type" can also be the "p-type", and the "second conductivity type" can also be the "n-type". In this case, a special arrangement is obtained by replacing the "n-type region" with the "p-type region" and vice versa, as described above and illustrated in the accompanying drawings. The "first conductivity type" and the "second conductivity type" are merely terms used to clarify the sequence of descriptions, and "n-type" can be expressed as the "second conductivity type", and "p-type" can be expressed as the "first conductivity type".

[0274] In the first to fourth preferred embodiments, the semiconductor substrate 13 can be replaced by n + -Type the SiC semiconductor substrate from p + -type can be applied. In this case, a semiconductor device incorporating an IGBT (Insulated Gate Bipolar Transistor) is available as the vertical transistor 2. In this case, in the description and drawings, a "source" of a MISFET is replaced by an "emitter" of an IGBT, and a "drain" of a MISFET is replaced by a "collector" of an IGBT. The emitter of the IGBT (emitter electrode) is an example of the first main electrode, and the collector of the IGBT (collector electrode) is an example of the second main electrode. In the semiconductor device according to each of the preferred embodiments, the same effects as those described above can be obtained if an IGBT is included instead of a MISFET.

[0275] The arrangements of the first to fourth preferred embodiments and those of the modified examples of the first to fourth preferred embodiments can be used in combination whenever necessary. For example, in the semiconductor device containing the gate pad, the current sensing pad, and the temperature sensing pad, the arrangements described in the preferred embodiments can be applied to each of the gate pad, the current sensing pad, and the temperature sensing pad. It is therefore possible to provide a high-performance semiconductor device with both current sensing and temperature sensing functionality without reducing the active region area.

[0276] Examples of features extracted from the present description and the drawings are given below. Although alphanumeric reference numerals in parentheses below express or name corresponding components, etc., they are not intended to imply that the protection zones of the respective items of the preferred embodiments described above are restricted. The "semiconductor component" according to the items below can be replaced by a "wide bandgap semiconductor component," by a "SiC semiconductor component," by a "wide bandgap semiconductor switching component," or by a "SiC semiconductor switching component."

[0277] A conventional semiconductor device includes a gate pad and a source pad, to which a wire bond is applied. An active region, containing a FET structure, is located beneath the source pad. A non-active region, not containing a FET structure, is located beneath the gate pad. The gate pad must be larger than a specified size to ensure sufficient bonding area for a wire. Therefore, if the size of the active region is increased without changing the size of the gate pad, the size of the chip itself must also be increased.

[0278] One objective of the following items is therefore to specify a semiconductor device capable of relaxing design rules derived from an electrode. Another objective of the following items is to specify a semiconductor device capable of increasing the size of an active region without increasing the size of the chip. [A1] Semiconductor device (1, 101, 101a, 201, 201a, 201b, 501: hereinafter referred to simply as ‘semiconductor device (1, etc.)’) comprising: a semiconductor layer (10) containing SiC and having a first principal area (11) on one side and a second principal area (12) on the other side; a vertical transistor (2) formed in the semiconductor layer (10); a first electrode (50 / 150) arranged on the first main surface (11); a second electrode (55) arranged on the first main surface (11) at a distance from the first electrode (50 / 150); a first electrode pad (70 / 170) arranged on the side opposite the semiconductor layer (10) with respect to the first electrode (50 / 150) such that it overlaps at least partially with the first electrode (50 / 150) in a top view and is electrically connected to the first electrode (50 / 150);and an electrode (40) arranged on the second main surface (12), wherein the first electrode pad (70 / 170) overlaps with part of the second electrode (55) in a top view. [A2] Semiconductor component (1, etc.) according to A1, further comprising: a first insulating layer (63) arranged in a direction (z) vertically or perpendicularly to the first main surface (11) between the first electrode pad (70 / 170) and the second electrode (55). [A3] Semiconductor device (1, etc.) according to A2, wherein a side surface of the first insulating layer (63) is formed in a plane extending in the vertical direction (z). [A4] Semiconductor component (1, etc.) according to A2 or A3, further comprising: a second electrode pad (75) which is electrically connected to the second electrode (55); wherein an end section of the second electrode pad (75) located on the side of the first electrode pad (70 / 170) is positioned on the first insulating layer (63). [A5] Semiconductor component (1, etc.) according to A4, further comprising: a second insulating layer (66) covering a boundary section (80) between the first electrode pad (70 / 170) and the second electrode pad (75). [A6] Semiconductor device (1, etc.) according to any one from A1 to A5, wherein the vertical transistor (2) has a source region (17) formed on a front surface section of the first main surface (11), a gate insulating film (23) covering the source region (17), a gate electrode (20) opposite the source region (17) across the gate insulating film (23), and a drain region (10, 13, 14) formed in the semiconductor layer (10), wherein the first electrode (50 / 150) is electrically connected to the gate electrode (20), wherein the second electrode (55) is electrically connected to the source region (17), and wherein the electrode (40) is electrically connected to the drain region (10, 13, 14). [A7] Semiconductor device (1, etc.) according to A6, wherein the vertical transistor (2) has a main cell region (103) generating a drain current and a current detecting cell region (104) generating a sense current which detects the drain current, in a top view, wherein the second electrode (55) is arranged in a region which overlaps with the main cell region (103) in a top view. [A8] Semiconductor device (1, etc.) according to A7, further comprising: a third electrode (150) arranged in a region which, in a top view, overlaps the current sensing cell region (104) at a distance from the first electrode (50) and the second electrode (55), and a third electrode pad (170) arranged on the side opposite the semiconductor layer (10) with respect to the third electrode (150), such that, in a top view, it overlaps at least partially with the third electrode (150) and is electrically connected to the third electrode (150). [A9] Semiconductor device (1, etc.) according to A8, wherein the third electrode pad (170) overlaps with part of the second electrode (55) in a top view. [A10] Semiconductor device (1, etc.) according to any one from A1 to A9, further comprising: an insulating layer (260) covering part of the first main area (11); a diode (290) arranged on the insulating layer (260) having a first pole section (291) and a second pole section (292) forming a pn junction with the first pole section (291); a first pole electrode pad (270) electrically connected to the first pole section (291) on the diode (290); and a second pole electrode pad (275) electrically connected to the second pole section (292) on the diode (290). [A11] Semiconductor device (1, etc.) according to A10, wherein the first pole electrode pad (270) and / or the second pole electrode pad (275) overlaps with part of the second electrode (55) in a top view. [A12] Method for fabricating a semiconductor device (1, etc.) comprising: a step that provides a semiconductor layer (10) containing SiC, having a first principal surface (11) on one side and a second principal surface (12) on the other side, and comprising a vertical transistor (2); a step that forms a first electrode (50 / 150) and a second electrode (55) spaced apart on the first principal surface (11); and a step forming a first electrode pad (70 / 170) at a position opposite the first electrode (50 / 150) of the semiconductor layer (10) in respect of the first electrode (50 / 150), such that it overlaps at least partially with the first electrode (50 / 150) in a top view, and such that it is electrically connected to the first electrode (50 / 150), wherein in the step of forming the first electrode pad (70 / 170) the first electrode pad (70 / 170) is formed which overlaps with part of the second electrode (55). [B1] Semiconductor device (1, etc.) comprising: a semiconductor layer (10) having a main surface (11); a switching element (2) formed in the semiconductor layer (10); a first electrode (50 / 150) arranged on the main surface (11) and electrically connected to the switching element (2); a second electrode (55) arranged on the main surface (11) at a distance from the first electrode (50 / 150) and electrically connected to the switching element (2); a first terminal electrode (70 / 170) having a section overlapping the first electrode (50 / 150) in a top view and a section overlapping the second electrode (55), and electrically connected to the first electrode (50 / 150); and a second terminal electrode (75) which has a section that overlaps with the second electrode (55) in a top view and is electrically connected to the second electrode (55). [B2] Semiconductor component (1, etc.) according to B1, wherein the semiconductor layer (1, etc.) contains SiC. [B3] Semiconductor device (1, etc.) according to B1 or B2, wherein the first terminal electrode (70 / 170) is connected to the first electrode (50 / 150) in a first area or first area and has an electrode area (73) that is larger than the first area or first area. [B4] Semiconductor device (1, etc.) according to any one from B1 to B3, wherein the second terminal electrode (75) has an area in a top view which is greater than or equal to that of the first terminal electrode (70 / 170). [B5] Semiconductor device (1, etc.) according to any one from B1 to B4, wherein the first terminal electrode (70 / 170) in a top view intersects at least part of the first electrode (50 / 150). [B6] Semiconductor device (1, etc.) according to any one from B1 to B5, wherein the second terminal electrode (75) has a section which overlaps with the first electrode (50 / 150) in a top view. [B7] Semiconductor component (1, etc.) according to any one from B1 to B6, wherein the first electrode (50 / 150) is a control electrode which transmits a control signal of the switching component (2), and wherein the second electrode (55) is a non-control electrode. [B8] Semiconductor device (1, etc.) according to any one from B1 to B7, wherein the switching device (2) includes a gate (20) and a source (17), wherein the first electrode (50 / 150) is electrically connected to the gate (20), and wherein the second electrode (55) is electrically connected to the source (17). [B9] Semiconductor device (1, etc.) according to any one from B1 to B8, further comprising: a first insulator (63) covering the second electrode; wherein the first terminal electrode (70 / 170) has a section opposite the second electrode (55) across the first insulator (63), and wherein the second terminal electrode (75) has a section opposite the second electrode (55) across the first insulator (63). [B10] Semiconductor device (1, etc.) according to B9, wherein the first terminal electrode (70 / 170) has a side surface arranged above the second electrode (55) such that it is opposite the second electrode (55) via the first insulator (63), and wherein the second terminal electrode (75) has a side surface arranged above the second electrode (55) such that it is opposite the second electrode (55) via the first insulator (63), and which forms a gap or crack (80) that exposes the first insulator (63) between the second terminal electrode (75) and the side surface of the first terminal electrode (70 / 170). [B11] Semiconductor component according to B10, further comprising: a second insulator (66) covering the first insulator (63) within the gap (80) and opposite the second electrode (55) over the first insulator (63). [B12] Semiconductor device (1, etc.) according to any one from B9 to B11, wherein the first insulator (63) covers the first electrode (50 / 150), wherein the first terminal electrode (70 / 170) has a section opposite the first electrode (50 / 150) across the first insulator (63), and wherein the second terminal electrode (75) has a section opposite the first electrode (50 / 150) across the first insulator (63). [B13] Semiconductor component (1, etc.)) according to any one from B1 to B12, further comprising: an active region (3, 103, 203) provided in the semiconductor layer (10); and a non-active region (4, 104, 204) provided in the semiconductor layer (10) in a region other than the active region (3, 103, 203); wherein the switching component (2) is formed in the active region (3, 103, 203), wherein the first electrode (50 / 150) is arranged in a region which overlaps with the non-active region (4, 104, 204) in a top view, wherein the second electrode (55) is arranged in a region which overlaps with the active region (3, 103, 203) in a top view, wherein the first terminal electrode (70 / 170) is arranged in a region which overlaps with the active region (3, 103, 203) and the non-active region (4, 104, 204) in a top view, and wherein the second terminal electrode (75) is arranged in a region which overlaps with the active region (3, 103, 103) in a top view. [B14] Semiconductor device (1, etc.) according to B13, wherein the active region (3, 103, 203) has a main cell region (103) provided in the semiconductor layer (109), wherein the non-active region (4, 104, 204) has a sensing cell region (104) provided in the semiconductor layer (10) in a region other than the main cell region (103), and wherein the switching device (2) includes a main switching device (2) formed in the main cell region (103) to generate a main current, and a sensing switching device (2) formed in the sensing cell region (104) to generate a monitoring current that sensing the main current. [B15] Semiconductor device (1, etc.) according to B14, wherein the first electrode (50 / 150) is electrically connected to the main switching device (2), wherein the second electrode (55) is arranged in a region which overlaps with the main cell region (103) in a top view and is electrically connected to the main switching device (2), wherein the first terminal electrode (70 / 170) is arranged in a region which overlaps with the main cell region (103) and the non-active region (4, 104, 204) in a top view, and wherein the second terminal electrode (75) is arranged in a region which overlaps with the main cell region in a top view. [B16] Semiconductor component (1, etc.) according to B14 or B15, wherein the first electrode (50 / 150) is electrically connected to the detection switching component (2). [B17] Semiconductor component (1, etc.) according to any one of B14 to B16, further comprising: a third electrode (150) arranged in a region which overlaps with the sensing cell region (104) in a plan view, at a distance from the first electrode (50) and the second electrode (55), and which is electrically connected to the sensing switching component (2); and a third terminal electrode (170) which has a section which overlaps with the third electrode (150) in a plan view, and which is electrically connected to the third electrode (150). [B18] Semiconductor device (1, etc.) according to any one from B13 to B17, further comprising: a diode (290) formed in the non-active region (4, 104, 204); and a pole-terminal electrode (270, 275) having a section overlapping the diode (290) in a top view and electrically connected to the diode (290). [B19] Semiconductor device (1, etc.) comprising: a semiconductor layer (10) having a main area (11); a main component (2) formed in the semiconductor layer (10) generating a main current; a sensing component (2) formed in the semiconductor layer (10) in a different region than the main component (2) generating a monitoring current that monitors the main current; a first electrode (50) arranged on the main area (11) and electrically connected to the main component (2); a second electrode (55) arranged on the main area (11) at a distance from the first electrode (50) and electrically connected to the main component (2); a third electrode (150) arranged on the main area (11) at a distance from the first electrode (50) and the second electrode (55) and electrically connected to the sensing component (2);a first terminal electrode (70) electrically connected to the first electrode (50) on or above the first electrode (50); a second terminal electrode (75) electrically connected to the second electrode (55) on or above the second electrode (55); and a third terminal electrode (170) having a section that overlaps with the third electrode (150) in a top view and a section that overlaps with the second electrode (55), and which is electrically connected to the third electrode (150). [B20] Semiconductor device (1, etc.) comprising: a semiconductor layer (10) having a main area (11); a switching element (2) formed in the semiconductor layer (10); a diode (290) formed in the semiconductor layer (10) in a region distinct from the switching element (2); a first electrode (50 / 150) arranged on the main area (11) and electrically connected to the switching element (2); a second electrode (55) arranged on the main area (11) at a distance from the first electrode (50 / 150) and electrically connected to the switching element (2); a first terminal electrode (70 / 170) electrically connected to the first electrode (50 / 150) on or above the first electrode (50 / 150); a second terminal electrode (75) which is electrically connected to the second electrode (55), namely on orabove the second electrode; and a pole-terminal electrode (270, 275) which has a section overlapping with the diode (290) in a top view, and has a section overlapping with the second electrode (55), and which is electrically connected to the diode (290). [C1] Semiconductor device (1, etc.) comprising: a semiconductor layer (10) having a first main surface (11) on one side and a second main surface (12) on the other side, and containing SiC; an active region (3, 103, 203) provided on the first main surface (11); a non-active region (4, 104, 204) provided on the first main surface (11) in a region other than the active region (3, 103, 203); an insulating layer (61) covering the first main surface (11); a first main electrode layer (55) arranged on the first insulating layer (61) such that it overlaps the active region (3, 103, 203) in a top view;a first conductive layer (50 / 150 / 290) arranged on the first insulating layer (61) at a distance from the first main electrode layer (55) such that it overlaps the non-active region (4, 104, 204) in a top view and is electrically disconnected from the first main electrode layer (55); a second insulating layer (63) covering the first main electrode layer (55) and the first conductive layer (50 / 150 / 290); a second conductive layer (70 / 170 / 270 / 275) arranged on the second insulating layer (63) such that it overlaps with the first main electrode layer (55) in a top view, is electrically disconnected from the first main electrode layer (55), and is electrically connected to the first conductive layer (50 / 150 / 290); and an electrode (40) covering the second main surface (12). [C2] Semiconductor component (1, etc.) according to C1, further comprising: a switching component (2) formed in the active region (3, 103, 203) in the semiconductor layer (10); wherein the first conductive layer (50 / 150 / 290) and the second conductive layer (70 / 170 / 270 / 275) are electrically connected to the switching component (2). [C3] Semiconductor component (1, etc.) according to C2, wherein the switching component (2) comprises at least one of a MISFET (metal insulator semiconductor field-effect transistor) and an IGBT (bipolar transistor with insulated gate). [C4] Semiconductor device (1, etc.) according to C3, wherein the first conductive layer (50 / 150) and the second conductive layer (70 / 170) are electrically connected to a gate of the switching device (2) and form a transmission path of a gate voltage. [C5] Semiconductor component (1, etc.) according to C1, further comprising: a current sensing component (2) formed in the semiconductor layer (10); wherein the first conductive layer (150) and the second conductive layer (170) are electrically connected to the current sensing component (2) and form a second transmission path of a signal generated by the current sensing component (2). [C6] Semiconductor component (1, etc.) according to C5, wherein the current sensing component (2) is formed in the non-active region (4, 104, 204). [C7] Semiconductor device (1, etc.) according to C1, wherein the first conductive layer (290) is composed of a diode (290) and forms a third transmission path of a current flowing through the diode (290) between the first conductive layer (290) and the second conductive layer (270 / 275). [C8] Semiconductor component (1, etc.) according to C7, wherein the diode (290) is a temperature-sensitive diode or temperature sensing diode (290), and wherein the transmission path transmits a signal that detects a temperature of the semiconductor layer (10). [C9] Semiconductor component (1, etc.) after C7 or C8, wherein the diode (290) is formed in the non-active region (4, 104, 204). [C10] Semiconductor device (1, etc.) according to any one from C1 to C9, wherein the first conductive layer (50 / 150 / 290) is constructed with substantially the same thickness and of substantially the same material as the first main electrode layer (55). Here, “substantially the same” means that the first main electrode layer (55) and the first conductive layer (50 / 150 / 290) are formed by the same process (fabrication step) and therefore have the same arrangement or configuration (with respect to thickness and material). [C11] Semiconductor device (1, etc.) according to any one from C1 to C10, further comprising: a second main electrode layer (75) arranged on the second insulating layer (63) at a distance from the second conductive layer (70 / 170 / 270 / 275) such that it overlaps with the first main electrode layer (55) in a top view. [C12] Semiconductor device (1, etc.) according to C11, wherein the second main electrode layer (75) is constructed with substantially the same thickness and of substantially the same material as the second conductive layer (70 / 170 / 270 / 275). Here, “substantially the same” means that the second main electrode layer (75) and the second conductive layer (70 / 170 / 270 / 275) are formed by the same process (manufacturing step), thus having the same arrangement or configuration (with respect to thickness and material). [C13] Semiconductor device (1, etc.) according to C 11 or C12, wherein the second conductive layer (70 / 170 / 270 / 275) and / or the second main electrode layer (75) are exposed to the outside, such that they are electrically connected to an external terminal (302d, 302g, 302s, 402). [C14] Semiconductor device (1, etc.) according to C13, wherein the second conductive layer (70 / 170 / 270 / 275) and / or the second main electrode layer (75) are arranged such that they are electrically connected to the external terminal (302d, 302g, 303s) via a bond wire (303g, 303s), via a soldering process or solder (502) or via a sintered metal (502). [C15] Semiconductor component (1, etc.) to C13 or C14, wherein the external terminal (302d, 302g, 302s, 402) is a lead frame. [C16] Semiconductor device (1, etc.) according to any one from C1 to C10, wherein the first main electrode layer (55) is exposed to the outside, such that it is electrically connected to the external terminal (302d, 302g, 302s, 402). [C17] Semiconductor device (1, etc.) according to C16, wherein the first main electrode layer (55) is arranged such that it is electrically connected to the external terminal (302d, 302g, 303s) via a bond wire (303g, 303s), via a soldering process or solder (502) or via a sintered metal (502). [C18] Semiconductor component (1, etc.) according to C16 or C17, wherein the external terminal (302d, 302g, 302s, 402) is a connector frame.

[0279] The semiconductor device according to [C1] to [C18] can include at least one of the first transmission path, the second transmission path, and the third transmission path according to [C4] to [C8]. That is, the first transmission path, the second transmission path, and the third transmission path can each be provided individually or in combination in the semiconductor device. More precisely, a semiconductor device can be used that includes only one of the first transmission path, the second transmission path, and the third transmission path.

[0280] Furthermore, a semiconductor device can be used that includes only any two of the first, second, and third transmission paths. Alternatively, a semiconductor device can be used that includes all paths of the first, second, and third transmission paths. If a plurality of transmission paths are provided, preferably at least one of the transmission paths has the arrangement according to [C1], as described above. In this case, it is particularly preferred if all of the plurality of transmission paths have the arrangement according to [C1], as described above. [D1] Semiconductor device comprising a vertical transistor, the semiconductor device comprising: a semiconductor layer having a first principal surface and a second principal surface on a side opposite the first principal surface and comprising SiC as a principal component; a first electrode covering a portion of the first principal surface; a second electrode being provided at a distance from the first electrode in a plan view and covering a portion of the first principal surface; a first electrode pad being provided on the side opposite the semiconductor layer with respect to the first electrode, overlapping at least partially with the first electrode in a plan view and being electrically connected to the first electrode; and an electrode being provided on the second principal surface;where the first electrode pad overlaps with part of the second electrode in a top view. [D2] Semiconductor device according to D1, further comprising: a first insulating layer positioned in a direction vertical or perpendicular to the first main surface between the first electrode pad and the second electrode. [D3] Semiconductor device according to D2, wherein a side surface of the first insulating layer is or defines a plane along a direction that is vertical or perpendicular to the first main surface. [D4] Semiconductor device according to D2 or D3, further comprising: a second electrode pad which is electrically connected to the second electrode; wherein an end section of the second electrode pad located on the side of the first electrode pad is positioned on or above the first insulating layer. [D5] Semiconductor component according to D4, further comprising: a second insulating layer covering a boundary section between the first electrode pad and the second electrode pad. [D6] Semiconductor device according to any one of D1 to D5, wherein the vertical transistor has a source region formed on a front surface of the semiconductor layer on the side of the first main surface, a gate electrode arranged adjacent to the source region via a gate insulating film, and a drain region formed in the semiconductor layer, wherein the first electrode is electrically connected to the gate electrode and wherein the second electrode is electrically connected to the source region. [D7] Semiconductor device according to D6, wherein the vertical transistor in a plan view comprises a main cell region for conducting a drain current and a current sensing cell region for sensing a drain current, and wherein the second electrode is arranged to correspond to the main cell region, and wherein the semiconductor device further comprises: a third electrode, which in a plan view is provided at a distance from the first electrode and the second electrode and which is arranged to correspond to the current sensing cell region; and a third electrode pad, which is provided on the side opposite the semiconductor layer with respect to the third electrode, which in a plan view overlaps at least partially with the third electrode and which is electrically connected to the third electrode, wherein the third electrode pad overlaps with a part of the second electrode in a plan view. [D8] Semiconductor device according to D6 or D7, further comprising: a diode provided on an insulating layer covering part of the first main surface; an anode electrode pad electrically connected to a p-type semiconductor layer of the diode; and a cathode electrode pad electrically connected to an n-type semiconductor layer of the diode; wherein the anode electrode pad and / or the cathode electrode pad overlaps with part of the second electrode in a top view. [D9] Method for manufacturing a semiconductor device containing a vertical transistor, the method for manufacturing the semiconductor device comprising: a first step in which a first electrode and a second electrode covering a part of a first principal area of ​​a semiconductor layer having the first principal area and a second principal area on a side opposite the first principal area and containing SiC as a principal component are formed at a distance from each other; and a second step in which a first electrode pad electrically connected to the first electrode is formed on a side of the semiconductor layer opposite the first electrode, such that at least a part of the first electrode pad overlaps with the first electrode in a top view, wherein the first electrode pad overlaps with a part of the second electrode in a top view. [E1] Semiconductor device comprising: a semiconductor layer having a first main surface with an active region and a non-active region and a second main surface on a side opposite the first main surface, and containing SiC as a major component; a first insulating layer formed on the first main surface; a first main electrode layer formed on the insulating layer and located in a region corresponding to the active region; a first conductive layer formed on the first insulating layer, electrically separated from the first main electrode layer and located in a region corresponding to the non-active region; a second insulating layer formed on the first main electrode layer and the first conductive layer;a second conductive layer formed on the second insulating layer, electrically connected to the first conductive layer, electrically separated from the first main electrode layer, and formed in a region that partially overlaps the first main electrode layer in a thickness direction of the semiconductor layer; and an electrode formed on the second main surface. [E2] Semiconductor device comprising a switching device of a type driven by an insulating gate (“insulating gate driving-type switching device”), wherein the switching device comprises a MOSFET or an IGBT, and wherein the first conductive layer and the second conductive layer form a transmission path for a control signal used to control the switching device of the type driven by an insulating gate. [E3] That is, the first conductive layer and the second conductive layer can be connected to a gate electrode of the switching device to form a first transmission path, which is a transmission path of the control signal of a gate voltage. [E4] Furthermore, the first conductive layer and the second conductive layer are connected to a source electrode (emitter electrode) of a current sensing device to form a second transmission path, which is a transmission path for a sensing signal that detects a current flowing through the semiconductor device. [E5] Furthermore, the first conductive layer and the second conductive layer can be connected to an electrode of a diode that detects a temperature of the semiconductor device to form a third transmission path, which is a transmission path of a detection signal that detects a temperature of the semiconductor device. [E6] The first, second or third transmission path may be provided in the semiconductor device alone, or a plurality of them may be provided. [E7] More precisely, an arrangement may exist in which only the first transmission path is provided. In addition to the first transmission path, the second transmission path or the third transmission path may be provided. Alternatively, the semiconductor device may be provided with or equipped with all of the first, second, and third transmission paths. [E8] If a plurality of transmission paths are provided, an arrangement in which all of the transmission paths satisfy the arrangement described above is preferred. However, it is possible that at least one of the transmission paths meets the above description. [E9] The first main electrode layer and the first conductive layer may be of substantially the same thickness and made of substantially the same material. In this context, ‘substantially the same’ means that the first main electrode layer and the first conductive layer are formed by the same process, resulting in the same arrangement and configuration. [E10] Furthermore, the second main electrode layer can be formed in such a way that it overlaps the first main electrode layer from above. [E11] In this case, the second main electrode layer and the second conductive layer can be of substantially the same thickness and made of substantially the same material. [E12] The second conductive layer and the second main electrode layer are exposed on a front surface of the semiconductor device and are used for connection to a suitable external terminal. [E13] If no second main electrode layer is provided, the first main electrode layer may be exposed at the front surface of the semiconductor device and used for connection to an external terminal. [E14] Bonding or joining between the second conductive layer / second main electrode layer and the respective external terminals, such as connection frames, is carried out by wire bonding. However, the second conductive layer / second main electrode layer and the external terminals can be bonded by soldering or by using a sintered metal. [E15] Bonding between the second conductive layer and the external terminal can be carried out by wire bonding, and the second main electrode layer and the external terminal can be bonded by soldering or by using a sintered metal.

[0281] With regard to its industrial applicability, the present invention can be applied to semiconductor components, semiconductor housings, etc. Reference symbol list 1 Semiconductor component 2 vertical transistor 3 active regions 4 inactive regions 10 Semiconductor layer 11 first main area 12 second main area 13 Semiconductor substrate 14 Epitaxial layer 17 Source Region 20 Gate electrode 23 Gate insulating layer 40 Drain electrode 50 Main surface gate electrode 55 Main surface source electrode 63 upper insulating layer 66 Protective insulating layer 70 Gate Pad 75 Source-Pad 80 Border section 101 Semiconductor component 101a Semiconductor component 103 active regions 104 inactive regions 150 current sensing electrode 170 current sensing pad 201 Semiconductor component 201a Semiconductor component 201b Semiconductor component 203 active regions 204 inactive regions 260 Insulation layer 270 anode electrode pads 275 cathode electrode pads 290 Diode 291 p-type semiconductor layer 292 n-type semiconductor layer 302d Terminal 302g Terminal 302s Terminal 402 Terminal 303g Bond wire 303s Bond wire 501 Semiconductor component 502 Bond material

Claims

A method for fabricating a semiconductor device (1) comprising the steps of: a step of providing a semiconductor layer (10) having a main area and including an active region (3) and a non-active region (4) which is a region other than the active region; a step of forming a FET structure having a gate electrode (20), a source region (17) or an emitter region and a drain region (40) or a collector region in the active region (3); a step of forming a first insulating layer (61) having contact holes (61b) in the active region (3) on the semiconductor layer (10); a step of forming a first metal film on the first insulating layer (61) having a section embedded in the contact hole (61b);a step of forming a first main surface electrode (50) located in the non-active region (4) and electrically connected to the gate electrode (20) of the FET structure, and of forming a second main surface electrode (55) located in the active region (3) and electrically connected inside the contact holes (61b) to the source region (17) or the emitter region of the FET structure by removing part of the first metal film; a step of forming a second insulating layer (63) covering part of the first main surface electrode (50) and part of the second main surface electrode (55);a step of forming an end insulating layer (65) covering an outer circumferential section of the semiconductor layer (10), wherein the step of forming the end insulating layer (65) is carried out simultaneously with the step of forming the second insulating layer (63), a step of forming a second metal film on the second insulating layer (63), the first main surface electrode (50) and the second main surface electrode (55) which are exposed relative to the second insulating layer (63);a step of forming a first pad (70) which, when viewed from a top view, overlaps the first main surface electrode (50) and the second main surface electrode (55) and is electrically connected to the first main surface electrode (50), and of forming a second pad (75) which, when viewed from a top view, overlaps the second main surface electrode (55) and is electrically connected to the second main surface electrode (55), by removing part of the second metal film; a step of forming a third insulating layer (66) on the first pad (70), the second pad (75) and the second insulating film (63);and a step of exposing a part of the first pad (70) and a part of the second pad (75) by removing a part of the third insulating layer (66), wherein the step of forming the second insulating layer (63) includes a step of forming the second insulating layer (63) in such a way that it has a through-hole (63a) which selectively exposes a part of the first main surface electrode (50), and wherein the first pad (70) is electrically connected to the first main surface electrode (50) via the through-hole (63a). Method for manufacturing the semiconductor component according to claim 1, wherein the step of forming the third insulating layer (66) includes a step of forming the third insulating layer (66) such that it covers the final insulating layer (65) which covers the outer circumferential section of the semiconductor layer (10). Method for manufacturing the semiconductor component according to claim 1, wherein the step of forming the first insulating layer (61) includes a step of forming the first insulating layer on the outer circumferential section of the semiconductor layer (10), wherein the step of forming the final insulating layer (65) includes a step of forming the final insulating layer (65) such that it covers the first insulating layer (61) formed in the outer circumferential section of the semiconductor layer (10), and wherein the step of forming the third insulating layer (66) includes a step of forming the third insulating layer (66) such that it covers the final insulating layer (65) formed in the outer circumferential section of the semiconductor layer (10). Method for manufacturing the semiconductor component according to claim 1, wherein the step of forming the first metal film on the first insulating layer (61) includes a step of embedding tungsten in the contact holes (61b) and a step of forming an aluminum-based metal material on the first insulating layer (61) and the tungsten. Method for manufacturing the semiconductor component according to claim 4, wherein the step of embedding the tungsten in the contact holes (61b) includes a step of embedding the tungsten over a barrier film made of titanium or titanium nitride. Method for manufacturing the semiconductor component according to claim 1, further comprising: a step of forming a plating layer on a surface of the second pad (75) which is exposed relative to the third insulating layer (66). Method for manufacturing the semiconductor component according to claim 6, wherein the plating layer includes a first metal layer comprising nickel as a major component. Method for manufacturing the semiconductor component according to claim 6, wherein the plating layer comprises a nickel layer and a palladium layer formed on the nickel layer. Method for manufacturing the semiconductor component according to claim 6, further comprising: a step of bonding a metal plate to the plating layer, namely via a bonding material. Method for manufacturing the semiconductor component according to claim 1, further comprising: a step of bonding a bond wire to the first pad (70) such that, when viewed from a top view, it does not overlap with the through hole (63a). Method for manufacturing the semiconductor component according to claim 1, wherein the step of providing the semiconductor layer (10) includes a step of providing a semiconductor layer made of SiC. Method for manufacturing the semiconductor component according to claim 1, wherein the FET structure includes the gate electrode (20), the source region (17) and the drain region (40), wherein the first main surface electrode (50) is a gate main surface electrode, wherein the second main surface electrode (55) is a source main surface electrode, wherein the first pad (70) is a gate pad and wherein the second pad (75) is a source pad. Method for manufacturing the semiconductor component according to one of claims 1 to 12, wherein the second main surface electrode (55) is arranged such that it surrounds a circumference of the first main surface electrode (50) in the top view. Method for manufacturing the semiconductor component according to one of claims 1 to 13, wherein the second pad (75) is arranged such that it surrounds a circumference of the first pad (70). Method for manufacturing the semiconductor component according to one of claims 1 to 14, wherein the second pad (75) has an area that is smaller than the area of ​​the second main surface electrode (55). Method for manufacturing the semiconductor component according to claim 14, wherein the third insulating layer (66) is formed in a rectangular ring shape on a section that covers a boundary section (80) between the first pad (70) and the second pad (75). Method for manufacturing the semiconductor component according to one of claims 1 to 16, wherein the third insulating layer (66) covers an entire circumference of the outer circumferential section of the semiconductor layer (10).

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