DATA TRANSMISSION USING A CONTINUOUSLY WEIGHTED PPM TIME SIGNAL

Abstract

A computer-implemented method for processing signals, comprising: generating (602) a temporary continuous weighted pulse position modulation (CW PPM) time-duration signal (92, 100) from an analog input signal (10, 20, 30), wherein the generation (602) includes: receiving the analog input signal (70) at a positive terminal of a comparator (88), feeding a first signal (76) of a sync clock controller (74) to a waveform merger (90) and the comparator (88), a second signal (78) of the sync clock controller (74) to the comparator (88), a third signal (80) of the sync clock controller (74) to a transfer gate (81), and a fourth signal (82) of the sync clock controller (74) to a circuit configuration (85),- Processing the fourth signal (82) by the circuit configuration (85) (85),and providing an output (84) of the circuit configuration (85) based on processing, processing the output (84) by an analog buffer (87) and feeding the output (84) of the analog buffer to a negative terminal of the comparator (88), switching the output (84) on and off by the third signal (80) using the transfer gate, providing a comparison result (89) of the comparator (88) to the waveform merger (90) based on a comparison of the signals (70, 84) at the positive and negative terminals of the comparator (88), the comparison being triggered by the first signal (76), providing the CW-PPM time-duration signal (92, 100) by the waveform merger based on the comparison result (89) and the first signal (76),- Resetting the comparison result (89) of the comparator (88) by the second signal (78); Converting (604) the CW PPM time duration signal into a working memory access signal; Performing (608) a multiply and accumulate (MAC) operation with the working memory access signal; and Regenerating (610) the analog input signal from a result of the MAC operation by an activation function (AF).

Description

BACKGROUND

[0001] The present invention relates generally to data transmission techniques, and more particularly to data transmission using continuous weighted pulse position modulation (PPM) duration signals.

[0002] In electronics, modulation is the application of a controlling or changing influence to something. Modulation is also referred to as a variation in the pitch, strength, or tone of a frequency, such as in the human voice. In terms of applications, however, modulation techniques are most commonly used to control devices such as direct current (DC) motors and light-emitting diodes (LEDs). In such cases, the technique is referred to as pulse-width modulation (PWM).

[0003] Modulation refers to the ability to exert control over a device or system. Therefore, techniques exist in the field of electronics in a myriad of applications. One of the more common uses for modulation as a control technique is PWM. The extensive use of PWM is due to its adaptability. PWM is a technique that reduces the average amount of deliverable power from an applied electrical signal. Furthermore, the process is achieved by effectively chopping the signal into different parts. In terms of functional operation, PWM achieves this control by controlling the average current and voltage delivered to the load. This process is achieved by rapidly turning the switch between the load and the source on and off.However, when comparing the on and off periods of the switch, an increase in the on time compared to the off time increases the total power supplied to the load.

[0004] Furthermore, the PWM switching frequency must be high enough not to affect the load, but the resulting waveform detected by the load should also be smooth. Typically, the frequency at which the power supply must be switched varies greatly, depending on the unit and its application. For example, switching must be performed multiple times per minute and well into the ranges of tens or hundreds of kHz for PC power supplies and audio amplifiers. One of the advantages of using PWM is that power dissipation in the switching units is essentially low. In fact, during the turn-off phase of a switch, there is virtually no power. Furthermore, during the turn-on phase of a switch, there is virtually no voltage drop across the switch while power is being transferred to its load.Since power dissipation is a result of both voltage and current, this results in virtually zero power loss for PWM. This allows PWM to be used successively for data transmission applications.

[0005] In particular, hardware processor cores of neural networks can use analog memory to achieve data transmission using PWM signals. The output of such neural network processor cores is analog data, even though the signal level is the same as that of a digital signal. Data transmission using PWM signals enables analog data transmission without analog-to-digital (ADC) and digital-to-analog conversion (DAC). However, PWM signals require long periods of time to transmit large-value data because the duration width corresponds to the value of the data. The performance (operating speed) of a system is difficult to increase unless the data transmission period is shortened. Thus, other approaches are necessary to achieve efficient data transmission. SUMMARY OF THE INVENTION

[0006] According to one embodiment, a computer-implemented method for processing signals is provided. A computer-implemented method includes generating a temporally continuous weighted pulse position modulation (CW PPM) duration signal from an analog input signal, converting the CW PPM duration signal into a memory access signal, performing a multiply and accumulate (MAC) operation on the memory access signal, and generating the analog input signal from a result of the MAC operation through an activation function (AF).

[0007] According to a further embodiment, a computer program product for processing signals is provided. The computer program product comprises a computer-readable storage medium having program instructions embodied thereon, wherein the program instructions are executable by a computer to cause the computer to generate a temporally continuous weighted pulse position modulation (CW PPM) duration signal from an analog input signal, convert the CW PPM duration signal into a memory access signal, perform a multiply and accumulate (MAC) operation on the memory access signal, and generate the analog input signal from a result of the MAC operation by means of an activation function (AF).

[0008] According to yet another embodiment, a signal processing system for an analog neural network unit is provided. The signal processing system includes a signal generator for generating a temporally continuous weighted pulse position modulation (CW PPM) duration signal from an analog input signal, a converter for converting the CW PPM duration signal into a memory access signal, a multiply and accumulate (MAC) operator for processing by accessing the memory with the memory access signal, and an activation function (AF) operator for processing a result of the MAC operator and generating the analog input signal for the signal generator.

[0009] According to another embodiment, an array structure is provided. The array structure comprises a plurality of memory cells integrated between a plurality of bit rows and a plurality of word rows, each memory cell comprising: a field-effect transistor (FET) comprising a gate contact, a source contact, and a drain contact; and a variable resistor having one end electrically connected to the drain contact of the FET and the other end electrically connected to a word row of the plurality of word rows. A slope signal is applied to the word row and a window signal is applied to the gate contact of the FET, such that the ramp signal and the window signal are combined to form a memory access signal derived from a continuous weighted pulse position modulation (CW PPM) duration signal.

[0010] According to yet another embodiment, a method for constructing an array structure is provided. The method includes integrating a plurality of memory cells between a plurality of bit rows and a plurality of word rows, each memory cell comprising: a field-effect transistor (FET) having a gate contact, a source contact, and a drain contact; and a variable resistor having one end electrically connected to the drain contact of the FET and the other end electrically connected to a word row of the plurality of word rows; and supplying a ramp signal to the word row and a window signal to the gate contact of the FET such that the ramp signal and the window signal combine to form a memory access signal derived from a continuous weighted pulse position modulation (CW PPM) duration signal.

[0011] The advantages of the present invention include providing efficient data transfer for large amounts of data. The advantages of the present invention also include more efficient use of the central processing unit (CPU) and more efficient use of input / output (I / O) bandwidth due to efficient data transfer for large amounts of data. Other advantages include higher quality, reduced costs, greater performance, faster performance, fewer application errors, and fewer data errors.

[0012] In a preferred aspect, the CW PPM duration signal is transmitted from a presynaptic neuron to a postsynaptic neuron by a network router.

[0013] In a further preferred aspect, the CW PPM duration signal is a weighted exponential decay signal.

[0014] In yet another preferred aspect, the weighted exponential decay signal is based on a time from which a synchronization pulse is added immediately before the weighted exponential decay signal.

[0015] In yet another preferred aspect, the steps are repeated by using the CW PPM duration signal generated from the analog input value that is an output of the MAC and the AF.

[0016] In yet another preferred aspect, the CW PPM duration signal enables data transmission by shortening a duration pulse.

[0017] In yet another preferred aspect, the memory access signal is separated into a ramp signal and a window signal.

[0018] In yet another preferred aspect, the ramp signal and the window signal determine a memory access amount for controlling data transfer.

[0019] It should be noted that the exemplary embodiments of the present invention are described with reference to different subject-matters of the claims. In particular, some embodiments are described with reference to claims for one type of method, while other embodiments have been described with reference to claims for one type of apparatus. However, a person skilled in the art will appreciate from the foregoing and the following description that, unless otherwise stated, in addition to any combination of features belonging to one type of subject-matter of the claims, any combination between features relating to different subject-matters of the claims, in particular between features of the claims for the method type and features of the claims for the apparatus type, is also considered to be described in this document.

[0020] These and other features and advantages will become apparent from the following detailed description of corresponding illustrative embodiments, which should be read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The invention provides details in the following description of preferred embodiments with reference to the following figures in which: Fig. 1 illustrates an exemplary continuous weighted pulse position modulation (PPM) duration scheme according to an embodiment of the present invention; Fig. 2 illustrates exemplary memory access signals for a memory access set according to an embodiment of the present invention; Fig. 3 is a block diagram / flowchart of an exemplary data process flow for the continuous weighted PPM duration scheme according to an embodiment of the present invention; Fig. 4 is an exemplary current-to-voltage converter according to an embodiment of the present invention; Fig. 5 is an exemplary signal processing system for the continuous weighted PPM duration scheme according to an embodiment of the present invention; Fig. 6 is an exemplary generator of a continuous weighted PPM duration signal according to an embodiment of the present invention; Fig. 7 is an exemplary converter of a continuous weighted PPM duration signal to access signals according to an embodiment of the present invention; Fig. 8 is an exemplary cell and array structure with memory access signals according to an embodiment of the present invention; Fig. 9 is a block diagram / flowchart of an exemplary processing system utilizing the continuous weighted PPM duration scheme according to an embodiment of the present invention; Fig. 10 is a block diagram / flowchart of an exemplary cloud computing environment according to an embodiment of the present invention; Fig. 11 is a block diagram of exemplary abstraction model layers according to an embodiment of the present invention; Fig. 12 illustrates exemplary applications for using the continuous weighted PPM duration scheme according to an embodiment of the present invention; Fig. 13 is a block diagram / flowchart of an exemplary method for using the continuous weighted PPM duration scheme according to an embodiment of the present invention.

[0022] The same or similar reference symbols represent the same or similar elements throughout the drawings. DETAILED DESCRIPTION

[0023] Embodiments according to the present invention provide methods and units for using continuous weighting for the position of duration pulses to shorten the duration pulse. The duration pulse can be shortened by converting the continuous weighted pulse position modulation (PPM) signal into memory access signals according to the added continuous weighting. After accessing the analog memory with converted signals, a multiply and accumulate (MAC) operation is achieved with a memory array and a current-to-voltage converter. The result of the MAC is sent to an activation function (AF), and a duration signal pulse is generated. The duration signal pulse is converted into a continuous weighted PPM duration signal.

[0024] PPM is a signal modulation technique that allows computers to share data by measuring the time it takes for each packet to reach the computer. PPM works by sending electrical, electromagnetic, or optical pulses to a computer or other device to transfer data. PPM requires that both devices be synchronized to the same clock so that when a series of pulses is sent, the device decodes the information based on the time at which the pulses were sent. PPM can be used advantageously to transfer large amounts of data.

[0025] The ability to act quickly and decisively in today's increasingly competitive marketplace is critical to the success of organizations. The volume of information available to companies is growing rapidly and is often overwhelming. Those organizations that effectively and efficiently manage these massive amounts of data and use the information to make business decisions gain a competitive advantage in the marketplace. Such competitive advantages can be achieved by using the continuous weighted (CW) PPM duration scheme presented herein, which transfers large amounts of data quickly and efficiently.

[0026] It should be understood that the present invention will be described in terms of a particular illustrative architecture; however, other architectures, structures, substrate materials, and process features and steps / blocks may be changed within the scope of aspects of the present invention. It should be noted that certain features may not be shown in all figures for clarity. This should in no way be construed as a limitation of any particular embodiment or illustration, or of the scope of the claims.

[0027] Fig. 1 illustrates an exemplary continuous weighted pulse position modulation (PPM) duration scheme according to an embodiment of the present invention.

[0028] Waveforms 5 show the input of the continuous-to-access conversion, whereas waveforms 5' show the output of the continuous-to-access conversion. The exemplary embodiments convert waveforms 5 into a memory access set. The maximum duration of the data period for both waveforms is 2 n on (In 2 n + α) or less.

[0029] Fig. 2 illustrates exemplary memory access signals for a memory access set according to an embodiment of the present invention.

[0030] The memory access amount can advantageously be separated into a "ramp" signal and a "window" signal. The first memory access amount signal 10 can be separated into a ramp signal 12 and a window signal 14. The window signal 14 can have a width of w1. The second memory access amount signal 20 can be separated into a ramp signal 22 and a window signal 24. The window signal 24 can have a width of w2, where w2 < w1. The third memory access amount signal 30 can be separated into a ramp signal 32 and a window signal 34. The window signal 34 can have a width of w3, where w3 < w2 < w1.

[0031] This correspondence can be explained with the following descriptions. The memory access amount signal 10 (memory access amount 1) may be an exponentially decaying signal with no delay from an initial time point. The memory access amount signal 20 (memory access amount 2) may be an exponentially decaying signal with a delay x1 from an initial time point, whereas the memory access amount signal 30 (memory access amount 3) may be the same signal with a delay x2 from an initial time point. The memory access amount may be controlled by the period of the active waveform of the exponentially decaying signal. The x i determines the period of the active waveform w i+1 , because in this case x i plus w i+1is constant. Therefore, the memory access amount can be determined by the initial time of the exponentially decaying signal and the period of the active waveform (w i+1 ). Thus, data transmission rates can be controlled by the CW PPM duration signal.

[0032] PPM is an analog modulation scheme in which the amplitude and width of the pulses are kept constant, whereas the position of each pulse relative to the position of a reference pulse varies according to the immediately sampled value of the message signal. The transmitter must send synchronization pulses (or sync pulses) to keep the transmitter and receiver synchronized. These sync pulses help maintain the position of the pulses. Pulse position modulation occurs according to the pulse-width modulated signal. Any trailing edge of the pulse-width modulated signal becomes the starting point for pulses in the PPM signal. Thus, the position of these pulses is proportional to the width of the PWM pulses.

[0033] Fig. 3 is a block diagram / flowchart of an exemplary data process flow for the continuous weighted PPM duration scheme according to an embodiment of the present invention.

[0034] At a block 40, a conversion from continuous to access signal takes place.

[0035] At a block 42, a multiply-accumulate (MAC) operation takes place on the memory cells.

[0036] A conversion of current into voltage takes place at a block 44.

[0037] An activation function is implemented at a block 46.

[0038] A continuous generation is carried out at a block 48.

[0039] A network router is advantageously used at a block 49.

[0040] Fig. 4 is an exemplary current-to-voltage converter according to an embodiment of the present invention.

[0041] The current-to-voltage converter 50 includes a first field-effect transistor (FET) 52, a second FET 54, and the second FET 54 is connected to a third FET 56. The third FET 56 is connected to a fourth FET 58, which in turn is connected to a capacitor 59. The third FET 56 and the fourth FET 58 may be p-type metal-oxide-semiconductor (PMOS) transistors, whereas the first FET 52 and the second FET 54 may be n-type metal-oxide-semiconductor (NMOS) transistors. One of ordinary skill in the art may consider a variety of different FET configurations to achieve current-to-voltage conversion.

[0042] Fig. 5 is an exemplary signal processing system for the continuous weighted PPM duration scheme according to an embodiment of the present invention.

[0043] The signal processing system 60 may advantageously include a signal generator 62, a converter 64, a MAC operation unit 66, an activation function operation unit 68, and an output 69. Thus, the signal processing system 60 for an analog neural network unit may include a signal generator 62 for generating a temporarily continuous weighted pulse position modulation (CW PPM) duration signal from an analog input signal, a converter 64 for converting the CW-PPM duration signal into a memory access signal, a multiplier and accumulator (MAC) operation unit 66 for processing by accessing the memory with the above-mentioned memory access signal, and an activation function (AF) operation unit 68 for processing the result 69 of the MAC operation unit and for generating the analog input signal for the signal generator.

[0044] Fig. 6 is an exemplary generator of a continuous weighted PPM duration signal according to an embodiment of the present invention.

[0045] An input signal vdg_level_in (70) is received from the positive terminal of comparator 88. The operational amplifier in the form of a comparator 88 can advantageously be used to search for the value of an input voltage that is greater than a specified range. In other embodiments, the operational amplifier in the form of a comparator 88 can advantageously be used to search for the value of positive and negative voltages when the specific value of a reference voltage source is connected to the inverting input.

[0046] A signal vdg_sync_in (72) is received by a sync timing controller 74. The sync timing controller 74 outputs four signals. The first signal, vdg_delayed_sync (76), is received by a waveform merger 90. The vdg_delayed_sync (76) is also fed to comparator 88 as an en_trig input, which triggers activation of comparator 88. The second signal, vdg_duration_end (78), is fed to comparator 88 as a reset trigger signal (rst_trig), which resets the output of comparator 88, vdg_cmp_result (89), to zero. The third signal, vdg_sync1 (80), is fed to a transfer gate (T-gate) 81, which operates as an ON / OFF switch with the supplied signal. The fourth signal vdg_sync2 (82) is received by a T-gate 83 in a circuit configuration 85 with a resistor “R” and a capacitor “C”.The output of circuit configuration 85 is a signal vdg_rc_slope (84), which is fed to an analog buffer 87 connected to the negative terminal of comparator 88. Comparator 88 advantageously outputs a comparison result as a signal vdg_cmp_result (89). The signal vdg_cmp_result (89) is provided to waveform merger 90 with the signal vdg_delayed_sync (76).

[0047] The vdg_rc_slope (84) signal, which is applied to the negative terminal of comparator 88, is an exponentially decaying signal, and the vdg_level_in (70) input signal, which is applied to the positive terminal of comparator 88, is an analog level signal. Comparator 88 compares these signals and advantageously provides the output signal vdg_out (92). The continuous weighted PPM duration signal (92), which is the output of waveform merger 90, is illustrated in the lower right corner.

[0048] Fig. 7 is an exemplary converter of a continuous weighted PPM duration signal to access signals according to an embodiment of the present invention.

[0049] The signal vdasc_in (100) is received by a sync_duration_separator 102. The signal vdasc_in (100) is the signal (92) received by the CW PPM duration signal generator of Fig. 6 is generated.

[0050] The sync_duration_separator 102 advantageously outputs three signals. The first signal is vdasc_window_out (104). The second signal vdasc_sync1 (106) is fed to a T-gate 107. The third signal vdasc_sync2 (108) is fed to a T-gate 109 in a circuit configuration 115 with a resistor "R" and a capacitor "C." The analog buffer 112 receives the signal vdasc_rc_slope (110), which is generated from the signals vdasc_sync1 (106) and vdasc_sync2 (108). The output of the analog buffer 112 is a signal vdasc_slope_out (114). The waveforms of the input signal vdasc_rc_slope (110) and the output signal vdasc_slope_out (114) are almost identical, since the analog buffer 112 only controls the analog input signal and generates the analog output signal. The signal vdasc_slope_out (114) is an exponentially decaying signal. Thus, the signal vdasc_in (100) has been advantageously converted into a memory access signal vdasc_slope_out (114).

[0051] Fig. Figure 8 is an exemplary cell and array structure with memory access signals according to an embodiment of the present invention.

[0052] An array structure 190 includes a plurality of cells. A first cell 130 includes an FET 132 and a variable resistor 134. The variable resistor 134 can be connected to the drain (D) of the FET 132. The source (S) of the FET 132 can be connected to a bit row 192. The bit row 192 can connect the source (S) of multiple FETs of different cells. For example, a cell 150 and a cell 170 are vertically aligned with the cell 130. Cell 150 includes a variable resistor 154 and an FET 152, and cell 170 includes a variable resistor 174 and an FET 172. Similarly, cell 140 may be horizontally aligned with cell 130, cell 160 may be horizontally aligned with cell 150, and cell 180 may be horizontally aligned with cell 170. For example, cell 140 includes a variable resistor 144 and an FET 142.The source (S) of FET 140 can be connected to a bit line 194. Bit line 194 can connect the source (S) of multiple FETs of different cells, i.e., cells 160, 180.

[0053] The signal vdasc_slope_out_0 (120) is advantageously received by one of the word rows 136 of the first row of horizontal cells 130, 140, etc. The signal vdasc_window_out_0 (122) is advantageously received by another word row 138 connected to the gate of FET 132 of cell 130 and FET 132 of cell 130 and FET 142 of cell 140, etc. The signal 120 may be an exponentially decaying signal, whereas the signal 122 may be a pulse signal. The pulse signal may have a width of w4. The memory access amount may be specified by w4. The signal vdasc_slope_out_0 (120) is a fully exponentially decaying signal and the signal vdasc_window_out_0 (122) is high during the limited period (w4).For these two signals, the access current from memory cell 130 is proportional to the level of signal vdasc_slope_out_0 (120) only during period w4, because FET 132 is ON when signal vdasc_window_out_0 (122) is high. In other words, no read current comes from cell 130 when signal vdasc_window_out_0 (122) is low.

[0054] The signal vdasc_slope_out_1 (124) is advantageously received by one of the word rows 156 of the first row of horizontal cells 150, 160, etc. The signal vdasc_window_out_1 (126) is advantageously received by another word row 158 connected to the gate of FET 152 of cell 150, FET 132 of cell 130, FET 162 of cell 160, etc. The signal 124 may be an exponentially decaying signal, whereas the signal 126 may be a pulse signal. The pulse signal may have a width of w5. The memory access amount may be specified by w5. The signal vdasc_slope_out_1 (124) is a fully exponentially decaying signal and the signal vdasc_window_out_1 (126) is high during the limited period (ws).For these two signals, the access current from memory cell 150 is proportional to the level of vdasc_slope_out_1 (124) only during period w5, because FET 152 is ON when signal vdasc_window_out_1 (126) is high. In other words, no read current comes from cell 150 when signal vdasc_window_out_1 (126) is low.

[0055] The signal vdasc_slope_out_n-1 (128) is advantageously received by one of the word rows 176 of the first row of horizontal cells 170, 180, etc. The signal vdasc_window_out_n-1 (129) is advantageously received by another word row 178 connected to the gate of FET 172 of cell 170 and FET 182 of cell 189, etc. Signal 128 may be an exponentially decaying signal, whereas signal 129 may be a pulse signal. The pulse signal may have a width of w6. The memory access amount may be specified by w6. The signal vdasc_slope_out_n-1 (128) is a fully exponentially decaying signal and the signal vdasc_window_out_n-1 (129) is high during the limited period (w6).For these two signals, the access current from memory cell 170 is proportional to the level of vdasc_slope_out_n-1 (128) only during period w6, because FET 172 is ON when signal vdasc_window_out_n-1 (129) is high. In other words, no read current comes from cell 170 when signal vdasc_window_out_n-1 (129) is low. Thus, the signal vdasc_slope_out_0 (120), the signal vdasc_slope_out_1 (124), ... and the signal vdasc_slope_out_n-1 (128) all have the same shape, while the signal vdasc_window_out_0 (122), the signal vdasc_window_out_1 (124), ... and the signal vdasc_window_out_n-1 (129) are different word for word.

[0056] Therefore, data transmission can be achieved using CW PPM time-duration signals. The data rate is a measurement of the amount of data sent between two points on a network in a given period of time. High data rates are an important concept in modern business networking, enabling networks to be used for complex tasks such as online streaming. Knowing the data rate could help improve the performance of a business's own network. The data rate is typically measured in bits per second (bps), where a "bit" corresponds to a single binary number. This is similar to the networking concept of bandwidth, which is also measured in bps. However, data rate and bandwidth are two different things.The transfer rate checks the amount of data that has actually been transferred between two different points, whereas the bandwidth is a measurement of the theoretical maximum transmission capacity of a particular point on the network.

[0057] Every network application requires a certain amount of data to function effectively. For example, a web browser needs to receive the necessary data from a website each time a user navigates to a new page. A low transfer rate impairs the delivery of this data to applications. This typically causes slow performance, such as reduced speed or choppy streaming. Furthermore, a very low transfer rate could cause some applications to stop working altogether. Some online tasks require a higher data transfer rate than others. For example, online streaming actually requires a computer to download a new image every fraction of a second. This consumes far more data than, say, sending an email.Therefore, the effects of a low data rate are most noticeable for organizations and individuals who regularly deal with data-intensive applications. The CW PPM duration signals used herein, as shown in . Fig. 1 to 8 can advantageously achieve fast and efficient data transmission rates.

[0058] Fig. 9 is a block diagram / flowchart of an exemplary processing system utilizing the continuous weighted PPM duration scheme according to an embodiment of the present invention.

[0059] Fig. Figure 9 illustrates a block diagram of components of the system 200, which includes a data processing unit 205. It should be clear that Fig. 9 provides only an illustration of one implementation and does not imply limitations on the environments in which various embodiments may be implemented. Many modifications may be made to the illustrated environment.

[0060] The data processing unit 205 includes a data transfer structure 202 that provides data transfers between one or more computer processors 204, a memory 206, persistent storage 208, a data transfer unit 210, and one or more input / output (I / O) interfaces 212. The data transfer structure 202 may be implemented using any architecture designed for passing data and / or controlling information between processors (such as microprocessors, data and network processors, etc.), system memories, peripheral units, and any other hardware components in a system. For example, the data transfer structure 202 may be implemented using one or more buses.

[0061] The memory 206, the cache memory 216, and the persistent storage 208 are computer-readable storage media. In this embodiment, the memory 206 comprises random access memory (RAM) 214. In another embodiment, the memory 206 may be flash memory. In general, the memory 206 may comprise any suitable volatile or non-volatile computer-readable storage medium.

[0062] In some embodiments of the present invention, program 225 is contained within and operated by an AI accelerator chip 222 as a component of data processing unit 205. In other embodiments, program 225 is stored in persistent storage 208 for execution by an AI accelerator chip 222 in conjunction with one or more of the respective computer processors 204 via one or more memory locations of memory 206. The AI ​​accelerator chip 222 may advantageously drive a neural network unit 250 via CW PPM duration signal processing. In this embodiment, persistent storage 208 comprises a magnetic hard disk.Alternatively or in addition to a magnetic hard disk, the permanent storage 208 may comprise a solid-state hard disk, a semiconductor memory device, a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, or any other computer-readable storage medium capable of storing program instructions or digital information.

[0063] The media used by the persistent storage 208 may also be removable. For example, a removable hard drive may be used for the persistent storage 208. Other examples include optical and magnetic disks, USB flash drives, and smart cards used for data transfer to a drive on another computer-readable storage medium that is also part of the persistent storage 208.

[0064] In these examples, the communication unit 210 provides data communications with other computing systems or devices, including resources of a distributed computing environment. In these examples, the communication unit 210 includes one or more network interface cards. The communication unit 210 may provide data communications using physical and / or wireless communication links. A deep learning program 225 may be downloaded to the persistent storage 208 via the communication unit 210.

[0065] One or more I / O interfaces 212 enable the input and output of data with other devices that may be connected to the data processing system 200. For example, the I / O interface 212 may provide a connection to external devices 218, such as a keyboard, keypad, touchscreen, and / or other suitable input device. The external devices 218 may also include portable, computer-readable storage media, such as USB flash drives, portable optical or magnetic disks, and memory cards.

[0066] The display 220 provides a mechanism for displaying data to a user and may be, for example, a computer monitor.

[0067] Fig. 10 is a block diagram / flowchart of an exemplary cloud computing environment according to an embodiment of the present invention.

[0068] Although this invention includes a detailed description of cloud computing, it should be understood that implementation of the teachings herein is not limited to a cloud computing environment. Rather, embodiments of the present invention may be implemented in conjunction with any type of computing environment now known or later developed.

[0069] Cloud computing is a service delivery model for enabling seamless, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) that can be rapidly provisioned and released with minimal management effort or interaction with a service provider. This cloud model can include at least five characteristics, at least three service models, and at least four usage models.

[0070] The properties are as follows:

[0071] On-demand self-service: A cloud user can unilaterally and automatically provision data processing functions such as server time and network storage as needed, without requiring human interaction with the service provider.

[0072] Broad Network Access: Functions are available over a network and accessed through standard mechanisms that support use by heterogeneous thin or thick client platforms (e.g., mobile phones, laptops, and PDAs).

[0073] Resource Pooling: The provider's computing resources are pooled to serve multiple users using a multi-tenant model, with various physical and virtual resources dynamically allocated and reassigned as needed. There is a perceived location independence, as the user generally has no control or knowledge over the exact location of the provided resources, but may be able to specify a location at a higher level of abstraction (e.g., country, state, or data center).

[0074] Rapid Elasticity: Features can be deployed quickly and elastically for rapid horizontal scaling out, in some cases automatically, and released quickly for rapid scale-in. To the user, the features available for deployment often appear unlimited, and they can be purchased in any quantity at any time.

[0075] Measured Service: Cloud systems automatically control and optimize resource usage by leveraging a metering function at a certain level of abstraction appropriate for the type of service (e.g., storage, processing, bandwidth, and active user accounts). Resource consumption can be monitored, controlled, and reported, creating transparency for both the provider and the user of the service.

[0076] The service models are as follows:

[0077] Software as a Service (SaaS): The functionality provided to the user is to use the provider's applications running on a cloud infrastructure. The applications are accessible from various client devices via a thin client interface such as a web browser (e.g., a web-based email). The user does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, storage, or even individual application functions, with the possible exception of limited user-specific application configuration settings.

[0078] Platform as a Service (PaaS): The functionality provided to the user is to deploy applications created or obtained by the user, using programming languages ​​and tools supported by the provider, into the cloud infrastructure. The user does not manage or control the underlying cloud infrastructure, including networks, servers, operating systems, or storage, but has control over the deployed applications and possibly over configurations of the application hosting environment.

[0079] Infrastructure as a Service (IaaS): The functionality provided to the user consists of providing processing, storage, networking, and other basic computing resources, allowing the user to deploy and run any software, including operating systems and applications. The user does not manage or control the underlying cloud infrastructure, but has control over operating systems, storage, deployed applications, and potentially limited control over selected network components (e.g., host firewalls).

[0080] The usage models are as follows:

[0081] Private Cloud: The cloud infrastructure is operated exclusively for an organization. It can be managed by the organization or a third party and can be located on or off-premises.

[0082] Community Cloud: The cloud infrastructure is shared by multiple organizations and supports a specific community with common problems (e.g., considering objectives, security requirements, policies, and compliance). It can be managed by the organizations or a third party and can be located on or off-premises.

[0083] Public Cloud: The cloud infrastructure is made available to the general public or a large industry group and is owned by an organization that sells cloud services.

[0084] Hybrid Cloud: The cloud infrastructure is a composition of two or more clouds (private, community, or public) that remain separate entities but are interconnected by a standardized or proprietary technology that enables data and application portability (e.g., cloud targeting for load balancing between clouds).

[0085] A cloud computing environment is service-oriented, with an emphasis on statelessness, low coupling, modularity, and semantic interoperability. At the core of cloud computing is an infrastructure comprising a network of interconnected nodes.

[0086] With reference to Fig. 10, an illustrative cloud computing environment 350 is depicted to enable use cases of the present invention. As shown, the cloud computing environment 350 includes one or more cloud computing nodes 310 with which local computing devices employed by users of the cloud, such as personal digital assistant (PDA) or cellular phone 354a, desktop computer 354b, laptop computer 354c, and / or vehicle computer system 354n, can communicate. The nodes 310 can communicate with each other. They can be physically or virtually grouped in one or more networks (not shown), such as private, community, public, or hybrid clouds, as described hereinabove, or a combination thereof.This allows cloud computing environment 350 to offer infrastructure, platforms, and / or software as services without requiring a cloud user to maintain any resources on a local computing device. It should be understood that the types of computing devices 354a through n described in . Fig. 10 are for illustrative purposes only, and that the cloud computing nodes 310 and the cloud computing environment 350 can communicate with any type of computerized device over any type of network and / or network-addressable connection (e.g., using a web browser).

[0087] Fig. 11 is a block diagram of exemplary abstraction model layers according to an embodiment of the present invention. It should be clear from the outset that the Fig. The components, layers, and functions shown in Figure 11 are for illustrative purposes only, and embodiments of the invention are not limited thereto. As shown, the following layers and corresponding functions are provided:

[0088] A hardware and software layer 460 includes hardware and software components. Examples of hardware components include: mainframes 461; servers based on a RISC (Reduced Instruction Set Computer) architecture 462; servers 463; blade servers 464; storage devices 465; and networks and networked components 466. In some embodiments, software components include network application server software 467 and database software 468.

[0089] A virtualization layer 470 provides an abstraction layer from which the following example virtual entities may be deployed: virtual servers 471; virtual storage 472; virtual networks 473, including virtual private networks; virtual applications and operating systems 474; and virtual clients 475.

[0090] In one example, a management layer 480 may provide the functions described below. Resource provisioning 481 provides for dynamic procurement of computing resources and other resources used to perform tasks within the cloud computing environment. Metering and pricing 482 enable cost tracking and billing or invoicing for the use of resources within the cloud computing environment. In one example, these resources may include licenses for application software. A security function provides identity verification for cloud users and tasks, as well as protection for data and other resources. A user portal 483 provides access to the cloud computing environment for users and system administrators.Service Level Management 484 ensures the allocation and management of cloud computing resources so that required service levels are met. Service Level Agreement (SLA) planning and contract fulfillment 485 provides advance agreement and procurement of cloud computing resources for which future demand is expected according to an SLA.

[0091] A workload layer 490 provides examples of functionality for which the cloud computing environment can be utilized. Examples of workloads and functions that can be provided from this layer include: mapping and navigation 491; software development and lifecycle management 492; virtual training delivery 493; data analysis processing 494; transaction processing 495; and CW-PPM duration signal processing 496.

[0092] Fig. 12 illustrates practical applications for using the continuous weighted PPM duration scheme according to an embodiment of the present invention.

[0093] The artificial intelligence (AI) accelerator chip 501 can implement or drive the neural network unit 250 via the CW PPM duration signal processing 496 and can be used in a wide variety of practical applications, including, but not limited to, robotics 510, industrial applications 512, cellular or Internet of Things (IoT) 514, PC 516, consumer electronics 518, server data centers 520, physics and chemistry applications 522, healthcare applications 524, and financial applications 526.

[0094] For example, robotic process automation, or RPA 510, enables organizations to automate tasks, streamline processes, increase employee productivity, and ultimately deliver a superior customer experience. Using RPA 510, a robot can perform large, high-volume tasks, freeing the company's resources to work on higher-value activities. An RPA 510 robot emulates a human performing manual, repetitive tasks, making decisions based on a defined set of rules, and integrating with existing applications. All of this ensures compliance, reduces errors, and improves customer experience and employee engagement.

[0095] Fig.13 is a block diagram / flowchart of an exemplary method for using the continuous weighted PPM duration scheme according to an embodiment of the present invention.

[0096] At a block 602, a temporally continuous weighted pulse position modulation (CW PPM) duration signal is generated from an analog input signal.

[0097] At a block 604, the CW PPM duration signal is transmitted through a network router from a presynaptic neuron to a postsynaptic neuron.

[0098] At a block 606, the CW PPM duration signal is converted into a memory access signal.

[0099] At a block 608, a multiply and accumulate (MAC) operation is performed on the memory access signal.

[0100] At a block 610, the aforementioned analog input signal is generated from the result of the MAC operation by an activation function (AF).

[0101] The present invention may be a system, a method, and / or a computer program product. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions stored thereon for causing a processor to perform aspects of the present invention.

[0102] The computer-readable storage medium may be any physical device capable of retaining and storing instructions for use by a device for executing instructions. The computer-readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer-readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory (EPROM).Flash memory), a static random access memory, a portable CD-ROM, a DVD, a memory stick, a floppy disk, a mechanically encoded device such as punched cards or raised structures in a groove on which instructions are stored, and any suitable combination of the foregoing. A computer-readable storage medium, as used herein, should not be construed as containing transient signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., pulses of light carried through a fiber optic cable), or electrical signals carried through a wire.

[0103] Computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to respective computing / processing units or to an external computer or storage unit via a network such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may include copper transmission cables, fiber optic transmission lines, wireless transmission, routers, firewalls, switching units, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing unit receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium within the respective computing / processing unit.

[0104] Computer-readable program instructions for performing operations of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, or the like, as well as conventional procedural programming languages ​​such as the "C" programming language or similar programming languages.The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer over any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, over the Internet using an Internet service provider).In some embodiments, electronic circuits, including, for example, programmable logic circuits, field programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), may execute the computer-readable program instructions by utilizing state information of the computer-readable program instructions to personalize the electronic circuits to perform aspects of the present invention.

[0105] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, may be implemented using computer-readable program instructions.

[0106] These computer-readable program instructions may be provided to at least one processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that the instructions executing via the processor of the computer or other programmable data processing apparatus produce a means for implementing the functions / steps specified in the flowchart and / or block diagram block(s) or modules.These computer-readable program instructions may also be stored on a computer-readable storage medium that can direct a computer, a programmable data processing apparatus, and / or other devices to function in a particular manner, such that the computer-readable storage medium having instructions stored thereon comprises an article of manufacture, including instructions that implement aspects of the function / step specified in the flowchart block(s) and / or block diagrams or modules.

[0107] The computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process such that the instructions executing on the computer, other programmable apparatus, or other device implement the functions / steps specified in the block(s) of flowcharts and / or block diagrams or modules.

[0108] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions containing one or more executable instructions for implementing the particular logical function(s). In some alternative implementations, the functions specified in the blocks may occur in a different order than shown in the figures. For example, two blocks shown consecutively may actually execute substantially in parallel, or the blocks may sometimes execute in the reverse order, depending on the functionality involved.It is further to be understood that each block of the block diagrams and / or flowchart illustrations, and combinations of blocks in the block diagrams and / or flowchart illustrations, may be implemented by special purpose hardware-based systems that perform the specified functions or acts, or by combinations of special purpose hardware and computer instructions.

[0109] Reference in the specification to "the one embodiment" or "an embodiment" of the present principles, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment are included in at least one embodiment of the present principles. Thus, the appearances of the phrase "in the one embodiment," "in an embodiment," and any variations thereof appearing in various places throughout the specification do not necessarily all refer to the same embodiment.

[0110] It should be recognized that the use of each of the subsequent “ / ”, “and / or”, and “at least one of”, for example, in the cases of “A / B”, “A and / or B”, and “at least one of A and B”, is intended to include only the selection of the first listed option (A), or only the selection of the second listed option (B), or both options (A and B). As a further example, in the cases of “A, B, and / or C” and “at least one of A, B, and C”, such wording is intended to include only the selection of the first listed option (A), or only the selection of the second listed option (B), or only the selection of the third listed option (C), or only the selection of the first and second listed options (A and B), or only the selection of the first and third listed options (A and C), or only the selection of the second and third listed options (B and C), or all three options (A, B, and C).This can, as will be readily apparent to a person skilled in this and related fields, be extended as often as listed.

[0111] Having described preferred embodiments of a method for transmitting data using continuous weighted pulse position modulation (PPM) duration signals (which are to be considered illustrative and not limiting), it is noted that modifications and variations may be made by those skilled in the art in light of the above teachings. It should therefore be understood that changes may be made to the particular embodiments described which are within the scope of the invention as set forth by the appended claims. After describing aspects of the invention with the detail and particularity required by the patent laws, the appended claims set forth what is claimed and desired to be protected by the patent.

Claims

[1] A method for processing signals implemented by a computer, the method comprising: Generating a temporally continuous weighted pulse position modulation (CW PPM) duration signal from an analog input signal; Converting the CW PPM duration signal into a memory access signal; Performing a multiply and accumulate (MAC) operation with the memory access signal; and Generating the analog input signal from a result of the MAC operation by an activation function (AF). [2] The computer-implemented method of claim 1, wherein the CW PPM duration signal is transmitted from a presynaptic neuron to a postsynaptic neuron by a network router. [3] A computer implemented method according to claim 1 or 2, wherein the CW PPM duration signal is a weighted exponential decay signal. [4] A computer-implemented method according to claim 3, wherein the weighted exponential decay signal is based on a time from which a synchronization pulse is added immediately before the weighted exponential decay signal. [5] A computer implemented method according to any preceding claim, further comprising repeating each of the steps by using the CW PPM duration signal generated from the analog input value that is an output of the MAC and the AF. [6] A computer-implemented method according to any preceding claim, wherein the CW PPM duration signal enables data transmission by shortening a duration pulse. [7] A computer-implemented method according to any preceding claim, wherein the memory access signal is separated into a ramp signal and a window signal. [8] A computer-implemented method according to claim 7, wherein the ramp signal and the window signal determine a memory access amount for controlling data transfer. [9] A computer program product for processing signals, the computer program product comprising a computer-readable storage medium having program instructions embodied thereon, the program instructions being executable by a computer to cause the computer to: Generating a temporally continuous weighted pulse position modulation (CW PPM) duration signal from an analog input signal; Converting the CW PPM duration signal into a memory access signal; Performing a multiply and accumulate (MAC) operation with the memory access signal; and Generating the analog input signal from a result of the MAC operation by an activation function (AF). [10] The computer program product of claim 9, wherein the CW PPM duration signal is transmitted by a network router from a presynaptic neuron to a postsynaptic neuron. [11] A computer program product according to claims 9 or 10, wherein the CW PPM duration signal is a weighted exponential decay signal. [12] The computer program product of claim 11, wherein the weighted exponential decay signal is based on a time from which a synchronization pulse is added immediately before the weighted exponential decay signal. [13] The computer program product of any of claims 9 to 12, further comprising repeating each of the steps by using the CW PPM duration signal generated from the analog input value that is an output of the MAC and the AF. [14] A computer program product according to any one of claims 9 to 13, wherein the CW PPM duration signal enables data transmission by shortening a duration pulse. [15] A computer program product according to any one of claims 9 to 14, wherein the memory access signal is separated into a ramp signal and a window signal. [16] The computer program product of claim 15, wherein the ramp signal and the window signal determine a memory access amount for controlling data transfer. [17] A signal processing system for an analog neural network unit, the system comprising: a signal generator for generating a temporally continuous weighted pulse position modulation (CW PPM) duration signal from an analog input signal; a converter for converting the CW PPM duration signal into a memory access signal; a multiply and accumulate (MAC) operator for processing by accessing the memory with the memory access signal; and an activation function (AF) operator for processing a result of the MAC operator and generating the analog input signal for the signal generator. [18] The system of claim 17, wherein the CW PPM duration signal is transmitted by a network router from a presynaptic neuron to a postsynaptic neuron. [19] The system of claim 17 or 18, wherein the CW PPM duration signal is a weighted exponential decay signal. [20] The system of claim 19, wherein the weighted exponential decay signal is based on a time from which a synchronization pulse is added immediately before the weighted exponential decay signal. [21] A system according to any one of claims 17 to 20, wherein the CW PPM duration signal enables data transmission by shortening a duration pulse. [22] A system according to any one of claims 17 to 21, wherein the memory access signal is separated into a ramp signal and a window signal. [23] The system of claim 22, wherein the ramp signal and the window signal determine a memory access amount for controlling data transfer. [24] Array structure that has: a plurality of memory cells integrated between a plurality of bit lines and a plurality of word lines, each memory cell comprising: a field-effect transistor (FET) comprising a gate, a source, and a drain; and a variable resistor having one end electrically connected to the drain of the FET and the other end electrically connected to one of the word rows of the two word rows in a memory cell; wherein a ramp signal is applied to one of the word lines and a window signal is applied to another word line connected to the gate of the FET, such that the ramp signal and the window signal are combined to form a memory access signal derived from a continuous weighted pulse position modulation (CW PPM) duration signal. [25] A method for constructing an array structure, the method comprising: Integrating a plurality of memory cells between a plurality of bit lines and a plurality of word lines, each memory cell comprising: a field-effect transistor (FET) comprising a gate, a source, and a drain; and a variable resistor having one end electrically connected to the drain of the FET and the other end electrically connected to one of the word rows of the two word rows in a memory cell; and Supplying a ramp signal to one of the word lines and a window signal to another word line connected to the gate of the FET such that the ramp signal and the window signal are combined to form a memory access signal derived from a continuous weighted pulse position modulation (CW PPM) duration signal.