semiconductor chip

Abstract

A semiconductor chip (1) comprises a plurality of transistor cells (100) arranged side by side along a first direction (Y). The transistor cells include a gate junction (22a, 22b) extending along a second direction (X) orthogonal to the first direction, and a first semiconductor region (17) extending along the second direction and of a first conductive type. The gate junction is arranged such that the mutual inductance generated between the gate junction of one transistor cell and the gate junction of another transistor cell is negative, with the two transistor cells being adjacent.The first semiconductor area is arranged such that a mutual inductance generated between the first semiconductor area of ​​one transistor cell and the first semiconductor area of ​​another transistor cell has a negative value, with the one transistor cell and the other transistor cell being adjacent to each other.

Description

[0001] The present invention relates to semiconductor chips. State of the art

[0002] This application claims priority from Japanese Patent Application No. 2022-082048 filed on May 19, 2022, and the entire contents of this Japanese patent application are hereby incorporated by reference.

[0003] Semiconductor chips with a plurality of transistor cells arranged in parallel are known (see, for example, Patent Literature 1). List of citationsPatent literature

[0004] Patent Literature 1: Published Japanese Patent Application No. 2012-23291 Summary of the invention

[0005] A semiconductor chip of the present invention comprises a plurality of transistor cells arranged adjacent to each other in a first direction. The transistor cells include: a gate interconnect extending along a second direction orthogonal to the first direction; and a first semiconductor region extending along the second direction and being of a first conductive type. The gate interconnect is arranged such that a mutual inductance generated between the gate interconnection of one transistor cell of the transistor cells and the gate interconnection of another transistor cell of the transistor cells has a negative value, the one transistor cell and the other transistor cell being adjacent to each other.The first semiconductor region is arranged such that a mutual inductance generated between the first semiconductor region of one transistor cell of the transistor cells and the first semiconductor region of another transistor cell of the transistor cells has a negative value, the one transistor cell and the other transistor cell being adjacent to each other. Short description of the drawings Fig. 1 is a circuit diagram showing a semiconductor chip according to an embodiment. Fig. 2 is a plan view showing the semiconductor chip according to the embodiment. Fig. 3 is a perspective cross-sectional view showing the semiconductor chip according to the embodiment. Fig. 4 is a cross-sectional view showing configurations of an electric field relaxation region and a connection region in the semiconductor chip according to the embodiment. Fig. 5 is a cross-sectional view showing configurations of a contact region and the connection region in the semiconductor chip according to the embodiment. Fig. 6 is a cross-sectional view showing the semiconductor chip according to the embodiment (part 1). Fig. 7 is a cross-sectional view showing the semiconductor chip according to the embodiment (part 2). Fig. 8 is a cross-sectional view showing the semiconductor chip according to the embodiment (part 3). Fig. 9 is a cross-sectional view showing the semiconductor chip according to the embodiment (part 4). Fig. 10 is a cross-sectional view showing the semiconductor chip according to the embodiment (part 5). Detailed description of the invention [Problems to be solved by the present invention]

[0006] In existing semiconductor chips, a current flows in the same direction through the p+ body layers of adjacent transistor cells. Therefore, the internal inductance of the p+ body layers can increase due to the mutual inductance generated between adjacent p+ body layers.

[0007] In existing semiconductor chips, a current of the same direction flows through the gate interconnections of adjacent transistor cells. Therefore, the internal inductance of the gate interconnections can increase due to the mutual inductance generated between the adjacent gate interconnections.

[0008] It is an object of the present invention to provide a semiconductor chip in which the internal inductance can be reduced. [Effects of the present invention]

[0009] According to the present invention, it is possible to reduce the internal inductance.

[0010] Embodiments of the present invention are described below. [Description of Embodiments of the Present Invention]

[0011] First, the embodiments of the present invention are listed and described. In the following description, the same or corresponding elements are denoted by the same symbols, and the same description will not be repeated.

[0012] [1] A semiconductor chip according to one aspect of the present invention comprises: a plurality of transistor cells arranged side by side along a first direction, the transistor cells comprising a gate interconnection extending along a second direction orthogonal to the first direction and a first semiconductor region extending along the second direction and being of a first conductive type, the gate interconnection being arranged such that a mutual inductance generated between the gate interconnection of one transistor cell of the transistor cells and the gate interconnection of another transistor cell of the transistor cells has a negative value, the one transistor cell and the other transistor cell being adjacent to each other, and the first semiconductor region being arranged such thatthat a mutual inductance generated between the first semiconductor region of one transistor cell of the transistor cells and the first semiconductor region of another transistor cell of the transistor cells has a negative value, with the one transistor cell and the other transistor cell being adjacent to each other. In this case, the mutual inductance of the gate interconnections acts in a direction that reduces the self-inductance of the gate interconnections. This can reduce the internal inductance of the gate lines. Therefore, gate voltage hum can be suppressed. Furthermore, the mutual inductance of the first semiconductor regions acts in a direction that reduces the self-inductance of the first semiconductor regions. This can reduce the internal inductance of the first semiconductor regions. Therefore, a semiconductor chip with excellent switching characteristics is obtained.

[0013] [2] In [1], the gate interconnection may be arranged such that the directions of the currents flowing along the second direction between the gate interconnection of one transistor cell and the gate interconnection of the other transistor cell are opposite. In this case, the mutual inductance is likely to assume a negative value.

[0014] [3] In [1] or [2], the semiconductor chip may comprise: a semiconductor substrate; a gate contact arranged on the semiconductor substrate; a first interconnection configured to electrically connect the gate interconnection and the gate contact; and a second interconnection configured to electrically connect the gate interconnection and the gate contact, wherein the first interconnection may extend along the first direction, wherein the second interconnection may be arranged such that a plurality of gate interconnections are located between the second interconnection and the first interconnection, the plurality of gate interconnections each constitute the gate interconnection, the gate interconnections include a first gate interconnection electrically connected to the first interconnection and a second gate interconnection,which is electrically connected to the second interconnect, and the first gate interconnect and the second gate interconnect may be arranged alternately along the first direction. In this case, currents from opposite directions are likely to flow through the adjacent gate interconnects.

[0015] [4] In [3], the first gate interconnection and the second gate interconnection may be parallel to each other. In this case, the mutual inductance is likely to act in the direction of reducing the self-inductance.

[0016] [5] In [3] or [4], the semiconductor substrate may be a silicon carbide substrate. In this case, an excellent breakdown voltage is likely to be achieved.

[0017] [6] In [1] to [5], the transistor cells may be electrically connected to a common source terminal and a common drain terminal. In this case, a plurality of transistor cells may be mounted on a single semiconductor chip.

[0018] [7] In [1] to [6], the first semiconductor region may be arranged such that the directions of the currents flowing along the second direction between the first semiconductor region of one transistor cell and the first semiconductor region of the other transistor cell are opposite. In this case, the mutual inductance is likely to assume a negative value.

[0019] [8] In [1] to [7], the transistor cells may further comprise: a source electrode; and a second semiconductor region electrically connected to the first semiconductor region and the source electrode and of the first conductive type, wherein the second semiconductor region may be arranged such that the second semiconductor region of one transistor cell may be arranged at a position different in the second direction from that of the second semiconductor region of the other transistor cell. In this case, currents from opposite directions are likely to flow through the first semiconductor regions side by side.

[0020] [9] In [8], a plurality of second semiconductor regions, each constituting the second semiconductor region, may be arranged along the second direction, and positions in the second direction at which the second semiconductor regions are arranged in one transistor cell may represent an intermediate position between two second semiconductor regions of the second semiconductor regions of the other transistor cell, wherein the two second semiconductor regions are adjacent to each other in the second direction. In this case, currents from opposite directions are likely to flow through the first semiconductor regions adjacent to each other.

[0021]

[10] In [1] to [9], the first semiconductor regions can represent an electric field relaxation region. In this case, the internal inductance of the E-field relaxation region can be reduced.

[0022]

[11] In [1] to

[10] , the transistor cells can represent a vertical transistor cell. In this case, both a reduction in on-state resistance and an increase in breakdown voltage can be achieved. [Details of embodiments of the present invention]

[0023] Embodiments of the present invention are described in detail below. However, the present invention is not limited thereto.

[0024] A semiconductor chip 1 according to an embodiment is described.

[0025] Fig. 1 is a circuit diagram showing the semiconductor chip 1 according to the embodiment. As shown in Fig. 1, the semiconductor chip 1 according to the embodiment comprises a plurality of transistor cells 100.

[0026] The transistor cells 100 are electrically connected in parallel. The transistor cells 100 are electrically connected to a common gate terminal G, a common source terminal S, and a common drain terminal D. In this case, the transistor cells 100 can be mounted on a single semiconductor chip 1. In each of the transistor cells 100, a body diode BD is formed between the source terminal S and the drain terminal D.

[0027] Each transistor cell 100 is connected to the gate terminal G via a gate interconnect 22. The gate interconnect 22 may have an internal inductance. The internal inductance includes: a self-inductance of each gate interconnect 22 and a mutual inductance between this gate interconnect 22 and the gate interconnect 22 adjacent to this gate interconnect 22.

[0028] Each gate interconnection 22 is arranged such that the mutual inductance generated between this gate interconnection 22 and the gate interconnection 22 of the adjacent transistor cell 100 has a negative value. In this case, the mutual inductance acts in a direction that reduces self-inductance. This can reduce the internal inductance of the gate interconnection 22. Therefore, gate voltage ripple can be suppressed.

[0029] For example, if the absolute value of the self-inductance of each gate interconnection 22 is denoted by L1 and the absolute value of the mutual inductance between the gate interconnections 22 is denoted by M1, the internal inductance of each gate interconnection 22 is L1-M1. Therefore, the internal inductance of each gate interconnection 22 can be reduced.

[0030] If each gate interconnection 22 is arranged such that the mutual inductance generated between that gate interconnection 22 and the gate interconnection 22 of the adjacent transistor cell 100 has a positive value, the internal inductance of each gate interconnection 22 is L1+M1. Therefore, the internal inductance of each gate interconnection 22 increases.

[0031] Each transistor cell 100 may have an internal inductance in a semiconductor region between the source terminal S and the drain terminal D. The internal inductance includes the mutual inductance between the semiconductor region of each transistor cell 100 and the semiconductor region of the transistor cell 100 adjacent to that transistor cell 100.

[0032] Each semiconductor region is arranged such that the mutual inductance generated between this semiconductor region and the semiconductor region of the adjacent transistor cell 100 has a negative value. In this case, the mutual inductance acts in the direction in which the self-inductance is reduced, and thus the internal inductance of the semiconductor region can be reduced. Therefore, a semiconductor chip 1 with excellent switching characteristics is obtained. Furthermore, the reverse recovery characteristics of the body diode BD are improved, and a jump in the drain voltage can be suppressed.

[0033] For example, if the absolute value of the self-inductance of each semiconductor region is denoted by L2 and the absolute value of the mutual inductance between the semiconductor regions is denoted by M2, the internal inductance of each semiconductor region is L2-M2. Therefore, the internal inductance of each semiconductor region can be reduced.

[0034] If each semiconductor region is arranged so that the mutual inductance generated between that semiconductor region and the semiconductor region of the adjacent transistor cell 100 has a positive value, the internal inductance of each semiconductor region is L2+M2. Therefore, the internal inductance of each semiconductor region increases.

[0035] Each semiconductor region extends in a predetermined direction and is arranged, for example, such that the direction of the current flowing in the predetermined direction is opposite between this semiconductor region and the semiconductor region of the adjacent transistor cell 100. In this case, the mutual inductance can easily be achieved with a negative value.

[0036] Each semiconductor region can be an E-field relaxation region 17, described below. In this case, the internal inductance of the E-field relaxation region 17 can be reduced.

[0037] Next, a configuration of a field effect transistor which is an example of the semiconductor chip 1 according to the embodiment will be described.

[0038] Fig. 2 is a plan view showing the semiconductor chip 1 according to the embodiment. Fig. 3 is a perspective cross-sectional view showing the semiconductor chip 1 according to the embodiment. In Fig. 3, a gate insulating film 21, a gate interconnection 22, an interlayer insulating layer 23, and a source electrode 30 are not shown, which will be described later. Fig. 4 is a cross-sectional view showing the configuration of the electric field relaxation region 17 and a connection region 18 in the semiconductor chip 1 according to the embodiment. Fig. 4 is a cross-sectional view along the lower end surface of the connecting portion 18 in Fig. 3. Fig. 5 is a cross-sectional view showing configurations of a contact region 16 and the connection region 18 in the semiconductor chip 1 according to the embodiment. Fig. 5 is a cross-sectional view taken along the upper end surface of the contact portion 16 in Fig. 3 was recorded.

[0039] According to the presentation in the Fig. 2 to 5, the semiconductor chip 1 according to the embodiment comprises the transistor cells 100.

[0040] The transistor cells 100 are arranged side by side along a Y-axis direction, with the X-axis direction being a longitudinal direction. The Y-axis direction is an example of the first direction, and the X-axis direction is an example of the second direction. Each transistor cell 100 is, for example, a vertical transistor cell with a trench gate structure. Each transistor cell 100 may be a vertical transistor cell with a planar gate structure. When each transistor cell 100 is a vertical transistor cell, both a reduction in on-resistance and an increase in breakdown voltage can be achieved. Each transistor cell 100 has a gate interconnect 22 that extends in the X-axis direction.

[0041] For example, each gate interconnect 22 is arranged such that the direction of the current flowing along the X-axis is opposite between that gate interconnect 22 and the gate interconnect 22 of the adjacent transistor cell 100. In this case, the mutual inductance is likely to assume a negative value.

[0042] The gate interconnections 22 include a first gate interconnection 22a and a second gate interconnection 22b. The first gate interconnection 22a is electrically connected to a gate runner 51 and non-electrically connected to a gate runner 52. The second gate interconnection 22b is electrically connected to the gate runner 52 and non-electrically connected to the gate runner 51. The first gate interconnection 22a and the second gate interconnection 22b are arranged alternately along the Y-axis direction, for example. In this case, currents of opposite directions are likely to flow through the adjacent gate interconnections 22. In a plan view from a direction orthogonal to the X-axis direction and the Y-axis direction, the first gate interconnection 22a, the second gate interconnection 22b, and the gate runners 51 and 52 are arranged in a comb shape, for example.The gate runners 51 and 52 are electrically connected to a gate contact 60.

[0043] For example, the gate interconnections 22 are parallel to each other. In this case, the mutual inductance likely acts in the direction of reducing the self-inductance.

[0044] Fig. 6 to 10 are cross-sectional views showing the semiconductor chip 1 according to the embodiment. Fig. 6 is a cross-sectional view taken along line AA in Fig. 2 and the line DD in Fig. 4 and Fig. 5. Fig. 7 is a cross-sectional view taken along line BB in Fig. 2. Fig. 8 is a cross-sectional view taken along line CC in Fig. 2. Fig. 9 is a cross-sectional view taken along the line EE in Fig. 4 and Fig. 5. Fig. 10 is a cross-sectional view taken along the line FF in Fig. 4 and Fig. 5.

[0045] As shown in the Fig. 6 to 10, the semiconductor chip 1 according to the embodiment mainly includes a silicon carbide substrate 10, the gate insulating film 21, the gate interlayer 22, the interlayer insulating layer 23, the source electrode 30, a drain electrode 40, the gate runners 51 and 52, and the gate contact 60.

[0046] The silicon carbide substrate 10 is an example of a semiconductor substrate. When the silicon carbide substrate 10 is used, an excellent breakdown voltage can be achieved. The silicon carbide substrate 10 includes a silicon carbide single-crystal substrate 11; and a silicon carbide epitaxial layer 12 on the silicon carbide single-crystal substrate 11. The silicon carbide substrate 10 includes a first main surface 10A and a second main surface 10B opposite the first main surface 10A. The silicon carbide epitaxial layer 12 forms the first main surface 10A, and the silicon carbide single-crystal substrate 11 forms the second main surface 10B. The silicon carbide single-crystal substrate 11 and the silicon carbide epitaxial layer 12 are formed, for example, from hexagonal polytype 4H silicon carbide. The silicon carbide single crystal substrate 11 comprises an n-type dopant such as nitrogen (N) or the like and is of a conductive n-type.The transistor cells 100 are formed on the silicon carbide substrate 10.

[0047] The silicon carbide epitaxial layer 12 essentially comprises a drift region 13, a body region 14, a source region 15, the contact region 16, the electric field relaxation region 17 and the connection region 18.

[0048] The drift region 13 comprises an n-type dopant, such as nitrogen, phosphorus (P), or the like, and is of the conductive n-type. The drift region 13 comprises a first region 13A, a second region 13B, and a third region 13C.

[0049] The body region 14 is provided on the drift region 13. The body region 14 comprises a p-type dopant, such as aluminum (Al) or the like, and is of a conductive p-type.

[0050] The source region 15 is provided on the body region 14. The source region 15 comprises an n-type dopant, such as nitrogen, phosphorus, or the like, and is of a conductive n-type. The source region 15 is separated from the drift region 13 by the body region 14. The source region 15 forms the first main surface 10A.

[0051] The contact region 16 comprises a p-type dopant, such as aluminum or the like, and is of the conductive p-type. The contact region 16 penetrates the source region 15 and contacts the body region 14. The contact region 16 forms the first main surface 10A. The effective concentration of the p-type dopant in the contact region 16 is, for example, 1×10 18 cm -3 or higher and 2×10 20 cm -3 or lower.

[0052] The first main surface 10A is provided with a gate trench 5 defined by a side surface 3 and a bottom surface 4. The side surface 3 penetrates the source region 15 and the body region 14 and reaches the drift region 13. The side surface 3 can be, for example, a surface inclined with respect to the second main surface 10B or a surface perpendicular to the second main surface 10B. The bottom surface 4 is connected to the side surface 3. The bottom surface 4 is located in the drift region 13. The bottom surface 4 is, for example, a flat plane parallel to the second main surface 10B. The gate trench 5 is provided, for example, in the shape of an island along the X-axis. In a plan view from a direction perpendicular to the first main surface 10A, the gate trenches 5 are arranged at regular intervals in the Y-axis direction.

[0053] The E-field relaxation region 17 includes a p-type dopant, e.g., aluminum or the like, and is of the conductive p-type. The E-field relaxation region 17 extends in the X-axis direction. The E-field relaxation region 17 is located somewhere between the body region 14 and the second main surface 10B. In a plan view from the direction perpendicular to the first main surface 10A, the E-field relaxation region 17 includes a portion overlapping the gate trench 5. The E-field relaxation region 17 reduces the concentration of the electric field on the gate insulating film 21 in contact with the bottom surface 4 upon application of a high voltage. In the direction perpendicular to the second main surface 10B, the upper end surface of the E-field relaxation region 17 is separated from the bottom surface 4. The upper end surface of the E-field relaxation region 17 may comprise the bottom surface 4 of the gate trench 5.A portion of the upper end surface of the E-field relaxation region 17 faces a portion of the lower end surface of the body region 14. The E-field relaxation region 17 is electrically connected to the source electrode 30. In this case, the E-field relaxation region 17 is at a source potential, and thus the parasitic capacitance between the gate interconnection 22 and the drain electrode 40 can be reduced. Therefore, the switching speed is increased. The effective concentration of the p-type dopant in the E-field relaxation region 17 is, for example, 5×10-6 . 17 cm -3 or higher and 5×10 18 cm -3 or lower. The E-field relaxation region 17 is an example of the first semiconductor region.

[0054] The connecting region 18 comprises a p-type dopant, e.g., aluminum or the like, and is of a conductive p-type. The connecting region 18 penetrates the first region 13A and reaches the E-field relaxation region 17. The connecting region 18 electrically connects the body region 14 and the E-field relaxation region 17. In this case, as indicated by the arrows in the Fig. 9 and Fig. 10, currents flow from the source electrode 30 to the E-field relaxation region 17 by passing through the contact region 16, the body region 14, and the connection region 18 in this order. The connection region 18 touches the body region 14. The connection region 18 may be in contact with the contact region 16. The terminal region 18 may be in contact with both the body region 14 and the contact region 16. The connection region 18 is located between the contact region 16 and the E-field relaxation region 17. The connection region 18 is closer to the second main surface 10B than the contact region 16. The connection region 18 is closer to the first main surface 10A than the E-field relaxation region 17. The connection regions 18 are arranged, for example, at regular intervals along the X-axis.The effective concentration of the p-type dopant in the junction region 18 may be substantially the same as that of the p-type dopant in the E-field relaxation region 17. The effective concentration of the p-type dopant in the junction region 18 is, for example, 5×10. 17 cm -3 or higher and 5×10 13 cm -3 or lower. The connection region 18 is an example of the second semiconductor region.

[0055] The connection region 18 is arranged in the direction of the X-axis at a different position than the connection region 18 of the adjacent transistor cell 100. In this case, as indicated by the arrows in Fig. 4, probably currents with opposite directions through the adjacent E-field relaxation regions 17.

[0056] The position in the X-axis direction at which the connection region 18 is arranged may, for example, be an intermediate position between the two connection regions 18 of the adjacent transistor cell 100 that are adjacent to each other in the X-axis direction. In this case, currents with opposite directions are likely to flow through the adjacent E-field relaxation regions 17.

[0057] The first region 13A of the drift region 13 is located somewhere between the body region 14 and the electric field relaxation region 17. The first region 13A is in contact with the body region 14 and the E-field relaxation region 17. The first region 13A is closer to the first main surface 10A than the E-field relaxation region 17.

[0058] The second region 13B is closer to the second main surface 10B than the first region 13A. The second region 13B is connected to the first region 13A. The second region 13B is in contact with the E-field relaxation region 17 in a direction parallel to the second main surface 10B. The second region 13B and the E-field relaxation region 17 may be arranged in the same plane parallel to the second main surface 10B. The effective concentration of the n-type dopant in the second region 13B may be higher than that of the n-type dopant in the first region 13A.

[0059] The third region 13C is closer to the second main surface 10B than the second region 13B. The third region 13C is connected to the second region 13B. The third region 13C is in contact with the E-field relaxation region 17. The third region 13C is closer to the second main surface 10B than the E-field relaxation region 17. The third region 13C may be located between the second region 13B and the silicon carbide single crystal substrate 11. The third region 13C may be continuous with the silicon carbide single crystal substrate 11. The effective concentration of the n-type dopant in the third region 13C may be the same as that of the n-type dopant in the second region 13B.

[0060] The gate insulating film 21 is, for example, an oxide film. The gate insulating film 21 is formed of a material including silicon dioxide or the like. The gate insulating film 21 is in contact with the side surface 3 and the bottom surface 4. The gate insulating film 21 is in contact with the first region 13A at the bottom surface 4. The gate insulating film 21 is in contact with the source region 15, the body region 14, and the first region 13A at the side surface 3. The gate insulating film 21 may be in contact with the source region 15 at the first main surface 10A.

[0061] The gate interconnection 22 is provided on the gate insulating film 21. The gate interconnection 22 is formed, for example, from polysilicon with conductive impurities. The gate interconnection 22 is located in the gate trench 5. A part of the gate interconnection 22 may be provided on the first main surface 10A.

[0062] The insulating interlayer 23 covers the gate interconnection 22. The insulating interlayer 23 is in contact with the gate interconnection 22 and the gate insulating film 21. The insulating interlayer 23 is, for example, an oxide film. The insulating interlayer 23 is formed, for example, from a material including silicon dioxide. The insulating interlayer 23 electrically insulates the gate interconnection 22 and the source electrode 30 from each other. A part of the insulating interlayer 23 may be provided in the gate trench 5.

[0063] Contact holes 24 are formed in the interlayer insulating layer 23 and the gate insulating film 21. The contact holes 24 are arranged at regular intervals in the Y-axis direction. In a plan view from the direction perpendicular to the first main surface 10A, the contact holes 24 are arranged so that the gate trench 5 is juxtaposed between the contact holes 24 in the Y-axis direction. The contact holes 24 extend in the X-axis direction. The source region 15 and the contact region 16 are exposed from the interlayer insulating layer 23 and the gate insulating film 21 through the contact holes 24. The contact region 16 does not need to extend continuously along the X-axis and may be formed periodically. A barrier metal film may be formed covering the top and side surfaces of the interlayer insulating layer 23 and the side surface of the gate insulating film 21.

[0064] The source electrode 30 is in contact with the first main surface 10A. The source electrode 30 includes a contact electrode 31 and a source connection 32.

[0065] The contact electrode 31 is in contact with the source region 15 and the contact region 16 on the first main surface 10A. The contact electrode 31 is formed, for example, from a material comprising nickel silicide (NiSi). The contact electrode 31 can be formed from a material comprising titanium, aluminum, and silicon. The contact electrode 31 is in ohmic contact with the contact region 16.

[0066] The source interconnect 32 covers the top and side surfaces of the insulating interlayer 23 and the top surface of the contact electrode 31. The source interconnect 32 is in contact with the contact electrode 31. The source interconnect 32 is formed, for example, from a material including aluminum.

[0067] The drain electrode 40 is in contact with the second main surface 10B. The drain electrode 40 is in contact with the silicon carbide single-crystal substrate 11 at the second main surface 10B. The drain electrode 40 is electrically connected to the drift region 13. The drain electrode 40 is made of, for example, a material including nickel silicide. The drain electrode 40 may be formed of a material including titanium, aluminum, and silicon. The drain electrode 40 is in ohmic contact with the silicon carbide single-crystal substrate 11.

[0068] The gate runner 51 is located on the positive X-axis side of the gate interconnections 22. The gate runner 51 extends in the Y-axis direction. The gate runner 51 electrically connects the first gate interconnections 22a and the gate contact 60. The gate runner 51 is electrically connected to the ends of the first gate interconnections 22a on the positive X-axis side. In this case, charging currents flow from the positive X-axis side to the negative X-axis side, as indicated by the arrows in Fig. 2 and the arrow in Fig. 7. At the same time, discharge currents flow from the negative X-axis side to the positive X-axis side. The gate runner 51 is formed from a material whose electrical resistance is lower than that of the gate interconnections 22. The gate runner 51 is formed, for example, from a material such as aluminum or copper. The gate runner 51 may be formed from a material comprising aluminum and copper. The gate runner 51 is an example of a first interconnection.

[0069] The gate runner 52 is provided on the negative X-axis side of the gate interconnections 22. The gate runner 52 extends in the Y-axis direction. The gate runner 52 is arranged so that the gate interconnections 22 are located between the gate runner 52 and the gate runner 51. The gate runner 52 electrically connects the second gate interconnections 22b and the gate contact 60. The gate runner 52 is electrically connected to the ends of the second gate interconnections 22b on the negative X-axis side. In this case, charging currents flow from the negative X-axis side to the positive X-axis side, as indicated by the arrows in Fig. 2 and the arrow in Fig.8. Meanwhile, the discharge currents flow from the positive X-axis side to the negative X-axis side. Therefore, the direction in which the charge currents flow through the first gate interconnections 22a is opposite to the direction in which the charge currents flow through the second gate interconnections 22b. Likewise, the direction in which the discharge currents flow through the first gate interconnections 22a is opposite to the direction in which the discharge currents flow through the second gate interconnections 22b. The gate runner 52 is formed of the same material as the gate runner 51. The gate runner 52 is an example of the second interconnection line.

[0070] The gate contact 60 is provided on the positive Y-axis side of the gate interconnections 22. The gate contact 60 may be provided on the negative Y-axis side of the gate interconnections 22. The gate contact 60 has a rectangular shape or the like. The gate contact 60 is formed, for example, from a material such as aluminum or copper. The gate contact 60 may be formed from a material comprising aluminum and copper.

[0071] Although the embodiments have been described in detail above, the present invention is not limited to the specific embodiments. Various modifications and changes are possible within the scope of the appended claims. List of reference symbols 1 semiconductor chip 3 side surface 4 Floor area 5 Gate trench 10 Silicon carbide substrate 10A First main area 10B Second main area 11 Silicon carbide single crystal substrate 12 Silicon carbide epitaxial layer 13 Drift report 13A First Area 13B Second area 13C Third Area 14 Body area 15 Source area 16 Contact area 17 E-field relaxation region 18 Connection area 21 Gate insulating film 22 Gate interconnection 22a First gate interconnection 22b Second gate interconnect 23 Insulating intermediate layer 24 contact holes 30 Source electrode 31 Contact electrode 32 Source Interconnect 40 Drain electrode 51 Gate Runners 52 gate runners 60 Gate contact 100 transistor cells BD body diode D Drain connection G Gate connection S Source connection QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2022-082048

[0002] JP 2012-23291

[0004]

Claims

[1] Semiconductor chip, comprising: a plurality of transistor cells arranged side by side in a first direction, wherein the transistor cells comprise: a gate interconnect extending along a second direction orthogonal to the first direction, and a first semiconductor region extending along the second direction and being of a first conductive type, wherein the gate interconnection is arranged such that a mutual inductance generated between: the gate interconnection of one transistor cell of the transistor cells; and the gate interconnection of another transistor cell of the transistor cells has a negative value, wherein the one transistor cell and the other transistor cell are adjacent to each other, and wherein the first semiconductor region is arranged such that a mutual inductance generated between: the first semiconductor region of one transistor cell of the transistor cells; and the first semiconductor region of another transistor cell of the transistor cells has a negative value, wherein the one transistor cell and the other transistor cell are adjacent to each other. [2] The semiconductor chip according to claim 1, wherein the gate interconnection is arranged such that directions of currents flowing along the second direction are opposite between the gate interconnection of the one transistor cell and the gate interconnection of the other transistor cell. [3] The semiconductor chip of claim 1, further comprising: a semiconductor substrate; a gate contact arranged on the semiconductor substrate; a first connection interconnect configured to electrically connect the gate interconnect and the gate contact; and a second interconnection configured to electrically connect the gate interconnection and the gate contact, wherein the first interconnection extends along the first direction, wherein the second connection interconnection is arranged with a plurality of gate interconnections between the second connection interconnection and the first connection interconnection, wherein the plurality of gate interconnections each represents the gate interconnection, wherein the gate interconnections comprise: a first gate interconnection electrically connected to the first connection interconnection, and a second gate interconnection electrically connected to the second connection interconnection, and the first gate interconnection and the second gate interconnection are arranged alternately along the first direction. [4] The semiconductor chip according to claim 3, wherein the first gate interconnection and the second gate interconnection are parallel to each other. [5] The semiconductor chip according to claim 3, wherein the semiconductor substrate is a silicon carbide substrate. [6] A semiconductor chip according to claim 1, wherein the transistor cells are electrically connected to a common source terminal and to a common drain terminal. [7] The semiconductor chip according to claim 1, wherein the first semiconductor region is arranged such that directions of currents flowing along the second direction are opposite between the first semiconductor region of the one transistor cell and the first semiconductor region of the other transistor cell. [8] The semiconductor chip of claim 1, wherein the transistor cells further comprise: a source electrode; and a second semiconductor region electrically connected to the first semiconductor region and the source electrode and of the first conductive type, wherein the second semiconductor region is arranged such that the second semiconductor region of the one transistor cell is arranged at a position different in the second direction from that of the second semiconductor region of the other transistor cell. [9] Semiconductor chip according to claim 8, wherein a plurality of second semiconductor regions each constituting the second semiconductor region is arranged along the second direction, and wherein positions in the second direction at which the second semiconductor regions are arranged in the one transistor cell represent an intermediate position between two second semiconductor regions of the second semiconductor regions of the other transistor cell, wherein the two second semiconductor regions are adjacent to one another in the second direction. [10] The semiconductor chip of claim 1, wherein the first semiconductor regions constitute an E-field relaxation region. [11] Semiconductor chip according to one of claims 1 to 10, wherein the transistor cells are a vertical transistor cell.

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