A VIDEO DATA ENCODER AND AN ENCODING METHOD

Abstract

Among the examples disclosed herein is a video data encoder. The video data encoder can encode a 4x4 data block into a bitstream using context-adaptive variable-length encoding. The 4x4 data block can represent video data. When encoding the 4x4 data block, the video data encoder can ignore at least some coefficients of the 4x4 data block. In some examples, the video data encoder can ignore at least some coefficients of the 4x4 data block by setting at least some coefficients of the 4x4 data block to zero before encoding. Associated devices, systems, and methods are also disclosed.

Description

PRIORITY CLAIM

[0001] This application claims the benefit of the priority date of Indian Provisional Patent Application No. 202241030058, filed on May 25, 2022, entitled “IMPROVEMENTS TO CONTEXT ADAPTIVE VARIABLE LENGTH CODING,” the disclosure of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Various examples generally relate to encoding video, images, and / or audio data in a digital format. More specifically, some examples relate to improvements related to context adaptive variable length coding (CAVLC). CAVLC may be used in accordance with Recommendation H.264: Advanced Video Coding for Generic Audiovisual Services (H.264), also known in the art as Motion Picture Experts Group (MPEG)-4 Advanced Video Coding (AVC). H.264 is a video coding format for recording and / or distributing video, images, and / or audio. Unless otherwise noted herein, references to "H.264" should be understood to include MPEG-4AVC. Additionally, apparatus, systems, and methods are disclosed. BACKGROUND

[0003] CAVLC can be used without restrictions in video coding, e.g., video coding according to Recommendation H.264. CAVLC can encode blocks of coefficients into a bitstream. CAVLC can utilize various properties of blocks of quantized coefficients. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] While this disclosure concludes with claims that particularly point out and distinctly claim particular examples, various features and advantages of examples within the scope of this disclosure may be more readily appreciated from the following description when read in conjunction with the accompanying drawings, in which: Fig. 1 is a functional block diagram illustrating a device according to one or more examples. Fig. 2 is a functional block diagram illustrating a device according to one or more examples. Fig. 3 is a functional block diagram illustrating a device according to one or more examples. Fig. 4 is a flowchart of a method according to one or more examples. Fig. 5A and Fig. 5B together are a flowchart of a method according to one or more examples. Fig. 6A and Fig. 6B together are a flowchart of a method 600 according to one or more examples. Fig. 7 is a block diagram of an apparatus that may be used, in one or more examples, to implement various functions, operations, acts, processes, or methods disclosed herein. MODE(S) FOR CARRYING OUT THE INVENTION

[0005] H.264 describes a video compression algorithm that can compress video data, such as video data in a red, green, blue (RGB) format or in a luma, or brightness, blue projection, and red projection (YUV) format, into a compressed format without restriction. H.264 can work with data blocks, meaning one data block at a time. H.264 includes prediction, transformation, and quantization operations. After the prediction, transformation, and quantization operations, the data blocks are typically sparse, meaning most data blocks contain primarily zeros.

[0006] CAVLC is an entropy coding scheme used in H.264 video compression after prediction, transformation, and quantization. CAVLC encodes 4x4 data blocks into bitstreams by exploiting the properties of quantized 4x4 data blocks (including, for example, the sparse nature of 4x4 data blocks, but without limitation).

[0007] The contents of the 4x4 data blocks (e.g., values ​​of the 4x4 data blocks) are often referred to as "coefficients." After prediction, transformation, and quantization, the coefficients may include non-zero coefficients, +1s, -1s, and zeros. Following prediction, transformation, and quantization, the 4x4 data blocks may be scanned according to a zigzag scan pattern, for example, ordering the coefficients from a first to a last coefficient. Ordering the coefficients may correspond to ordering the coefficients from low frequency to high frequency according to the transform. As a non-limiting example, the transform may be an integer transform or a cosine transform. The +1s and -1s that correspond to high frequencies according to the transform (e.g., the latter coefficients) may be referred to as "trailing 1s," "trailing 1s," or "trailing 1s."

[0008] The CAVLC encoding of a 4×4 data block includes five stages as follows: Stage 1 - Encode all non-zero coefficients. Standard lookup tables are used to encode non-zero coefficients, using a number of non-zero coefficients and a number of trailing ones of the 4x4 data block. The choice of lookup table is determined by the number of non-zero coefficients in the adjacent blocks. Stage 1 of CAVLC typically takes 1 clock cycle. Stage 2 - Encoding the signs of trailing ones. A bit is assigned to each trailing one based on its sign, where 0 corresponds to +1 and 1 corresponds to -1. Stage 2 of CAVLC typically takes 1 clock cycle. Stage 3 - Encoding the remaining non-zero coefficient levels. This step takes one clock cycle per non-zero coefficient. Stage 3 of CAVLC can take up to 16 clock cycles. As a non-limiting example, for a 4x4 data block with 16 non-zero coefficients, this stage of CAVLC typically takes 16 clock cycles. Stage 4 - Encoding the total number of zeros before the last non-zero coefficient. Stage 4 of CAVLC typically takes 1 clock cycle. Stage 5 - Encoding each sequence of zeros. Stage 5 of CAVLC typically takes one clock cycle for each zero before the last non-zero coefficient. This stage can take up to 15 clock cycles. As a non-limiting example, in a case where a 4x4 block includes a non-zero coefficient at the last position (according to the zigzag scan pattern) and 15 zeros before the last coefficient, this stage takes 15 clock cycles.

[0009] The runtimes of stage 3 and stage 5 can complement each other. For example, stage 3 takes one clock cycle for each non-zero coefficient, and stage 5 takes one clock cycle for each zero before the last non-zero coefficient. Therefore, more non-zero coefficients mean that stage 3 will be longer and stage 5 will be shorter, and more zero coefficients (before the last non-zero coefficient) mean that stage 5 will be longer and stage 3 will be shorter.

[0010] In some CAVLC implementations, stage 3 and stage 5 are executed in parallel, so that the encoded output of stage 5 is available at the end of stage 4. In such CAVLC implementations, processing a 4x4 data block can take up to 19 clock cycles.

[0011] As an example of processing time for all five stages, in the case of a 4x4 data block with 6 non-zero coefficients, where the 6 non-zero coefficients include two trailing ones, and the last non-zero coefficient is in the tenth position, CAVLC can take one clock cycle for stage 1, one clock cycle for stage 2, four clock cycles for stage 3 (one for each of the non-zero coefficients except the trailing ones), one clock cycle for stage 4, and four clock cycles for stage 5 (one for each of the zeros before the last non-zero coefficient in the tenth position) (stage 5 can run in parallel with stage 3 without adding any clock cycles, since stages 3 and 5 can run in parallel) - a total of seven clock cycles.

[0012] As an example of processing time for all five stages, in the case of a 4x4 data block with 16 non-zero coefficients, none of which are trailing ones (the case where stage 3 will take the longest), CAVLC may take one clock cycle for stage 1, one clock cycle for stage 2, 16 clock cycles for stage 3, one clock cycle for stage 4, and zero clock cycles for stage 5 (stage 5 can be skipped because there are no zero coefficients) - a total of 19 clock cycles.

[0013] As another example of processing time for all five stages, in the case of a 4x4 data block with 15 zeros and a single non-zero coefficient in the last position (the non-zero coefficient is not a trailing one, i.e., in this case, stage 5 takes the longest), CAVLC can take one clock cycle for stage 1, one clock cycle for stage 2, one clock cycle for stage 3 (stage 3 can run in parallel with stage 5 without adding any clock cycles, since stages 3 and 5 can run in parallel), one clock cycle for stage 4, and 15 clock cycles for stage 5 - a total of 18 clock cycles.

[0014] CAVLC can receive one coefficient per clock cycle, e.g., one coefficient can be stored in a buffer without restriction per clock cycle. As a non-limiting example, if CAVLC takes 19 clock cycles to encode a 4x4 data block with 16 coefficients into a bitstream, CAVLC will take longer to process the 4x4 data block than it takes to receive the blocks. This can cause a delay in the video encoding process. As a non-limiting example, the input may have to wait 3 clock cycles every 16 clock cycles to allow CAVLC to complete all 5 encoding stages. This wait incurs an additional 18.75% latency for each block, and therefore for the entire video frame.

[0015] This impacts the bandwidth and frame rate of the entire H.264 encoder. An alternative solution to avoid the latency is to run CAVLC at a higher clock frequency, such as 1.1875 times the clock frequency of the quantization module. However, this increases CAVLC's power consumption and leads to clock domain crossing (CDC), which may require CDC first-in, first-out circuits (FIFOs).

[0016] In some examples, the coefficients of a 4x4 data block are set to zero to reduce the number of clock cycles required by CAVLC in the longest cases. Some examples may set at least some coefficients of a 4x4 data block to zero before, at the beginning of, or during CAVLC operations. In some examples, two coefficients may be set to zero. In some examples, the last two coefficients (corresponding to a zigzag scan pattern) may be set to zero. Alternatively, some examples may ignore one or more coefficients during one or more CAVLC operations.

[0017] In H.264, 4x4 data blocks are typically sparse after prediction, transformation, and quantization. In particular, most of the coefficients of most 4x4 data blocks are zeros. Furthermore, based on the transformation, such as the integer transform, most 4x4 data blocks have zeros as the last two coefficients (e.g., the high-frequency coefficients) without restriction. Therefore, setting the last two coefficients of most 4x4 data blocks to zero may not affect the coefficient values ​​of most 4x4 data blocks. Furthermore, because the last two coefficients represent high-frequency data (e.g., according to the integer transform), setting the last two coefficients to zero may have no visually perceptible effect on video quality.

[0018] Setting two coefficients of 4x4 data blocks to zero causes stage 3 of CAVLC to take a maximum of 14 clock cycles. For example, the 4x4 data block that would take the longest to process in stage 3 of CAVLC would be a 4x4 data block with 16 non-zero coefficients, none of which is a trailing one. Using a conventional CAVLC, encoding 16 non-zero coefficients in CAVLC stage 3 would take 16 clock cycles. By setting the last two coefficients to zero, stage 3 takes a maximum of 14 clock cycles, according to various examples, because there are a maximum of 14 non-zero coefficients to encode in stage 3.

[0019] In some non-limiting examples, where a 4x4 data block contains 16 non-zero coefficients, none of which is a trailing one, various examples may compute stage 1 and stage 2 in the same clock cycle. Various examples may compute stage 3 in 14 clock cycles because, after setting two coefficients of 4x4 data blocks to zero, there are 14 non-zero coefficients in the 4x4 data block. Stage 4 may be computed in one clock cycle. Stage 5 may be omitted because, in the case of 14 non-zero coefficients (e.g., after the last two coefficients are set to zero according to various examples), no zero sequences need to be encoded in stage 5. Alternatively, stage 5 may be processed in parallel with stage 3 and may not add any clock cycles to the total runtime of CAVLC.Thus, even in the case of a 4x4 data block with 16 non-zero coefficients, none of which is a trailing one, various examples may require 16 clock cycles to process the 4x4 data block according to CAVLC.

[0020] In cases where a 4x4 data block contains 15 zeros and a non-zero final coefficient (which may be the 4x4 data block that takes the longest to process in stage 5), various examples can set the final coefficient to zero. With 16 zeros, stages 1 and 2 may take one clock cycle, stage 3 may take zero (because there are no non-zero coefficients to encode), alternatively, stage 3 may be processed in parallel with stage 5 and add no clock cycles to the total runtime of CAVLC, stage 4 may take one clock cycle, and stage 5 may take zero (because there are no zeros before a non-zero final coefficient).

[0021] In cases where a 4x4 data block contains 13 zeros and a non-zero coefficient in the 14th position (which may be the 4x4 data block that takes the longest to process in stage 5 after the last two coefficients are zeroed), various examples can set the last two coefficients to zero. With 13 zeros, stages 1 and 2 might take one clock cycle, stage 3 might take one clock cycle (for the non-zero coefficient in the 14th position), stage 4 might take one clock cycle, and stage 5 might take 13 clock cycles (for the 13 zeros before the 14th non-zero coefficient). Because stages 3 and 5 can be processed in parallel, stages 1 through 5 of CAVLC can be completed in 15 clock cycles.

[0022] Setting the last two coefficients of 4x4 data blocks to zero may thus enable CAVLC to process all 4x4 data blocks in 16 or fewer clock cycles.

[0023] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific examples in which the present disclosure may be practiced. These examples are described in sufficient detail to enable those skilled in the art to practice the present disclosure. However, other examples may be utilized, and structural, material, and procedural changes may be made without departing from the scope of the disclosure.

[0024] The illustrations presented herein are not intended to be actual views of any particular method or system, device, or structure, but are merely idealized representations used to describe the examples of the present disclosure. The drawings presented herein are not necessarily to scale. Similar structures or components in the various drawings may retain the same or similar numbering for the convenience of the reader; however, similarity in numbering does not imply that the structures or components are necessarily identical in size, composition, configuration, or any other characteristic.

[0025] The following description may include examples to enable those skilled in the art to practice the disclosed examples. The use of the terms "exemplary," "as an example," and "for example" means that the accompanying description is illustrative, and while the scope of the disclosure is intended to include the examples and their legal equivalents, the use of these terms is not intended to limit the scope of any example of this disclosure to the specified components, steps, features, functions, or the like.

[0026] It will be readily appreciated that the components of the examples generally described herein and illustrated in the drawings may be arranged and configured in a variety of different configurations. Thus, the following description of various examples is not intended to limit the scope of the present disclosure, but is merely representative of various examples. While the various aspects of the examples may be illustrated in the drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0027] Furthermore, the specific implementations shown and described are only examples and should not be construed as the only way to implement the present disclosure unless otherwise stated herein. Elements, circuits, and functions may be shown in block diagram form in order not to obscure the present disclosure with unnecessary detail. Conversely, the specific implementations shown and described are only examples and should not be construed as the only way to implement the present disclosure unless otherwise stated herein. Furthermore, block definitions and the partitioning of logic between different blocks are one example of a specific implementation. It will be readily apparent to those skilled in the art that the present disclosure may be practiced using numerous other partitioning solutions.Details of timing considerations and the like have largely been omitted to the extent that such details are not necessary for a complete understanding of the present disclosure and are within the capabilities of those skilled in the art.

[0028] Those skilled in the art would understand that information and signals may be represented using a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, and symbols that may be referred to in this description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings may illustrate signals as a single signal for clarity of illustration and description. Those skilled in the art will understand that the signal may represent a bus of signals, where the bus may have a variety of bit widths, and the present disclosure may be implemented with any number of data signals, including a single data signal.Those skilled in the art will recognize that the present disclosure encompasses the communication of quantum information and qubits used to represent quantum information.

[0029] The various illustrative logic blocks, modules, and circuits described in connection with the examples disclosed herein may be implemented or performed using a general-purpose processor, a special-purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof configured to perform the functions described herein.A general-purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but alternatively, it may be any conventional processor, control unit, microcontroller, or state machine. A processor may also be implemented as a combination of data processing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. A general-purpose computer, including a processor, is considered a special-purpose computer, while the general-purpose computer is used to execute computational instructions (e.g., software code, without limitation) related to examples of the present disclosure.

[0030] The examples may be described with respect to a process represented as a flowchart, a flow sheet, a structural diagram, or a block diagram. Although a flowchart may describe operational acts as a sequential process, many of these acts may be performed in a different sequence, in parallel, or substantially concurrently. Furthermore, the order of the acts may be changed. A process may correspond, without limitation, to a method, a thread, a function, a procedure, a subroutine, or a subprogram. Further, the methods disclosed herein may be implemented in hardware, software, or both. When implemented in software, the functions may be stored or dispatched as one or more instructions or as code on computer-readable media.Computer-readable media includes both computer storage media and communications media, including any media that supports the transfer of a computer program from one location to another.

[0031] In this specification, the term "coupled" and derivatives thereof may be used to indicate that two elements cooperate or interact with each other. When one element is described as being "coupled" to or with another element, the elements may be in direct physical or electrical contact, or there may be one or more intervening elements or layers. Conversely, when an element is described as being "directly coupled" to or with another element, no intervening elements or layers are present. It is understood that when an element is described as "coupling" a first element and a second element, it is coupled to the first element and is coupled to the second element.

[0032] Fig. 1 is a functional block diagram illustrating a device 100 according to one or more examples. The device 100 can compress video data 104 into compressed video data 106 in 16 or fewer clock cycles.

[0033] The device 100 may include a video data encoder 102. The video data encoder 102 may encode video data 104 to generate compressed video data 106. Encoding video data 104 to generate compressed video data 106 may include encoding a 4x4 data block 110 into a bitstream 118 according to a CAVLC 120. The 4x4 data block 110 may be representative of video data 104. Encoding video data 104 to generate compressed video data 106 may include ignoring at least some coefficients 112 of the 4x4 data block 110 during encoding the 4x4 data block 110. In some non-limiting examples, ignoring at least some coefficients 112 of the 4x4 data block 110 prior to encoding the 4x4 data block 110 may include setting at least some coefficients 112 of the 4x4 data block 110 to zero.

[0034] The video data encoder 102 may be or include logic for performing operations to compress video data 104 into compressed video data 106. The video data encoder 102 may be or include a video codec.

[0035] The video data 104 may be or include video data, image data, and / or audio data in any suitable format, including, for example, without limitation, video data consisting of images, including RGB data or YUV data.

[0036] The compressed video data 106 may be representative of video data 104. The compressed video data 106 may be augmented to recover data substantially identical to the video data 104. Some of the recovered data may not include high-frequency aspects that were present in the video data 104. Nevertheless, the recovered data may be substantially identical to the video data 104.

[0037] The 4x4 data block 110 may be or include 16 coefficients 112. The coefficients 112 of the 4x4 data block 110 may have corresponding positions in a 4x4 matrix. Additionally or alternatively, the coefficients 112 of the 4x4 data block 110 may have an order according to a zigzag scan pattern (in Fig. 1 not shown) of the 4x4 data block 110.

[0038] The 4x4 data block 110 may be representative of video data 104. As a non-limiting example, the 4x4 data block 110 may be representative of pixels of an image of the video data 104. As a non-limiting example, a block of 16 pixels of an image of the video data 104 may be identified or selected. A prediction may be performed relative to the pixels. Values ​​related to the identified 16 pixels may be transformed without restriction, e.g., using an integer transformation. The transformed values ​​may be quantized. The 4x4 data block 110 may be the quantized values.

[0039] Video data encoder 102 may encode 4x4 data block 110 as bitstream 118 according to CAVLC 120. As a non-limiting example, video data encoder 102 may encode 4x4 data block 110 as bitstream 118 according to the five CAVLC stages described above.

[0040] However, according to some non-limiting examples, video data encoder 102 may ignore at least some of the coefficients 112 of the 4x4 data block 110 while encoding the 4x4 data block 110 into the bitstream 118. For example, video data encoder 102 may ignore at least two of the coefficients 112 of the 4x4 data block 110 while performing operations of CAVLC 120. In one or more examples, video data encoder 102 may ignore the last two coefficients 112 of the 4x4 data block 110 according to a zigzag scan pattern.

[0041] Additionally or alternatively, according to some non-limiting examples, the video data encoder 102 may set at least some of the coefficients 112 of the 4x4 data block 110 to zero before or at the beginning of encoding the 4x4 data block 110 into the bitstream 118. For example, the video data encoder 102 may set at least two of the coefficients 112 of the 4x4 data block 110 to zero before performing operations of CAVLC 120. The video data encoder 102 may set the last two coefficients 112 of the 4x4 data block 110 to zero (i.e., set the value to zero) according to a zigzag scan pattern (i.e., the last two coefficients traversed according to the zigzag scan pattern). Setting at least some of the coefficients 112 to zero may be an example of ignoring at least some of the coefficients 112.

[0042] Fig. 2 is a functional block diagram illustrating a device 200 according to one or more examples. The device 200 can compress video data 204 into compressed video data 206 in 16 or fewer clock cycles 222.

[0043] The device 200 may be an example of the device 100 of Fig. 1. In particular, the video data encoder 202 may be an example of the video data encoder 102 of Fig. 1, the video data 204 may be an example of the video data 104 of Fig. 1, the compressed video data 206 may be an example of the compressed video data 106 of Fig. 1, the 4x4 data block 210 may be an example of the 4x4 data block 110 of Fig. 1, the coefficients 212 can be an example of the coefficients 112 of Fig. 1, the bit stream 218 may be an example of the bit stream 118 of Fig. 1 and CAVLC 220 can be an example of CAVLC 120 from Fig. 1.

[0044] Additionally illustrated Fig. 2, a zigzag scan pattern 214. The zigzag scan pattern 214 may define a path for traversing the 4x4 data block 210 to order the coefficients 212 of the 4x4 data block 210. The zigzag scan pattern 214 may order the coefficients 212 according to the transformation of the values ​​of the pixel block that formed the 4x4 data block 210, from a coefficient with the lowest frequency to a coefficient with the highest frequency. In particular, a coefficient in the upper left of the 4x4 data block 210 may be a coefficient with the lowest frequency of the coefficients 212, and a coefficient in the lower right of the 4x4 data block 210 may be a coefficient with the highest frequency of the coefficients 212.

[0045] The video data encoder 202 may ignore at least some of the coefficients 212 of the 4x4 data block 210 while encoding the 4x4 data block 210 into the bitstream 218 according to CAVLC 220. The video data encoder 202 may ignore at least two of the coefficients 212 of the 4x4 data block 210 while performing operations of CAVLC 220. The video data encoder 202 may ignore the last two coefficients 216 of the 4x4 data block 210 according to the zigzag scan pattern 214.

[0046] Additionally or alternatively, before or at the beginning of encoding the 4x4 data block 210 into the bitstream 218 according to CAVLC 220, the video data encoder 202 may set at least some of the coefficients 212 of the 4x4 data block 210 to zero. The video data encoder 202 may set at least two of the coefficients 212 of the 4x4 data block 210 to zero. The video data encoder 202 may set the last two coefficients 216 of the 4x4 data block 210 to zero according to a zigzag scan pattern 214. Setting at least some of the coefficients 212 to zero may be an example of ignoring at least some of the coefficients 212.

[0047] Fig. 3 is a functional block diagram illustrating a device 300 according to one or more examples. Device 300 can compress video data into compressed video data in 16 or fewer clock cycles.

[0048] The device 300 may be an example of the device 100 of Fig. 1. In particular, the video data encoder 302 may be an example of the video data encoder 102 of Fig. 1, the video data 304 may be an example of the video data 104 of Fig. 1, the 4x4 data block 310 may be an example of the 4x4 data block 110 of Fig. 1, the coefficients 312 can be an example of the coefficients 112 of Fig. 1, the bit stream 318 may be an example of the bit stream 118 of Fig. 1 and CAVLC 320 can be an example of CAVLC 120 from Fig. 1.

[0049] The device 300 may include a video data encoder 302. The video data encoder 302 may encode a 4x4 data block 310 into a bitstream 318 according to CAVLC 320. The 4x4 data block 310 may be representative of video data 304 (e.g., the 4x4 data block 310 may include data of the video data 304 that has been selected, predicted, transformed, and / or quantized). The video data encoder 302 may ignore at least some coefficients 312 of the 4x4 data block 310 when encoding the 4x4 data block 310. In some non-limiting examples, ignoring at least some coefficients 312 of the 4x4 data block 310 prior to encoding the 4x4 data block 310 may include setting at least some of the coefficients 312 of the 4x4 data block 310 to zero.

[0050] The video data encoder 302 may ignore at least some of the coefficients 312 of the 4x4 data block 310 while encoding the 4x4 data block 310 into the bitstream 318 according to CAVLC 320. The video data encoder 302 may ignore at least two of the coefficients 312 of the 4x4 data block 310 while performing operations of CAVLC 320. The video data encoder 302 may ignore the last two coefficients of the 4x4 data block 310 according to a zigzag scan pattern.

[0051] Additionally or alternatively, before or at the beginning of encoding the 4x4 data block 310 into the bitstream 318 according to CAVLC 320, the video data encoder 302 may set at least some of the coefficients 312 of the 4x4 data block 310 to zero. The video data encoder 302 may set at least two of the coefficients 312 of the 4x4 data block 310 to zero. The video data encoder 302 may set the last two coefficients of the 4x4 data block 310 to zero according to a zigzag scan pattern. Setting at least some of the coefficients 312 of the 4x4 data block 310 to zero may be an example of ignoring at least some of the coefficients 312 of the 4x4 data block 310.

[0052] Fig. 4 is a flowchart of a method 400 according to one or more examples. At least a portion of the method 400 may, in some non-limiting examples, be performed by an apparatus or system such as the device 100 of Fig. 1, the device video data encoder 102 from Fig. 1, the facility 200 from Fig. 2, the video data encoder 202 from Fig. 2, the facility 300 from Fig. 3, the video data encoder 302 from Fig. 3 or another device or system. Although illustrated as discrete blocks, various blocks may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation.

[0053] At operation 402, video data may be encoded to generate compressed video data. As a non-limiting example, video data 104 may be Fig. 1 into compressed video data 106 from Fig. 1. When performing operation 402, one or more of operation 404 and operation 406 may be performed. In other words, one or more of operation 404 and operation 406 may be substeps of operation 402.

[0054] At operation 404, the 4x4 data block may be encoded into a bitstream according to CAVLC. The 4x4 data block may represent the video data. As a non-limiting example, data from the video data may have been identified, predicted, transformed, and / or quantized to generate the 4x4 data block. The bitstream may represent compressed video data. As a non-limiting example of operation 404, the 4x4 data block 110 may be encoded according to CAVLC 120 from Fig. 1 into the bit stream 118 of Fig. 1 be encoded.

[0055] At operation 406, at least some coefficients of a 4x4 data block may be ignored when encoding the 4x4 data block. As a non-limiting example of operation 404, at least some of the coefficients 112 of Fig. 1 of the 4x4 data block 110 may be ignored when encoding the data block 110 into the bit stream 118. In some non-limiting examples, at least two of the coefficients of the 4x4 data block may be ignored. In some non-limiting examples, the last two coefficients of the 4x4 data block may be ignored according to a zigzag scan pattern.

[0056] Setting the coefficients to zero can be an example of ignoring the coefficients. For example, at least some coefficients (e.g., two, without limitation, e.g., the last two coefficients, without limitation) can be set to zero at operation 406.

[0057] Fig. 5A and Fig. 5B together are a flowchart of a method 500 according to one or more examples. At least a portion of the method 500 may, in some non-limiting examples, be performed by an apparatus or system, such as the device 100 of Fig. 1, the device video data encoder 102 from Fig. 1, the facility 200 from Fig. 2, the video data encoder 202 from Fig. 2, the facility 300 from Fig. 3, the video data encoder 302 from Fig. 3 or another device or system. Although illustrated as discrete blocks, various blocks may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation.

[0058] At operation 502, video data may be encoded to generate compressed video data. As a non-limiting example, video data 104 may be Fig. 1 into compressed video data 106 from Fig. 1. When performing operation 502, one or more of operation 504, operation 506, operation 508, operation 510, operation 512, operation 514, operation 516, operation 518, operation 520, operation 522, and operation 524 may be performed. In other words, one or more of operation 504, operation 506, operation 508, operation 510, operation 512, operation 514, operation 516, operation 518, operation 520, operation 522, and operation 524 may be substeps of operation 502.

[0059] At operation 504, a data block representing video data may be transformed using an integer transform. As a non-limiting example, the data block may represent a group of pixels of an image of video data. As a non-limiting example of operation 504, a data block representing the video data 104 may be transformed using an integer transform.

[0060] At operation 506, the transformed data block may be quantized to produce a 4x4 data block. As a non-limiting example, the data block transformed at operation 504 may be quantized to produce the 4x4 data block 110 of Fig. 1 to generate.

[0061] At operation 508, at least some coefficients of the 4x4 data block may be set to zero. The 4x4 data block may represent the video data. Data from the video data may have been identified, predicted, transformed (e.g., at operation 504), and / or quantized (e.g., at operation 506) to generate the 4x4 data block. As a non-limiting example of operation 508, at least some of the coefficients 112 of Fig. 1 of the 4x4 data block 110 may be set to zero. In some non-limiting examples, at least two of the coefficients of the 4x4 data block may be set to zero. In some non-limiting examples, the last two coefficients of the 4x4 data block may be set to zero according to a zigzag scan pattern.

[0062] At operation 510, the 4x4 data block may be encoded into a bitstream according to CAVLC. The bitstream may represent compressed video data. As a non-limiting example of operation 510, the 4x4 data block 110 may be encoded according to CAVLC 120 from Fig. 1 into the bit stream 118 of Fig. 1. When performing operation 510, one or more of operation 512, operation 514, operation 516, operation 518, operation 520, operation 522, and operation 524 may be performed. In other words, one or more of operation 512, operation 514, operation 516, operation 518, operation 520, operation 522, and operation 524 may be substeps of operation 510.

[0063] At operation 512, the number of non-zero coefficients of the 4x4 data block may be counted according to CAVLC.

[0064] At operation 514, the number of trailing ones of the 4x4 data block may be counted according to CAVLC.

[0065] In operation 516, the number of non-zero coefficients and the number of trailing ones can be encoded according to CAVLC. Operation 512, operation 514, and operation 516 can be performed according to level 1 of CAVLC.

[0066] In operation 518, the sign of each of the subsequent ones may be encoded according to CAVLC. Operation 518 may be performed according to level 2 of CAVLC.

[0067] In some non-limiting examples, operation 512, operation 514, operation 516, and operation 518 may be performed during the same clock cycle. In some non-limiting examples, stage 1 and stage 2 of CAVLC may be performed during the same clock cycle.

[0068] At operation 520, the levels of remaining non-zero coefficients may be encoded according to CAVLC. Operation 520 may be performed according to level 3 of CAVLC.

[0069] In operation 522, a number of zeros before a final non-zero coefficient may be encoded according to CAVLC. Operation 522 may be performed according to level 4 of CAVLC.

[0070] In operation 524, zeros before the last non-zero coefficient may be encoded according to CAVLC. Operation 524 may be performed according to level 5 of CAVLC.

[0071] In some non-limiting examples, operation 520 may be performed in parallel with operation 524. In some non-limiting examples, stage 3 and stage 5 of the CAVLC may be performed in parallel.

[0072] Fig. 6A and Fig. 6B together are a flowchart of a method 600 according to one or more examples. At least a portion of the method 600 may, in some non-limiting examples, be performed by an apparatus or system, such as the device 100 of Fig. 1, the device video data encoder 102 from Fig. 1, the facility 200 from Fig. 2, the video data encoder 202 from Fig. 2, the facility 300 from Fig. 3, the video data encoder 302 from Fig. 3 or another device or system. Although illustrated as discrete blocks, various blocks may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation.

[0073] At operation 602, video data may be encoded to generate compressed video data. As a non-limiting example, video data 104 may be Fig. 1 into compressed video data 106 from Fig. 1. When performing 602, one or more of operation 604, operation 606, operation 608, operation 610, operation 612, operation 614, operation 616, operation 618, operation 620, operation 622, operation 624, operation 626, operation 628, operation 630, operation 632, and operation 634 may be performed. In other words, one or more of operation 604, operation 606, operation 608, operation 610, operation 612, operation 614, operation 616, operation 618, operation 620, operation 622, operation 624, operation 626, operation 628, operation 630, operation 632, and operation 634 may be substeps of operation 602.

[0074] At operation 604, a data block representing video data may be transformed using an integer transform. As a non-limiting example, the data block may represent a group of pixels of an image of video data. As a non-limiting example of operation 604, a data block representing the video data 104 may be transformed using an integer transform.

[0075] At operation 606, the transformed data block may be quantized to produce a 4x4 data block. As a non-limiting example, the data block transformed at operation 604 may be quantized to produce the 4x4 data block 110 of Fig. 1 to generate.

[0076] At operation 608, the 4x4 data block may be encoded into a bitstream according to CAVLC. The bitstream may represent compressed video data. As a non-limiting example of operation 608, the 4x4 data block 110 may be encoded according to CAVLC 120 from Fig. 1 into the bit stream 118 of Fig. 1. When performing operation 610, one or more of operation 610, operation 612, operation 614, operation 616, operation 618, operation 620, operation 622, operation 624, operation 626, operation 628, operation 630, operation 632, and operation 634 may be performed. In other words, one or more of operation 610, operation 612, operation 614, operation 616, operation 618, operation 620, operation 622, operation 624, operation 626, operation 628, operation 630, operation 632, and operation 634 may be substeps of operation 608.

[0077] At operation 610, when encoding the 4x4 data block (e.g., at operation 608), at least some of the coefficients of the 4x4 data block may be ignored. The 4x4 data block may represent the video data. As a non-limiting example, data from the video data may have been identified, predicted, transformed (e.g., at operation 604), and / or quantized (e.g., at operation 606) to generate the 4x4 data block. As a non-limiting example, at least some of the coefficients 112 of Fig. 1 of the 4x4 data block 110 may be ignored. In some non-limiting examples, at least two of the coefficients of the 4x4 data block may be ignored. In some non-limiting examples, the last two coefficients of the 4x4 data block may be ignored according to a zigzag scan pattern. Some or all of operation 614, operation 618, operation 622, operation 628, and operation 630 may be examples of ignoring coefficients of operation 612 at various stages of the CAVLC.

[0078] At operation 612, a number of non-zero coefficients of the 4x4 data block may be counted according to CAVLC.

[0079] In operation 614, when counting non-zero coefficients according to CAVLC (e.g., in operation 612), the last two coefficients may not be counted as non-zero coefficients, regardless of whether the last two coefficients are non-zero coefficients. In other words, when counting non-zero coefficients according to CAVLC (e.g., in operation 612), the last two coefficients may be ignored.

[0080] At 616, the number of subsequent ones of the 4x4 data block can be counted according to CAVLC.

[0081] At operation 618, when counting trailing ones according to CAVLC (e.g., at operation 616), the last two coefficients may not be counted as trailing ones, regardless of whether the last two coefficients are ones. In other words, the last two coefficients may be ignored when counting trailing ones according to CAVLC (e.g., at operation 616).

[0082] At operation 620, the number of non-zero coefficients and the number of trailing ones may be encoded according to CAVLC. Operation 612, operation 616, and operation 620 may be performed according to CAVLC level 1. Operation 614 and operation 618 may be changes that affect CAVLC level 1.

[0083] In operation 622, the sign of each of the subsequent ones may be encoded according to CAVLC. Operation 622 may be performed according to level 2 of CAVLC.

[0084] In operation 624, when encoding the signs of trailing ones according to CAVLC (e.g., in operation 622), a sign of the last two coefficients may not be encoded. In other words, the last two coefficients may be ignored when encoding the signs of trailing ones according to CAVLC. Operation 624 may be a change that affects level 2 of CAVLC.

[0085] In some non-limiting examples, one or more of operation 612, operation 616, operation 620, and operation 622 may be performed during the same clock cycle. As a non-limiting example, stage 1 of CAVLC and stage 2 of CAVLC may be performed during the same clock cycle. Furthermore, in some non-limiting examples, one or more of operation 614, operation 618, and operation 624 may be performed during the same clock cycle, i.e., the same clock cycle during which one or more of operation 612, operation 616, operation 620, and operation 622 were performed.

[0086] In operation 626, the levels of the remaining non-zero coefficients may be encoded according to CAVLC. Operation 626 may be performed according to level 3 of CAVLC.

[0087] In operation 628, one level of the last two coefficients may not be encoded when encoding the levels according to CAVLC (e.g., in operation 626). In other words, when encoding the levels of the remaining non-zero coefficients according to CAVLC, the last two coefficients may be ignored. Operation 628 may be a change that affects level 3 of CAVLC.

[0088] At operation 630, a number of zeros before a final non-zero coefficient may be encoded according to CAVLC. Operation 630 may be performed according to level 4 of CAVLC.

[0089] In operation 632, zeros before the last non-zero coefficient may be encoded according to CAVLC. Operation 632 may be performed according to level 5 of CAVLC.

[0090] In some non-limiting examples, one or both of operation 626 and operation 628 may be performed in parallel with operation 632. As a non-limiting example, stage 3 and stage 5 of the CAVLC may be performed in parallel.

[0091] At operation 634, when identifying the last non-zero coefficient according to CAVLC (e.g., the last non-zero coefficient of one or both of operation 630 and operation 632), the last two coefficients may not be included for consideration. In other words, when identifying the last non-zero coefficient according to CAVLC, the last two coefficients may be ignored. Operation 634 may be a change that affects one or both of Stage 4 and Stage 5 of CAVLC.

[0092] Modifications, additions, or omissions may be made to method 400, method 500, and / or method 600 without departing from the scope of the present disclosure. For example, the acts of method 400, method 500, and / or method 600 may be implemented in different orders. Furthermore, the outlined acts and actions are provided only as examples, and some of the acts and actions may optionally be combined into fewer acts and actions or expanded into additional acts and actions without affecting the essence of the disclosed example.

[0093] Fig. 7 is a block diagram of an apparatus 700 that may be used, in one or more examples, to implement various functions, operations, acts, processes, or methods disclosed herein. Apparatus 700 includes one or more processors 702 (sometimes referred to herein as "processors 702") operably coupled to one or more devices, such as data storage devices (sometimes referred to herein as "data storage 704"), without limitation. Data storage 704 includes machine-executable code 706 stored thereon (e.g., stored on a computer-readable memory, without limitation), and processors 702 include logic circuitry 708. Machine-executable code 706 includes information describing functional elements that may be implemented (e.g., performed) by logic circuitry 708.Logic circuitry 708 implements (e.g., performs) the functional elements described by machine-executable code 706. Apparatus 700, when executing the functional elements described by machine-executable code 706, should be considered special-purpose hardware for executing functional elements disclosed herein. In one or more examples, processors 702 may execute the functional elements described by machine-executable code 706 sequentially, concurrently (e.g., on one or more different hardware platforms), or in one or more parallel process streams.

[0094] When implemented by the logic circuitry 708 of the processors 702, the machine-executable code 706 may adapt the processors 702 to perform operations of examples disclosed herein. For example, the machine-executable code 706 may adapt the processors 702 to perform at least a portion or all of the method 400 of Fig. 4, of the procedure 500 of Fig. 5A and Fig. 5B and Procedure 600 of Fig. 6A and Fig. 6B. As another example, machine-executable code 706 may adapt processors 702 to execute at least a portion or all of the functions provided to device 100 of Fig. 1, the video data encoder 102 of Fig. 1, the establishment of 200 of Fig. 2, the video data encoder 202 of Fig. 2, the establishment of 300 of Fig. 3 or the video data encoder 302 of Fig. 3 carry out the processes discussed.

[0095] Processors 702 may include a general-purpose processor, a special-purpose processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, another programmable device, or any combination thereof configured to perform the functions disclosed herein. A general-purpose computer, including a processor, is considered a special-purpose computer, while the general-purpose computer executes computational instructions (e.g., software code, without limitation) related to examples.It should be noted that a general-purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but alternatively, processors 702 may include any processor, controller, microcontroller, or state machine known in the art. Processors 702 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0096] In one or more examples, data storage 704 includes volatile data storage (e.g., random access memory (RAM), without limitation), non-volatile data storage (e.g., flash memory, a hard disk drive, a solid-state drive, erasable programmable read-only memory (EPROM), without limitation). In one or more examples, processors 702 and data storage 704 may be implemented in a single device (e.g., a semiconductor device product, a system-on-chip (SOC), without limitation). In one or more examples, processors 702 and data storage 704 may be implemented in separate devices.

[0097] In one or more examples, machine-executable code 706 may include computer-readable instructions (e.g., software code, firmware code, without limitation). As a non-limiting example, the computer-readable instructions may be stored via data storage 704, directly accessed by processors 702, and executed by processors 702 using at least logic circuitry 708. Also as a non-limiting example, the computer-readable instructions may be stored in data storage 704, transferred to a storage device (not shown) for execution, and executed by processors 702 using at least logic circuitry 708. Accordingly, in one or more examples, logic circuitry 708 includes electrically configurable logic circuitry.

[0098] In one or more examples, machine-executable code 706 may describe hardware (e.g., circuitry, without limitation) to be implemented in logic circuitry 708 to perform the functional elements. This hardware may be described at a variety of abstraction levels, from low-level transistor layouts to high-level description languages. At a high abstraction level, a hardware description language (HDL) such as, but not limited to, an Institute of Electrical and Electronics Engineers (IEEE) standard hardware description language (HDL) may be used. As non-limiting examples, Verilog™, SystemVerilog™, or Very Large Scale Integration (VLSI) hardware description languages ​​(VHDL™) may be used.

[0099] HDL descriptions can be freely converted into descriptions at any of numerous other abstraction levels. As a non-limiting example, a high-level description can be converted into a logic-level description, such as a register transfer language (RTL), a gate-level description (GL), a layout-level description, or a mask-level description. As a non-limiting example, micro-operations performed by hardware logic circuits (e.g.,Gates, flip-flops, registers, without limitation) of logic circuit 708 may be described in an RTL and then converted into a GL description by a synthesis tool, and the GL description may be converted into a layout-level description by a placement and routing tool, corresponding to a physical layout of an integrated circuit, a programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. Accordingly, in one or more examples, machine-executable code 706 may include an HDL, an RTL, a GL description, a mask-level description, another hardware description, or any combination thereof.

[0100] In examples where machine-executable code 706 includes a hardware description (at any level of abstraction), a system (not shown, but including data storage 704) may implement the hardware description described by machine-executable code 706. As a non-limiting example, processors 702 may include a programmable logic device (e.g., an FPGA or a PLC, without limitation), and logic circuitry 708 may be electrically controlled to implement circuitry in logic circuitry 708 corresponding to the hardware description. Also as a non-limiting example, logic circuitry 708 may include hard-wired logic manufactured by a manufacturing system (not shown, but including memory 704) according to the hardware description of machine-executable code 706.

[0101] Regardless of whether the machine-executable code 706 includes computer-readable instructions or a hardware description, the logic circuit 708 performs those functional elements described by the machine-executable code 706 when it implements the functional elements of the machine-executable code 706. It should be noted that although a hardware description may not directly describe functional elements, a hardware description indirectly describes functional elements that the hardware elements described by the hardware description can perform.

[0102] As used herein, the term "substantially" with respect to a given parameter, property, or condition means, and includes, to the extent understood by one skilled in the art, that the given parameter, property, or condition is satisfied with a small degree of variance, such as within acceptable manufacturing tolerances. For example, a substantially satisfied parameter may be satisfied to at least about 90%, at least about 95%, or even at least about 99%.

[0103] As used in the present disclosure, the terms "module" or "component" may refer to specific hardware implementations configured to perform the actions of the module or component, or software objects or software routines that may be stored on or executed by general-purpose hardware (e.g., computer-readable media, processing devices, without limitation) of the computing system. In some further examples, the various components, modules, engines, and services described in the present disclosure may be implemented as objects or processes executing on the computing system (e.g., as separate threads, without limitation).Although some of the systems and methods described in the present disclosure are generally described as being implemented in software (stored on or executed by general-purpose hardware), specific hardware implementations or a combination of software and specific hardware implementations are also possible and are contemplated.

[0104] As used in the present disclosure, the term "combination" with reference to a plurality of elements may include a combination of all of the elements or any of various different subcombinations of some of the elements. For example, the phrase "A, B, C, D, or combinations thereof" may refer to one of A, B, C, or D; the combination of each of A, B, C, and D; and any subcombination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0105] Terms used in the present disclosure, and particularly in the appended claims (e.g., subject matter of the appended claims), are generally intended to be "open-ended" terms (e.g., the term "including" should be interpreted as "including, but not limited to," the term "comprising" should be interpreted as "at least comprising," the term "includes" should be interpreted as "includes, but is not limited to," but not limited to). As used herein, "each" means some or a whole. As used herein, "all" means a whole.

[0106] Furthermore, if a specific number of an introduced claim statement is intended, that intention will be expressly stated in the claim, and in the absence of such a statement, no such intention exists. As an aid to understanding, for example, the following accompanying claims may include the use of the introductory phrases "at least one" and "one or more" to introduce claim statements. However, the use of such phrases should not be construed to imply that the introduction of a claim statement by the indefinite articles "a" or "an" limits a particular claim containing such an introduced claim statement to examples containing only one such statement, even if the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an" (e.g.,"a" or "an" means "at least one" or "one or more"; the same applies to the use of certain articles used to introduce claim particulars.

[0107] Furthermore, even if a particular number of introduced claim details is explicitly recited, those skilled in the art will recognize that such a recited number should be interpreted to mean at least the recited number (e.g., simply stating "two details" without other modifiers means at least two details or two or more details). Furthermore, where a convention analogous to "at least one of, but not limited to, A, B, and C" or "one or more of, but not limited to, A, B, and C" is used, such construction is generally intended to include A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together, but not limited to.

[0108] Furthermore, any disjunctive word or phrase representing two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibility of including either of the terms, one or the other, or both. For example, the phrase "A or B" should be understood to include the possibilities "A" or "B" or "A and B."

[0109] Additional, non-limiting examples of the disclosure may include: Example 1: An apparatus comprising: a video data encoder to: encode a 4x4 data block into a bitstream according to context-adaptive variable-length coding, the 4x4 data block representing video data; and, while encoding the 4x4 data block, ignore at least some coefficients of the 4x4 data block. Example 2: The device of example 1, wherein the video data encoder ignores at least some coefficients of the 4x4 data block by setting at least some coefficients of the 4x4 data block to zero before encoding the 4x4 data block. Example 3: The apparatus of examples 1 and 2, wherein the video data encoder, after setting at least some coefficients of the 4x4 data block to zero to encode the 4x4 data block into the bitstream: counts a number of non-zero coefficients of the 4x4 data block; counts a number of trailing ones of the 4x4 data block; encodes the number of non-zero coefficients and the number of trailing ones according to context-adaptive variable-length coding; encodes a sign of each of the trailing ones according to context-adaptive variable-length coding; encodes coefficient levels according to context-adaptive variable-length coding; a number of zeros before a last non-zero coefficient is encoded according to context-adaptive variable-length encoding, and zeros before the last non-zero coefficient are encoded according to context-adaptive variable-length encoding. Example 4: The apparatus of examples 1 to 3, wherein the video data encoder, to ignore at least some coefficients of the 4x4 data block when encoding the 4x4 data block, performs one or more of the following: not counting at least some coefficients as non-zero coefficients when counting the non-zero coefficients according to the context-adaptive variable-length encoding; not counting at least some coefficients as trailing ones when counting the trailing ones according to the context-adaptive variable-length encoding; not encoding a sign of at least some coefficients when the signs of the trailing ones are encoded according to the context-adaptive variable-length encoding; not encoding a level of at least some coefficients when levels are encoded according to the context-adaptive variable-length encoding;and not including at least some coefficients if a last non-zero coefficient is identified according to the context-adaptive variable-length coding.; Example 5: The device of examples 1 to 4, wherein the at least some coefficients comprise at least two coefficients. Example 6: The device of examples 1 to 5, wherein the at least some coefficients comprise the last two coefficients of the 4x4 data block according to a zigzag scan pattern of the coefficients in the 4x4 data block. Example 7: The apparatus of Examples 1 to 6, wherein the video data encoder encodes the number of non-zero coefficients and the number of trailing ones and encodes the sign of each of the trailing ones during the same clock cycle. Example 8: The apparatus of Examples 1 to 7, wherein the video data encoder encodes the 4x4 data block into the bitstream in 16 or fewer clock cycles. Example 9: An apparatus comprising: a video data encoder to: encode a 4x4 data block into a bitstream according to context-adaptive variable-length coding, the 4x4 data block representing the video data; and during encoding the 4x4 data block, ignore at least some coefficients of the 4x4 data block, thereby encoding video data to produce compressed video data. Example 10: The apparatus of Example 9, wherein the video data encoder, prior to encoding the 4x4 data block, sets at least some coefficients of the 4x4 data block to zero to ignore at least some coefficients of the 4x4 data block. Example 11: The apparatus of Examples 9 and 10, wherein the video data encoder, after setting at least some coefficients of the 4x4 data block to zero, counts a number of non-zero coefficients of the 4x4 data block according to the variable-length context-adaptive coding; counts a number of trailing ones of the 4x4 data block according to the variable-length context-adaptive coding; encodes the number of non-zero coefficients and the number of trailing ones according to the variable-length context-adaptive coding; encodes a sign of each of the trailing ones according to the variable-length context-adaptive coding; encodes coefficient levels according to the variable-length context-adaptive coding;encoding a number of zeros before a last non-zero coefficient according to context-adaptive variable-length coding and encoding zeros before the last non-zero coefficient according to context-adaptive variable-length coding, thereby encoding the 4x4 data block into the bit stream; Example 12: The apparatus of examples 9 to 11, wherein the video data encoder performs one or more of the following: not counting the at least some coefficients as non-zero coefficients when the non-zero coefficients are counted according to the context-adaptive variable-length coding; not counting at least some coefficients as trailing ones when the trailing ones are counted according to the context-adaptive variable-length coding; not encoding a sign of at least some coefficients when the signs of the trailing ones are encoded according to the context-adaptive variable-length coding; not encoding a level of at least some coefficients when levels are encoded according to the context-adaptive variable-length coding;and not including at least some coefficients if a last non-zero coefficient is identified according to the context-adaptive variable-length encoding, thereby ignoring at least some coefficients of the 4x4 data block when encoding the 4x4 data block; Example 13: The device of examples 9 to 12, wherein the at least some coefficients comprise at least two coefficients. Example 14: The apparatus of examples 9 to 13, wherein the at least two coefficients comprise the last two coefficients of the 4x4 data block according to a zigzag scan pattern of the coefficients in the 4x4 data block to zero. Example 15: The apparatus of examples 9 to 14, wherein the video data encoder: transforms a data block representing a group of pixels of an image of the video data using an integer transform; and quantizes the transformed data block to generate a 4x4 data block. Example 16: A method comprising: encoding video data to generate compressed video data, wherein the encoding comprises: encoding a 4x4 data block into a bitstream according to a context-adaptive variable-length encoding, the 4x4 data block representing the video data; and ignoring, during the encoding of the 4x4 data block, at least some coefficients of the 4x4 data block. Example 17: The method of Example 16, wherein ignoring at least some coefficients of the 4x4 data block comprises setting at least some coefficients of the 4x4 data block to zero prior to encoding the 4x4 data block. Example 18: The method of Examples 16 and 17, wherein encoding the 4x4 data block into the bitstream after setting at least some coefficients of the 4x4 data block to zero comprises: counting a number of non-zero coefficients of the 4x4 data block according to the variable-length context-adaptive encoding; counting a number of trailing ones of the 4x4 data block according to the variable-length context-adaptive encoding; encoding the number of non-zero coefficients and the number of trailing ones according to the variable-length context-adaptive encoding; encoding the sign of each of the trailing ones according to the variable-length context-adaptive encoding; encoding coefficient levels according to the variable-length context-adaptive encoding;Encoding a number of zeros before a last non-zero coefficient according to context-adaptive variable-length coding and encoding zeros before the last non-zero coefficient according to context-adaptive variable-length coding.; Example 19: The method of examples 16 to 18, wherein encoding the 4x4 data block into the bitstream while ignoring at least some coefficients of the 4x4 data block comprises one or more of: not counting the at least some coefficients as non-zero coefficients when counting non-zero coefficients according to the context-adaptive variable-length coding; not counting at least some coefficients as trailing ones when counting the trailing ones according to the context-adaptive variable-length coding; not encoding a sign of at least some coefficients when encoding the signs of the trailing ones according to the context-adaptive variable-length coding; not encoding a level of at least some coefficients when encoding levels according to the context-adaptive variable-length coding;and not including at least some coefficients if a last non-zero coefficient is identified according to the context-adaptive variable-length coding.; Example 20: The process of Examples 16 to 19, further comprising: Transforming a data block representing a group of pixels of an image of the video data using an integer transformation and Quantize the transformed data block to generate a 4x4 data block.

[0110] While the present disclosure has been described with reference to certain illustrated examples, those skilled in the art will recognize and understand that the present invention is not limited thereto. Rather, many additions, omissions, and modifications may be made to the illustrated and described examples without departing from the scope of the invention as claimed below, along with their legal equivalents. Furthermore, features of one example may be combined with features of another example and still be included within the scope of the invention contemplated by the inventor.

Claims

[1] Facility comprising: a video data encoder to: encode a 4x4 data block into a bitstream according to a context-adaptive variable-length coding, wherein the 4x4 data block represents video data; and to ignore at least some coefficients of the 4x4 data block while encoding the 4x4 data block. [2] The apparatus of claim 1, wherein the video data encoder ignores at least some coefficients of the 4x4 data block by setting at least some coefficients of the 4x4 data block to zero before encoding the 4x4 data block. [3] The apparatus of claim 2, wherein the video data encoder, after setting at least some coefficients of the 4x4 data block to zero to encode the 4x4 data block into the bitstream: counts a number of non-zero coefficients of the 4x4 data block; counts the number of subsequent ones of the 4x4 data block; the number of non-zero coefficients and the number of trailing ones are encoded according to context-adaptive variable-length coding; a sign of each of the subsequent ones is encoded according to context-adaptive variable-length encoding; Coefficient levels encoded according to context-adaptive variable-length coding; a number of zeros before a last non-zero coefficient is encoded according to context-adaptive variable-length coding and Zeros before the last non-zero coefficient are encoded according to context-adaptive variable-length coding. [4] The apparatus of claim 1, wherein the video data encoder, for ignoring at least some coefficients of the 4x4 data block when encoding the 4x4 data block, performs one or more of: Not counting at least some coefficients as non-zero coefficients when counting the non-zero coefficients according to the context-adaptive variable-length encoding; Not counting at least some coefficients as trailing ones when counting the trailing ones according to the context-adaptive variable-length encoding; not encoding a sign of at least some coefficients when the signs of the subsequent ones are encoded according to the context-adaptive variable-length encoding; Not encoding a level of at least some coefficients when encoding levels according to context-adaptive variable-length encoding; and Not including at least some coefficients if a last non-zero coefficient is identified according to context-adaptive variable-length coding. [5] The device of claim 1, wherein the at least some coefficients comprise at least two coefficients. [6] The device of claim 1, wherein the at least some coefficients comprise at least the last two coefficients of the 4x4 data block according to a zigzag scan pattern of the coefficients in the 4x4 data block. [7] The apparatus of claim 1, wherein the video data encoder encodes the number of non-zero coefficients and the number of trailing ones and encodes the sign of each of the trailing ones during the same clock cycle. [8] The apparatus of claim 1, wherein the video data encoder encodes the 4x4 data block into the bitstream in 16 or fewer clock cycles. [9] Facility comprising: a video data encoder to: encode a 4x4 data block into a bitstream according to a context-adaptive variable-length coding, the 4x4 data block representing the video data; and to ignore at least some coefficients of the 4x4 data block during encoding of the 4x4 data block, thereby encoding video data to generate compressed video data. [10] The apparatus of claim 9, wherein the video data encoder, prior to encoding the 4x4 data block, sets at least some coefficients of the 4x4 data block to zero to ignore at least some coefficients of the 4x4 data block. [11] The device of claim 10, wherein the video data encoder, after setting at least some coefficients of the 4x4 data block to zero: counts a number of non-zero coefficients of the 4x4 data block according to the context-adaptive variable-length coding; counts a number of trailing ones of the 4x4 data block according to the context-adaptive variable-length encoding; the number of non-zero coefficients and the number of trailing ones are encoded according to context-adaptive variable-length coding; a sign of each of the subsequent ones is encoded according to context-adaptive variable-length encoding; Coefficient levels encoded according to context-adaptive variable-length coding; a number of zeros before a last non-zero coefficient is encoded according to context-adaptive variable-length coding and Zeros before the last non-zero coefficient are encoded according to context-adaptive variable-length coding, to encode the 4x4 data block into the bitstream. [12] The apparatus of claim 9, wherein the video data encoder performs one or more of: Not counting at least some coefficients as non-zero coefficients when counting the non-zero coefficients according to the context-adaptive variable-length encoding; Not counting at least some coefficients as trailing ones, when the trailing ones are counted according to context-adaptive variable-length coding; not encoding a sign of at least some coefficients when the signs of the subsequent ones are encoded according to the context-adaptive variable-length encoding; Not encoding a level of at least some coefficients when encoding levels according to context-adaptive variable-length encoding; and Not including at least some coefficients if a last non-zero coefficient is identified according to the context-adaptive variable-length coding, in order to ignore at least some coefficients of the 4x4 data block when encoding the 4x4 data block. [13] The apparatus of claim 9, wherein the at least some coefficients comprise at least two coefficients. [14] The device of claim 13, wherein the at least two coefficients comprise at least the last two coefficients of the 4x4 data block according to a zigzag scan pattern of the coefficients in the 4x4 data block to zero. [15] The device of claim 9, wherein the video data encoder: transforms a data block representing a group of pixels of an image of the video data using an integer transformation and quantizes the transformed data block to generate a 4x4 data block. [16] A method comprising: Encoding video data to produce compressed video data, wherein the encoding comprises: Encoding a 4x4 data block into a bitstream according to a context-adaptive variable-length coding, wherein the 4x4 data block represents the video data; and Ignoring, while encoding the 4x4 data block, at least some coefficients of the 4x4 data block. [17] The method of claim 16, wherein ignoring at least some coefficients of the 4x4 data block comprises setting at least some coefficients of the 4x4 data block to zero prior to encoding the 4x4 data block. [18] The method of claim 17, wherein encoding the 4x4 data block into the bitstream after setting the at least some coefficients of the 4x4 data block to zero comprises: Counting a number of non-zero coefficients of the 4x4 data block according to the context-adaptive variable-length coding; Counting a number of trailing ones of the 4x4 data block according to the context-adaptive variable-length encoding; Encoding the number of non-zero coefficients and the number of trailing ones according to context-adaptive variable-length encoding; Encoding the sign of each of the subsequent ones according to context-adaptive variable-length encoding; Coding coefficient levels according to context-adaptive variable-length coding; Encoding a number of zeros before a last non-zero coefficient according to context-adaptive variable-length coding and Encoding zeros before the last non-zero coefficient according to context-adaptive variable-length encoding. [19] The method of claim 16, wherein encoding the 4x4 data block into the bitstream while ignoring at least some coefficients of the 4x4 data block comprises one or more of: Not counting at least some coefficients as non-zero coefficients when counting the non-zero coefficients according to the context-adaptive variable-length encoding; Not counting at least some coefficients as trailing ones, when the trailing ones are counted according to context-adaptive variable-length coding; not encoding a sign of at least some coefficients when the signs of the subsequent ones are encoded according to the context-adaptive variable-length encoding; Not encoding a level of at least some coefficients when encoding levels according to context-adaptive variable-length encoding; and Not including at least some coefficients if a last non-zero coefficient is identified according to context-adaptive variable-length coding. [20] The method of claim 16, further comprising: Transforming a data block representing a group of pixels of an image of the video data using an integer transformation and Quantize the transformed data block to generate a 4x4 data block.

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