DISPLAY FIELD AND DISPLAY DEVICE

Abstract

A display field comprises a substrate, a plurality of first subpixels, and a plurality of first light-shielding sections. The plurality of first subpixels is arranged on the substrate and is located within the functional device configuration region. A first subpixel comprises a first pixel circuit and a first light-emitting device. The first light-emitting device comprises a first electrode that is electrically connected to the first pixel circuit. Part of an orthographic projection of the first pixel circuit onto the substrate lies outside an orthographic projection of the first electrode onto the substrate. The plurality of first light-shielding sections is spaced apart from one another on a side of the plurality of first light-emitting devices facing away from the substrate and is located within the functional device configuration region.Each first light-shielding section is provided with a multitude of first aperture regions. A light-emitting region of the first light-emitting component is located in the corresponding first aperture region. An orthographic projection of a first part of the first pixel circuit onto the substrate lies within an orthographic projection of the first light-shielding section onto the substrate. The first part is a portion of the first pixel circuit whose orthographic projection onto the substrate lies outside the orthographic projection of the first electrode onto the substrate.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of display technology, in particular to a display panel and a display device. STATE OF THE ART

[0002] With the rapid development of display technology, display devices have gradually entered people's lives. Due to advantages such as self-illumination, low power consumption, wide viewing angle, fast response, high contrast, and flexible display, organic light-emitting diodes (OLEDs) are widely used in mobile phones, televisions, notebooks, and other smart products. DISCLOSURE OF THE INVENTION

[0003] In one aspect, a display panel is provided. The display panel has a functional device configuration area. The display panel includes a substrate, a plurality of first subpixels, and a plurality of first light-shielding portions. The plurality of first subpixels are arranged on the substrate and located in the functional device configuration area. At least one first subpixel includes a first pixel circuit and a first light-emitting device. The first light-emitting device includes a first electrode. The first electrode is electrically connected to the first pixel circuit. A portion of an orthographic projection of the first pixel circuit onto the substrate is located outside an orthographic projection of the first electrode onto the substrate.

[0004] The plurality of first light-shielding sections are arranged spaced apart from one another on a side of a plurality of the first light-emitting components facing away from the substrate and are located in the functional component configuration region. Each first light-shielding section is provided with a plurality of first opening regions. Each first opening region corresponds to an individual first light-emitting component, and a light-emitting region of the first light-emitting component is located in the corresponding first opening region. An orthographic projection of a first part of the first pixel circuit onto the substrate is located within an orthographic projection of the first light-shielding section onto the substrate. The first part is a part of the first pixel circuit whose orthographic projection onto the substrate lies outside the orthographic projection of the first electrode onto the substrate.

[0005] In some embodiments, the display panel includes a plurality of first pixel units arranged in the functional component configuration area. Each first pixel unit includes a plurality of first subpixels of the first subpixels. The plurality of first opening areas of each first light-shielding portion correspond one-to-one to a plurality of first subpixels of the same first pixel unit.

[0006] In some embodiments, for a plurality of first subpixels located within an outer boundary of a same first light-shielding portion, a distance between the centers of two first subpixels adjacent in an adjustment direction is a first distance. In the adjustment direction, a distance between the centers of two adjacent first subpixels located within the outer boundaries of two adjacent first light-shielding portions is a second distance. The first distance is smaller than the second distance.

[0007] In some embodiments, the plurality of first subpixels includes a plurality of red subpixels, a plurality of first green subpixels, a plurality of second green subpixels, and a plurality of blue subpixels.

[0008] The plurality of red subpixels and the plurality of first green subpixels are alternately arranged in a first oblique direction, and the plurality of red subpixels and the plurality of second green subpixels are alternately arranged in a second oblique direction. The plurality of blue subpixels and the plurality of second green subpixels are alternately arranged in the first oblique direction, and the plurality of blue subpixels and the plurality of first green subpixels are alternately arranged in the second oblique direction. The plurality of first green subpixels and the plurality of second green subpixels are alternately arranged in a first direction, and the plurality of red subpixels and the plurality of blue subpixels are alternately arranged in a second direction. The first direction is substantially perpendicular to the second direction. The first oblique direction intersects the second oblique direction.Both the first oblique direction and the second oblique direction intersect the first direction; and both the first oblique direction and the second oblique direction intersect the second direction.

[0009] In some embodiments, the adjustment direction is at least one of the following: the first direction, the second direction, the first oblique direction, and the second oblique direction.

[0010] In some embodiments, the display panel includes a plurality of first pixel units. Each first pixel unit includes a red subpixel, a first green subpixel, a second green subpixel, and a blue subpixel that are adjacent. In the same first pixel unit, the red subpixel and the blue subpixel are arranged in the second direction, and the first green subpixel and the second green subpixel are arranged in the first direction. An outer boundary of an orthographic projection of the first light-shielding portion onto the substrate has a shape of an approximate rhombus.

[0011] In some embodiments, the plurality of first light-shielding sections are arranged in a plurality of rows and a plurality of columns. Each row includes a plurality of first light-shielding sections arranged in a first direction, and each column includes a plurality of first light-shielding sections arranged in a second direction. The first direction is substantially perpendicular to the second direction.

[0012] In some embodiments, the display panel further comprises a second electrode layer. The second electrode layer is arranged between the first electrodes and the first light-shielding sections. A portion of the second electrode layer arranged in the functional device configuration area is provided with a plurality of second opening areas. Orthographic projections of the plurality of second opening areas onto the substrate are located in a region between orthographic projections of the plurality of first light-shielding sections onto the substrate.

[0013] In some embodiments, the plurality of first light-shielding portions are arranged in a plurality of rows and a plurality of columns. Each row includes a plurality of first light-shielding portions arranged in a first direction, and each column includes a plurality of first light-shielding portions arranged in a second direction. The first direction is substantially perpendicular to the second direction. A second opening region is arranged between two first light-shielding portions adjacent in the first direction; and / or the second opening region is arranged between two first light-shielding portions adjacent in the second direction.

[0014] In some embodiments, a plurality of first light-shielding portions in two adjacent rows are arranged offset from each other, and a plurality of first light-shielding portions in two adjacent columns are arranged offset from each other.

[0015] In some embodiments, the second opening region has a shape of an approximate circle or an approximate ellipse.

[0016] In some embodiments, the display substrate further includes a main display area. The main display area at least partially surrounds the functional device configuration area. The display panel further includes a plurality of second subpixels and a second light-shielding portion. The plurality of second subpixels are arranged on the substrate and located in the main display area. Each second subpixel includes a second pixel circuit and a second light-emitting device. At least one second light-emitting device includes a third electrode. The third electrode is electrically connected to the second pixel circuit. A portion of an orthographic projection of the second pixel circuit onto the substrate is located outside an orthographic projection of the third electrode onto the substrate.

[0017] The second light-shielding portion is arranged on a side of the plurality of second subpixels facing away from the substrate and is located in the main display area. The second light-shielding portion comprises a plurality of third opening areas. Each third opening area corresponds to an individual second light-emitting device, and a light-emitting area of ​​the second light-emitting device is located in the corresponding third opening area. An orthographic projection of a second part of a plurality of second pixel circuits onto the substrate is located within an orthographic projection of the second light-shielding portion onto the substrate. The second part is a part of the second pixel circuits whose orthographic projection onto the substrate lies outside the orthographic projection of the third electrode onto the substrate.

[0018] In some embodiments, the orthographic projection of the second light-shielding portion onto the substrate covers a first region. The first region is an area between the plurality of second light-emitting devices in the main display area.

[0019] In some embodiments, a portion of the second electrode layer disposed in the main display area has a continuous film layer structure.

[0020] In some embodiments, the first light-shielding portions are made of the same material as the second light-shielding portion and are arranged in the same layer as the second light-shielding portion.

[0021] In some embodiments, the first subpixels further comprise a plurality of first filter sections. Each first filter section corresponds to a single first opening area, and a boundary of an orthographic projection of the first filter section onto the substrate is located within an orthographic projection of a corresponding first light-shielding section onto the substrate. In a case where the display panel further comprises a plurality of second subpixels and a second light-shielding section, the second subpixels further comprise a plurality of second filter sections. Each second filter section corresponds to a single third opening area, and a boundary of an orthographic projection of the second filter section onto the substrate is located within an orthographic projection of the second light-shielding section onto the substrate.

[0022] In some embodiments, the display panel further comprises an encapsulation layer. The encapsulation layer is disposed between the plurality of first light-shielding portions and the first light-emitting components.

[0023] In some embodiments, the display panel further comprises a plurality of signal lines. The plurality of signal lines are electrically connected to the first pixel circuit. At least one signal line comprises a signal trace and a switching line. The signal trace is used to connect to an external signal source. The switching line is connected to the first pixel circuit. A portion of the signal trace located in the functional component configuration area is transparent.

[0024] In some embodiments, the plurality of signal lines includes scan signal lines, reset signal lines, enable signal lines, and initialize signal lines.

[0025] The scanning signal lines include first scanning traces and first switching lines. The first switching lines extend substantially in a first direction and are electrically connected to the first pixel circuits. The first scanning traces each extend at one end into the functional component configuration area to be electrically connected to the first switching lines. A portion of the first scanning traces arranged in the functional component configuration area is transparent.

[0026] The reset signal lines include first reset traces and second switching lines. The second switching lines extend substantially in the first direction and are electrically connected to the first pixel circuits. The first reset traces each extend with one end into the functional component configuration area to be electrically connected to the second switching lines. A portion of the first reset traces arranged in the functional component configuration area is transparent.

[0027] The enable signal lines include first enable traces and third switching lines. The third switching lines extend substantially in the first direction and are electrically connected to the first pixel circuits. The first enable traces each extend at one end into the functional component configuration area to be electrically connected to the third switching lines. A portion of the first enable traces arranged in the functional component configuration area is transparent.

[0028] The initialization signal lines include first initialization traces and fourth switching lines. The fourth switching lines extend substantially in the first direction and are electrically connected to the first pixel circuits. The first initialization traces each extend with one end into the functional component configuration area to be electrically connected to the fourth switching lines. A portion of the first initialization traces arranged in the functional component configuration area is transparent.

[0029] In some embodiments, the display panel comprises a semiconductor layer, a first gate conductive layer, a second gate conductive layer, a first source-drain conductive layer, and a transparent conductive layer arranged sequentially in a direction perpendicular to and away from the substrate. The first switching lines, the second switching lines, and the third switching lines are located in the first gate conductive layer, and the fourth switching lines are located in the second gate conductive layer; and / or portions of the first scan tracks, the first reset tracks, the first enable tracks, and the first initialization tracks arranged in the functional device configuration area are located in the transparent conductive layer.

[0030] In some embodiments, the plurality of signal lines further includes first voltage signal lines and data lines. The first voltage signal lines and the data lines extend substantially in a second direction and are both electrically connected to the first pixel circuits. At least a portion of the first voltage signal lines and the data lines located in the functional device configuration area is transparent.

[0031] In some embodiments, the first voltage signal lines include first voltage traces and fifth switching lines. The fifth switching lines are arranged on a side of the first pixel circuits facing away from the substrate and are electrically connected to the first voltage traces.

[0032] In some embodiments, the display substrate comprises a semiconductor layer, a first gate conductive layer, a second gate conductive layer, a first source-drain conductive layer, a transparent conductive layer, and a second source-drain conductive layer arranged sequentially in a direction perpendicular to and away from the substrate. A portion of the first voltage traces and the data lines arranged in the functional device configuration area is located in the transparent conductive layer. The fifth switching lines are located in the second source-drain conductive layer.

[0033] In another aspect, a display device is provided. The display device comprises a housing and a display panel as described in any of the above embodiments arranged in the housing. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] To more clearly describe the technical solutions in the present disclosure, accompanying drawings to be used in some embodiments of the present disclosure are briefly presented below. Obviously, the accompanying drawings described below are merely accompanying drawings of some embodiments of the present disclosure, and those skilled in the art can also obtain other drawings according to these accompanying drawings. Furthermore, the accompanying drawings in the following description may be regarded as schematic representations, but do not represent limitations on an actual size of a product, an actual process of a method, and an actual timing of a signal included in the embodiments of the present disclosure. Fig. 1 is a structural diagram of a display device according to some embodiments; Fig. 2 is an exploded view of a display device according to some embodiments; Fig. 3A is a cross-sectional view of a functional component configuration area of ​​a display panel according to some embodiments; Fig. 3B is a cross-sectional view of a main display area of ​​a display panel according to some embodiments; Fig. 4 is an equivalent circuit diagram of a pixel driver circuit according to some embodiments; Fig. 5 is a timing diagram of a pixel driver circuit according to some embodiments; Fig. 6A is a plan view of an arrangement of pixel circuits of a functional device configuration area of ​​a display panel according to some embodiments; Fig. 6B is a plan view of an arrangement of light-emitting devices of a functional device configuration area of ​​the display panel according to some embodiments; Fig. 6C is a plan view of a functional component configuration area of ​​a display panel provided with first light shielding portions according to some embodiments; Fig. 6D is a plan view of a functional component configuration area of ​​another display panel provided with first light-shielding portions according to some embodiments; Fig. 6E is a plan view of a functional component configuration area of ​​a display panel according to some embodiments; Fig. 7 is a structural diagram of a first light-shielding portion of a display panel according to some embodiments; Fig. 8 is an enlarged view of a pixel unit of a functional component configuration area of ​​a display panel according to some embodiments; Fig. 9A is a plan view of an array of pixel circuits of a main display area of ​​a display panel according to some embodiments; Fig. 9B is a plan view of an array of light-emitting devices of a main display area of ​​a display panel according to some embodiments; Fig. 9C is a plan view of a functional component configuration area of ​​a display panel provided with a second light shielding portion according to some embodiments; Fig. 9D is a plan view of a functional component configuration area of ​​another display panel provided with a second light-shielding portion according to some embodiments; Fig. 10A is a structural diagram of a second light-emitting portion of a display panel according to some embodiments; Fig. 10B is an enlarged view of a red subpixel of a main display area of ​​a display panel, according to some embodiments; Fig. 11 is a plan view of a semiconductor layer of a functional device configuration region of a display panel according to some embodiments; Fig. 12 is a plan view of a structure obtained by adding a first gate conductive layer to the gate conductive layer shown in Fig. 11 shown semiconductor layer of the functional device configuration region is obtained; Fig. 13 is a plan view of a structure obtained by adding a second gate conductive layer to the gate layer shown in Fig. 12 shown first gate conductive layer of the functional device configuration region is obtained; Fig. 14 is a plan view of a structure obtained by adding a first source-drain conductive layer to the Fig. 13 shown second gate conductive layer of the functional device configuration region is obtained; Fig. 15 is a plan view of a structure obtained by adding a transparent conductive layer to the Fig. 14 shown first source-drain conductive layer of the functional device configuration region is obtained; Fig. 16 is a plan view of a structure obtained by adding a second source-drain conductive layer to the Fig. 15 shown transparent conductive layer of the functional device configuration area is obtained; Fig. 17 is a plan view of a structure obtained by adding a first electrode to the Fig. 16 shown second source-drain conductive layer of the functional device configuration region is obtained; Fig. 18 is a plan view of a semiconductor layer of a main display region of a display panel according to some embodiments; Fig. 19 is a plan view of a structure obtained by adding a first gate conductive layer to the gate conductive layer shown in Fig. 18 shown semiconductor layer of the main display area is obtained; Fig. 20 is a plan view of a structure obtained by adding a second gate conductive layer to the gate layer shown in Fig. 19 shown first gate conductive layer of the main display area is obtained; Fig. 21 is a plan view of a structure obtained by adding a first source-drain conductive layer to the Fig. 20 shown second gate conductive layer of the main display area is obtained; Fig. 22 is a plan view of a structure obtained by adding a transparent conductive layer to the Fig. 21 shown first source-drain conductive layer of the main display area is obtained; Fig. Figure 23 is a plan view of a structure obtained by adding a second source-drain conductive layer to the Fig. 22 shown transparent conductive layer of the main display area is obtained; and Fig. 24 is a plan view of a structure obtained by adding first electrodes to the Fig. 23 shown second source-drain conductive layer of the main display area is obtained. EMBODIMENTS OF THE INVENTION

[0035] Technical solutions in some embodiments of the present disclosure will be described clearly and completely below with reference to the accompanying drawings. Obviously, the described embodiments are merely some, but not all, embodiments of the present disclosure. All other embodiments that one skilled in the art obtains based on the embodiments of the present disclosure are intended to be included within the scope of the present disclosure.

[0036] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the singular form "comprises" and the present participle form "comprising," are interpreted as having an open and inclusive meaning, that is, "including, but not limited to." In describing the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples" are intended to indicate that specific features, structures, materials, or properties related to the embodiment(s) or examples are included in at least one embodiment or at least one example of the present disclosure.The schematic representation of the above terms does not necessarily refer to the same embodiment(s) or example(s). Furthermore, the specific features, structures, materials, or properties may be included in any suitable manner in one or more embodiments or examples.

[0037] Hereinafter, terms such as "first" and "second" are used for descriptive purposes only, but should not be construed as indicating or implying the relative importance or the number of the specified technical features in an implicit manner. Thus, the features defined as "first" and "second" may explicitly or implicitly encompass one or more of the features. In the description of the embodiments of the present disclosure, the term "a plurality of" means two or more, unless otherwise specified.

[0038] In the description of some embodiments, the terms "connected" and "electrically connected" and their derivatives may be used. For example, the term "connected" may be used in the description of some embodiments to indicate that two or more components are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the content contained herein. As another example, the term "electrically connected" may be used in the description of some embodiments to indicate that two or more components are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the content contained herein.

[0039] The phrase "at least one of A, B, and C" has the same meaning as the phrase "at least one of A, B, or C," and both include the following combinations of A, B, and C: A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0040] The term “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0041] The term “applicable to” or “configured for,” as used herein, indicates an open and inclusive term that does not exclude devices that are applicable or configured to perform additional tasks or steps.

[0042] Furthermore, the use of the term “based on” should be understood in an open and inclusive manner, since a process, step, calculation or other action that is “based” on one or more of the specified conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those specified.

[0043] As used herein, the terms "parallel," "perpendicular," or "equal" encompass a specified case and a case similar to the specified case. The similar case lies within an acceptable range of deviation, and the acceptable range of deviation will be determined by one skilled in the art in light of the measurement in question and the errors associated with measuring a particular quantity (i.e., limitations of a measurement system). For example, the term "parallel" encompasses absolute parallelism and approximate parallelism, where, for example, an acceptable range of deviation of approximate parallelism may be a deviation within 5°. For example, the term "perpendicular" encompasses absolute perpendicularity and approximate perpendicularity, where, for example, an acceptable range of deviation of approximate perpendicularity may also be a deviation within 5°.The term "equal" includes absolute equality and approximate equality, where an acceptable range of deviation of approximate equality may, for example, refer to a difference between two equals being less than or equal to 5% of one of the two equals.

[0044] It is to be understood that where a layer or component is described as being disposed on another layer or substrate, the layer or component may be disposed directly on the other layer or substrate, or there may be one or more intermediate layers between the layer, component, and the other layer or substrate.

[0045] Example embodiments are described herein with reference to sectional views and / or plan views as idealized example drawings. In the accompanying drawings, the thicknesses of layers and regions are shown enlarged for clarity. Therefore, shape deviations with respect to the accompanying drawings, for example due to manufacturing technologies and / or tolerances, are conceivable. Therefore, the example embodiments should not be construed as being limited to the shapes of the regions shown herein, but should include shape deviations, for example due to manufacturing. For example, an etched region shown in a rectangular shape generally has the property of being curved.Therefore, the regions shown in the accompanying drawings are schematic in nature, and their shapes are not intended to show the actual shapes of a region in a device and are not intended to limit the scope of the exemplary embodiments.

[0046] Transistors used in pixel driver circuits (pixel circuits) provided in embodiments of the present disclosure may be thin-film transistors (TFTs), field-effect transistors (e.g., metal oxide semiconductors, MOS), or other switching elements with the same properties. Embodiments of the present disclosure are all described using an example in which the transistors are thin-film transistors.

[0047] Furthermore, the pixel driver circuits (the pixel circuits) provided in the embodiments of the present disclosure are all described using an example in which the transistors are P-type transistors. It should be noted that the embodiments of the present disclosure include, but are not limited to, such an example. For example, one or more transistors in a pixel driver circuit provided in the embodiments of the present disclosure may also use N-type transistors, as long as the coupling of the individual electrodes of the selected transistor types is performed with respect to individual electrodes of the corresponding thin-film transistors in the embodiments of the present disclosure, and corresponding high voltages or corresponding low voltages are provided through corresponding voltage terminals.

[0048] Herein, control electrodes of the respective thin-film transistors used in the pixel drive circuits (the pixel circuits) are gate electrodes of the transistors, first electrodes of the thin-film transistors are one of the source electrodes and drain electrodes of the thin-film transistors, and second electrodes of the thin-film transistors are the other of the source electrodes and drain electrodes of the thin-film transistors. Since a source electrode and a drain electrode of a thin-film transistor can be structurally symmetrical, the source electrode and drain electrode of the thin-film transistor may have no structural difference. That is, in the embodiments of the present disclosure, there may be no structural difference between the first electrodes and the second electrodes of the thin-film transistors.For example, in a case where the thin-film transistors are P-type transistors, the first electrodes of the thin-film transistors are source electrodes, and the second electrodes of the thin-film transistors are drain electrodes. For example, in a case where the thin-film transistors are N-type transistors, the first electrodes of the thin-film transistors are drain electrodes, and the second electrodes of the thin-film transistors are source electrodes.

[0049] In the pixel driver circuits (pixel circuits) provided in the embodiments of the present disclosure, capacitors may be individually formed capacitors through a process. For example, the capacitors are obtained by forming special capacitor electrodes, and each capacitor electrode of the capacitors may be formed by a metal layer, a semiconductor layer (e.g., doped polysilicon), etc. The capacitors may also be parasitic capacitors between the transistors, or may be formed by the transistors themselves, other components or lines, or even by parasitic capacitors between lines of the circuits themselves.

[0050] With reference to Fig. 1, some embodiments of the present disclosure provide a display device 1000. The display device 1000 may be any device that displays text or images, whether in motion (e.g., videos) or in stationary form (e.g., still images). By way of example, the display device 1000 may be any product or component with a display function, such as a television, a notebook computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, or a virtual reality (VR) device.

[0051] Here, the display device 1000 is an electroluminescent display device or a photoluminescent display device. In a case where the display device is an electroluminescent display device, the electroluminescent display device may be an organic electroluminescent display device (e.g., organic light-emitting diode, or OLED) or a quantum dot electroluminescent display device (e.g., quantum dot light-emitting diode, or QLED). In a case where the display device is a photoluminescent display device, the photoluminescent display device may be a quantum dot photoluminescent display device.

[0052] In some embodiments, with reference to Fig. 1 and Fig. 2, the display device 1000 includes a housing 100 and a display panel 200, a functional component 300, a circuit board 400, and other electronic accessories arranged in the housing 100.

[0053] The circuit board 400 can be bonded to the display panel 200 at one end and arranged on the back of the display panel 200 by bending to realize a full-screen design. The functional component 300 can be integrated into the back of the display panel 200 to realize the full-screen design.

[0054] It should be noted that the functional component 300 may be a camera, an infrared sensor, a proximity sensor, an eyeball tracking module, a face recognition module, etc. With reference to Fig. 1 and Fig. 2, the functional component 300 is, for example, a camera.

[0055] In some embodiments, as in Fig. 2, Fig. 3A and Fig. 3B, the display panel 200 includes a display substrate 10 and an encapsulation layer 20 for encapsulating the display substrate 10.

[0056] The display substrate 10 has a light-exiting side and a non-light-exiting side that are opposite each other. The encapsulation layer 20 is arranged on the light-exiting side of the display substrate 10. The encapsulation layer 20 can be an encapsulation film or an encapsulation substrate.

[0057] With reference to Fig. 2, the display panel 200 has a display area A and a border area B arranged on at least one side of the display area A. Fig. 2 shows an example in which the border area B is arranged around the display area A.

[0058] Here, the display area A is an area for displaying images and is configured to include a plurality of pixel units R. The edge area B is an area where no image is displayed and is configured to include pixel drive circuits such as a gate drive circuit and a source drive circuit.

[0059] It should be noted that in a case where the functional component 300 is integrated into the display panel on the back of the display panel 200, the display area A further comprises a functional component configuration area A1 and a main display area A2 that at least partially surrounds the functional component configuration area A1. The functional component 300 is located in the functional component configuration area A1. Fig. 1 and Fig. 2 illustrate examples where the main display area A2 surrounds the functional component configuration area A1.

[0060] By way of example, with reference to Fig. 2 and Fig. 6B, the display area A of the display panel 200 is provided with a plurality of pixel units P, and each pixel unit P may include subpixels P' that emit light of a plurality of colors. For example, the subpixels P' that emit light of the plurality of colors include red subpixels, green subpixels, and blue subpixels.

[0061] With reference to Fig. 3A and Fig. 3B, each subpixel P' comprises a substrate 11, a light-emitting component 12, and a pixel driver circuit 13 arranged on the substrate 11. The pixel driver circuit 13 comprises a plurality of transistors 130. A transistor 130 comprises a channel region S, a source electrode 131, a drain electrode 132, and a gate electrode 133. The source electrode 131 and the drain electrode 132 are each in contact with the channel region S. In a direction perpendicular to the substrate 11 and away from this substrate 11, the light-emitting component 12 comprises a first electrode 121, a light-emitting functional layer 122, and a second electrode 123.

[0062] With reference to Fig. 6A and Fig. 6B, a part of the orthographic projections of the pixel driver circuits 13 onto the substrate 11 is located outside orthographic projections of the first electrodes 121 onto the substrate 11. That is, a part of the edges of the pixel driver circuits 13 are not covered by the first electrodes 121.

[0063] It should be noted that, for the sake of simplicity, a pixel circuit 13 mentioned below refers to the pixel driver circuit 13 mentioned above.

[0064] Here, the first electrode 121 is an anode of the light-emitting device 12 and the second electrode 123 is a cathode of the light-emitting device 12. Alternatively, the first electrode 121 is a cathode of the light-emitting device 12 and the second electrode 123 is an anode of the light-emitting device 12.

[0065] For example, as in Fig. 3A and Fig. 3B, the first electrode 121 is an anode of the light-emitting device 12 and the second electrode 123 is a cathode of the light-emitting device 12. The first electrode 121 is electrically connected to a source electrode 131 or a drain electrode 132 of a transistor 130 of the pixel circuit 13. Fig. 3A and Fig. 3B illustrate examples in which the first electrode 121 is electrically connected to the source electrode 131 of a transistor 130 of the pixel circuit 13.

[0066] In some embodiments, the light-emitting functional layer 122 comprises only a light-emitting layer. In some other embodiments, the light-emitting functional layer 122 further comprises, in addition to the light-emitting layer, at least one of the following layers: an electron transport layer (ETL), an electron injection layer (EIL), a hole transport layer (HTL), and a hole injection layer (HIL).

[0067] Furthermore, a structure of the above-mentioned pixel circuit 13 may vary, which can be determined according to actual needs. For example, the structure of the pixel circuit 13 may be a structure of "2T1C," "3T1C," "6T1C," "7T1C," "6T2C," or "7T2C," and the like. "T" stands for "transistor," a number before "T" represents the number of transistors, "C" stands for "storage capacitor," and a number before "C" represents the number of storage capacitors.

[0068] During use of the display panel 200, the stability of the transistors in the pixel circuit 13 and the light-emitting device 12 may decrease (e.g., a threshold voltage of a driver transistor drifts), which affects the display effects of the display panel 200. Therefore, compensation for the pixel circuit 13 is required.

[0069] The manner in which pixel circuit 13 is compensated may vary and can be determined depending on the actual requirements. For example, it is possible to incorporate a pixel compensation circuit into pixel circuit 13 so that the pixel compensation circuit can be used to perform internal compensation for pixel circuit 13. In another example, it is possible to detect the driver transistor or the light-emitting device using a transistor within pixel circuit 13, and detect the detected data to an external detection circuit so that a drive voltage value required for compensation is calculated using the external detection circuit, and then feedback is performed, thereby realizing external compensation for pixel circuit 13.

[0070] The present disclosure uses internal compensation, and the pixel circuit 13 takes the structure of “7T1C” as an example to illustrate the structure and working process of the pixel circuit 13.

[0071] For example, as in Fig. 4, the pixel circuit 13 may comprise a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driver transistor Td, and a storage capacitor C.

[0072] A control electrode of the first transistor T1 is electrically connected to a scanning signal terminal GATE, a first electrode of the first transistor T1 is electrically connected to a second electrode of the driver transistor Td, and a second electrode of the first transistor T1 is electrically connected to a control electrode of the driver transistor Td.

[0073] A control electrode of the second transistor T2 is electrically connected to the scanning signal terminal GATE, a first electrode of the second transistor T2 is electrically connected to a data signal terminal DATA, and a second electrode of the second transistor T2 is electrically connected to a first electrode of the driver transistor Td.

[0074] A control electrode of the third transistor T3 is electrically connected to a reset signal terminal RESET, a first electrode of the third transistor T3 is electrically connected to an initialization signal terminal VINIT, and a second electrode of the third transistor T3 is electrically connected to the control electrode of the driver transistor Td.

[0075] A control electrode of the fourth transistor T4 is electrically connected to an enable signal terminal EM, a first electrode of the fourth transistor T4 is electrically connected to a first voltage signal terminal VDD, and a second electrode of the fourth transistor T4 is electrically connected to the first electrode of the driver transistor Td.

[0076] A control electrode of the fifth transistor 15 is electrically connected to the enable signal terminal EM, a first electrode of the fifth transistor T5 is electrically connected to the second electrode of the driver transistor Td, and a second electrode of the fifth transistor 15 is electrically connected to the first electrode 121 (see Fig. 3A) of the light-emitting component 12.

[0077] A control electrode of the sixth transistor T6 is electrically connected to the scanning signal terminal GATE, a first electrode of the sixth transistor T6 is electrically connected to the initialization signal terminal VINIT, and a second electrode of the sixth transistor T6 is electrically connected to the first electrode 121 (see Fig. 3A) of the light-emitting component 12.

[0078] A first electrode plate C1 (see Fig. 3A) of the first storage capacitor C is electrically connected to the control electrode of the driver transistor Td, and a second electrode plate C2 (see Fig. 3A) of the storage capacitor C is electrically connected to the first voltage signal terminal VDD.

[0079] Based on the above structure of the pixel circuit 13 as shown in Fig. 4 and Fig. 5, in a single display frame, an operation of the subpixel may include, for example, a reset phase S1, a data write phase S2, and a light emission phase S3.

[0080] In the reset phase S1, the sixth transistor T6 is turned on under the control of a scanning signal Gate from the scanning signal terminal GATE, so that a voltage of the first electrode of the light-emitting device 12 is reset to an initialization voltage signal Vinit; and the third transistor T3 is turned on under the control of a reset signal Reset from the reset signal terminal RESET, so that a voltage of the control electrode of the driver transistor Td and a voltage of the first electrode plate C1 of the storage capacitor C are reset to the initialization voltage signal Vinit.

[0081] In the data write phase S2, the first transistor T1 and the second transistor T2 are turned on under the control of the scan signal Gate from the scan signal terminal GATE, and the driver transistor Td is turned on under the control of the initialization voltage signal stored in the storage capacitor C, so that a data signal Data is written from the data signal terminal DATA to the storage capacitor C.

[0082] In the light emission phase S3, the fourth transistor T4 and the fifth transistor T5 are turned on under the control of an enable signal Em of the enable signal terminal EM, so that a drive current signal is output to the light-emitting device 12 to drive the light-emitting device 12 to emit light.

[0083] In some embodiments, as in Fig. 3A and Fig. 3B, the display substrate 10 further comprises a pixel definition layer 14. The pixel definition layer 14 is arranged on a side of the first electrode 121 facing away from the substrate 11. The pixel definition layer 14 comprises a plurality of opening regions. A light-emitting component 12 is arranged in each opening region. That is, a light-emitting functional layer 122 of the light-emitting component 12 is in contact with the first electrode 121 in the opening region.

[0084] It should be noted that, in order to reduce processing difficulties, an area of ​​the first electrode 121 is larger than an area of ​​the respective opening region of the pixel definition layer 14, thereby ensuring that the entire opening region of the pixel definition layer 14 is a light-emitting region of the light-emitting device 12. That is, a portion of the light-emitting device 12 in which the first electrode 121, the second electrode 123, and the light-emitting functional layer 122 overlap with each other forms the light-emitting region of the light-emitting device 12. That is, a portion of the light-emitting device 12 in which the first electrode 121, the second electrode 123, and the light-emitting functional layer 122 correspond to the region in which the opening region of the pixel definition layer 14 is located forms the light-emitting region of the light-emitting device 12.

[0085] It is understood that in the case where the functional component 300 on the back side of the display panel 200 is integrated into the display panel 200, poor light transmittance of the display panel 200 adversely affects the light sensitivity of the functional component 300 on the back side of the display panel 200, while high reflectivity of the display panel 200 adversely affects the display effects of the display panel 200.

[0086] Based on this, in some related techniques, a polarizer is provided on a light-output side of a display panel to reduce the reflection intensity of external ambient light at the display panel. However, 50% to 60% of the light emitted from the display panel is lost after the light passes through the polarizer. That is, the polarizer significantly reduces the transmittance of a display device, resulting in an increase in the power consumption of the display device and a deterioration in the light sensitivity of a camera on a back side of the display panel. In addition, since parts of the edges of pixel circuits are not covered by first electrodes, external ambient light is reflected from the parts of the edges of the pixel circuits, causing a serious diffraction problem that causes a reduction in the light sensitivity of the functional device.

[0087] In some other related techniques, a color filter layer is provided on a light-output side of a display panel instead of a polarizer. However, compared with the related technique where a polarizer is provided on the light-output side of the display panel, the reflection intensity of external ambient light by the display panel is still large. Especially for an area where a camera is located, a light-shielding layer cannot completely cover the area between subpixels to ensure the light sensitivity of the functional device. Therefore, the reflection intensity in the functional device configuration area is too large, which impairs the display effects.In addition, since parts of the edges of the pixel circuits are not covered by first electrodes, the external ambient light is reflected from the parts of the edges of the pixel circuits, causing a serious diffraction problem that causes a reduction in the light sensitivity of the functional device.

[0088] Based on this, some embodiments of the present disclosure provide a display panel 200. Referring to Fig. 6C and Fig. 6D, the display panel 200 further includes a plurality of first light shielding portions 15.

[0089] It should be noted that, in order to distinguish pixel units P, subpixels P, light-emitting devices 12, and pixel circuits 13 in the functional device configuration area A1 from pixel units P, subpixels P, light-emitting devices 12, and pixel circuits 13 in the main display area A2, the pixel units P, the subpixels P', the light-emitting devices 12, and the pixel circuits 13 in the functional device configuration area A1 are referred to herein as first pixel units P1, first subpixels P1', first light-emitting devices 124, and first pixel circuits 135, respectively, and the pixel units P, the subpixels P', the light-emitting devices 12, and the pixel circuits 13 in the main display area A2 are referred to herein as second pixel units P2, second subpixels P2', second light-emitting devices 125, and second pixel circuits 136, respectively.

[0090] Fig. 6A to Fig. 6D are top views of the functional component configuration area of ​​the display panel according to some embodiments. Fig. 7 is a structural diagram of a first light shielding portion of the display panel according to some embodiments. Fig. 8 is an enlarged view of a single pixel unit in the functional component configuration area of ​​the display panel according to some embodiments.

[0091] As in Fig. 6A to Fig. 6D, the plurality of first light-shielding sections 15 are arranged at a distance from each other on a side facing away from the substrate 11 of a plurality of first light-emitting components 124, and are located in the functional component configuration area A1. As shown in Fig. 6B, Fig. 6C and Fig. 7, each first light shielding portion 15 is provided with a plurality of first opening regions 151, each first opening region 151 corresponding to a single first light-emitting device 124, and a light-emitting region of the first light-emitting device 124 is located in the corresponding first opening region 151.

[0092] As in Fig. 6A to Fig. 6D, an orthographic projection of a first part of the first pixel circuits 135 onto the substrate 11 is located within orthographic projections of the first light-shielding portions 135 onto the substrate 11. The first part is a part of a first pixel circuit 135 whose orthographic projection onto the substrate 11 is outside an orthographic projection of a first electrode 121 onto the substrate 11.

[0093] In this case, in the functional device configuration area A1, the orthographic projection of the first part of the first pixel circuits 135 onto the substrate 11 is located within the orthographic projections of the first light-shielding portions 135 onto the substrate 11. That is, the orthographic projections of the first pixel circuits 135 onto the substrate 11 are located within the orthographic projections of the first electrodes 121 and the first light-shielding portions 135 onto the substrate 11.In this way, the external ambient light can be prevented from directly irradiating the first pixel circuits 135, the reflection intensity of the external ambient light in the functional component configuration area A1 of the display panel 200 can be reduced, and a diffraction problem caused by the external ambient light directly irradiating the edges of the first pixel circuits 135 can be prevented, thereby improving the light sensitivity of the functional component 300. Furthermore, channel regions S of transistors 130 (e.g., first transistors T1) of the first pixel circuits 135 can be covered by the first electrodes 121 and the first light-shielding portions 135, so that a risk of drift of the threshold voltages of the transistors 130 is reduced, which improves the accuracy of the drive currents and the display effects in the functional component configuration area A1 of the display panel 200.

[0094] In some embodiments, as in Fig. 6B, Fig. 6C and Fig. As shown in Figure 7, each first light-shielding portion 15 corresponds to a single first pixel unit P1. That is, the plurality of first opening areas 151 of each first light-shielding portion 15 correspond to the plurality of first sub-pixels P1' of a same first pixel unit P1 in a one-to-one manner. In this way, the shielding areas of the first light-shielding portions 15 are the same for each first pixel unit P1, which avoids a problem of luminance unevenness or color cast due to different light transmittance areas for the plurality of first pixel units P1. Therefore, the display effects of the display panel 200 in the functional component configuration area A1 are improved.

[0095] It is understood that in order to reduce the areas of the first light-shielding portions 15 and to reduce an influence of the first light-shielding portions 15 on the transmittance of the display panel 200 in the functional component configuration area A1, as shown in Fig. 6B and Fig. 6C, for a plurality of first subpixels P1' located within an outer boundary of a same first light-shielding portion 15, a distance between the centers of two first subpixels P1' adjacent in an adjustment direction is a first distance L1, and in the adjustment direction, a distance between the centers of two adjacent first subpixels P1' each located within the outer boundaries of two adjacent first light-shielding portions 15 is a second distance L2. The first distance L1 is smaller than the second distance L2. Fig. 6C illustrates an example where the adjustment direction is a first direction X.

[0096] It should be noted that the first pixel circuits 135 in the functional component configuration area A1 are designed in a compact manner to increase the transmittance of the display panel 200 in the functional component configuration area A1. As shown in Fig. 6A and Fig. As shown in FIG. 6B, in the functional component configuration area A1, an arrangement of the first pixel circuits 135 is similar to an arrangement of the first light-emitting components 124. Thus, a geometric center of a first pixel circuit 135 substantially coincides with a geometric center of a respective first light-emitting component 124. Based on this, a center of an above-mentioned first subpixel P1' may refer to a center of a light-emitting region of a first light-emitting component 124 of the first subpixel P1'.

[0097] The above-mentioned adjustment direction may be an arrangement direction of any two adjacent first subpixels P1'.

[0098] In this case, since the distances between the plurality of first subpixels P1' that the first light-shielding portion 15 must cover are shortened, the area of ​​the first light-shielding portion 15 can be reduced accordingly. Thus, the transmittance of the display panel 200 in the functional component configuration area A1 is improved. Furthermore, since the distances between adjacent first light-shielding portions 15 are larger, the difficulty of a process for forming the first light-shielding portions 15 is reduced.

[0099] In some embodiments, with reference to Fig. 6B, Fig. 6C and Fig. 6D, the plurality of first subpixels P1' includes a plurality of red subpixels R, a plurality of first green subpixels G1, a plurality of second green subpixels G2, and a plurality of blue subpixels B. The plurality of red subpixels R and the plurality of first green subpixels G1 are alternately arranged in a first oblique direction Z1, and the plurality of red subpixels R and the plurality of second green subpixels G2 are alternately arranged in a second oblique direction Z2. The blue subpixels B and the second green subpixels G2 are alternately arranged in the first oblique direction Z1, and the blue subpixels B and the plurality of first green subpixels G1 are alternately arranged in the second oblique direction Z2. The first green subpixels G1 and the second green subpixels G2 are alternately arranged in the first direction X.The red subpixels R and the blue subpixels B are arranged alternately in the second direction Y.

[0100] The first direction X is substantially perpendicular to the second direction Y. The first oblique direction Z1 intersects the second oblique direction Z2. The first oblique direction Z1 and the second oblique direction Z2 each intersect the first direction X. The first oblique direction Z1 and the second oblique direction Z2 each intersect the second direction Y.

[0101] It should be noted that an included angle between the first oblique direction Z1 and the first direction X can be approximately in a range of 40° to 50°. An included angle between the first oblique direction Z1 and the second direction Y can be approximately in a range of 40° to 50°. An included angle between the second oblique direction Z2 and the first direction X can be approximately in a range of 130° to 140°. An included angle between the second oblique direction Z1 and the second direction Y can be approximately in a range of 40° to 50°.

[0102] Here, the above-mentioned adjustment direction may be at least one of the first direction X, the second direction Y, the first oblique direction Z1, and the second oblique direction Z2. For example, the adjustment direction includes the first direction X, the second direction Y, the first oblique direction Z1, and the second oblique direction Z2. That is, in a case where each first pixel unit P1 corresponds to a first light-shielding portion 15, the distances between a plurality of first sub-pixels P1' located in the same first pixel unit P1 are shortened, so that the plurality of first sub-pixels P1' are closer to each other.

[0103] On this basis, with reference to Fig. 6B and Fig. 6D, each first pixel unit P1 includes a red subpixel R, a first green subpixel G1, a second green subpixel G2, and a blue subpixel B that are adjacent. That is, four first subpixels P1' form a single minimum repeating unit. In the same first pixel unit P1, the red subpixel R and the blue subpixel B are arranged in the second direction Y, and the first green subpixel G1 and the second green subpixel G2 are arranged in the first direction X.

[0104] In this case, an outer boundary of the first light-shielding portion 15 may have substantially the shape of a rhombus, and two diagonal lines of the rhombus are substantially parallel to the first direction X and the second direction Y, respectively.

[0105] It should be noted that the term "substantially in the shape of a rhombus" herein means that the overall shape takes on a rhombus, but is not limited to a standard rhombus. That is, the "rhombus" here includes not only a standard rhombus, but also a shape that resembles a rhombus, taking into account the processing conditions. For example, one corner of the rhombus is curved. That is, the corner is smoothed.

[0106] In some embodiments, with reference to Fig. 6B, the first pixel units P1 are arranged in a plurality of rows and a plurality of columns. Each row thereof comprises a plurality of first pixel units P1 arranged in the first direction X, and each column thereof comprises a plurality of first pixel units P1 arranged in the second direction Y. On this basis, with reference to Fig. 6C, the plurality of first light-shielding portions 15 are arranged in a plurality of rows and a plurality of columns. Each row includes a plurality of first light-shielding portions 15 arranged in the first direction X, and each column includes a plurality of first light-shielding portions 15 arranged in the second direction Y.

[0107] Furthermore, with reference to Fig. 6B, a plurality of first pixel units P1 in each two adjacent rows may be arranged offset from each other, and a plurality of first pixel units P1 in each two adjacent columns may be arranged offset from each other, whereby the arrangement of the first pixel units P1 is more compact, which improves the display effects. On this basis, with reference to Fig. 6C, a plurality of first light-shielding portions 15 in each two adjacent rows may be arranged offset from each other, and a plurality of first light-shielding portions 15 in each two adjacent columns may be arranged offset from each other.

[0108] In some embodiments, as in Fig. 3A, Fig. 3B and Fig. 6B, the display panel 200 further includes a second electrode layer 1230. The second electrode layer 123 includes second electrodes 123 of the light-emitting devices 12 and is arranged between the first electrodes 121 and the first light-shielding portions 15.

[0109] A part of the second electrode layer 1230, which is located in the functional component configuration area A1, is provided with a plurality of second opening areas 1231. Orthographic projections of the second opening areas 1231 onto the substrate 11 are located in a region between the orthographic projections of the plurality of first light-shielding sections 15 onto the substrate 11 (see Fig. 6A). In this way, it may be possible to reduce an area of ​​the region of the second electrode layer 1230 located between the first light-shielding portions 15, so that the reflection of the external ambient light by the second electrode layer 1230 is reduced, which further reduces the reflection intensity of the external ambient light in the functional component configuration area A1 of the display panel 200.

[0110] It is understood that a second opening region 1231 may be provided between any two adjacent first light-shielding sections 15. For example, the plurality of first light-shielding sections 15 are arranged in a plurality of rows and a plurality of columns, each row comprising a plurality of first light-shielding sections 15 arranged in the first direction X, and each column comprising a plurality of first light-shielding sections 15 arranged in the second direction Y. In this case, a second opening region 1231 may be provided between two first light-shielding sections 15 adjacent in the first direction X, or a second opening region 1231 may be provided between two first light-shielding sections 15 adjacent in the second direction Y.

[0111] As in Fig. 6C, a plurality of first light-shielding sections 15 in each two adjacent rows may be arranged offset from one another, a plurality of first light-shielding sections 15 in each two adjacent columns may be arranged offset from one another, and the outer boundaries of the first light-shielding sections 15 have a substantially rhombus shape. In this case, the second opening regions 1231 are located between first light-shielding sections 15 that are adjacent to one another in the first direction X and between first light-shielding sections 15 that are adjacent to one another in the second direction Y. At this time, an area of ​​a region between two adjacent first light-shielding sections 15 in the first direction X and an area of ​​a region between two adjacent first light-shielding sections 15 in the second direction Y are larger, which reduces the difficulty of a process for patterning the second electrode layer 1230, that is,which contributes to the formation of the second opening regions 1231 on the second electrode layer 1230.

[0112] Here, the second opening region 1231 has the shape of an approximate circle or an approximate ellipse. It should be understood that by using a circular or ellipse shape, the areas of the second opening regions 1231 can be set relatively large. This means that an area of ​​the second electrode layer 1230 between the first light-shielding portions 15 can be reduced, so that the reflection intensity of the external ambient light in the functional component configuration area A1 of the display panel 200 is reduced.

[0113] It should be noted that the term "a shape of an approximate circle or an approximate ellipse" herein means that the shape is a circle or ellipse overall, but is not limited to a standard circle or ellipse. That is, the circle or ellipse here includes not only a standard circle or ellipse, but also a shape similar to a circle or ellipse taking process conditions into account. For example, part of a boundary of the circle or ellipse is a straight line.

[0114] It is understood that with reference to Fig. 6B, the first light-emitting devices 124 of the first subpixels P1' may be configured to emit white light or colored light.

[0115] Examples include Fig. 6C, the first light-emitting devices 124 of the first subpixels P1' are configured to emit colored light, and the colored light exits directly at an outer side of the display panel 200.

[0116] As in Fig. 6C, for example, the plurality of first subpixels P1' includes the red subpixels R, the first green subpixels G1, the second green subpixels G2, and the blue subpixels B. First light-emitting devices 124 of the red subpixels R are configured to emit red light, first light-emitting devices 124 of the first green subpixels G1 and first light-emitting devices 124 of the second green subpixels G2 are configured to emit green light, and first light-emitting devices 124 of the blue subpixels B are configured to emit blue light to achieve a color display.

[0117] Examples include, with reference to Fig. 6C and Fig. 6D, the first light-emitting components 124 of the first subpixels P1' are configured to emit white light. The first subpixels P1' further comprise a plurality of first filter sections 21. As shown in Fig. 6D, Fig. 7 and Fig. 8, each first filter section 21 corresponds to a first opening area 151, and a boundary S1 of an orthographic projection of the first filter section 21 onto the substrate 11 (see Fig. 6A) is located within a range of an orthographic projection of the corresponding first light-shielding portion 15 onto the substrate 11 (see Fig. 6A), so that light from first light-emitting components 124 is filtered, and the first light-shielding section 15 is prevented from interfering with the light reception of the functional component 300 (see Fig. 2). The plurality of first filter sections 21 can each transmit different monochromatic light, and the white light emitted by the first light-emitting devices 124 of the first subpixels P1' is irradiated onto the corresponding first filter sections 21, so that monochromatic light of the corresponding colors emerges to achieve a full-color display.

[0118] For example, as in Fig. 6C and Fig. 6D, the plurality of first subpixels P1' includes the red subpixels R, the first green subpixels G1, the second green subpixels G2, and the blue subpixels B. First filter portions 21 of the red subpixels R can transmit red light, first filter portions 21 of the first green subpixels G1 and the first filter portions 21 of the second green subpixels G2 can transmit green light, and first filter portions 21 of the blue subpixels B can transmit blue light. At this time, the white light emitted by the first light-emitting devices 124 of the red subpixels R, the first green subpixels G1, the second green subpixels G2, and the blue subpixels B is irradiated onto the corresponding first filter portions 21, so that monochromatic light of the corresponding colors emerges to achieve a full-color display.

[0119] In addition, since the first filter sections 21 transmit monochromatic light, light of most wavelength bands in the external ambient light can be filtered out by the first filter sections 21, whereby the reflection intensity of the external ambient light in the functional component configuration area A1 of the display panel 200 can be further reduced.

[0120] Fig. 9A to Fig. 9D are top views of a main display area of ​​the display panel according to some embodiments. Fig. 10A is a structural diagram of a second light shielding portion of the display panel according to some embodiments. Fig. 10B is an enlarged view of a single red subpixel in the main display area of ​​the display panel, according to some embodiments.

[0121] As in Fig. 9A to Fig. As shown in Figure 9D, the display panel 200 further includes a second light-shielding portion 16 located in the main display area A2. The second light-shielding portion 16 is arranged on a side of a plurality of second subpixels P2' facing away from the substrate 11.

[0122] It should be noted that the second light-shielding portion 16 may be made of the same material and arranged on the same layer as the first light-shielding portions 15.

[0123] With reference to Fig. 9B, Fig. 9C and Fig. 10A, the second light-shielding portion 16 includes a plurality of third opening regions 161. Each third opening region 161 corresponds to a second light-emitting device 125, and a light-emitting region of the second light-emitting device 125 is located within the third opening region 161.

[0124] As in Fig. 9A to Fig. 9D, an orthographic projection of a second part of the second pixel circuits 136 onto the substrate 11 is located within an orthographic projection of the second light-shielding portion 16 onto the substrate 11. The second part is a part of the second pixel circuits 136 whose orthographic projection onto the substrate 11 is outside orthographic projections of third electrodes 121 onto the substrate 11.

[0125] It should be noted that, to distinguish the first electrodes 121 of the second light-emitting devices 125 from the first electrodes 121 of the first light-emitting devices 124, the first electrodes 121 of the second light-emitting devices 125 are referred to herein as third electrodes 121. That is, the second light-emitting devices 125 include the third electrodes 121, and the third electrodes 121 are electrically connected to the second pixel circuits 136.

[0126] In this case, in the main display area A2, the orthographic projection of the second part of the second pixel circuits 136 onto the substrate 11 is located within the orthographic projection of the second light-shielding portion 136 onto the substrate 11. That is, the orthographic projections of the second pixel circuits 136 onto the substrate 11 are located within a range of the orthographic projections of the third electrodes 121 of the second light-shielding portion 136 onto the substrate 11. In this way, it is possible to prevent the external ambient light from directly irradiating the second pixel circuits 136, reduce the reflection intensity of the external ambient light in the main display area A2 of the display panel 200, and prevent a diffraction problem caused by external ambient light directly irradiating the edges of the second pixel circuits 136, thereby improving the display effects.Furthermore, channel regions S of transistors 130 (e.g., first transistors T1) of the second pixel circuits 136 can be covered by the third electrodes 121 and the second light shielding portion 136, so that a risk of drift of the threshold voltages of the transistors 130 is reduced, which improves the accuracy of the driving currents and the display effects in the main display area A2 of the display panel 200.

[0127] It should be understood that the main display area A2 of the display panel 200 is used only for displaying images and does not require the absorption of external ambient light. Therefore, in the main display area A2 of the display panel 200, there is no need to consider the transmittance of the area between the second subpixels P2'. The lower the reflection intensity of the external ambient light, the better the display effects.

[0128] Based on this, with reference to Fig. 9A to Fig. 9D, the orthographic projection of the second light-shielding portion 16 onto the substrate 11 covers a first region, which is a region between a plurality of second light-emitting devices 125 in the main display area A2. In this case, metal layers (e.g., the second electrode layer 1230) in the region between the plurality of second light-emitting devices 125 can all be covered by the second light-shielding portion 16, so that the reflection intensity of the external ambient light in the main display area A2 of the display panel 200 is reduced and the display effects of the main display area A2 are improved.

[0129] Based on this, a portion of the second electrode layer 1230 located in the main display area A2 may have a continuous film layer structure. This means that the portion of the second electrode layer 1230 located in the main display area A2 may not be subjected to a patterning process. That is, the portion of the second electrode layer 1230 located between the plurality of second subpixels P2' may not be provided with light-transmitting holes, simplifying the process.

[0130] Furthermore, since the orthographic projection of the second light-shielding portion 16 onto the substrate 11 covers the first region, that is, the region between the second light-emitting devices 125 of the second subpixels P2', the distances between the centers of the second light-emitting devices 125 of a plurality of second subpixels P2' of a same second pixel unit P2 do not need to be shortened. That is, the plurality of second light-emitting devices 125 are uniformly arranged.

[0131] Examples include, with reference to Fig. 9A to Fig. 9D, in the main display area A2, a plurality of red subpixels R and a plurality of first green subpixels G1 are alternately arranged in the first oblique direction Z1, and the plurality of red subpixels R and a plurality of second green subpixels G2 are alternately arranged in the second oblique direction Z2; the blue subpixels B and the second green subpixels G2 are alternately arranged in the first oblique direction Z1, and the blue subpixels B and the plurality of first green subpixels G1 are alternately arranged in the second oblique direction Z2; and the first green subpixels G1 and the second green subpixels G2 are alternately arranged in the first direction X, and the red subpixels R and the blue subpixels B are alternately arranged in the second direction Y.

[0132] On this basis, in an adjustment direction, the distances between the centers of the second light-emitting devices 125 of any two adjacent second subpixels P2' are approximately equal. The adjustment direction may be at least one of the first direction X, the second direction Y, the first oblique direction Z1, and the second oblique direction Z2.

[0133] It is understood that with reference to Fig. 9B, the second light-emitting devices 125 of the second subpixels P2' may be configured to emit white light or colored light.

[0134] For example, with reference to Fig. 9C, the second light-emitting devices 125 of the second subpixels P2' are configured to emit colored light. The colored light exits directly on the outside of the display panel 200.

[0135] For example, as in Fig. 9C, the plurality of second subpixels P2' includes the red subpixels R, the first green subpixels G1, the second green subpixels G2, and the blue subpixels B. Second light-emitting devices 125 of the red subpixels R are configured to emit red light, second light-emitting devices 125 of the first green subpixels G1 and second light-emitting devices 125 of the second green subpixels G2 are configured to emit green light, and second light-emitting devices 125 of the blue subpixels B are configured to emit blue light to achieve a color display.

[0136] For example, as in Fig. 9C and Fig. 9D, the second light-emitting components 125 of the second subpixels P2' are configured to emit white light. The second subpixels P2' further comprise a plurality of second filter sections 22. With reference to Fig. 9D, Fig. 10A and Fig. 10B, each second filter section 22 corresponds to a third opening area 161, and the boundaries S1 of the orthographic projections of the second filter sections 22 onto the substrate 11 are located within the orthographic projection of the second light-shielding section 16 onto the substrate 11 (see Fig. 9A) to filter light from the second light-emitting devices 125. The plurality of second filter sections 22 can each transmit different monochromatic light. The white light emitted by the second light-emitting devices 125 of the second subpixels P2' is irradiated onto the corresponding second filter sections 22, so that monochromatic light of the corresponding colors emerges to achieve a full-color display.

[0137] For example, as in Fig. 9C and Fig. 9D, the plurality of second subpixels P2' includes the red subpixels R, the first green subpixels G1, the second green subpixels G2, and the blue subpixels B. Second filter portions 22 of the red subpixels R can transmit red light, second filter portions 22 of the first green subpixels G1 and second filter portions 22 of the second green subpixels G2 can transmit green light, and second filter portions 22 of the blue subpixels B can transmit blue light. At this time, the white light emitted by the second light-emitting devices 125 of the red subpixels R, the first green subpixels G1, the second green subpixels G2, and the blue subpixels B is irradiated onto the corresponding second filter portions 22, so that monochromatic light of the corresponding colors emerges to achieve a full-color display.

[0138] In addition, since the second filter sections 22 transmit monochromatic light, light of most wavelength bands in the external ambient light can be filtered out by the second filter sections 22, whereby the reflection intensity of the external ambient light in the main display area A2 of the display panel 200 can be further reduced.

[0139] With reference to Fig. 6B, Fig. 6C, Fig. 9B and Fig. 9C, the plurality of first subpixels P1' and the plurality of second subpixels P2' each comprise red subpixels R, first green subpixels G1, second green subpixels G2, and blue subpixels B.

[0140] On this basis, in conjunction with Fig. 8, in the functional component configuration area A1, a distance between a boundary S2 of a light-emitting region of a red subpixel R and a corresponding inner boundary S3 of a corresponding first light-shielding portion 15, a distance between a boundary S2 of a light-emitting region of a first green subpixel G1 and a corresponding inner boundary S3 of a corresponding first light-shielding portion 15, a distance between a boundary S2 of a light-emitting region of a second green subpixel G2 and a corresponding inner boundary S3 of a corresponding first light-shielding portion 15, and a distance between a boundary S2 of a light-emitting region of a blue subpixel B and a corresponding inner boundary S3 of a corresponding first light-shielding portion 15 are approximately equal,so that the problem of luminance unevenness or color cast in the functional component configuration area A1 is avoided, which improves the display effects of the display panel 200 in the functional component configuration area A1.

[0141] Combined with Fig. 10B, in the main display area A2, a distance between a boundary S2 of a light-emitting region of a red sub-pixel R and a corresponding inner boundary S3 of the second light-shielding portion 16, a distance between a boundary S2 of a light-emitting region of a first green sub-pixel G1 and a corresponding inner boundary S3 of the second light-shielding portion 16, a distance between a boundary S2 of a light-emitting region of a second green sub-pixel G2 and a corresponding inner boundary S3 of the second light-shielding portion 16, and a distance between a boundary S2 of a light-emitting region of a blue sub-pixel B and a corresponding inner boundary S3 of the second light-shielding portion 16 are approximately equal, so that the problem of luminance unevenness or color cast in the main display area A2 is avoided, thereby improving the display effects of the display panel 200 in the main display area A2.

[0142] An illustration of this can be found in Fig. 10B using the example of the red subpixel R.

[0143] On this basis, the distance between the boundaries S2 of the light-emitting regions of the first sub-pixels P1' and the respective inner boundaries S3 of the first light-shielding portions 15 in the functional component configuration area A1 is approximately equal to the distance between the boundaries S2 of the light-emitting regions of the second sub-pixels P2 and the respective inner boundaries S3 of the second light-shielding portion 16 in the main display area A2, so that the problem of luminance unevenness or color cast between the functional component configuration area A1 and the main display area A2 is avoided, thereby improving the display effects of the display panel 200.

[0144] It should be noted that a boundary S2 of a light-emitting region herein is a boundary of each opening region of the pixel definition layer 14.

[0145] It is understood that, with reference to Fig. 3A, Fig. 6A, Fig. 6E and Fig. 24, the display panel 10 described above further includes a plurality of signal lines. The plurality of signal lines are electrically connected to the pixel circuits 13 (including the first pixel circuits 135 and the second pixel circuits 136). At least one of these signal lines includes a signal trace and a switching line. The signal trace is used for connection to an external signal source, and the switching line is connected to a first pixel circuit 135. A portion of the signal trace located in the functional component configuration area A1 is transparent to improve the transmittance of the display panel 200 in the functional component configuration area A1.

[0146] Examples include, with reference to Fig. 3A, Fig. 12 and Fig. 16, the plurality of signal lines scan signal lines GL, reset signal lines RL, enable signal lines EL, initialization signal lines INL, first voltage signal lines VDL and data lines DL.

[0147] The scanning signal lines GL are electrically connected to scanning signal terminals GATE of the pixel circuits 13. The reset signal lines RL are electrically connected to reset signal terminals RESET of the pixel circuits 13. The enable signal lines EL are electrically connected to enable signal terminals EM of the pixel circuits 13. The initialization signal lines INL are electrically connected to initialization signal terminals of the pixel circuits 13. The first voltage signal lines VDL are electrically connected to first voltage signal terminals VDD of the pixel circuits 13. The data lines DL are electrically connected to data signal terminals DATA of the pixel circuits 13.

[0148] In some embodiments, with reference to Fig. 6E, Fig. 12, Fig. 17 and Fig. 19, the scanning signal lines GL include first scanning traces GL1 and first switching lines GL2. The first switching lines GL2 extend substantially in the first direction X and are electrically connected to the first pixel circuits 135. The first scanning traces GL1 each extend at one end into the functional device configuration area A1 and are electrically connected to the first switching lines GL2, thereby avoiding interference between the scanning signal lines GL and some other signal lines (e.g., the data lines DATA) due to wiring overlaps.

[0149] On this basis, in the functional component configuration area A1, a part of the first scanning tracks GL1 located in the functional component configuration area A1 is transparent in order to improve the light transmittance of the display panel 200 in the functional component configuration area A1.

[0150] For example, as in Fig. 15 and Fig. As shown in Figure 19, the first scanning tracks GL1 include first sub-scanning tracks GL11 and second sub-scanning tracks GL12. The first sub-scanning tracks GL11 are located in the functional component configuration area A1. The second sub-scanning tracks GL12 are located in the main display area A2. The first sub-scanning tracks GL11 are transparent. The second sub-scanning tracks GL12 can be transparent or opaque.

[0151] In some embodiments, with reference to Fig. 6E, Fig. 12, Fig. 15 and Fig. 19, the reset signal lines RL include first reset traces RL1 and second switching lines RL2. The second switching lines RL2 extend substantially in the first direction X and are electrically connected to the first pixel circuits 135. The first reset traces RL1 each extend at one end into the functional device configuration area A1 and are electrically connected to the second switching lines RL2, thereby avoiding interference between the reset signal lines RL and some other signal lines (e.g., the data lines DATA) due to wiring overlaps.

[0152] On this basis, in the functional component configuration area A1, a part of the first reset traces RL1 located in the functional component configuration area A1 is transparent in order to improve the light transmittance of the display panel 200 in the functional component configuration area A1.

[0153] For example, as in Fig. 15 and Fig. As shown in Figure 19, the first reset traces RL1 include first sub-reset traces RL11 and second sub-reset traces RL12. The first sub-reset traces RL11 are located in the functional component configuration area A1. The second sub-reset traces RL12 are located in the main display area A2. The first sub-reset traces RL11 are transparent. The second sub-reset traces RL12 can be transparent or opaque.

[0154] In some embodiments, with reference to Fig. 6E, Fig. 12, Fig. 15 and Fig. 19, the enable signal lines EL include first enable traces EL1 and third switching lines EL2. The third switching lines EL2 extend substantially in the first direction X and are electrically connected to the first pixel circuits 135. The first enable traces EL1 each extend at one end into the functional device configuration area Ai and are electrically connected to the third switching lines EL2, thereby avoiding interference between the enable signal lines EL and some other signal lines (e.g., the data lines DATA) due to wiring overlaps.

[0155] On this basis, in the functional component configuration area A1, a part of the first enable tracks EL1 located in the functional component configuration area A1 is transparent in order to improve the light transmittance of the display panel 200 in the functional component configuration area A1.

[0156] For example, as in Fig. 15 and Fig. As shown in Figure 19, the first enable tracks EL1 include first sub-enable tracks EL11 and second sub-enable tracks EL12. The first sub-enable tracks EL11 are located in the functional component configuration area A1. The second sub-enable tracks EL12 are located in the main display area A2. The first sub-enable tracks EL11 are transparent. The second sub-enable tracks EL12 can be transparent or opaque.

[0157] In some embodiments, with reference to Fig. 6E, Fig. 13, Fig. 15 and Fig. 20, the initialization signal lines INL include first initialization traces INL1 and fourth switching lines INL2. The fourth switching lines INL2 extend substantially in the first direction X and are electrically connected to the first pixel circuits 135. The first initialization traces INL1 each extend at one end into the functional component configuration area A1 and are electrically connected to the fourth switching lines INL2, thereby avoiding interference between the initialization signal lines INL and some other signal lines (e.g., the data lines DATA) due to wiring overlaps.

[0158] On this basis, in the functional component configuration area A1, a part of the first initialization traces INL1 located in the functional component configuration area A1 is transparent in order to improve the light transmittance of the display panel 200 in the functional component configuration area A1.

[0159] For example, as in Fig. 15 and Fig. As shown in Figure 20, the first initialization tracks INL1 include first sub-initialization tracks INL11 and second sub-initialization tracks INL12. The first sub-initialization tracks INL11 are located in the functional component configuration area A1. The second sub-initialization tracks INL12 are located in the main display area A2. The first sub-initialization tracks INL11 are transparent. The second sub-initialization tracks INL12 can be transparent or opaque.

[0160] In some embodiments, with reference to Fig. 6E, Fig. 16 and Fig. 23, the first voltage signal lines VDL and the data lines DL extend substantially in the first direction X. In the functional component configuration area A1, at least a part of the first voltage signal lines VDL located in the functional component configuration area A1 and at least a part of the data lines DL located in the functional component configuration area A1 are transparent to improve the transmittance of the display panel 200 in the functional component configuration area A1.

[0161] For example, as in Fig. 6E, Fig. 16 and Fig. As shown in Figure 23, the first voltage signal lines VDL include first voltage traces VDL1 and fifth switching lines VDL2. The fifth switching lines VDL2 are arranged on a side of the first pixel circuits 135 facing away from the substrate 11 and are electrically connected to the first voltage traces VDL1. That is, the fifth switching lines VDL2 cross over the first pixel circuits 135 (see Fig. 6A). In this case, if the first voltage signal lines VDL are connected across the first pixel circuits 135 (see Fig. 6A), a distance between the first voltage signal lines VDL and the first pixel circuits 135 (see Fig. 6A) can be increased by means of the fifth switching lines VDL2 so that electromagnetic interference is reduced.

[0162] On this basis, as in Fig. 16 and Fig. 23, the first voltage traces VDL1 further comprise first sub-voltage traces VDL11 and second sub-voltage traces VDL12. The first sub-voltage traces VDL11 are located in the functional component configuration area A1. The second sub-voltage traces VDL12 are located in the main display area A2. The data lines DL comprise first sub-data lines DL1 and second sub-data lines DL2. The first sub-data lines DL1 are located in the functional component configuration area A1. The second sub-data lines DL2 are located in the main display area A2. Both the first sub-voltage traces VDL11 and the first sub-data lines DL1 can be transparent.

[0163] The signal lines contained in individual film layers and some other patterned film layers are explained below by way of example in connection with a film layer structure of the display substrate 10.

[0164] As in Fig. 17 and Fig. 24, the display substrate 10 includes a semiconductor layer ACT, a first gate conductive layer GT1, a second gate conductive layer GT2, a first source-drain conductive layer SD1, a transparent conductive layer TC, and a second source-drain conductive layer SD2, which are arranged sequentially in the direction perpendicular to the substrate 11 and away from this substrate 11.

[0165] It should be noted that an insulating film layer is disposed between any two adjacent layers of the semiconductor layer ACT, the first gate conductive layer GT1, the second gate conductive layer GT2, the first source-drain conductive layer SD1, the transparent conductive layer TC, and the second source-drain conductive layer SD2, for example, with reference to Fig. 3A and Fig. 3B, a first gate insulating layer GI1, a second gate insulating layer GI2, an interlayer insulating layer ILD, a first planarization layer PLN1, a second planarization layer PLN2, and a third planarization layer PLN3, etc., which is not specifically limited in embodiments of the present disclosure.

[0166] As in Fig. 3A, Fig. 3B, Fig. 11 and Fig. 18, the semiconductor layer ACT comprises channel regions S, source electrodes 131 (which are shown in Fig. 11 and Fig. 18 are not shown schematically) and drain electrodes 132 (which are shown in Fig. 11 and Fig. 18 are not shown schematically) of the individual transistors 130 of the pixel circuits 13.

[0167] It should be noted that a material of the semiconductor layer ACT includes amorphous silicon, monocrystalline silicon, polycrystalline silicon, or a metal oxide semiconductor material. For example, the material of the semiconductor layer ACT includes indium gallium zinc oxide (IGZO) and / or zinc oxide (ZnO), and the embodiments of the present disclosure are not limited thereto.

[0168] As in Fig. 12 and Fig. 19, the first gate conductive layer GT1 includes the first switching lines GL2, the second switching lines RL2, the third switching lines EL2, the second sub-scan tracks GL12, the second sub-reset tracks RL12, the second sub-enable tracks EL12, and the first electrode plates C1 of the storage capacitors C. That is, the first switching lines GL2, the second switching lines RL2, the third switching lines EL2, the second sub-scan tracks GL12, the second sub-reset tracks RL12, the second sub-enable tracks EL12, and the first electrode plates C1 of the storage capacitors C are arranged on the same layer, that is, are located on the first gate conductive layer GT1.

[0169] It should be noted that a material of the first gate conductive layer GT1 contains metal. For example, the material of the first gate conductive layer GT1 contains at least one of aluminum, copper, and molybdenum, and the embodiments of the present disclosure are not limited thereto. That is, materials of the first switching lines GL2, the second switching lines RL2, the third switching lines EL2, and the first electrode plates C1 of the storage capacitors C contain metal.

[0170] With reference to Fig. 12, a portion of the first switching lines GL2 that overlaps with the semiconductor layer ACT forms control electrodes of first transistors T1, control electrodes of second transistors T2, and control electrodes of sixth transistors T6. A portion of the second switching lines RL2 that overlaps with the semiconductor layer ACT forms control electrodes of third transistors T3. A portion of the third switching lines EL2 that overlaps with the semiconductor layer forms control electrodes of fourth transistors T4 and control electrodes of fifth transistors T5. First electrode plates C1 of the storage capacitors C, which are located in the functional component configuration area A1, are arranged between respective first switching lines GL2 and respective third switching lines EL2.

[0171] Furthermore, with reference to Fig. 19, a part of the second sub-reset tracks RL12 overlapping with the semiconductor layer ACT forms control electrodes of third transistors T3 and control electrodes of sixth transistors T6; a part of the second sub-scan tracks GL12 overlapping with the semiconductor layer ACT forms control electrodes of first transistors T1 and control electrodes of second transistors T2; and a part of the second sub-enable tracks EL12 overlapping with the semiconductor layer ACT forms control electrodes of the fourth transistor T4 and control electrodes of the fifth transistor T5. First electrode plates C1 of storage capacitors C located in the main display area A2 are located between respective second sub-scan tracks GL12 and respective second sub-enable tracks EL12.

[0172] As in Fig. 13 and Fig. 20, the second gate conductor layer GT2 includes the fourth switching lines INL2, the second sub-initialization tracks INL12, and second electrode plates C2 of the storage capacitors C. Orthographic projections of the second electrode plates C2 onto the substrate 11 partially overlap with orthographic projections of the respective first electrode plates onto the substrate 11.

[0173] Note that a material of the second gate conductive layer GT2 includes metal. For example, the material of the second gate conductive layer GT2 includes at least one of aluminum, copper, and molybdenum, and the embodiments of the present disclosure are not limited thereto.

[0174] With reference to Fig. 13 and Fig. 20, the storage capacitors C are formed in regions where the orthographic projections of the second electrode plates C2 onto the substrate 11 overlap with the orthographic projections of the first electrode plates C1 onto the substrate 11. The fourth switching lines INL2 are electrically connected via connecting lines to the third transistors T3 and the sixth transistor T6 of the first pixel circuits 135. The second sub-initialization tracks INL12 are electrically connected via connecting lines to the third transistors T3 and the sixth transistor T6 of the second pixel circuits 136.

[0175] In some embodiments, with reference to Fig. 20 and Fig. 21, the second gate conductive layer GT2 further includes shielding patterns 40 located in the main display area A2. The shielding patterns 40 are located between the second sub-reset tracks RL12 and the second sub-scan tracks GL12. Orthographic projections of the shielding patterns 40 onto the substrate 11 at least partially overlap with orthographic projections of the respective second sub-voltage tracks VDL12 onto the substrate 11, and the shielding patterns 40 are electrically connected to the second sub-voltage tracks VDL12 to reduce electromagnetic interference between the tracks.

[0176] As in Fig. 14 and Fig. As shown in Figure 21, the first source-drain conductive layer SD1 includes first interconnect lines 50, second interconnect lines 60, third interconnect lines 70, fourth interconnect lines 80, and the second sub-voltage traces VDL12. The first interconnect lines 50 and the second interconnect lines 60 are distributed in both the functional device configuration area A1 and the main display area A2. The third interconnect lines 70 and the fourth interconnect lines 80 are distributed only in the functional device configuration area A1.

[0177] It should be noted that a material of the first source-drain conductive layer SD1 includes metal. For example, the material of the first source-drain conductive layer SD1 includes at least one of the following materials: aluminum, copper, and molybdenum, and the embodiments of the present disclosure are not limited thereto.

[0178] In the functional component configuration area A1, as shown in Fig. 13 and Fig. 14, a first connecting line 50 is electrically connected to a first electrode of a respective third transistor T3 and to a first electrode of a respective sixth transistor T6. A second connecting line 60 is electrically connected to an electrode plate C1 of a respective capacitor C, a second electrode of a respective first transistor T1, and a second electrode of a respective third transistor T3. A third connecting line 70 is electrically connected to a second electrode plate C2 of a respective storage capacitor C and a first electrode of a respective fourth transistor T4. A fourth connecting line 80 is electrically connected to a second electrode of a respective fifth transistor T5 and a second electrode of a respective sixth transistor T6.

[0179] In the main display area A2, as shown in Fig. 20 and Fig. 21, a first connecting line 50 is electrically connected to a first electrode of a respective third transistor T3 and a first electrode of a respective sixth transistor T6. A second connecting line 60 is electrically connected to an electrode plate C1 of a respective storage capacitor C, a second electrode of a respective first transistor T1, and a second electrode of a respective third transistor T3.

[0180] As in Fig. 15 and Fig. 22, at least the parts of the first scanning tracks GL1, the first reset tracks RL1, the first enable tracks EL1, the first initialization tracks INL1, the data lines DL and the first voltage signal lines VDL located in the functional component configuration area A1 are transparent.

[0181] For example, as in Fig. 15 and Fig. 22, the transparent conductive layer TC includes the first sub-scan tracks GL11, the first sub-reset tracks RL11, the first sub-enable tracks EL11, the first sub-initialization tracks INL11, the first sub-voltage tracks VDL11, and the first sub-data lines DL1.

[0182] It should be noted that a material of the transparent conductive layer TC includes a transparent conductive material. A transmittance of the transparent conductive layer TC made of the transparent conductive material is greater than or equal to 60%. For example, the material of the transparent conductive layer TC includes indium tin oxide, and the embodiments of the present disclosure are not limited thereto.

[0183] As in Fig. 16 and Fig. 23, both the fifth switching lines VDL2 and the second sub-data lines DL2 may be located on the second source-drain conductive layer SD2.

[0184] It should be noted that a material of the second source-drain conductive layer SD2 includes metal. For example, the material of the second source-drain conductive layer SD2 includes at least one of the following materials: aluminum, copper, and molybdenum, and the embodiments of the present disclosure are not limited thereto.

[0185] In addition, with reference to Fig.23, the second source-drain conductive layer SD2 may include further support patterns 90 located in the main display area A2. The support patterns 90 and the second sub-data lines DL2 are arranged parallel to each other on two sides of the respective second pixel circuits 136 to play a role in supporting and balancing the first electrodes 121 of the light-emitting devices 12. Furthermore, the support patterns 90 may be electrically connected to the second sub-voltage traces VDL12, which can also reduce electromagnetic interference between signal lines.

[0186] Based on the above, the pads M of the pixel circuits 13 may consist of one or more layers of weld patterns formed in the first source-drain conductive layer SD1, the transparent conductive layer TC, and the second source-drain conductive layer SD2. For example, the pads M are formed by sequentially stacking the weld patterns in the first source-drain conductive layer SD1, the weld patterns in the transparent conductive layer TC, and the weld patterns in the second source-drain conductive layer SD2.

[0187] The above descriptions are merely specific implementations of the present disclosure. However, the scope of the present disclosure is not limited thereto. Modifications or substitutions that anyone skilled in the art can conceive within the technical scope of the present disclosure are intended to be included within the scope of the present disclosure. Therefore, the scope of the present disclosure is subject to the scope of the claims.

Claims

[1] A display panel having a functional component configuration area, the display panel comprising: a substrate; a plurality of first subpixels arranged on the substrate and located in the functional device configuration area, wherein at least one first subpixel comprises a first pixel circuit and a first light-emitting device, the first light-emitting device comprises a first electrode, and the first electrode is electrically connected to the first pixel circuit, wherein a portion of an orthographic projection of the first pixel circuit onto the substrate is located outside an orthographic projection of the first electrode onto the substrate; and a plurality of first light-shielding sections arranged at a distance from one another on a side of a plurality of the first light-emitting components facing away from the substrate and located in the functional component configuration region, wherein each first light-shielding section is provided with a plurality of first opening regions, each first opening region corresponds to an individual first light-emitting component, and a light-emitting region of the first light-emitting component is located in the corresponding first opening region, wherein an orthographic projection of a first part of the first pixel circuit onto the substrate is located within an orthographic projection of the first light-shielding section onto the substrate, wherein the first part is a part of the first pixel circuit,whose orthographic projection onto the substrate lies outside the orthographic projection of the first electrode onto the substrate., [2] The display panel according to claim 1, wherein the display panel comprises a plurality of first pixel units arranged in the functional component configuration area, each first pixel unit comprising a plurality of first sub-pixels of the first sub-pixels, wherein the plurality of first opening areas of each first light-shielding portion correspond one-to-one to a plurality of first sub-pixels of the same first pixel unit. [3] A display panel according to claim 1 or 2, wherein, for a plurality of first sub-pixels arranged within an outer boundary of a same first light-shielding portion, a distance between the centers of two first sub-pixels adjacent in an adjusting direction is a first distance; wherein, in the adjustment direction, a distance between the centers of two adjacent first subpixels located within the outer boundaries of two adjacent first light-shielding portions is a second distance; and where the first distance is smaller than the second distance. [4] The display panel of claim 3, wherein the plurality of first subpixels comprises a plurality of red subpixels, a plurality of first green subpixels, a plurality of second green subpixels, and a plurality of blue subpixels; wherein the plurality of red subpixels and the plurality of first green subpixels are arranged alternately in a first oblique direction, and the plurality of red subpixels and the plurality of second green subpixels are arranged alternately in a second oblique direction, wherein the plurality of blue subpixels and the plurality of second green subpixels are arranged alternately in the first oblique direction, and the plurality of blue subpixels and the plurality of first green subpixels are arranged alternately in the second oblique direction, and wherein the plurality of first green subpixels and the plurality of second green subpixels are arranged alternately in a first direction, and the plurality of red subpixels and the plurality of blue subpixels are arranged alternately in a second direction; and wherein the first direction is substantially perpendicular to the second direction, wherein the first oblique direction intersects the second oblique direction, and wherein both the first oblique direction and the second oblique direction each intersect the first direction, and both the first oblique direction and the second oblique direction each intersect the second direction. [5] The display panel according to claim 4, wherein the adjusting direction is at least one of the following: the first direction, the second direction, the first oblique direction, and the second oblique direction. [6] A display panel according to claim 4 or 5, wherein the display panel comprises a plurality of first pixel units, each first pixel unit comprising a red subpixel, a first green subpixel, a second green subpixel and a blue subpixel which are adjacent; wherein, in the same first pixel unit, the red subpixel and the blue subpixel are arranged in the second direction, and the first green subpixel and the second green subpixel are arranged in the first direction; and wherein an outer boundary of an orthographic projection of the first light-shielding portion onto the substrate has a shape of an approximate rhombus. [7] The display panel according to any one of claims 1 to 6, wherein the plurality of first light-shielding portions are arranged in a plurality of rows and a plurality of columns, each row comprising a plurality of first light-shielding portions arranged in a first direction, and each column comprising a plurality of first light-shielding portions arranged in a second direction, the first direction being substantially perpendicular to the second direction. [8] A display panel according to any one of claims 1 to 7, further comprising: a second electrode layer arranged between the first electrodes and the first light-shielding sections, wherein a part of the second electrode layer arranged in the functional device configuration region is provided with a plurality of second opening regions, wherein orthographic projections of the plurality of second opening regions onto the substrate are located at least partially in a region between orthographic projections of the plurality of first light-shielding sections onto the substrate. [9] A display panel according to claim 8, wherein the plurality of first light-shielding portions are arranged in a plurality of rows and a plurality of columns, each row comprising a plurality of first light-shielding portions arranged in a first direction, and each column comprising a plurality of first light-shielding portions arranged in a second direction, the first direction being substantially perpendicular to the second direction; and wherein a second opening region is arranged between two first light-shielding sections adjacent in the first direction, and / or the second opening region is arranged between two first light-shielding sections adjacent in the second direction. [10] A display panel according to claim 9, wherein a plurality of first light-shielding portions are arranged offset from each other in two adjacent rows, and a plurality of first light-shielding portions are arranged offset from each other in two adjacent columns. [11] A display panel according to any one of claims 8 to 10, wherein the second opening portion has a shape of an approximate circle or an approximate ellipse. [12] A display panel according to any one of claims 1 to 11, wherein the display panel further comprises a main display area at least partially surrounding the functional component configuration area, the display panel further comprising: a plurality of second subpixels arranged on the substrate and located in the main display area, each second subpixel comprising a second pixel circuit and a second light-emitting device, at least one second light-emitting device comprising a third electrode electrically connected to the second pixel circuit, a portion of an orthographic projection of the second pixel circuit onto the substrate being outside an orthographic projection of the third electrode onto the substrate; and a second light-shielding portion disposed on a side of the plurality of second sub-pixels remote from the substrate and located in the main display area, the second light-shielding portion comprising a plurality of third opening areas, each third opening area corresponding to an individual second light-emitting component, and a light-emitting area of the second light-emitting component being located in the corresponding third opening area, an orthographic projection of a second portion of a plurality of second pixel circuits onto the substrate being located within an orthographic projection of the second light-shielding portion onto the substrate, the second portion being a portion of the second pixel circuits whose orthographic projection onto the substrate is outside the orthographic projection of the third electrode onto the substrate. [13] The display panel according to claim 12, wherein the orthographic projection of the second light-shielding portion onto the substrate covers a first region, the first region being a region between the plurality of second light-emitting devices in the main display region. [14] A display panel according to claim 12 or 13, wherein a portion of the second electrode layer disposed in the main display area has a continuous film layer structure. [15] A display panel according to any one of claims 12 to 14, wherein the first light-shielding portions are made of the same material and are arranged in the same layer as the second light-shielding portion. [16] A display panel according to any one of claims 1 to 15, wherein the first subpixels further comprise: a plurality of first filter sections, each first filter section corresponding to a single first opening area, and wherein a boundary of an orthographic projection of the first filter section onto the substrate is located within an orthographic projection of a corresponding first light-shielding section onto the substrate; and wherein in a case that the display panel further comprises a plurality of second sub-pixels and a second light-shielding portion, the second sub-pixels further comprise: a plurality of second filter sections, each second filter section corresponding to a single third opening area, and wherein a boundary of an orthographic projection of the second filter section onto the substrate is located within an orthographic projection of the second light-shielding section onto the substrate. [17] A display panel according to any one of claims 1 to 16, further comprising: an encapsulation layer disposed between the plurality of first light-shielding portions and the first light-emitting devices. [18] A display panel according to any one of claims 1 to 17, further comprising: a plurality of signal lines electrically connected to the first pixel circuit, wherein at least one signal line comprises a signal trace and a switching line, wherein the signal trace is used for connecting to an external signal source, and the switching line is connected to the first pixel circuit, wherein a portion of the signal trace located in the functional device configuration area is transparent. [19] A display panel according to claim 18, wherein the plurality of signal lines comprises: Scanning signal lines comprising first scanning traces and first switching lines, the first switching lines extending substantially in a first direction and being electrically connected to the first pixel circuits, the first scanning traces each extending with one end into the functional component configuration area to be electrically connected to the first switching lines, a part of the first scanning traces arranged in the functional component configuration area being transparent; Reset signal lines comprising first reset traces and second switching lines, the second switching lines extending substantially in the first direction and being electrically connected to the first pixel circuits, the first reset traces each extending with one end into the functional device configuration area to be electrically connected to the second switching lines, a part of the first reset traces arranged in the functional device configuration area being transparent; Enable signal lines comprising first enable traces and third switching lines, wherein the third switching lines extend substantially in the first direction and are electrically connected to the first pixel circuits, wherein the first enable traces each extend with one end into the functional component configuration area to be electrically connected to the third switching lines, wherein a part of the first enable traces arranged in the functional component configuration area is transparent; and Initialization signal lines comprising first initialization traces and fourth switching lines, wherein the fourth switching lines extend substantially in the first direction and are electrically connected to the first pixel circuits, wherein the first initialization traces each extend with one end into the functional component configuration area to be electrically connected to the fourth switching lines, wherein a part of the first initialization traces arranged in the functional component configuration area is transparent. [20] The display panel according to claim 19, wherein the display panel comprises a semiconductor layer, a first gate conductive layer, a second gate conductive layer, a source-drain conductive layer, and a transparent conductive layer arranged sequentially in a direction perpendicular to and away from the substrate, and wherein the first switching lines, the second switching lines, and the third switching lines are located in the first gate conductive layer, and the fourth switching lines are located in the second gate conductive layer; and / or wherein parts of the first scan tracks, the first reset tracks, the first enable tracks, and the first initialization tracks arranged in the functional device configuration area are located in the transparent conductive layer. [21] The display panel according to any one of claims 18 to 20, wherein the plurality of signal lines further comprises first voltage signal lines and data lines, the first voltage signal lines and the data lines extending substantially in a second direction and both being electrically connected to the first pixel circuits; and wherein at least a portion of the first voltage signal lines and the data lines located in the functional device configuration area is transparent. [22] The display panel of claim 20, wherein the first voltage signal lines comprise first voltage traces and fifth switching lines, the fifth switching lines being arranged on a side of the first pixel circuits facing away from the substrate and being electrically connected to the first voltage traces. [23] The display panel according to claim 21, wherein the display substrate comprises a semiconductor layer, a first gate conductive layer, a second gate conductive layer, a first source-drain conductive layer, a transparent conductive layer, and a second source-drain conductive layer arranged sequentially in a direction perpendicular to and away from the substrate; and wherein a part of the first voltage traces and the data lines arranged in the functional device configuration area is located in the transparent conductive layer, the fifth switching lines being located in the second source-drain conductive layer. [24] Display device comprising: a housing; and a display panel according to any one of claims 1 to 23, wherein the display panel is arranged in the housing.

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