Display field and manufacturing process therefor, display device

Abstract

A display field, a manufacturing process for it, and a display device are provided. The display field comprises: a substrate (BP), a driver layer (CL), and a light-emitting layer (EE). The driver layer (CL) comprises a plurality of groups of pixel circuits (PDCA). The source-drain metal layer (SD) of the driver layer (CL) includes an auxiliary electrode (PA), and the auxiliary electrode (PA) is located on one side of a group of pixel circuits (PDCA). The light-emitting layer (EL) comprises a light-emitting element (LED) and an adapter structure (PAS). The second electrode (COM) of the light-emitting element covers at least a portion of the adapter structure (PAS) and is connected to the auxiliary electrode (PA).In one embodiment of the disclosure, the potential uniformity of the second electrode (COM) can be effectively improved by inserting the auxiliary electrode (PA); and since the light-emitting functional layer (EL) covers both the first electrode (An) and the adapter structure (PAS), the manufacturing process is simplified compared to the patterned light-emitting functional layer (EL).

Description

Technical field

[0001] The present disclosure relates to the field of display technology and in particular to a display field and a manufacturing process therefor as well as a display device. State of the art

[0002] With the rapid development of display panels, users are placing ever higher demands on the image display. The display panel comprises a multitude of light-emitting elements to achieve image display through light emission. Each light-emitting element consists of a first electrode, a light-emitting functional layer, and a second electrode, stacked sequentially. The second electrode is shared by multiple light-emitting elements. During the image display control process, the potential at the second electrode is uneven due to the influence of the voltage drop across it. This results in varying light brightness from the multiple light-emitting elements, leading to uneven brightness of the displayed image.

[0003] It should be noted that the information disclosed in the section entitled "Prior Art" is only intended to improve the understanding of the background of the present disclosure and may therefore contain information that is not part of the prior art known to the person skilled in the art. Disclosure of the invention

[0004] The present disclosure is based on the task of providing a display field, a manufacturing process for it and a display device.

[0005] According to a first aspect of the present disclosure, a display field is provided which includes: a substrate; a driver layer located on one side of the substrate and comprising a plurality of groups of pixel circuits arranged in a row direction, wherein the driver layer comprises a source-drain metal layer, the source-drain metal layer comprising auxiliary electrodes corresponding one-to-one to at least one group of pixel circuits, and one of the auxiliary electrodes being located on one side of a corresponding group of pixel circuits; a light-emitting layer located on a side of the driver layer facing away from the substrate, wherein the light-emitting layer comprises a light-emitting element and an adapter structure comprising those arranged at intervals, wherein there is an overlap region between the orthographic projections of the adapter structure and the auxiliary electrode on the substrate, wherein the light-emitting element is a first electrode, comprising a light-emitting functional layer and a second electrode arranged sequentially in a direction away from the substrate, the first electrode being connected to one of the pixel circuits, the light-emitting functional layer covering the first electrode and the adapter structure and forming a fracture step at at least one partial edge of the adapter structure, the second electrode covering the light-emitting functional layer and an exposed part of the adapter structure located at the fracture step of the light-emitting functional layer and being connected to the auxiliary electrode.

[0006] In the display field according to one of the present disclosures, the driver layer has an opening facing the light-emitting layer, wherein the orthographic projection of at least one partial edge of the adapter structure on the substrate is located within the orthographic projection of the opening on the substrate; wherein the auxiliary electrode comprises an exposed section at the opening, wherein the light-emitting functional layer comprises a cover section and a separation section, wherein the cover section and the separation section form a fracture step at at least one partial edge of the adapter structure, wherein the cover section covers the first electrode and the adapter structure, wherein the separation section is located within the opening, and at least one partial edge of the orthographic projection from the exposed section of the auxiliary electrode on the substrate extends beyond the orthographic projection of the separation section on the substrate; wherein the second electrode covers a side surface of the adapter structure and a part of the exposed section which part is not covered by the separating section, and wherein a part of the second electrode covering the light-emitting functional layer and a part of the second electrode covering the exposed section are continuous.

[0007] In the display field according to one of the present disclosures, the adapter structure has a bore, and the orthographic projection of at least a part of a bore edge of the adapter structure on the substrate is located within the orthographic projection of the opening on the substrate.

[0008] Display field according to one of the present disclosures, wherein the center line of the bore of the adapter structure coincides with the center line of the opening of the driver layer, and the bore dimension of the bore is smaller than the opening dimension of the opening.

[0009] Display field according to one of the present disclosures, wherein the length of the edge of the adapter structure extending into a corresponding area of ​​the opening is greater than or equal to 0.8 micrometers and less than or equal to 1.2 micrometers.

[0010] Display field according to one of the present disclosures, wherein the adapter structure comprises a first conductive layer, a metal layer and a second conductive layer arranged successively in the direction away from the substrate; wherein the orthographic projection of at least one partial margin of at least one structural layer of the first conductive layer, the metal layer and the second conductive layer on the substrate is within the orthographic projection of the aperture on the substrate, and there is no overlap area between the orthographic projections of the remaining structural layers on the substrate and the orthographic projection of the aperture on the substrate.

[0011] Display field according to one of the present disclosures, wherein the first conductive layer, the metal layer and the second conductive layer each have a bore; wherein the edges of the bores of the first conductive layer and the metal layer are flush with the opening wall of the opening, and the orthographic projection of at least part of a bore edge of the second conductive layer on the substrate is within the orthographic projection of the openings on the substrate.

[0012] Display field according to one of the present disclosures, wherein the adapter structure is connected to the auxiliary electrode through a through-hole.

[0013] Display field according to one of the present disclosures, wherein the adapter structure comprises a first conductive layer, a third conductive layer, a metal layer and a second conductive layer arranged successively in the direction away from the substrate; wherein the first conductive layer is connected to the auxiliary electrode by a through-hole; the third conductive layer is made of an inorganic material; the orthographic projection of the metal layer on the substrate is located within the orthographic projection of the third conductive layer on the substrate; and at least a partial margin of the second conductive layer extends out from the margin of the metal layer; wherein the light-emitting functional layer covers the first electrode, the second conductive layer and the third conductive layer, and the light-emitting functional layer forms a fracture step at the edge of the second conductive layer to expose at least a part of the third conductive layer and / or a side face of the metal layer; wherein the second electrode layer further covers a part of the third conductive layer that is not covered by the light-emitting functional layer and / or the side face of the metal layer.

[0014] Display field according to one of the present disclosures, wherein the edge of the orthographic projection of the metal layer on the substrate is located within the orthographic projection of the second conductive layer on the substrate.

[0015] Display field according to one of the present disclosures, wherein the source-drain metal layer comprises a plurality of power supply lines that correspond one-to-one to the plurality of groups of pixel circuits, wherein one of the power supply lines is connected to a corresponding group of pixel circuits and one of the power supply lines is located on a side of a corresponding group of pixel circuits facing away from the auxiliary electrode.

[0016] Display field according to one of the present disclosures, wherein the auxiliary electrode has an extension section on a side facing away from the corresponding power supply line, wherein there is an overlap area between the orthographic projections of the adapter structure and the extension section on the substrate, wherein the second electrode covers the adapter structure and is connected to the extension section.

[0017] Display field according to one of the present disclosures, wherein the pixel circuit comprises a first transistor, a second transistor, a third transistor and a storage capacitor; wherein the control electrode of the first transistor is connected to a first plate of the storage capacitor and the first electrode of the second transistor, wherein the first electrode of the first transistor is provided for charging a power supply signal, wherein the second electrode of the first transistor is connected to the second plate of the storage capacitor, the first electrode of the third transistor and to one of the first electrodes; wherein the control electrode of the second transistor is provided for loading a first sampling signal, and the second electrode of the second transistor is provided for loading a data signal; wherein the control electrode of the third transistor is provided for loading a second sampling signal, and the second electrode of the third transistor is provided for loading a sensor signal.

[0018] Display field according to one of the present disclosures, wherein the driver layer comprises: a masking layer located on one side of the substrate and comprising a masking sheet; a semiconductor layer located on a side of the masking layer facing away from the substrate and comprising active sections of the first transistor, the second transistor and the third transistor, wherein the active section is a channel region and comprises two connecting sections, which are located on both sides of the canal area; a gate metal layer located on a side of the semiconductor layer facing away from the substrate and comprising a first scanning line, a second scanning line and a second storage capacitor plate, wherein the first scanning line is provided for charging the first scanning signal at the control electrode of the second transistor and the second scanning line is provided for charging the second scanning signal at the control electrode of the third transistor; a source-drain metal layer located on a side of the gate metal layer facing away from the substrate, further comprising a power supply line, a data line, a sensor line and the first plate of the storage capacitor, wherein the power supply line is provided for charging the power supply signal at the first electrode of the first transistor, the data line is provided for charging the data signal at the second electrode of the second transistor, and the sensor line is provided for charging the sensor signal at the second electrode of the third transistor, wherein the first plate of the storage capacitor is directly opposite the masking sheet and is connected to it by a through-hole; a flat layer located on a side of the source-drain metal layer facing away from the substrate, covering at least the power supply line, the data line, the sensor line, the first plate of the storage capacitor and the auxiliary electrode.

[0019] Display field according to one of the present disclosures, wherein a group of pixel circuits comprises a plurality of circuit units arranged in a column direction, wherein one of the circuit units comprises four pixel circuits arranged in two rows and two columns, wherein for one of the circuit units: the power supply line and the auxiliary electrode each extend in the column direction and are arranged in the row direction, the power supply line being provided to charge power supply signals onto the first electrodes of the first transistors of four of the pixel circuits; four of the masking sheets are located between the power supply line and the auxiliary electrode, and the orthographic projections of the first plate and the second plate of each storage capacitor on the substrate are each located within the orthographic projection of the masking sheet of the same pixel circuit on the substrate; the first scanning line and the second scanning line extend in the row direction and are located between two of the masking sheets in the column direction, the first scanning line being provided to load first scanning signals onto the control electrodes of the second transistors of four of the pixel circuits, and the second scanning line being provided to load second scanning signals onto the control electrodes of the third transistors of four of the pixel circuits; the data lines extend in the column direction, with one data line provided on each side of the two masking sheets in the row direction, and four of the data lines are located between the power supply line and the auxiliary electrode, with one of the data lines being provided to load a data signal onto the second electrode of the second transistor of one of the pixel circuits; the sensor line extends in the column direction and is located between two of the masking sheets in the row direction, the sensor line being designed to load sensor signals onto the second electrodes of the third transistors of four of the pixel circuits.

[0020] According to a second aspect of the present disclosure, a method for manufacturing a display field is provided, the method comprising: Providing a substrate; Fabricating a driver layer on one side of the substrate, wherein the driver layer comprises a plurality of groups of pixel circuits arranged in a row direction, wherein the driver layer comprises a source-drain metal layer, wherein the source-drain metal layer comprises auxiliary electrodes that correspond one-to-one to at least one group of pixel circuits, and one of the auxiliary electrodes is located on one side of a corresponding group of pixel circuits; Producing a first electrode layer on a side of the driver layer facing away from the substrate, wherein the first electrode layer comprises first electrodes and an adapter structure spaced at intervals, one of the first electrodes being connected to one of the pixel circuits and there being an overlap area between the orthographic projections of the adapter structure and the auxiliary electrode on the substrate; Etching the adapter structure and the driver layer to form an opening in the driver layer facing the first electrode layer and exposing the auxiliary electrode, wherein the orthographic projection of at least one partial margin of the adapter structure on the substrate is within the orthographic projection of the opening on the substrate; Producing a light-emitting functional layer on a side of the first electrode layer facing away from the substrate, wherein the light-emitting functional layer comprises a cover section and a separation section, wherein the cover section covers the first electrode and the adapter structure, wherein the separation section is located within the opening, wherein the cover section and the separation section form a fracture step at at least one partial edge of the adapter structure, and wherein at least one partial edge of the orthographic projection from the exposed section of the auxiliary electrode on the substrate extends beyond the orthographic projection of the separation section on the substrate; Producing a second electrode layer on a side of the light-emitting functional layer facing away from the substrate, wherein the second electrode layer covers the light-emitting functional layer and a portion of the exposed section of the auxiliary electrode, which portion is not covered by the separation section.

[0021] According to a third aspect of the present disclosure, a method for manufacturing a display field is provided, the method comprising: Providing a substrate; Producing a driver layer on one side of the substrate, wherein the driver layer comprises a plurality of groups of pixel circuits arranged in a row direction, wherein the driver layer comprises a source-drain metal layer, wherein the source-drain metal layer comprises auxiliary electrodes that correspond one-to-one to at least one group of pixel circuits, and one of the auxiliary electrodes is located on one side of a corresponding group of pixel circuits; Fabricating a first electrode layer on a side of the driver layer facing away from the substrate, wherein the first electrode layer comprises first electrodes and an adapter structure spaced at intervals, wherein one of the first electrodes is connected to one of the pixel circuits, wherein the adapter structure comprises a first conductive layer, a third conductive layer, a metal layer and a second conductive layer arranged sequentially in the direction away from the substrate, wherein the third conductive layer is made of an inorganic material, wherein the orthographic projection of the metal layer on the substrate is within the orthographic projection of the third conductive layer on the substrate, and at least a partial border of the second conductive layer extends out of the border of the metal layer; Producing a light-emitting functional layer on a side of the first electrode layer facing away from the substrate, wherein the light-emitting functional layer covers the first electrode, the second conductive layer, the third conductive layer, and the light-emitting functional layer forms a fracture step at the edge of the second conductive layer to expose at least a part of the second conductive layer and / or a side face of the metal layer; Producing a second electrode layer on a side of the light-emitting functional layer facing away from the substrate, wherein the second electrode layer covers the light-emitting functional layer and a portion of the second conductive layer that is not covered by the light-emitting functional layer and / or a side face of the metal layer.

[0022] According to a fourth aspect of the present disclosure, a display device is provided which includes a display field as described above in the first aspect.

[0023] It is understood that the above general description and the following detailed description are merely exemplary and explanatory and should not limit the present disclosure. Brief description of the drawings

[0024] The accompanying drawings, which are included in the description and form part of it, show, by way of example, embodiments of the present disclosure. Together with the description, the drawings explain the principles of the present disclosure. Obviously, the drawings in the following description represent only some of the embodiments of the present disclosure, and the person skilled in the art can derive other drawings from the drawings described herein without inventive effort. Fig. Figure 1 shows a schematic sectional view of a display field provided by an embodiment of the present disclosure; Fig. Figure 2 shows a schematic sectional view of another display field provided by an embodiment of the present disclosure; Fig. Figure 3 shows a schematic representation of a layout of a driver layer provided by an embodiment of the present disclosure; Fig. Figure 4 shows a schematic representation of a layout of a source-drain metal layer provided by an embodiment of the present disclosure; Fig. Figure 5 shows a schematic representation of a layout of another driver layer provided by an embodiment of the present disclosure; Fig. Figure 6 shows a schematic representation of a pixel circuit provided by an embodiment of the present disclosure; Fig. Figure 7 shows a schematic representation of a layout of a masking layer provided by an embodiment of the present disclosure; Fig. Figure 8 shows a schematic representation of a layout of a semiconductor layer provided by an embodiment of the present disclosure; Fig. Figure 9 shows a schematic representation of a layout of a gate metal layer provided by an embodiment of the present disclosure; Fig. Figure 10 shows a schematic flowchart of a manufacturing process for a display field provided by an embodiment of the present disclosure; Fig. Figure 11 shows a schematic flowchart of another manufacturing process for a display field provided by an embodiment of the present disclosure. Detailed descriptions

[0025] For example, embodiments are now described in more detail with reference to the accompanying drawings. However, the embodiments can be implemented in a multitude of forms and should not be understood as being limited to those presented here. Rather, these embodiments are provided to make the present disclosure more comprehensive and complete, in order to convey the idea of ​​the exemplary embodiments to the person skilled in the art. Identical reference numerals in the drawings denote identical or similar structures, and their repeated description is omitted. Furthermore, the drawings are merely schematic representations of the present disclosure and are not necessarily drawn to scale.

[0026] Although relative terms such as "top" and "bottom" are used in the description to describe the relative relationship of one designated component to another, these terms serve only for convenience in the description, e.g., according to an example direction shown in the drawings. It is understood that if the depicted device is turned upside down, the described top component becomes a bottom component. When a structure is "on" another structure, this can mean that the structure is formed integrally on the other structure, or that the structure is arranged "directly" on the other structure, or that the structure is arranged "indirectly" via other structures on the other structure.

[0027] The expressions "a", "an", "this", "the", and "at least one" are used to indicate that there is one or more elements / components or the like; the expressions "comprise" and "have" are used to indicate an open meaning of "include" and mean that there may be further elements / components / etc. in addition to the listed elements / components / etc.; the expressions "first", "second", and "third", etc., are used only as markers and do not limit the number of objects.

[0028] A transistor refers to a device that has at least three terminals: a gate electrode, a drain electrode, and a source electrode. Between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), the transistor has a channel region, and current can flow through the drain electrode, the channel region, and the source electrode. In this description, the channel region refers to the area through which the current predominantly flows.

[0029] In the present disclosure, the first electrode can be the drain electrode and the second electrode can be the source electrode, or the first electrode can be the source electrode and the second electrode can be the drain electrode. The functions of the "source electrode" and the "drain electrode" can be interchanged if transistors of opposite polarity are used or if the current direction changes during circuit operation. Therefore, in this disclosure, "first electrode" and "second electrode" are interchangeable.

[0030] One embodiment of the present disclosure provides a display field. As in Fig. 1 or Fig. As shown in Figure 2, the display panel comprises a substrate BP, a driver layer CL, and a light-emitting layer EE, wherein the driver layer CL is located on one side of the substrate BP and the light-emitting layer EE is located on the opposite side of the driver layer CL from the substrate BP. The driver layer CL comprises a plurality of pixel circuits PDCA. The light-emitting layer EE comprises a plurality of light-emitting elements arranged in an array. The plurality of pixel circuits PDCA corresponds one-to-one to the plurality of light-emitting devices, and each light-emitting element is connected to a corresponding pixel circuit PDCA. In this way, the light emission of the corresponding light-emitting element can be controlled by driving the pixel circuit PDCA to realize the image display on the display panel.

[0031] The substrate BP can be an inorganic or an organic material. In some embodiments, the substrate BP material can be, for example, a glass material such as soda-lime glass, quartz glass, sapphire glass, or a metal material such as stainless steel, aluminum, nickel, or the like. In other embodiments, the substrate BP material can be polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyethersulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or a combination thereof.

[0032] Optionally, the substrate BP can consist of several material layers in addition to a single material layer. In some embodiments, the substrate BP comprises, for example, a base film layer, a pressure-sensitive adhesive layer, a first polyimide layer, and a second polyimide layer arranged sequentially on top of each other.

[0033] In one embodiment of the present disclosure, a pixel circuit PDCA can comprise a plurality of transistors and a storage capacitor CP.

[0034] The transistors can be thin-film transistors, which can be selected from a top-gate, bottom-gate, or double-gate type; and the storage capacitor CP can be a bipolar plate capacitor or a three-stage plate capacitor. The active layer material of the thin-film transistor can be an amorphous silicon semiconductor, a low-temperature polysilicon semiconductor, a metal oxide semiconductor, an organic semiconductor, or other types of semiconductor materials. The thin-film transistor can be an N-type or a P-type thin-film transistor.

[0035] It is understood that in a PDCA pixel circuit with a large number of transistors, the types of any two transistors can be the same or different. In some embodiments, for example, some of the transistors in a PDCA pixel circuit can be N-type transistors and some of the transistors can be P-type transistors. In other embodiments, the active layer material of some transistors in a PDCA pixel circuit can be, for example, a low-temperature polysilicon semiconductor material, and the active layer material of some transistors can be a metal oxide semiconductor material.

[0036] In one embodiment of the present disclosure, as in Fig. 1 or Fig. As shown in Figure 2, the driver layer CL comprises an insulating buffer layer BUF, a transistor layer, a dielectric intermediate layer ILD, a source-drain metal layer SD, and a flat layer PLN, arranged sequentially in a direction away from the substrate BP. The transistor layer comprises a semiconductor layer ACT, a gate insulating layer GI, and a gate metal layer Ga, stacked between the substrate BP and the dielectric intermediate layer ILD. The positional relationship between the individual film layers contained in the transistor layer can be determined based on the film layer structure of the thin-film transistor.

[0037] In some embodiments, the insulating buffer layer (BUF) material can be an inorganic insulating material such as silicon oxide, silicon nitride, etc. The insulating buffer layer (BUF) can be a single layer of inorganic material or multiple stacked layers of inorganic material. The semiconductor layer (ACT) can be used to form an active section of each transistor in the pixel circuit (PDCA), with each active section comprising a channel region and two interconnection sections (i.e., a source and a drain) located on either side of the channel region. The channel region can retain semiconductor properties, and the semiconductor materials corresponding to the two interconnection sections are partially or fully conductive.The gate metal layer Ga can be used to form gate metal layer wiring such as a scanning line, and can also be used to form a second plate CP2 of the storage capacitor CP. The source-drain metal layer SD can be used to form source-drain metal layer wiring such as a power supply line VDD, a data line DA, a sensor line SE, a connecting line, etc., and can also be used to form a first plate CP1 of the storage capacitor CP. A variety of first through-holes are provided in the flat layer PLN. The multiple pixel circuits PDCA, the multiple first through-holes, and the multiple light-emitting elements correspond one-to-one. A first electrode An of a light-emitting element is connected to a corresponding pixel circuit PDCA through a corresponding first through-hole.

[0038] In some embodiments, such as in Fig. 1 or Fig. As shown in Figure 2, the transistor layer comprises a semiconductor layer ACT, a gate insulating layer GI, and a gate metal layer Ga, stacked sequentially in one direction away from the substrate BP, and the thin-film transistor thus formed is a top-gate type thin-film transistor. In other embodiments, the transistor layer comprises a gate metal layer Ga, a gate insulating layer GI, and a semiconductor layer ACT, stacked sequentially in the direction away from the substrate BP, and the thin-film transistor thus formed is a bottom-gate type thin-film transistor.

[0039] In some embodiments, the semiconductor layer ACT can be a single semiconductor layer ACT or two semiconductor layers ACT. For example, the semiconductor layer ACT comprises a low-temperature polysilicon semiconductor layer ACT. The gate metal layer Ga can be a single gate metal layer Ga or two or three gate metal layers Ga. For example, the gate metal layer Ga comprises a single gate metal layer Ga.

[0040] It is understood that the gate insulating layer GI in the transistor layer can be adaptively increased or decreased if the gate metal layer Ga or the semiconductor layer ACT, etc., has a multilayer structure. In some embodiments, the transistor layer contained in the driver layer CL comprises, for example, a low-temperature polysilicon semiconductor layer, a gate insulating layer GI, and a gate metal layer Ga, which are stacked sequentially on the substrate BP.

[0041] In some embodiments, the source-drain metal layer SD can be a single source-drain metal layer SD, or two or three source-drain metal layers SD. For example, the source-drain metal layer SD contained in the driver layer CL comprises a single source-drain metal layer SD.

[0042] Optional, as in Fig. 1 or Fig. As shown in Figure 2, the driver layer CL also includes a passivation layer PVX, which is provided between the source-drain metal layer SD and the flat layer PLN to achieve protection of the source-drain metal layer SD by inserting the passivation layer PVX.

[0043] Optional, as in Fig. 1 or Fig. As shown in Figure 2, the driver layer CL further comprises a masking layer BSM, which is provided between the insulating buffer layer BUF and the substrate BP. The masking layer BSM can overlap with the channel region of at least some of the transistors to mask light radiated onto the transistor and thereby stabilize the electrical properties of the transistor.

[0044] In one embodiment of the present disclosure, the light-emitting element can be an organic electroluminescent diode, a micro light-emitting diode, a quantum dot organic electroluminescent diode, a quantum dot light-emitting diode, or other types of light-emitting elements.

[0045] In some embodiments, the display field is, for example, an OLED display field when the light-emitting element is an organic electroluminescent diode. A possible structure of the light-emitting element is described below using the example of an organic electroluminescent diode.

[0046] Optional, as in Fig. 1 or Fig. As shown in Figure 2, the light-emitting layer EE further comprises a pixel-defining layer PDL, which is provided on the side of the driver layer CL facing away from the substrate BP. The pixel-defining layer PDL is provided with pixel holes that correspond one-to-one to a plurality of light-emitting elements. The light-emitting element comprises a first electrode An, a light-emitting functional layer EL, and a second electrode COM, which are stacked sequentially in one direction away from the substrate BP. The first electrode An is connected to a pixel circuit PDCA via a through-hole. The first electrode An comprises an exposed area at the corresponding pixel hole and an area covered by the pixel-defining layer PDL. The exposed area of ​​the first electrode An forms a light-emitting area of ​​the corresponding light-emitting element.

[0047] The light-emitting functional layer EL can comprise an organic electroluminescent material layer and can include one or more of a hole injection layer, a hole transport layer, an electron barrier layer, a hole barrier layer, an electron transport layer and an electron injection layer.

[0048] In some embodiments, the display panel may also include a thin-film encapsulation layer. The thin-film encapsulation layer is provided on the side of the light-emitting layer EE facing away from the substrate BP and may comprise an inorganic encapsulation layer and an organic encapsulation layer arranged alternately. The inorganic encapsulation layer effectively blocks water and oxygen from the outside, thus preventing the penetration of water and oxygen into the organic, light-emitting functional layer EL and the associated material degradation. The organic encapsulation layer is positioned between two adjacent inorganic encapsulation layers to achieve a flattening effect and reduce stress between the inorganic encapsulation layers.

[0049] The display area comprises a display region and a peripheral region located at the periphery of the display region. The edge of the inorganic encapsulation layer may be located in the peripheral region, and the edge of the organic encapsulation layer may be located between the edge of the display region and the edge of the inorganic encapsulation layer. For example, the thin-film encapsulation layer comprises a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer stacked sequentially on a side of the light-emitting layer EE facing away from the substrate BP.

[0050] In some embodiments, the display field may also include a touch functional layer, wherein the touch functional layer is provided on the side of the thin-film encapsulation layer facing away from the substrate BP in order to enable touch operation of the display field.

[0051] In one embodiment of the present disclosure, as in Fig. 1 or Fig. As shown in Figure 2, the light-emitting element comprises a first electrode An, a light-emitting functional layer EL, and a second electrode COM, arranged sequentially in the direction away from the substrate BP. For a top-emitting light-emitting element, for example, with the second electrode COM acting as the cathode, the second electrode COM must be made of a material with high transmittance, low resistance, and low work function matching to ensure the light-emitting effect of the light-emitting element.

[0052] In the relevant technology, commonly used materials for the second electrode (COM) are IZO, Mg / Ag alloy, etc. Although these materials have good transmittance, their resistance is relatively high, which increases the voltage drop across the second electrode (COM). This means that the potential across the second electrode (COM) is uneven for multiple light-emitting elements. To ensure that the second electrode (COM) has good transmittance and a low voltage drop, an auxiliary electrode (PA) is typically fabricated simultaneously with the first electrode (An), spaced apart from it. The second electrode (COM) is then connected to the auxiliary electrode (PA). This increases the effective area of ​​the second electrode (COM), thereby reducing the voltage drop.

[0053] In one embodiment of the present disclosure, the driver layer CL comprises, as shown in Fig. 3 and Fig. Figure 4 shows a plurality of groups of PDCA pixel circuits arranged in a row direction. The driver layer CL comprises a source-drain metal layer SD. The source-drain metal layer SD includes auxiliary electrodes PA that correspond one-to-one to at least one group of PDCA pixel circuits, and one of the auxiliary electrodes PA is located on one side of a corresponding group of pixel circuits. As shown in Fig. 1 or Fig. As shown in Figure 2, the light-emitting layer EE comprises a light-emitting element and an adapter structure PAS, which are spaced apart. There is an overlap region between the orthographic projections of the adapter structure PAS and the auxiliary electrode PA on the substrate BP. The light-emitting functional layer EL of the light-emitting element covers both the first electrode An and the adapter structure PAS and forms a fracture edge at at least one partial margin of the adapter structure PAS. The second electrode COM of the light-emitting element covers both the light-emitting functional layer EL and an exposed portion of the adapter structure PAS located at the fracture edge of the light-emitting functional layer EL and is connected to the auxiliary electrode PA.

[0054] In this way, by inserting the auxiliary electrode PA into the source-drain metal layer SD and connecting the second electrode COM to the auxiliary electrode PA, the voltage drop across the second electrode COM can be effectively reduced. This effectively improves the potential uniformity across the second electrode COM of the multiple light-emitting elements and thus ensures uniform brightness when an image is displayed on the screen. Furthermore, the auxiliary electrode PA, positioned within the source-drain metal layer SD, can be designed to extend along the column direction, effectively increasing the area of ​​the orthographic projection of the auxiliary electrode PA onto the substrate BP, thereby further reducing the voltage drop across the second electrode COM.Furthermore, the use of the PAS adapter structure avoids the problem of the second electrode COM being fractured at the periphery of the light-emitting element. Similarly, when the light-emitting element is subsequently encapsulated by the encapsulation layer, the problem of the organic film layer contained within the encapsulation layer being fractured at the periphery of the light-emitting element is also avoided. Regarding the manufacturing process, it is simplified compared to the patterned light-emitting functional layer EL, as the EL can cover both the first electrode An and the PAS adapter structure.

[0055] In the case of multiple groups of PDCA pixel circuits, each group of PDCA pixel circuits in a subgroup of PDCA pixel circuits can have a corresponding auxiliary electrode PA, or each group of PDCA pixel circuits in multiple groups of PDCA pixel circuits can have a corresponding auxiliary electrode PA, and the embodiment of the present disclosure does not restrict this.

[0056] In one embodiment, as in Fig. As shown in Figure 1, the driver layer CL has an opening CL1 facing the light-emitting layer EE. The orthographic projection of at least one partial margin of the adapter structure PAS on the substrate BP lies within the orthographic projection of the opening CL1 on the substrate BP. The auxiliary electrode PA includes an exposed section PA1 at the opening CL1. The light-emitting functional layer EL comprises a cover section and a separation section. The cover section and the separation section form a break step at at least one partial margin of the adapter structure PAS. The cover section covers the first electrode An and the adapter structure PAS. The separation section lies within the opening CL1, and at least one partial margin of the orthographic projection of the exposed section PA1 of the auxiliary electrode PA on the substrate BP extends beyond the orthographic projection of the separation section on the substrate BP.The second electrode COM covers one side surface of the adapter structure PAS and a portion of the exposed section PA1 that is not covered by the separating section. Furthermore, the portion of the second electrode COM covering the light-emitting functional layer EL and the portion covering the exposed section PA1 are continuous.

[0057] In this way, the second electrode COM covers part of the exposed section PA1 of the auxiliary electrode PA, thus establishing a connection between the second electrode COM and the auxiliary electrode PA. For the adapter structure PAS, it is only necessary to ensure that the orthographic projection of at least one partial edge of the adapter structure PAS on the substrate BP lies within the orthographic projection of the aperture CL1 on the substrate BP. This prevents the adapter structure PAS from being too thick and reduces the possibility of bulges occurring during its fabrication. Furthermore, when etching to obtain the first electrodes of several light-emitting elements, the etching process can be performed simultaneously to create the adapter structure PAS, eliminating the need to fabricate the adapter structure PAS separately and simplifying the manufacturing process.

[0058] During the fabrication of the light-emitting layer EE, and in the event that the driver layer CL has an aperture CL1 and the orthographic projection of at least one partial edge of the adapter structure PAS on the substrate BP is located within the orthographic projection of the aperture CL1 on the substrate BP, the light-emitting functional layer EL can form a fracture step at at least one partial edge of the adapter structure PAS during the fabrication of the light-emitting functional layer EL, i.e.There is a break point between the aforementioned cover section and spacer section to ensure that, after the formation of the light-emitting functional layer EL, a portion of the exposed section PA1 of the auxiliary electrode PA remains uncovered by the light-emitting functional layer EL, thus ensuring that during the further production of the second electrode COM, the second electrode COM covers a portion of the exposed section PA1 of the auxiliary electrode PA that is not covered by the light-emitting functional layer EL, thereby establishing the connection between the second electrode COM and the auxiliary electrode PA.

[0059] The edge of the adapter structure PAS comprises at least one outer circumferential edge, which can be determined in particular based on the shape of the adapter structure PAS. For example, the adapter structure PAS has a notch or a bore PAS1. The edge of the adapter structure PAS then comprises an outer circumferential edge and a notch edge or a bore edge. For the outer circumferential edge of the adapter structure PAS, the orthographic projection of a portion of the outer circumferential edge onto the substrate BP must lie within the orthographic projection of the opening CL1 on the substrate BP.For the notch edge and the bore edge of the adapter structure PAS, taking the bore edge as an example, the orthographic projection of part of the bore edge of the adapter structure PAS on the substrate BP may lie within the orthographic projection of the opening CL1 on the substrate BP, or the orthographic projection of the entire bore edge on the substrate BP may lie within the orthographic projection of the opening CL1 on the substrate BP, as long as the support of the adapter structure PAS by the flat layer PLN can be ensured. The embodiments of the present disclosure do not restrict this.

[0060] Next, let's consider the example of the bore rim of the adapter structure PAS. If the orthographic projection of the entire bore rim of the adapter structure PAS on the substrate BP lies within the orthographic projection of the opening CL1 on the substrate BP, the probability that the light-emitting functional layer EL forms a fracture step at the bore rim of the adapter structure PAS can be increased, and it can be ensured that the exposed section PA1 of the auxiliary electrode PA is not completely covered by the light-emitting functional layer EL.

[0061] Taking the PAS adapter structure with a PAS1 bore as an example, as in Fig. As shown in Figure 1, the centerline of the PAS1 bore of the PAS adapter structure coincides with the centerline of the CL1 aperture of the CL driver layer, and the bore dimension of PAS1 is smaller than the aperture dimension of CL1. That is, the orthographic projection of the entire bore rim of the PAS adapter structure onto the BP substrate lies within the orthographic projection of the CL1 aperture onto the BP substrate.

[0062] In conjunction with the foregoing, the driver layer CL comprises a flat layer PLN located on the side of the source-drain metal layer SD facing away from the substrate BP. The flat layer PLN has openings CL1 to expose a portion of the auxiliary electrode PA. The flat layer PLN may have a single opening CL1 to expose the auxiliary electrode PA, or it may have multiple openings CL1 to expose the auxiliary electrode PA. In this way, the second electrode COM is connected to the auxiliary electrode PA at multiple points to ensure the stability of the connection.

[0063] The opening CL1 in the flat layer PLN can be obtained by etching according to the position of the adapter structure PAS after the adapter structure PAS has been formed, to ensure that the orthographic projection of a partial edge of the adapter structure PAS on the substrate BP is within the orthographic projection of the opening CL1 on the substrate BP.

[0064] If the opening CL1 is provided in the flat layer PLN to ensure that the light-emitting functional layer EL can form a break step at the edge of the adapter structure PAS and that the light-emitting functional layer EL cannot completely cover the exposed section PA1 of the auxiliary electrode PA, then the length of the edge of the adapter structure PAS extending into a corresponding area of ​​the opening CL1 is greater than or equal to 0.8 micrometers and less than or equal to 1.2 micrometers. That is, the radial dimension of the overlap area of ​​the orthographic projections of the openings CL1 onto the substrate BP is greater than or equal to 0.8 micrometers and less than or equal to 1.2 micrometers, which is the opening located in the adapter structure PAS and the driver layer CL.

[0065] In one embodiment of the present disclosure, the adapter structure PAS can be a single-layer structure or a multi-layer structure. If the adapter structure PAS is a single-layer structure, the material of the adapter structure PAS can be ITO or another conductive material. If the adapter structure PAS is a multi-layer structure, the adapter structure PAS comprises, for example, as shown in Fig. Figure 1 shows a first conductive layer PASa, a metal layer PASb and a second conductive layer PASc, arranged successively in the direction away from the substrate BP.

[0066] The orthographic projection of at least one partial edge of at least one structural layer of the first conductive layer PASa, the metal layer PASb, and the second conductive layer PASc on the substrate BP lies within the orthographic projection of the aperture CL1 on the substrate BP, and there is no overlap region between the orthographic projections of the remaining structural layers on the substrate BP and the orthographic projection of the aperture CL1 on the substrate BP. In this way, it can be ensured during the subsequent fabrication of the light-emitting functional layer EL that the EL forms a fracture step at this at least one partial edge.

[0067] The edge for each structural layer can be an outer circumferential edge, as described above, or a notched edge or a bore edge of the PAS adapter structure, as described above. As in Fig. As shown in Figure 1, the first conductive layer PASa, the metal layer PASb, and the second conductive layer PASc each have a bore PAS1. The bore edge of the first conductive layer PASa and the metal layer PASb is flush with the opening wall of the opening CL1. The orthographic projection of at least part of a bore edge of the second conductive layer PASc on the substrate BP lies within the orthographic projection of the openings CL1 on the substrate BP.

[0068] The material of the first conductive layer can be PASa, and the material of the second conductive layer PASc can be ITO or similar. The material of the metal layer PASb can be Al, Al alloy, Ag, or similar. The thickness of the metal layer PASb is greater than or equal to 30 nm and less than or equal to 150 nm, and the thickness of the second conductive layer PASc is greater than or equal to 10 nm and less than or equal to 140 nm.

[0069] In another embodiment, as in Fig. As shown in Figure 2, the adapter structure PAS is connected to the auxiliary electrode PA via a through-hole. This ensures that the second electrode COM connects to the auxiliary electrode PA, provided that the second electrode COM covers at least part of the adapter structure PAS.

[0070] To ensure that the second electrode COM covers at least part of the adapter structure PAS in this case, the adapter structure PAS, in some embodiments, comprises a first conductive layer PASa, a metal layer PASb, and a second conductive layer PASc, arranged sequentially in the direction away from the substrate BP. The first conductive layer PASa is connected to the auxiliary electrode PA through a through-hole. The orthographic projection of the metal layer PASb onto the substrate BP lies within the orthographic projection of the first conductive layer PASa onto the substrate BP, and at least a partial margin of the second conductive layer PASc extends from the margin of the metal layer PASb. In this way, the first conductive layer PASa, the metal layer PASb, and the second conductive layer PASc form a "-shaped structure".

[0071] The light-emitting functional layer EL covers the first electrode An, the second conductive layer PASc and the first conductive layer PASa, and the light-emitting functional layer EL forms a fracture step under the influence of the “ The "-shaped adapter structure PAS, i.e., the light-emitting functional layer EL, forms a fracture at the edge of the second conductive layer PASc to expose at least a portion of the first conductive layer PASa and / or a side face of the metal layer PASb. The second electrode COM covers not only the light-emitting functional layer EL but also a portion of the first conductive layer PASa that is not covered by the light-emitting functional layer EL, and / or the side face of the metal layer. In this way, at least a portion of the adapter structure PAS is covered by the second electrode COM.

[0072] In other embodiments, such as in Fig. As shown in Figure 2, the adapter structure PAS comprises a first conductive layer PASa, a third conductive layer PASd, a metal layer PASb, and a second conductive layer PASc, arranged sequentially in a direction opposite to the substrate BP. The first conductive layer PASa is connected to the auxiliary electrode PA via a through-hole. The third conductive layer PASd consists of inorganic material. The orthographic projection of the metal layer PASb onto the substrate BP lies within the orthographic projection of the third conductive layer PASd onto the substrate BP, and at least a partial margin of the second conductive layer PASc extends beyond the margin of the metal layer PASb. In this way, the third conductive layer PASd, the metal layer PASb, and the second conductive layer PASc form a "-shaped structure".

[0073] Continue as in Fig. As shown in Figure 2, the light-emitting functional layer EL covers the first electrode An, the second conductive layer PASc, and the third conductive layer PASd, and the light-emitting functional layer EL forms a fracture step under the influence of the “ The "-shaped adapter structure PAS, i.e., the light-emitting functional layer EL, forms a fracture at the edge of the second conductive layer PASc to expose at least a portion of the third conductive layer PASd and / or the side face of the metal layer. The second electrode COM covers not only the light-emitting functional layer EL but also a portion of the third conductive layer PASa that is not covered by the light-emitting functional layer EL, and / or the side face of the metal layer. In this way, at least a portion of the adapter structure PAS is covered by the second electrode COM.

[0074] In both of the above embodiments, it is possible that a partial edge of the second conductive layer PASc extends beyond the edge of the metal layer PASb, or that the entire edge of the second conductive layer PASc extends beyond the edge of the metal layer PASb. That is, the edge of the orthographic projection of the metal layer PASb on the substrate BP lies within the orthographic projection of the second conductive layer PASc on the substrate BP.If the edge of the orthographic projection of the metal layer PASb on the substrate BP is located within the orthographic projection of the second conductive layer PASc on the substrate BP, the probability that the light-emitting functional layer EL forms a fracture step at the edge of the second conductive layer PASc can be increased, and it can be ensured that the first conductive layer PASa or the third conductive layer PASd is not completely covered by the light-emitting functional layer EL.

[0075] For the PAS adapter structure, which comprises the first conductive layer PASa, the metal layer PASb, and the second conductive layer PASc, the patterned first conductive layer PASa is produced first to facilitate the capture of the pre-made film layer structure. After completion of the capture, the entire metal layer PASb and the entire second conductive layer PASc are first produced and then etched to create the “ to obtain a "-shaped adapter structure PAS. Since the metal layer PASb is in direct contact with the flat layer PLN (organic material layer) during the production of the entire metal layer PASb, the metal layer PASb tends to bulge in this case, i.e. the manufactured adapter structure PAS tends to bulge.

[0076] For the adapter structure PAS, which comprises the first conductive layer PASa, the third conductive layer PASd, the metal layer PASb and the second conductive layer PASc, the third conductive layer PASd, the metal layer PASb and the second conductive layer PASc can be produced simultaneously after receiving the patterned first conductive layer PASa, and then the third conductive layer PASd, the metal layer PASb and the second conductive layer PASc can be etched to create the “ to obtain a "-shaped adapter structure PAS. Since the entire third conductive layer PASd is produced first, and the third conductive layer PASd is a layer of inorganic material, contact between the metal layer PASb and the flat layer PLN (layer of organic material) is avoided, thus preventing the phenomenon of bulging of the metal layer PASb, i.e., the phenomenon of bulging of the adapter structure PAS.

[0077] In one embodiment of the present disclosure, the source-drain metal layer SD comprises, as shown in Fig. 3 and Fig. Figure 4 shows a plurality of power supply lines VDD that correspond one-to-one to the plurality of groups of pixel circuits PDCA. One of the power supply lines VDD is connected to a corresponding group of pixel circuits PDCA, and one of the power supply lines VDD is located on a side of the corresponding group of pixel circuits PDCA facing away from the auxiliary electrode PA.

[0078] In this way, in a group of PDCA pixel circuits, the power supply line VDD and the auxiliary electrode PA are arranged on both sides in the line direction to increase the distance between the power supply line VDD and the auxiliary electrode PA, thus avoiding the problem of mutual interference. To avoid a small distance between the power supply line VDD and the auxiliary electrode PA in multiple groups of PDCA pixel circuits, the wiring area between two adjacent groups of PDCA pixel circuits includes either the power supply lines VDD or the auxiliary electrode PA. As shown in Fig. As shown in Figure 5, the wiring area between two adjacent groups of PDCA pixel circuits includes, for example, only the auxiliary electrode PA; or the wiring area between two adjacent groups of PDCA pixel circuits includes both the power supply line VDD and the auxiliary electrode PA, and the distance between the power supply line VDD and the auxiliary electrode PA in the line direction is greater than the reference distance. In this way, the disturbance of the power supply line VDD corresponding to one group of PDCA pixel circuits can be reduced to the auxiliary electrode PA corresponding to the adjacent group of PDCA pixel circuits, thus ensuring the effectiveness of the auxiliary electrode PA (i.e., it can effectively reduce the voltage drop across the second electrode COM).In the event that the wiring area includes both the power supply line VDD and the auxiliary electrode PA, the distance between the power supply line VDD and the auxiliary electrode PA in the line direction can be determined on the basis of specific tests, and the embodiment of the present disclosure does not restrict this.

[0079] In this way, as in Fig. 3 or Fig. As shown in Figure 4, the auxiliary electrode PA has an extension section PA1 on the side facing away from the corresponding power supply line VDD. There is an overlap area between the orthographic projections of the adapter structure PAS and the extension section PA1 on the substrate BP. The second electrode COM covers at least part of the adapter structure and is connected to the extension section PA1. The number of extension sections PA1 can be one or more. As shown in Fig. 3 or Fig. As shown in Figure 4, the auxiliary electrode PA, for example, has four extension sections PA1. The second electrode COM is connected to the four extension sections PA1 to ensure the stability of the connection between the second electrode COM and the auxiliary electrode PA.

[0080] In one embodiment of the present disclosure, the pixel circuit PDCA can be a circuit such as 3T1C, 4T1C, etc., as long as it can drive the light-emitting element to emit light. The structure of the driver layer CL is explained in detail below using the 3T1C as an example.

[0081] As in Fig. As shown in Figure 6, the PDCA pixel circuit comprises a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor CP. The control electrode of the first transistor T1 is connected to the first plate CP1 of the storage capacitor CP and to the first electrode of the second transistor T2. The first electrode of the first transistor T1 is used to load a power supply signal. The second electrode of the first transistor T1 is connected to the second plate CP2 of the storage capacitor CP, the first electrode of the third transistor T3, and to one of the first electrodes An. The control electrode of the second transistor T2 is used to load a first sampling signal, and the second electrode of the second transistor T2 is used to load a data signal. The control electrode of the third transistor T3 is used to load a second sampling signal.The second electrode of the third transistor T3 is intended for charging a sensor signal.

[0082] As in Fig. 1 or Fig. As shown in Figure 2, the driver layer CL comprises a masking layer BSM, an insulating buffer layer BUF, a semiconductor layer ACT, a gate insulating layer GI, a gate metal layer Ga, a dielectric intermediate layer ILD, a source-drain metal layer SD, and a flat layer PLN.

[0083] As in Fig. 1 or Fig. 2 and Fig. 4, Fig. 7, Fig. 8 and Fig. As shown in Figure 9, the masking layer BSM is located on one side of the substrate BP and comprises a masking sheet BSM1. The semiconductor layer ACT is located on the opposite side of the masking layer BSM from the substrate BP and comprises an active section of the first transistor T1, the second transistor T2, and the third transistor T3. The active section comprises a channel region and two interconnect sections located on either side of the channel region. The gate metal layer Ga is located on the opposite side of the semiconductor layer ACT from the substrate BP and comprises a first sampling line G1, a second sampling line G2, and a second plate CP2 of the storage capacitor CP. The first sampling line G1 is used to load the first sampling signal at the control electrode of the second transistor T2, and the second sampling line G2 is used to load the second sampling signal at the control electrode of the third transistor T3.The source-drain metal layer SD is located on the side of the gate metal layer Ga facing away from the substrate BP and includes a power supply line VDD, a data line DA, a sensor line SE, and the first plate CP1 of the storage capacitor CP. The power supply line VDD is for charging the power supply signal to the first electrode of the first transistor T1. The data line DA is for charging the data signal to the second electrode of the second transistor T2. The sensor line SE is for charging the sensor signal to the second electrode of the third transistor T3. The first plate CP1 of the storage capacitor CP is directly opposite the masking sheet BSM1 and is connected to it by a through-hole.The flat layer PLN is located on a side of the source-drain metal layer SD facing away from the substrate BP and covers at least the power supply line VDD, the data line DA, the sensor line SE, the first plate CP1 of the storage capacitor CP and the auxiliary electrode PA.

[0084] A group of pixel circuits PDCA comprises several circuit units PDCC arranged in a column direction. One of the unit circuits comprises four pixel circuits PDCA arranged in two rows and two columns. For one of the circuit units PDCC: as in Fig. 3 and Fig. As shown in Figure 4, the power supply line VDD and the auxiliary electrode PA each extend in the column direction and are arranged in the row direction, with the power supply line VDD being provided to charge power supply signals onto the first electrodes of the first transistors T1 of four of the pixel circuits PDCC; as shown in Fig. 3 and Fig. As shown in Figure 7, four masking sheets BSM1 are located between the power supply line VDD and the auxiliary electrode PA; and as shown in Fig. 3, Fig. 8 and Fig. As shown in Figure 9, the orthographic projections of the first plate CP1 and the second plate CP2 of the storage capacitor CP of each pixel circuit PDCA on the substrate BP are each located within the orthographic projection of the masking sheet BSM1 of the same pixel circuit PDCA on the substrate BP; as shown in Fig. 3 and Fig. As shown in Figure 9, the first sampling line G1 and the second sampling line G2 extend in the row direction and are located between two masking sheets BSM1 in the column direction, the first sampling line G1 being intended to load first sampling signals onto the control electrodes of the second transistors T2 of the four pixel circuits PDCA, and the second sampling line G2 being intended to load second sampling signals onto the control electrodes of the third transistors T3 of the four pixel circuits PDCA; as shown in Fig. 3 and Fig. As shown in Figure 4, the data line DA extends in the column direction, with one data line DA provided on each side of the two masking sheets BSM1 in the row direction, and four data lines DA are located between the power supply line VDD and the auxiliary electrode PA, with one data line DA being provided to load a data signal onto the second electrode of the second transistor T2 of a pixel circuit PDCA; as shown in Fig. 3 and Fig. As shown in Figure 4, the sensor line SE extends in the column direction and is located between two masking sheets BSM1 in the row direction, with the sensor line SE being intended to load sensor signals onto the second electrodes of the third transistors T3 of four pixel circuits PDCA.

[0085] As in Fig. As shown in Figure 7, the masking layer BSM also includes a connecting sheet BSM2. As shown in Fig. As shown in Figure 9, the gate metal layer Ga further comprises a first horizontal segment L1 and a second horizontal segment L2, as well as a first vertical segment Y1 and a second vertical segment Y2. As shown in Fig. As shown in Figure 4, the source-drain metal layer SD further comprises a variety of connecting lines.

[0086] As in Fig. 3, Fig. 4, Fig. 7 and Fig. As shown in Figure 9, there is an overlap between the central part of the connecting sheet BSM2 and the sensor lead SE of the source-drain metal layer SD, and they are connected by a through-hole. The first horizontal segment L1 is connected to the first vertical segment Y1. There is an overlap between the first vertical segment Y1 and the power supply lead VDD of the source-drain metal layer SD, and they are connected by a through-hole. The second horizontal segment L2 is connected to the first scanning lead G1 via a connecting lead LA. There is an overlap between the second vertical segment Y2 and the auxiliary electrode PA of the source-drain metal layer SD, and they are connected by a through-hole. The second scanning lead G2 comprises a scanning lead body G21 and a scanning lead branch G22, which extend in the line direction.The scanning line branch G22 is located on a side of the scanning line body G21 that differs from the first scanning line G1, and at least one end of the scanning line branch G22 is connected to the scanning line body G21.

[0087] Furthermore, the number of the first horizontal segment L1 and the first vertical segment Y1 is at least two, and the number of the second vertical segment Y2 can be one or more.

[0088] For a pixel circuit PDCA, as in Fig. 3 and Fig. As shown in Figure 8, there is an overlap region between the orthographic projections of the channel region of the first transistor T1 and the second plate CP2 of the storage capacitor CP on the substrate BP. One connection section of the first transistor T1 is connected to the first plate CP1 of the storage capacitor CP via a through-hole, and another connection section of the first transistor T1 is connected to the first horizontal segment L1 via a connecting line LB. There is also an overlap region between the orthographic projections of the channel region of the second transistor T2 and the second horizontal segment L2 on the substrate BP. One connection section of the second transistor T2 is connected to the data line DA via a connecting line LC, and another connection section of the second transistor T2 is connected to the second plate CP2 of the storage capacitor CP via a connecting line LD.There is an overlap area between the orthographic projections of the channel region of the third transistor T3 and the scanning line body G21 or the scanning line branch G22 of the second scanning line G2 on the substrate BP. One connecting section of the third transistor T3 is connected to the first plate CP1 of the storage capacitor CP via a connecting line LE, and another connecting section of the third transistor T3 is connected to one end of the connecting sheet BSM2 via a connecting line LF.

[0089] For two pixel circuits PDCA in column direction in one circuit unit PDCC, as in Fig. 3 and Fig. As shown in Figure 8, the more active sections of the third transistors T3 of these two PDCA pixel circuits have an integral structure; that is, the two third transistors T3 share a connection section, and this common connection section is used to connect to one end of the BSM2 interconnect. With two PDCA pixel circuits in a row, a connection section of the first transistors T1 of these two PDCA pixel circuits is connected to the same first horizontal segment L1.

[0090] In one embodiment of the present disclosure, a method for manufacturing a display field is also provided. The method is used to manufacture a display field in one embodiment of the embodiments described above. As in Fig. As shown in Figure 10, the procedure comprises steps S110 to S160 as follows.

[0091] Step S110: Providing a substrate.

[0092] Step S1120: Fabricating a driver layer on one side of the substrate, wherein the driver layer comprises a plurality of groups of pixel circuits arranged in a row direction, wherein the driver layer comprises a source-drain metal layer, wherein the source-drain metal layer comprises auxiliary electrodes that correspond one-to-one to at least one group of pixel circuits, and one of the auxiliary electrodes is located on one side of a corresponding group of pixel circuits.

[0093] Step S130: Fabricating a first electrode layer on a side of the driver layer facing away from the substrate, wherein the first electrode layer comprises first electrodes and an adapter structure spaced at intervals, one of the first electrodes being connected to one of the pixel circuits and there being an overlap area between the orthographic projections of the adapter structure and the auxiliary electrode on the substrate.

[0094] Step S140: Etching the adapter structure and the driver layer to form an opening in the driver layer facing the first electrode layer and exposing the auxiliary electrode, wherein the orthographic projection of at least one partial margin of the adapter structure on the substrate is within the orthographic projection of the opening on the substrate.

[0095] Step S150: Forming a light-emitting functional layer on a side of the first electrode layer facing away from the substrate, wherein the light-emitting functional layer comprises a cover section and a separation section, wherein the cover section covers the first electrode and the adapter structure, wherein the separation section is located within the opening, wherein the cover section and the separation section form a break step at at least one partial edge of the adapter structure, and wherein at least one partial edge of the orthographic projection from the exposed section of the auxiliary electrode on the substrate extends beyond the orthographic projection of the separation section on the substrate.

[0096] Step S160: Producing a second electrode layer on a side of the light-emitting functional layer facing away from the substrate, wherein the second electrode layer covers the light-emitting functional layer and part of the exposed section of the auxiliary electrode, which part is not covered by the separation section.

[0097] Taking the adapter structure with the first conductive layer, the metal layer, and the second conductive layer as an example, the etching described above, which is carried out on the adapter structure and the driver layer, includes in particular: forming the first conductive layer, the metal layer, and the second conductive layer successively on the side of the driver layer facing away from the substrate; etching the first conductive layer, the metal layer, and the second conductive layer such that at least a partial edge of the second conductive layer extends from the edge of the metal layer and the edge of the metal layer is at least flush with the edge of the first conductive layer; etching the driver layer such that the driver layer has an opening facing the first electrode layer and the edge of the first conductive layer is flush with the wall of the opening.In this way, it can be ensured that the orthographic projection of at least one partial edge of the adapter structure on the substrate is located within the orthographic projection of the opening on the substrate.

[0098] In one embodiment of the present disclosure, the second electrode covers part of the exposed section of the auxiliary electrode to establish the connection between the second and auxiliary electrodes, thereby effectively reducing the voltage drop across the second electrode. This effectively improves the potential uniformity across the second electrode of the multiple light-emitting elements and ensures uniformity of brightness when an image is displayed on the screen. Furthermore, the auxiliary electrode provided in the source-drain metal layer can be designed to extend in the slit direction to effectively increase the area of ​​the orthographic projection of the auxiliary electrode onto the substrate, thereby further reducing the voltage drop across the second electrode.Furthermore, with the PAS adapter structure, it only needs to be ensured that the orthographic projection of at least one partial edge of the adapter structure on the substrate lies within the orthographic projection of the opening on the substrate. This prevents the adapter structure from being too thick and thus reduces the possibility of bulges occurring during its fabrication. Additionally, when etching to obtain the first electrodes of multiple light-emitting elements, the etching process can be performed simultaneously to create the adapter structure, eliminating the need to fabricate the adapter structure separately and simplifying the manufacturing process.

[0099] In one embodiment of the present disclosure, a further method for manufacturing a display field is also provided. This method is used to manufacture a display field in another embodiment of the embodiments described above. As in Fig. As shown in Figure 11, the procedure comprises steps S210 to S260 as follows.

[0100] Step S210: Providing a substrate.

[0101] Step S2220: Fabricating a driver layer on one side of the substrate, wherein the driver layer comprises a plurality of groups of pixel circuits arranged in a row direction, wherein the driver layer comprises a source-drain metal layer, wherein the source-drain metal layer comprises auxiliary electrodes that correspond one-to-one to at least one group of pixel circuits, and one of the auxiliary electrodes is located on one side of a corresponding group of pixel circuits.

[0102] Step S230: Fabricating a first electrode layer on a side of the driver layer facing away from the substrate, wherein the first electrode layer comprises first electrodes and an adapter structure spaced at intervals, wherein one of the first electrodes is connected to one of the pixel circuits, wherein the adapter structure comprises a first conductive layer, a third conductive layer, a metal layer and a second conductive layer arranged sequentially in the direction away from the substrate, wherein the third conductive layer is made of an inorganic material, wherein the orthographic projection of the metal layer on the substrate is within the orthographic projection of the third conductive layer on the substrate, and at least a partial border of the second conductive layer extends out of the border of the metal layer.

[0103] Step S240: Forming a light-emitting functional layer on a side of the first electrode layer facing away from the substrate, wherein the light-emitting functional layer covers the first electrode, the second conductive layer, the third conductive layer, and the light-emitting functional layer forms a fracture step at the edge of the second conductive layer to expose at least part of the second conductive layer and / or a side face of the metal layer.

[0104] Step S250: Producing a second electrode layer on a side of the light-emitting functional layer facing away from the substrate, wherein the second electrode layer covers the light-emitting functional layer and a portion of the second conductive layer not covered by the light-emitting functional layer and / or a side face of the metal layer.

[0105] Taking as an example the adapter structure with a first conductive layer, a third conductive layer, a metal layer, and a second conductive layer, the insertion of the adapter structure on a side of the driver layer facing away from the substrate includes, in particular: forming a patterned first conductive layer on the driver layer, wherein the first conductive layer is connected to the auxiliary electrode by a through-hole; forming the third conductive layer, the metal layer, and the second conductive layer successively on a side of the first conductive layer facing away from the substrate; etching the third conductive layer, the metal layer, and the second conductive layer to form a to form a "-shaped adapter structure (the orthographic projection of the metal layer on the substrate is located within the orthographic projection of the third conductive layer on the substrate, and at least a partial margin of the second conductive layer extends beyond the margin of the metal layer).

[0106] In one embodiment of the present disclosure, the adapter structure is connected to the auxiliary electrode via a through-hole, and the second electrode covers part of the adapter structure to establish the connection between the second electrode and the auxiliary electrode. This effectively reduces the voltage drop across the second electrode, thereby improving the potential uniformity of the multiple light-emitting elements at the second electrode and ensuring uniformity of brightness when an image is displayed on the screen. Furthermore, the auxiliary electrode provided in the source-drain metal layer can be designed to extend in the gap direction to effectively increase the area of ​​the orthographic projection of the auxiliary electrode onto the substrate, further reducing the voltage drop across the second electrode.Furthermore, the third conductive layer can be used for the adapter structure to insulate the contact between the metal layer and the flat layer (layer of organic material), thereby avoiding the phenomenon of bulging of the metal layer, i.e., the phenomenon of bulging of the adapter structure, and improving the yield of the display field.

[0107] It is noted that, although the various steps of the procedure for manufacturing the display field of the present disclosure are in a specific order in Fig. 10 and Fig.Figure 11 does not require or imply that the steps must be performed in this specific order, or that all of the steps shown must be performed to achieve the desired result. Additionally or alternatively, certain steps can be omitted, several steps can be combined to be performed as a single step, and / or a single step can be split to be performed as multiple steps, etc.

[0108] The present disclosure also provides a display device comprising a display field as described in the embodiments above. In this way, by using the display fields as described in the embodiments above, the uniformity of the brightness of the display image of the display device can be effectively improved, thereby enhancing the display effect.

[0109] Further embodiments of the present disclosure will be apparent to those skilled in the art from considering the description and practice of the disclosure herein. The present application is intended to cover all variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include such known technical knowledge or common technical procedures in this field as are not explicitly mentioned in this disclosure. It is intended that the description and embodiments be regarded as merely exemplary, with the true scope and spirit of the present disclosure being specified by the following claims.

Claims

[1] Display panel that includes: a substrate; a driver layer located on one side of the substrate and comprising a plurality of groups of pixel circuits arranged in a row direction, the driver layer comprising a source-drain metal layer, the source-drain metal layer comprising auxiliary electrodes corresponding one-to-one to at least one group of pixel circuits, one of the auxiliary electrodes being located on one side of a corresponding group of pixel circuits; a light-emitting layer located on a side of the driver layer facing away from the substrate, wherein the light-emitting layer comprises a light-emitting element and an adapter structure arranged at intervals, wherein there is an overlap region between the orthographic projections of the adapter structure and the auxiliary electrode on the substrate, wherein the light-emitting element comprises a first electrode, a light-emitting functional layer and a second electrode arranged sequentially in a direction away from the substrate, the first electrode being connected to one of the pixel circuits, the light-emitting functional layer covering the first electrode and the adapter structure and forming a fracture step at least at a partial edge of the adapter structure, the second electrode covering the light-emitting functional layer and an exposed part of the adapter structure located at the fracture step of the light-emitting functional layer and being connected to the auxiliary electrode. [2] The display panel of claim 1, wherein the driver layer has an opening facing the light-emitting layer, wherein the orthographic projection of at least a partial edge of the adapter structure on the substrate is located within the orthographic projection of the opening on the substrate; wherein the auxiliary electrode comprises an exposed portion at the opening, wherein the light-emitting functional layer comprises a cover portion and a separating portion, wherein the cover portion and the separating portion form a fracture step at at least a partial edge of the adapter structure, wherein the cover portion covers the first electrode and the adapter structure, wherein the separating portion is located within the opening, and at least a partial edge of the orthographic projection of the exposed portion of the auxiliary electrode on the substrate extends beyond the orthographic projection of the separating portion on the substrate; wherein the second electrode covers a side surface of the adapter structure and a part of the exposed portion, which part is not covered by the separating portion, and wherein a part of the second electrode covering the light-emitting functional layer and a part of the second electrode covering the exposed portion are continuous. [3] The display panel of claim 2, wherein the adapter structure comprises a bore, and the orthographic projection of at least a portion of a bore edge of the adapter structure on the substrate is located within the orthographic projection of the opening on the substrate. [4] The display panel of claim 3, wherein the centerline of the bore of the adapter structure coincides with the centerline of the opening of the driver layer, and the bore dimension of the bore is smaller than the opening dimension of the opening. [5] The display panel of claim 2, wherein the length of the edge of the adapter structure extending into a corresponding region of the opening is greater than or equal to 0.8 micrometers and less than or equal to 1.2 micrometers. [6] A display panel according to any one of claims 2 to 5, wherein the adapter structure comprises a first conductive layer, a metal layer and a second conductive layer arranged one after the other in the direction away from the substrate; wherein the orthographic projection of at least a partial edge of at least one structural layer of the first conductive layer, the metal layer and the second conductive layer on the substrate is located within the orthographic projection of the opening on the substrate, and there is no overlap region between the orthographic projections of the remaining structural layers on the substrate and the orthographic projection of the opening on the substrate. [7] A display panel according to claim 6, wherein the first conductive layer, the metal layer and the second conductive layer each have a via; wherein the edges of the vias of the first conductive layer and the metal layer are flush with the opening wall of the opening, and the orthographic projection of at least a portion of a via edge of the second conductive layer on the substrate is located within the orthographic projection of the openings on the substrate. [8] The display panel according to claim 1, wherein the adapter structure is connected to the auxiliary electrode through a through hole. [9] The display panel according to claim 8, wherein the adapter structure comprises a first conductive layer, a third conductive layer, a metal layer and a second conductive layer arranged sequentially in the direction away from the substrate; wherein the first conductive layer is connected to the auxiliary electrode through a through-hole; the third conductive layer is made of an inorganic material; the orthographic projection of the metal layer on the substrate is located within the orthographic projection of the third conductive layer on the substrate; and at least a partial edge of the second conductive layer extends out from the edge of the metal layer; wherein the light-emitting functional layer covers the first electrode, the second conductive layer, and the third conductive layer, and the light-emitting functional layer forms a fracture step at the edge of the second conductive layer to expose at least a part of the third conductive layer and / or a side surface of the metal layer; wherein the second electrode layer further covers a part of the third conductive layer not covered by the light-emitting functional layer and / or the side surface of the metal layer. [10] A display panel according to claim 9, wherein the edge of the orthographic projection of the metal layer on the substrate is located within the orthographic projection of the second conductive layer on the substrate. [11] A display panel according to any one of claims 1 to 10, wherein the source-drain metal layer comprises a plurality of power supply lines corresponding one-to-one to the plurality of groups of pixel circuits, one of the power supply lines being connected to a corresponding group of pixel circuits, and one of the power supply lines being located on a side of a corresponding group of pixel circuits remote from the auxiliary electrode. [12] A display panel according to claim 11, wherein the auxiliary electrode has an extension portion on a side remote from the corresponding power supply line, there being an overlap region between the orthographic projections of the adapter structure and the extension portion on the substrate, the second electrode covering the adapter structure and being connected to the extension portion. [13] A display panel according to any one of claims 1 to 10, wherein the pixel circuit comprises a first transistor, a second transistor, a third transistor and a storage capacitor; wherein the control electrode of the first transistor is connected to a first plate of the storage capacitor and the first electrode of the second transistor, wherein the first electrode of the first transistor is provided for charging a power supply signal, wherein the second electrode of the first transistor is connected to the second plate of the storage capacitor, the first electrode of the third transistor and to one of the first electrodes; wherein the control electrode of the second transistor is provided for charging a first scanning signal, and the second electrode of the second transistor is provided for charging a data signal; wherein the control electrode of the third transistor is provided for charging a second sensing signal, and the second electrode of the third transistor is provided for charging a sensor signal. [14] A display panel according to claim 13, wherein the driving layer comprises: a masking layer located on one side of the substrate and comprising a masking sheet; a semiconductor layer located on a side of the masking layer facing away from the substrate and comprising active portions of the first transistor, the second transistor and the third transistor, wherein the active portion comprises a channel region and comprises two connecting sections, which connecting sections are located on both sides of the canal area; a gate metal layer located on a side of the semiconductor layer facing away from the substrate and comprising a first scan line, a second scan line, and a second plate of the storage capacitor, wherein the first scan line is provided for charging the first scan signal at the control electrode of the second transistor, and the second scan line is provided for charging the second scan signal at the control electrode of the third transistor; a source-drain metal layer located on a side of the gate metal layer facing away from the substrate and further comprising a power supply line, a data line, a sensor line, and the first plate of the storage capacitor, wherein the power supply line is provided for charging the power supply signal at the first electrode of the first transistor, the data line is provided for charging the data signal at the second electrode of the second transistor, and the sensor line is provided for charging the sensor signal at the second electrode of the third transistor, wherein the first plate of the storage capacitor is directly opposite the masking sheet and is connected thereto by a through-hole; a flat layer located on a side of the source-drain metal layer facing away from the substrate and covering at least the power supply line, the data line, the sensor line, the first plate of the storage capacitor, and the auxiliary electrode. [15] A display panel according to claim 14, wherein a group of pixel circuits comprises a plurality of circuit units arranged in a column direction, one of the circuit units comprising four pixel circuits arranged in two rows and two columns, wherein for one of the circuit units: the power supply line and the auxiliary electrode each extend in the column direction and are arranged in the row direction, wherein the power supply line is provided to charge power supply signals to the first electrodes of the first transistors of four of the pixel circuits; four of the masking sheets are located between the power supply line and the auxiliary electrode, and the orthographic projections of the first plate and the second plate of each storage capacitor on the substrate are each located within the orthographic projection of the masking sheet of the same pixel circuit on the substrate; the first scanning line and the second scanning line extend in the row direction and are located between two of the masking sheets in the column direction, wherein the first scanning line is provided to charge first scanning signals onto the control electrodes of the second transistors of four of the pixel circuits, and the second scanning line is provided to charge second scanning signals onto the control electrodes of the third transistors of four of the pixel circuits; the data lines extend in the column direction, with one of the data lines being provided on each side of the two masking sheets in the row direction, and four of the data lines are located between the power supply line and the auxiliary electrode, one of the data lines being provided to load a data signal onto the second electrode of the second transistor of one of the pixel circuits; the sensor line extends in the column direction and is located between two of the masking sheets in the row direction, the sensor line being provided to load sensor signals onto the second electrodes of the third transistors of four of the pixel circuits. [16] A method of manufacturing a display panel, the method comprising: Providing a substrate; Forming a driver layer on one side of the substrate, the driver layer comprising a plurality of groups of pixel circuits arranged in a row direction, the driver layer comprising a source-drain metal layer, the source-drain metal layer comprising auxiliary electrodes corresponding one-to-one to at least one group of pixel circuits, and one of the auxiliary electrodes being located on one side of a corresponding group of pixel circuits; Producing a first electrode layer on a side of the driver layer facing away from the substrate, the first electrode layer comprising first electrodes and an adapter structure arranged at intervals, one of the first electrodes being connected to one of the pixel circuits and there being an overlap region between the orthographic projections of the adapter structure and the auxiliary electrode on the substrate; Etching the adapter structure and the driver layer to form an opening in the driver layer facing the first electrode layer and exposing the auxiliary electrode, wherein the orthographic projection of at least a partial edge of the adapter structure on the substrate is located within the orthographic projection of the opening on the substrate; Producing a light-emitting functional layer on a side of the first electrode layer facing away from the substrate, wherein the light-emitting functional layer comprises a cover portion and a separating portion, wherein the cover portion covers the first electrode and the adapter structure, wherein the separating portion is located within the opening, wherein the cover portion and the separating portion form a fracture step at at least a partial edge of the adapter structure, and wherein at least a partial edge of the orthographic projection of the exposed portion of the auxiliary electrode on the substrate extends beyond the orthographic projection of the separating portion on the substrate; Producing a second electrode layer on a side of the light-emitting functional layer facing away from the substrate, wherein the second electrode layer covers the light-emitting functional layer and a part of the exposed portion of the auxiliary electrode, which part is not covered by the separating portion. [17] A method of manufacturing a display panel, the method comprising: Providing a substrate; Forming a driver layer on one side of the substrate, the driver layer comprising a plurality of groups of pixel circuits arranged in a row direction, the driver layer comprising a source-drain metal layer, the source-drain metal layer comprising auxiliary electrodes corresponding one-to-one to at least one group of pixel circuits, and one of the auxiliary electrodes being located on one side of a corresponding group of pixel circuits; Producing a first electrode layer on a side of the driver layer facing away from the substrate, the first electrode layer comprising first electrodes and an adapter structure arranged at intervals, one of the first electrodes being connected to one of the pixel circuits, the adapter structure comprising a first conductive layer, a third conductive layer, a metal layer, and a second conductive layer arranged sequentially in the direction away from the substrate, the third conductive layer being made of an inorganic material, the orthographic projection of the metal layer on the substrate being located within the orthographic projection of the third conductive layer on the substrate, and at least a partial edge of the second conductive layer extending out from the edge of the metal layer; Producing a light-emitting functional layer on a side of the first electrode layer facing away from the substrate, wherein the light-emitting functional layer covers the first electrode, the second conductive layer, the third conductive layer, and the light-emitting functional layer forms a fracture step at the edge of the second conductive layer to expose at least a part of the second conductive layer and / or a side surface of the metal layer; Producing a second electrode layer on a side of the light-emitting functional layer facing away from the substrate, wherein the second electrode layer covers the light-emitting functional layer and a part of the second conductive layer that is not covered by the light-emitting functional layer and / or a side surface of the metal layer. [18] A display device comprising a display panel according to the preceding claims 1-15.

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