VERTICAL IGBT WITH COMPLEMENTARY CHANNEL FOR POT EXTRACTION

Abstract

The semiconductor device (100) is a vertical IGBT and comprises a semiconductor body (1) with a top surface (10), a main electrode (2) on the top surface, and a gate electrode (3). The semiconductor body includes a drift layer (11) of a first conductivity type, a first base region (12) of a second conductivity type, a second (complementary) base region (13) of the first conductivity type, a first contact region (14) of the first conductivity type, and a second contact region (15) of the second conductivity type. The second base region has a higher doping concentration than the drift layer. The first contact region is adjacent to the first base region and the top surface. The second contact region is adjacent to the second base region and the top surface. The main electrode is in electrical contact with the first and second contact regions.In a first lateral direction, at least part of the gate electrode is arranged between the first contact region and the second contact region. Upon switch-off, a hole inversion channel is induced in the second basal region (13) for hole extraction.

Description

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device.

[0002] There is a need for an improved semiconductor device, for example, a semiconductor device that enables efficient removal of charge carriers, such as holes, from the semiconductor body during turn-off transients without compromising on-state losses. Furthermore, there is a need for an improved method for fabricating such a semiconductor device.

[0003] Embodiments of the disclosure relate to an improved semiconductor device and an improved method of manufacturing a semiconductor device.

[0004] First, the semiconductor device is described in detail.

[0005] According to one embodiment, the semiconductor device comprises a semiconductor body having a top side, a main electrode on the top side, and a gate electrode. The semiconductor body comprises a drift layer of a first conductivity type. The semiconductor body further comprises a first base region of a second conductivity type, which is arranged vertically between the drift layer and the top side. In addition, the semiconductor body comprises a second base region of the first conductivity type, which is arranged vertically between the drift layer and the top side. The second base region has a higher doping concentration than the drift layer and borders the drift layer. Furthermore, the semiconductor body comprises a first contact region of the first conductivity type. The first contact region borders the first base region and the top side. Furthermore, the semiconductor body comprises a second contact region of the second conductivity type.The second contact region adjoins the second base region and the top surface. The main electrode is in electrical contact with the first contact region and the second contact region. In a first lateral direction, at least a portion of the gate electrode is arranged between the first contact region and the second contact region, and between the first base region and the second base region.

[0006] Bipolar semiconductor devices, such as IGBTs, are devices in which both electrons and holes participate in the conduction process. The injection of both electrons and holes leads to the formation of a high-density plasma in the drift layer, which lowers the resistance of this layer and thus reduces losses during the on-state. However, in the off-state, the stored plasma must be quickly removed to minimize switching losses. Thus, there is a trade-off between the on-state voltage drop (Vce-sat) and the off-state losses (Eoff) of such a device.

[0007] In the present invention, a complementary transistor for the controlled extraction of charge carriers of the second type, such as holes, is introduced by means of the second base region and the second contact region. The complementary transistor provides an additional extraction path for charge carriers of the second type, which remains active only during the off-period of the main transistor comprising the first base region and the first contact region. Thus, switching losses of the semiconductor device are reduced without affecting its on-state. The function of the semiconductor device is not limited by, for example, trench pitches. Furthermore, since no additional gate connection is required, the Miller capacitance, Cgc, is not affected.The concept applies, for example, to MOS-based bipolar devices such as IGBTs, reverse-conducting IGBTs (RC-IGBTs), bidirectional IGBTs (BIGTs), MOS-controlled diodes and can be implemented in both trench and planar architectures.

[0008] The semiconductor body can be based on Si, SiC, GaN, or any other semiconductor material. Lateral directions are defined here as directions parallel to the top surface of the semiconductor body. A vertical direction is defined here as a direction perpendicular to the top surface.

[0009] The main electrode may be formed of metal. The gate electrode may comprise or consist of highly doped metal or polysilicon. The gate electrode is in particular insulated from the semiconductor body by an electrically insulating material such as SiO2 or any other dielectric material, or a combination of two or more dielectric materials. Thus, the semiconductor device may be an insulated-gate device. In particular, the gate electrode and the main electrode are electrically insulated from each other, allowing them to be set to different electrical potentials for operation.

[0010] The drift layer can extend over the entire lateral extent of the semiconductor body. The drift layer is of the first conductivity type. The first conductivity type can be either electron conduction or hole conduction. The second conductivity type differs from the first conductivity type and is therefore either hole conduction or electron conduction. An electron-conducting region or layer is n-doped, and a hole-conducting region or layer is p-doped. For example, the doping concentration in the drift layer is at least 10 8 cm -3 and a maximum of 10 15 cm -3 .

[0011] The first base region is arranged vertically between the drift layer and the top surface, i.e., it is arranged vertically between the drift layer and the top surface. For example, the doping concentration in the first base region is at least 10 15 cm -3and / or a maximum of 10 18 cm -3 . The first base region may be adjacent to the drift layer and / or the top surface, i.e., it may be in direct contact with the drift layer and / or form part of the top surface.

[0012] The second base region is of the same conductivity type as the drift layer, but has a higher doping concentration than the drift layer, e.g., the doping concentration in the second base region is at least 10 times or at least 100 times higher than in the drift layer. For example, the doping concentration in the second base region is at least 10 15 cm -3 and / or a maximum of 10 18 cm -3 .

[0013] The second base region borders the drift layer, thus being in direct contact with it. In particular, no region of the second conductivity type is arranged vertically between the drift layer and the second base region. Furthermore, the second base region can border the top surface, thus forming part of it.

[0014] Here, when comparing doping concentrations of layers or regions, the average doping concentrations or maximum doping concentrations of these layers or regions are compared. Defining upper and lower limits of the doping concentration in a layer or region means that the maximum doping concentration in the respective layer / region does not exceed the upper limit, and the minimum doping concentration in the respective layer / region does not fall below the lower limit.

[0015] The first contact region borders the first base region and the top surface, i.e., it is in direct contact with the first base region and forms part of the top surface. For example, the first contact region is arranged vertically between the first base region and the top surface and borders the first base region in the vertical direction. Additionally or alternatively, the first contact region can border the first base region in the first lateral direction.

[0016] The first contact region may be at least partially embedded in the first base region. In particular, the first contact region may be at least partially laterally surrounded by the first base region. The doping concentration in the first contact region is, for example, greater than in the first base region, for example at least 10 times or at least 100 times greater. For example, the doping concentration in the first contact region is at least 10 17 cm -3or at least 10 18 cm -3 or at least 10 19 cm -3 .

[0017] The second contact region borders the second base region and the top surface, i.e., it is in direct contact with the second base region and forms part of the top surface. For example, the second contact region is arranged vertically between the second base region and the top surface and borders the second base region in the vertical direction. Additionally or alternatively, the second contact region can border the second base region in the first lateral direction.

[0018] The second contact region may be at least partially embedded in the second base region. In particular, the second contact region may be at least partially laterally surrounded by the second base region. The doping concentration in the second contact region is, for example, greater than in the second base region, for example at least 10 times or at least 100 times greater. For example, the doping concentration in the second contact region is at least 10 17 cm -3 or at least 10 18 cm -3 or at least 10 19 cm -3 .

[0019] The contact areas are also called source areas.

[0020] The thickness of the first and second base regions, measured in the vertical direction, can be at least 1 µm and / or at most 8 µm. The thickness of the first and second contact regions can each be at least 50 nm and / or at most 1 µm. The lateral extent of the first and second contact regions in the first lateral direction can each be at least 50 nm and / or at most 5 µm. The lateral extent in the first lateral direction of the first and second base regions can each be at least 500 nm and / or at most 5 µm.

[0021] The main electrode is in electrical contact with the first and second contact regions, i.e., direct electrical contact. For example, the main electrode borders the first and second contact regions on the top side. For example, the main electrode is not in direct electrical contact with the second base region. An ohmic contact can be formed between the main electrode and the contact regions.

[0022] In the first lateral direction, at least a part of the gate electrode, e.g., a major part of the gate electrode or the entire gate electrode, is arranged laterally between the first and second contact regions and between the first and second base regions. For example, only one gate electrode is arranged between the first and second contact regions and between the first and second base regions in the first lateral direction. For example, the distance measured in the first lateral direction between the first and second contact regions is at most twice or at most 1.5 times the lateral extent of the gate electrode in the first lateral direction. For example, the distance in the first lateral direction between the first and second contact regions is at most 10 µm.

[0023] According to a further embodiment, the semiconductor device is configured such that, by adjusting the electrical potential of the gate electrode, either a zone of the first base region is inverted by means of the gate electrode, i.e., the conductivity type in this zone is inverted, thus enabling a current flow of charge carriers of the first type between the drift layer and the first contact region through this zone. The inverted zone faces the gate electrode, i.e., it is a zone of the first base region that is closest to the gate electrode.

[0024] Alternatively, a zone of the second base region is inverted by the gate electrode, thus enabling a current flow of charge carriers of the second type between the drift layer and the second contact region through this zone. Here, too, the inverted zone faces the gate electrode, i.e., it is a zone of the second base region that is closest to the gate electrode.

[0025] Thus, the drift layer, the first base region and the first contact region form part of a first transistor (main transistor), and the drift layer, the second base region and the second contact region form part of a second transistor (complementary transistor).

[0026] If the first conductivity type is electron conduction, the charge carriers of the first type are electrons. Accordingly, the second conductivity type is hole conduction, and the charge carriers of the second type are holes.

[0027] For example, in the first case, when a zone of the first base region is inverted, the flow of charge carriers of the first type from the main electrode through the first contact region, the inverted zone of the first base region, and into the drift layer is enabled. For example, in the second case, when a zone of the second base region is inverted, the flow of charge carriers of the second type from the drift layer through the inverted zone of the second base region and the second contact region into the main electrode is enabled.

[0028] According to a further embodiment, the semiconductor device is a planar device, i.e., has a planar architecture, wherein the gate electrode is arranged on the top side. For example, the gate electrode is at least partially aligned with the first and second contact regions and / or with the first and second base regions in the first lateral direction. The gate electrode is thereby insulated from the contact regions by the electrically insulating layer. For example, in a top view of the top side, the gate electrode is at least partially overlapped with the first and second contact regions and with the first and second base regions.

[0029] According to a further embodiment, the semiconductor device is a trench device, i.e., has a trench architecture, wherein the gate electrode is arranged in an active trench. The active trench extends from the top side in a vertical direction into the semiconductor body. For example, the first and second contact regions and / or the first and second base regions are at least partially aligned with the gate electrode in a vertical direction. That is, in a side view along the first lateral direction, the active trench and the gate electrode therein partially or completely overlap the first and second contact regions and / or the first and second base regions. For example, the active trench extends deeper into the semiconductor body than the first and second contact regions and / or than the first and second base regions.For example, the active trench and the gate electrodes extend vertically into the semiconductor body by at least 2 µm or at least 4 µm and / or by at most 10 µm.

[0030] According to a further embodiment, the semiconductor device comprises a dummy trench arranged adjacent to the active trench and spaced from the active trench in the first lateral direction.

[0031] A trench with a gate electrode therein is referred to herein as an "active trench." Trenches without a gate electrode therein are referred to herein as "dummy trenches." For example, the second base region and the second contact region are arranged between the active trench and the dummy trench in the first lateral direction. The second base region may be adjacent to the active trench and the dummy trench in the first lateral direction.

[0032] According to a further embodiment, the dummy trench is filled with an electrically conductive material, such as highly doped polysilicon. The electrically conductive material is electrically insulated from the semiconductor body, for example, by insulating material. For example, the electrically conductive material in the dummy trench is electrically connected to the main electrode.

[0033] The trenches of the semiconductor device, whether active or dummy, can all have the same dimensions within manufacturing tolerances. Alternatively, the dummy trenches can be deeper or shallower than the active trenches.

[0034] For example, exactly one active trench is arranged between the first and second contact regions and between the first and second base regions. The first and second contact regions may border the active trench on different sides with respect to the first lateral direction. Likewise, the first and second base regions may border the active trench on different sides with respect to the first lateral direction.

[0035] According to a further embodiment, an enrichment region of the first conductivity type is arranged vertically between the first base region and the drift layer. For example, the enrichment region extends laterally over the entire lateral extent of the first base region. Thus, the enrichment layer is arranged over the entire lateral extent of the first base region between the drift layer and the first base region. The enrichment region can be adjacent to the first base region and / or the drift layer. This enrichment region is also referred to herein as the "first enrichment region."

[0036] According to a further embodiment, the enrichment region has a higher doping concentration than the drift layer. For example, the doping concentration in the first enrichment region is at least 10 times or at least 100 times higher than in the drift layer. For example, the doping concentration in the enrichment region is at least 10 15 cm -3 and / or a maximum of 10 19 cm -3 . The thickness of the enrichment area measured in the vertical direction is, for example, at least 1 µm and / or at most 3 µm.

[0037] The enrichment region is a barrier region for charge carriers of the second type, which are, for example, holes. It can therefore be referred to as a "hole barrier region" or "hole barrier layer."

[0038] According to a further embodiment, the semiconductor device comprises a third base region of the second conductivity type. The third base region is arranged adjacent to the second base region in the first lateral direction, such that the second base region is arranged between the first and third base regions in the first lateral direction. The second and third base regions can be spaced apart from each other in the first lateral direction by a trench, for example, by exactly one trench. This trench can be an active trench or a dummy trench.

[0039] The third base region is also arranged vertically between the top surface and the drift layer. It can be adjacent to the top surface and / or the drift layer. The doping concentration in the third base region can be in the same or a different range than the doping concentration in the first base region. The thickness of the third base region, measured in the vertical direction, is, for example, greater than that of the first base region, e.g., by at least 1 µm.

[0040] According to a further embodiment, the third base region extends from the top side into the semiconductor body. For example, the third base region extends deeper into the semiconductor body than the active trench or trenches. For example, the third base region extends at least 1 µm deeper into the semiconductor body than the trench or trenches. The third base region is, for example, a so-called p-well.

[0041] According to a further embodiment, the thickness of an insulating material between the first contact region and / or the first base region and the gate electrode is greater than the thickness of the insulating material between the second contact region and / or the second base region and the gate electrode. For example, the thickness between the first contact region / the first base region and the gate electrode is at least 1.5 times or at least twice greater than the thickness between the second contact region / the second base region and the gate electrode.

[0042] According to a further embodiment, the main electrode is not in direct electrical contact with the second base region. This means that charge carriers cannot flow directly from the main electrode to the second base region or vice versa. Rather, the charge carrier exchange must always occur via the second contact region.

[0043] According to a further embodiment, the semiconductor device comprises a further gate electrode. The further gate electrode is spaced apart from the gate electrode in the first lateral direction. For example, the further gate electrode is at the same electrical potential as the gate electrode. In other words, the gate electrode and the further gate electrode can be short-circuited.

[0044] In addition, the further gate electrode can be arranged in an active trench that extends from the top side into the semiconductor body.

[0045] According to a further embodiment, the second base region is arranged between the gate electrode and the further gate electrode in the first lateral direction. For example, no further gate electrodes are arranged between the gate electrode and the further gate electrode in the first lateral direction. The second base region can be adjacent to the two active trenches comprising the gate electrode and the further gate electrode in the first lateral direction.

[0046] According to a further embodiment, the semiconductor device is configured such that, by adjusting the electrical potential of the further gate electrode, a zone of the second base region is inverted by means of the further gate electrode, wherein the zone is located on a side of the second base region opposite the side of the second base region on which the zone of the second base region is inverted by means of the gate electrode. The further gate electrode thus provides a current path on this opposite side. "Opposite" here refers to the first lateral direction. In other words, the gate electrode and the further gate electrode invert zones of the second base region that are arranged on opposite sides and that are spaced apart, for example, in the first lateral direction.

[0047] In other words, the gate electrode and the further gate electrode form two channels, for example hole channels, for the transport of charge carriers.

[0048] According to a further embodiment, the first and / or second contact region are elongated regions extending in a second lateral direction that is oblique to the first lateral direction, for example, perpendicular to the first lateral direction. This means that the lateral extent of the first and / or second contact region is in each case greater in the second lateral direction than in the first lateral direction. For example, the lateral extent in the second lateral direction is in each case at least twice or at least five times greater than in the first lateral direction. The first and second contact regions can adjoin the upper side over the entire lateral extent in the first and / or second lateral direction.

[0049] Likewise, the first and second base regions may be elongated and extend in the second lateral direction. The trenches may also be elongated and extend in the second lateral direction.

[0050] According to a further embodiment, the semiconductor device comprises a plurality of first contact regions that adjoin the top side and the first base region and that are in electrical contact with the main electrode. These first contact regions are separated and spaced apart from one another in the second lateral direction. For example, each first contact region has a lateral extent in the second lateral direction of at least 500 nm or at least 1 µm. The distance between each two adjacent first contact regions in the second lateral direction can in any case be at least 500 nm or at least 1 µm. All features previously disclosed for a first contact region are also disclosed for all other first contact regions, in particular with regard to doping concentration and conductivity type.

[0051] According to a further embodiment, the semiconductor device comprises a plurality of second contact regions that adjoin the top side and the second base region and that are in electrical contact with the main electrode. These second contact regions are separated and spaced apart from one another in the second lateral direction. For example, each second contact region has a lateral extent in the second lateral direction of at least 500 nm or at least 1 µm. The distance between each two adjacent second contact regions in the second lateral direction can in any case be at least 500 nm or at least 1 µm. All features previously disclosed for a second contact region are also disclosed for all other second contact regions, in particular with regard to doping concentration and conductivity type.

[0052] According to a further embodiment, the semiconductor device is a power semiconductor device. For example, the semiconductor device is configured to process a current of at least 1 A and / or voltages of at least 100 V. The semiconductor device is, for example, a so-called vertical semiconductor device.

[0053] According to a further embodiment, the semiconductor device is a vertical device, i.e., it has a vertical architecture. The cathode and anode are then arranged on opposite sides of the semiconductor body.

[0054] According to a further embodiment, the semiconductor device is a bipolar semiconductor device in which both electrons and holes contribute to the electric current during operation.

[0055] According to another embodiment, the semiconductor device is an insulated-gate bipolar transistor (IGBT) or a MOS-controlled diode. The semiconductor device is, for example, a reverse-conducting IGBT (RC-IGBT) or a bidirectional IGBT (BIGT).

[0056] According to a further embodiment, the semiconductor device comprises a further main electrode applied to a rear side of the semiconductor body opposite the top side. The semiconductor body may comprise a contact layer (anode layer) and / or a buffer layer between the drift layer and the further main electrode.

[0057] The following is a detailed description of the method for manufacturing a semiconductor device. The method is particularly suitable for manufacturing a semiconductor device according to any of the embodiments described herein. Thus, all features disclosed for the semiconductor device are also disclosed for the method, and vice versa.

[0058] According to one embodiment of the method for manufacturing a semiconductor device, the method comprises a step of providing a semiconductor body having a top side and a drift layer of a first conductivity type. In further steps, a first base region, a second base region, a first contact region, and a second contact region are produced. The first base region is of a second conductivity type and is produced such that the first base region lies vertically between the drift layer and the top side. The second base region is of the first conductivity type and is produced such that the second base region lies vertically between the drift layer and the top side, wherein the second base region has a higher doping concentration than the drift layer and is adjacent to the drift layer.The first contact region is of the first conductivity type and is produced such that the first contact region adjoins the first base region and the top side. The second contact region is of the second conductivity type and is produced such that the second contact region adjoins the second base region and the top side. In a further step, a main electrode is applied to the top side and electrical contact is established between the main electrode and the first contact region and between the main electrode and the second contact region. In a further step, a gate electrode is formed such that finally at least a part of the gate electrode lies in a first lateral direction between the first contact region and the second contact region and between the first base region and the second base region.

[0059] Before forming the first and second base regions and the first and second contact regions, the drift layer may reach the top surface, e.g., forming the top surface. Forming the base regions and / or the contact regions may include implanting dopants, e.g., through the top surface. For example, masks are used to define the areas where the dopants for the various regions are to be implanted.

[0060] The following is a more detailed explanation of the semiconductor device and the method for manufacturing a semiconductor with reference to the drawings using exemplary embodiments. The attached figures are included to provide a better understanding. In the figures, elements of the same structure and / or function may be designated by the same reference numerals. It is understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale. To the extent that elements or components in different figures correspond to one another in function, their description will not be repeated for each of the following figures. For reasons of clarity, elements may not appear with corresponding reference numerals in all figures. Fig. 1 to 5, 9, 16, 18 to 29 and 31 show various embodiments of the semiconductor device in different views, Fig. 6 and Fig. 10 show a reference semiconductor device, Fig. 7, 8 and 11 to 15 show simulation results illustrating the behavior of an embodiment of the semiconductor device and a reference semiconductor device, Fig. 17 shows an example of a semiconductor device, Fig. 30 shows a flowchart of an embodiment of the method for manufacturing a semiconductor device.

[0061] Fig. Figure 1 shows a section of a first embodiment of the semiconductor device 100 in a cross-sectional view. The semiconductor device 100 comprises a semiconductor body 1, e.g., made of Si, SiC, or GaN. A main electrode 2 is applied to the top side 10 of the semiconductor body 1. The main electrode 2 is, for example, a metal electrode.

[0062] The semiconductor body 1 comprises a drift layer 11 of a first conductivity type. In the following, the first conductivity type is assumed to be electron conduction, and the corresponding doping is n-type. Thus, the drift layer 11 is n-doped. However, the described embodiments would also function if the first conductivity type were hole conduction.

[0063] A first base region 12 and a second base region 13 are each located vertically between the drift layer 11 and the top side 10. "Vertical" here means in the vertical direction V, which is a direction perpendicular to the top side 10. The first base region 12 and the second base region 13 are arranged next to one another in a first lateral direction L1, which is a direction parallel to the top side 10. The first base region 12 is of a second conductivity type that differs from the first conductivity type, i.e., p-doped in this case. The second base region 13 is of the first conductivity type, i.e., n-doped. The base regions 12, 13 both border the drift layer 11 and the top side 10.

[0064] A first contact region 14 is embedded in the first base region 12. The first contact region 14 is of the first conductivity type, i.e., n-doped, and borders the first base region 12 and the top side 10. At the top side 10, the first contact region 14 is in direct mechanical and electrical contact with the main electrode 2. The first base region 12 is also in direct mechanical and electrical contact with the main electrode 2 at the top side 10.

[0065] A second contact region 15 is embedded in the second base region 13. The second contact region 15 is of the second conductivity type, i.e., p-doped, and borders the second base region 13 and the top side 10. At the top side 10, the second contact region 15 is in direct mechanical and electrical contact with the main electrode 2. However, the main electrode 2 is not in direct mechanical or electrical contact with the second base region 13, so that an exchange of charge carriers between the main electrode 2 and the second base region 13 must always occur through the second contact region 15.

[0066] Laterally between the base regions 12, 13 and the contact regions 14, 15, an active trench 4 extends from the top side 10 into the semiconductor body 1 and opens into the drift layer 11. The depth of the active trench 4, measured in the vertical direction V, is greater than the thickness of the base regions 12, 13 and the contact regions 14, 15, also measured in the vertical direction V. A gate electrode 3 is arranged within the active trench 4. The gate electrode 3 consists, for example, of highly doped polysilicon. The gate electrode 3 is electrically insulated from the semiconductor body 1, in particular from the base regions 12, 13 and the contact regions 14, 15, by an electrically insulating material 5, which consists, for example, of SiO2. The semiconductor device 100 of Fig. 1 is a so-called trench device.

[0067] The doping concentration of the drift layer 11 is, for example, between 10 8 cm -3 and 1015 cm -3 . The doping concentration of each base region 12, 13 is, for example, in the range between 10 15 cm -3 and 10 18 cm -3 The doping concentration in the contact areas 14, 15 is in any case, for example, in the range between 10 18 cm -3 and 10 21 cm -3 .

[0068] During the on-state of the semiconductor device 100, the gate electrode 3 may be at a positive electrical potential with respect to the semiconductor body 1. As a result, an inverted zone is formed in the first base region 12 on the side facing the active trench 4, wherein the inverted zone extends along the active trench 4 from the first contact region 14 to the drift layer 11. As a result, electrons can be injected from the main electrode 2 into the contact region 14 and from there into the drift layer 11 within the inverted zone.

[0069] In the off-state of the semiconductor device 100, the gate electrode 3 may be at a negative electrical potential with respect to the semiconductor body 1. The electrical potentials of the main electrode 2 and the further main electrode may be the same as in the on-state. As a result, an inverted zone is formed in the second base region 13 on the side facing the active trench 4, wherein the inverted zone extends along the active trench 4 from the second contact region 15 to the drift layer 11. As a result, holes can exit the drift layer 11 via the inverted zone and travel along the inverted zone, then through the second contact region 15 and into the main electrode 2.

[0070] In particular, when the semiconductor device 100 is a bipolar device such as an IGBT, this enables very efficient hole removal, resulting in reduced turn-off losses.

[0071] The transistor implemented with the first base region 12 and the first contact region 14 is referred to here as the "main transistor," and the transistor implemented with the second base region 13 and the second contact region 15 is referred to here as the "complementary transistor." In the embodiments described here, the main transistor is an NMOS transistor and the complementary transistor is a PMOS transistor.

[0072] The embodiment of Fig. 2 shows a so-called planar device that does not have a Fig. 1 is used. Instead, the gate electrode 3 is arranged on the top side 10 and is electrically insulated from the semiconductor body 1 by an electrically insulating material 5. In a plan view of the top side 10, the gate electrode 3 partially covers, i.e., overlaps, the first 14 and the second 15 contact regions. While the inverted zones and the associated current paths in Fig. 1 are mainly aligned in the vertical direction V, the inverted zones and the associated current paths of Fig. 2 mainly oriented in the first lateral direction L1.

[0073] The embodiment of Fig. 3 shows a semiconductor device 100, which is an insulated-gate bipolar transistor, or IGBT for short. On the back side of the semiconductor body 1, opposite the top side 10, a further main electrode 6, which is made of metal, for example, is applied. The semiconductor body 1 comprises a further layer 20 of the second conductivity type, i.e., p-doped, which forms the back side and is in direct electrical and mechanical contact with the further main electrode 6. The doping concentration of the further layer 20 is, for example, greater than in the drift layer 11. A layer 19 of the first conductivity is applied between the drift layer 11 and the layer 20. The layer 19 borders the layer 20 and the drift layer 11. The doping concentration in the layer 19 is, for example, greater than in the drift layer 11. The layer 19 is a so-called buffer layer.

[0074] In Fig. 3, the first base region 12 borders active trenches 4 on both sides with respect to the first lateral direction L1. Both active trenches 4 are connected to a gate electrode 3. Second base regions 13 are arranged on both sides of the first base region 12, again with respect to the first lateral direction L1, each of which is spaced from the first base region 12 by one of the active trenches 4.

[0075] The second base regions 13 are each located between two trenches 4, 40 and border them. In both cases, only the trench closer to the first base region 12 is an active trench 4. The other trench 40 is a dummy trench. The dummy trenches 40 are filled with electrically conductive material, which is, for example, electrically connected to the main electrode 2 and thus at the same electrical potential as the main electrode 2. The dummy trenches 40 help reduce the capacitance between the gate electrodes 3 and the further main electrode 6, also referred to as the Miller capacitance or gate-collector capacitance (Cgc).

[0076] Fig. 3 and the other figures may show only a portion of a semiconductor device. The structures shown in these figures, which include the base regions 12, 13 and the contact regions 14, 15, may be repeated multiple times in the first lateral direction L1.

[0077] In the embodiment of Fig. 4, the semiconductor body 1 comprises third base regions 18, which are of the second conductivity type, i.e., p-doped, and border the dummy trenches 40 on the sides facing away from the second base regions 13. The doping concentration in the third base regions 18 can be the same as or different from that of the first base regions 12. The third base regions 18 form p-wells that extend deeper into the semiconductor body 1 than the trenches 4, 40. An improved breakdown voltage can be achieved with the third base regions 18.

[0078] Fig. 5 shows a detailed view of the embodiment of Fig. 4, wherein only one half of the first base region 12, the adjacent second base region 13 and the third base region 18 are shown. Fig. Figure 5 illustrates the doping profile using different hatching patterns. The higher the hatching point density, the higher the doping concentration.

[0079] Fig. 6 shows a reference semiconductor device 200, e.g., a reference IGBT. In contrast to the IGBT of Fig. 5, the second base region 13 and the second contact region 15 are omitted. Instead, the semiconductor body 1 adjacent to the top side 10, laterally between the dummy trench 40 and the active trench 4, also consists of semiconductor material of the second conductivity type, e.g., with the same doping concentration as the first base region 12. The main electrode 2 is in electrical and mechanical contact with the semiconductor body 1 (dummy contact) in the region between the two trenches 4, 40.

[0080] Fig. 7 and Fig. 8 show simulations of the output characteristics Ic as a function of Vce of the IGBT according to Fig. 5 (curve 100) compared to the output characteristics of the reference IGBT according to Fig. 6 (curve 200), i.e. without the second base area and the second contact area. Fig. 7 shows the range from 0 to 2 V and Fig. 8 shows the range from 0 to 25 V. The IGBT according to Fig. 5 shows an improvement of Vce-sat of ~130 mV compared to the reference IGBT according to Fig. 6. In the reference IGBT, the extraction of injected holes between the dummy trench 40 and the active trench 4 in the on-state leads to a decrease in the plasma concentration in the drift region (drift layer 11) and therefore leads to higher on-state losses. In the IGBT of Fig. 5, this hole extraction between the dummy trench 40 and the active trench 4 is significantly suppressed in the on-state (~50%, see also Fig. 9). This is a consequence of the placement of the second base region and the second contact region (PMOS transistor) between the active trench 4 and the dummy trench 40. This PMOS transistor is off during the IGBT on-state (Vge > Vth), thereby virtually eliminating the hole extraction path in the region between the active trench 4 and the dummy trench 40. This explains the higher Vce-sat of the IGBT, which is very close to the Vce-sat of an IGBT without electrical contact of the semiconductor body with the main electrode in the region of the top side laterally between the dummy trench 40 and the active trench 4 (i.e., without a dummy contact).

[0081] In short, the electrical contact with the main electrode 2 in the region between the active trench 4 and the dummy trench 40 is effectively invisible during the IGBT on-state, as desired to maintain the plasma concentration.

[0082] Fig. Figure 9 shows simulated hole current flow lines during the on-state operation of the IGBT according to Fig. 5, while Fig. 10 simulated hole current flow lines for the reference IGBT according to Fig. 6 shows. The density of the contour lines is proportional to the hole current. In the Fig. 9 and Fig. 10, Vce is chosen as 3 V. As can be seen, the current flow of holes between the active trench 4 and the dummy trench 40 for the IGBT is determined according to the Fig. 5 and Fig. 9 significantly suppressed.

[0083] Fig. Figure 11 shows a simulated hole current at the second contact region as a function of the voltage Vce during the on-state operation for the IGBT according to Fig. 5 (curve 100) and the reference IGBT (curve 200). As can be seen, the IGBT according to Fig. 5 a reduction of about 50% of the hole current in the switched-on state can be achieved.

[0084] Fig. Figure 12 shows simulations of Ic as a function of Vce for Vge = -15 V. As can be seen, the blocking capabilities of the IGBT are Fig. 5 (curve 100) and the reference IGBT according to Fig. 6 (curve 200) almost the same.

[0085] Fig. 13 shows simulations of the turn-off characteristics of the IGBT according to Fig. 5 (curves 100_i) and the reference IGBT according to Fig. 6 (curves 200_i). Curves 100_1, 200_1 show Vce as a function of time T, curves 100_2, 200_2 show Vge as a function of time T and curves 100_3, 200_3 show IC as a function of time T. The turn-off loss, Eoff, of the IGBT according to Fig. 5 is very close to that of the reference IGBT according to Fig. 6. It should also be noted that the Eoff of the IGBT according to Fig. 5 is lower than that of the reference IGBT without the electrical contact with the main electrode in the region between the trenches (see table below). This means that the PMOS transistor, which prevents holes from leaking in the on-state, is now active in the IGBT off-state, effectively extracting holes from the IGBT device, which in turn reduces its switching losses. In other words, the contact with the main electrode in the region between the dummy trench and the active trench, which was effectively invisible during the IGBT on-state, is visible during the IGBT off-state, as desired for simultaneously improved on-state and switching losses.

[0086] Fig. 14 shows simulations of the turn-on characteristics with the same nomenclature as in Fig. 13. The IGBT according to Fig. 5 shows lower turn-on losses, Eon, compared to the reference IGBT of Fig. 6 lower gate-emitter capacitance, Cge. The total losses E total , so E rec + E on , where E rec the diode reverse recovery losses remain the same (see table below).

[0087] Fig. 15 shows the simulated technology curve (E off as a function of V ce-sat ) at 25 °C for the IGBT according to Fig. 5 (curve 100) compared to the reference IGBT according to Fig. 6 (curve 200). The IGBT according to Fig. 5 exhibits a superior technology curve compared to the reference IGBT. For the same V ce-sat the IGBT shows according to Fig. 5 an 18% lower Eoff compared to the reference IGBT. While for the same E off V ce-sat of the IGBT according to Fig. 5 is 5% lower compared to that of the reference IGBT.

[0088] The following table shows a summary of the simulation results of the IGBT according to Fig. 5 (line 100) compared to the reference IGBT according to Fig. 6 (line 200) and compared to an IGBT according to Fig. 6, but without the electrical contact of the main electrode with the semiconductor body in the region between the active trench 4 and the dummy trench 40 (row 300), i.e. without dummy contact. IGBT V ce-sat E off E on E rec E tot 100 1,48 V 16,85 mJ 8 mJ 36,13 mJ 44,13 mJ 200 1,61 V 14,56 mJ 12,92 mJ 31,7 mJ 44,6 mJ 300 1,42 V 18,94 mJ

[0089] Fig. 16 shows another embodiment of the semiconductor device 100, which is similar to that of Fig. 3. In contrast to the embodiment of Fig. However, in FIG. 3, a first enhancement region 16 is arranged between the drift layer 11 and the first base region 12. The first enhancement region 16 is of the first conductivity type, i.e., n-doped, and has a higher doping concentration than the drift layer 11, e.g., a doping concentration greater by a factor of at least 10. The enhancement region 16 improves turn-on losses or Vce-sat by reducing the hole leakage loss.

[0090] Fig. 17 shows an example of an IGBT similar to Fig. 16, but in which second enhancement regions 17, which are of the second conductivity type, i.e., p-doped, are arranged vertically between the second base regions 13 and the drift layer 11. These enhancement regions 17 lead to reduced electron leakage via the electrical contact of the main electrode 2 with the second contact region 15 and to improved hole accumulation during turn-off.

[0091] Fig. 18 shows an embodiment similar to that of Fig. 4, but additionally comprises the first enrichment region 16 between the first base region 12 and the drift layer 11.

[0092] The embodiment of Fig. 19 is that of Fig. 18. However, in the active trenches 4, the electrically insulating layer 5 between the gate electrodes 3 and the first contact regions 14 is thicker than between the second contact regions 15 and the gate electrodes 3. This design can reduce the Vth of the PMOS transistor, enabling its early turn-on during IGBT off-states to further reduce switching losses. In turn, the doping concentration in the second base regions 13 can be further increased to reduce hole leakage by diffusion in the IGBT on-state.

[0093] In the example of Fig. 20, the first contact region 14 extends over the entire lateral extent of the first base region 12 in the first lateral direction L1. In other words, the first contact region 14 extends in the first lateral direction L1 from one active trench 4 to the next active trench 4. In this way, the hole path from the drift layer 11 to the main electrode 2 via the first base region 12 can be completely suppressed.

[0094] In the example of Fig. 21, the second contact regions 15 have the same lateral extent in the first lateral direction L1 as the second base regions 13. In other words, the second contact regions 15 extend in the first lateral direction L1 from the respective active trench 4 to the next dummy trench 40.

[0095] The embodiment of Fig. 22 is that of Fig. 21. However, the trenches on both sides of the second base regions 13 are now active trenches 4. In this embodiment, PMOS transistors are formed on both active trenches 4, which border the respective second base region 13.

[0096] The embodiment of Fig. 23 shows a similar embodiment as in Fig. 22, but with additional dummy trenches 40, between which the four active trenches 4 are arranged in the first lateral direction L1. Additional second base regions 13 are formed between the dummy trenches 40 and the active trenches 4. With the additional dummy trenches 40, the Miller capacitance Cgc can be further reduced.

[0097] In the example of Fig. 24 are in contrast to Fig. 23 second contact regions 15 are formed in the further second base regions 13. The main electrode 2 can also be in electrical contact with these second contact regions 15.

[0098] In the example of Fig. 25, the second base regions 13 are formed only between the active trenches 4 and the dummy trench 40. Third base regions 18 of the second conductivity type are formed on the other side of the dummy trenches 40. The dummy trenches 40 and the active trenches 4 extend deeper into the semiconductor body 1 than the base regions 12, 13, 18.

[0099] In the example of Fig. 26 is a planar IGBT 100 similar to that of Fig. 2. In addition, an enrichment region 16 of the first conductivity type is arranged between the first base region 12 and the drift layer 11.

[0100] Fig. 31 shows an embodiment of a planar IGBT 100 with a non-uniform thickness of the electrically insulating layer 5 for reducing the gate capacitance.

[0101] Fig. 27 shows an embodiment of a semiconductor device 100 in a plan view of the top side 10. As can be seen here, the base regions 12, 13 and the contact regions 14, 15 are elongated, wherein main extension directions each run parallel to a second lateral direction L2, which runs perpendicular to the first lateral direction L1.

[0102] In the example of Fig. 28, a plurality of first contact regions 14 are embedded in the same first base region 12. These first contact regions 14 are arranged one behind the other and spaced apart from each other in the second lateral direction L2.

[0103] In Fig. 29, a plurality of second contact regions 15 are embedded in the second base region 13. The second contact regions 15 are arranged one behind the other and spaced apart from each other in the second lateral direction L2. Unlike in Fig. 29, the first contact areas 14 do not have to be exactly opposite the second contact areas 15, but can be arranged in a staggered configuration.

[0104] Contrary to what was shown in the exemplary embodiments, the thicknesses (depths) of the first base region 12 and the one or more second base regions 13 could be different from each other. The distances between the trenches 4, 40 could also be different from each other.

[0105] Fig. 30 shows a flowchart of an embodiment of the method for manufacturing a semiconductor device.

[0106] In a step S1, a semiconductor body having a top side and a drift layer of a first conductivity type is provided. In further steps S2, S3, S4 and S5, a first base region, a second base region, a first contact region and a second contact region are produced. The first base region is of a second conductivity type and is produced such that the first base region lies vertically between the drift layer and the top side. The second base region is of the first conductivity type and is produced such that the second base region lies vertically between the drift layer and the top side, wherein the second base region has a higher doping concentration than the drift layer and borders the drift layer. The first contact region is of the first conductivity type and is produced such that the first contact region borders the first base region and the top side.The second contact region is of the second conductivity type and is formed such that the second contact region adjoins the second base region and the top surface. In a further step S6, a main electrode is applied to the top surface, and electrical contact is established between the main electrode and the first contact region, as well as between the main electrode and the second contact region. In a further step S7, a gate electrode is formed such that the gate electrode ultimately lies between the first contact region and the second contact region, as well as between the first base region and the second base region, in a first lateral direction.

[0107] The embodiments shown in the figures, as indicated, represent embodiments of the improved semiconductor device and the improved method for manufacturing a semiconductor device; therefore, they do not represent a complete list of all embodiments according to the improved semiconductor device and the improved method. Actual semiconductor devices and methods may differ from the embodiments shown, for example, in arrangements and elements. Reference symbol 1 semiconductor body 2 Main electrode 3 Gate electrode 4 active trench 5 electrically insulating material 6 additional main electrodes 10 Top 11 Drift layer 12 first base area 13 second base area 14 first contact area 15 second contact area 16 first enrichment area 17 second enrichment area 18 third base area 19 shift 20 layers 40 Dummy trench 100 semiconductor devices 200 reference semiconductor devices Si process step L1 first lateral direction L2 second lateral direction V vertical direction 100_i Designation for curves 200_i Designation for curves

Claims

[1] A semiconductor device (100) comprising: - a semiconductor body (1) with a top side (10), - a main electrode (2) on the top side (10) and - a gate electrode (3), wherein - the semiconductor body (1) comprises: - a drift layer (11) of a first conductivity type, - a first base region (12) of a second conductivity type arranged vertically between the drift layer (11) and the top side (10), - a second base region (13) of the first conductivity type, which is arranged vertically between the drift layer (11) and the top side (10), wherein the second base region (13) has a higher doping concentration than the drift layer (11) and is adjacent to the drift layer (11), - a first contact region (14) of the first conductivity type, wherein the first contact region (14) adjoins the first base region (12) and the top side (10), - a second contact region (15) of the second conductivity type, wherein the second contact region (15) adjoins the second base region (13) and the top side (10), - the main electrode (2) is in electrical contact with the first contact area (14) and the second contact area (15), - in a first lateral direction (L1) at least a part of the gate electrode (3) is arranged between the first contact region (14) and the second contact region (15) and between the first base region (12) and the second base region (13). [2] A semiconductor device according to claim 1, wherein - the semiconductor device (100) is designed such that by adjusting the electrical potential of the gate electrode (3), - either a zone of the first base region (12) is inverted by means of the gate electrode (3) and a current flow of charge carriers of the first type between the drift layer (11) and the first contact region (14) is enabled through this zone, - or a zone of the second base region (13) is inverted by means of the gate electrode (3) and a current flow of charge carriers of the second type between the drift layer (11) and the second contact region (14) is enabled through this zone. [3] A semiconductor device (100) according to claim 1 or 2, wherein - the semiconductor device (100) is a planar device, wherein the gate electrode (3) is arranged on the top side (10). [4] A semiconductor device (100) according to claim 1 or 2, wherein - the semiconductor device (100) is a trench device, wherein the gate electrode (3) is arranged in an active trench (4) which extends from the top side (10) in a vertical direction (V) into the semiconductor body (1). [5] The semiconductor device (100) of claim 4, further comprising: - at least one dummy trench (40) arranged adjacent to the active trench (4) and spaced from the active trench (4) in the first lateral direction (L1), wherein - the dummy trench (40) is filled with an electrically conductive material which is electrically connected to the main electrode (2). [6] Semiconductor device (100) according to one of the preceding claims, wherein - an enrichment region (16) of the first conductivity type is arranged vertically between the first base region (12) and the drift layer (11), - the enrichment region (16) has a higher doping concentration than the drift layer (11). [7] Semiconductor device (100) according to one of the preceding claims, wherein - a third base region (18) of the second conductivity type is arranged in the first lateral direction (L1) next to the second base region (13), so that the second base region (13) is arranged in the first lateral direction (L1) between the first (12) and the third (18) base region. [8] A semiconductor device (100) according to claim 7 as dependent on claim 4, wherein - the third base region (18) extends from the top side (10) into the semiconductor body (1) and deeper than the active trench (4) into the semiconductor body (1). [9] Semiconductor device (100) according to one of the preceding claims, wherein - a thickness of an insulating material (5) between the first contact region (14) and / or the first base region (12) and the gate electrode (3) is greater than a thickness of an insulating material (5) between the second contact region (15) and / or the second base region (13) and the gate electrode (3). [10] Semiconductor device (100) according to one of the preceding claims, wherein - the main electrode (2) is not in direct electrical contact with the second base region (13). [11] A semiconductor device (100) according to claim 2 or any one of claims 3 to 10 when dependent on claim 2, further comprising: - a further gate electrode (3) which is spaced from the gate electrode (3) in the first lateral direction (L1), wherein - the second base region (13) is arranged in the first lateral direction (L1) between the gate electrode (3) and the further gate electrode (3), - the semiconductor device (100) is designed such that by adjusting the electrical potential of the further gate electrode (3), a zone of the second base region (13) is inverted by means of the further gate electrode (3), wherein the zone is located on a side of the second base region (13) which is opposite the side of the second base region (13) on which the zone of the second base region (13) is inverted by means of the gate electrode (3), and thereby provides a current path on this opposite side. [12] Semiconductor device (100) according to one of the preceding claims, wherein - the first (14) and / or the second (15) contact area are elongated areas extending in a second lateral direction (L2) which is oblique to the first lateral direction (L1). [13] A semiconductor device (100) according to any one of the preceding claims, comprising: - a plurality of first contact regions (14) which adjoin the top side (10) and the first base region (12) and are in electrical contact with the main electrode (2), wherein the first contact regions (14) are separated and spaced apart from one another in a second lateral direction (L2) which is oblique to the first lateral direction (L1), and / or - a plurality of second contact regions (15) adjacent to the top side (10) and the second base region (13) and in electrical contact with the main electrode (2), wherein the second contact regions (15) are separated and spaced apart from one another in a second lateral direction (L2) which is oblique to the first lateral direction (L1). [14] Semiconductor device (100) according to one of the preceding claims, wherein - the semiconductor device (100) is an IGBT. [15] A method of manufacturing a semiconductor device (100), comprising: - Providing a semiconductor body (1) with a top side (10) and a drift layer (11) of a first conductivity type, - Produce - a first base region (12) which is of a second conductivity type, so that the first base region (12) lies vertically between the drift layer (11) and the top side (10), - a second base region (13) which is of the first conductivity type, such that the second base region (13) lies vertically between the drift layer (11) and the top side (10), wherein the second base region (13) has a greater doping concentration than the drift layer (11) and adjoins the drift layer (11), - a first contact region (14) of the first conductivity type, so that the first contact region (14) adjoins the first base region (12) and the top side (10), - a second contact region (15) of the second conductivity type, so that the second contact region (15) adjoins the second base region (13) and the top side (10), - applying a main electrode (2) to the top side (10) and establishing an electrical contact between the main electrode (2) and the first contact region (14) and between the main electrode (2) and the second contact region (15), - forming a gate electrode (3) such that finally at least a part of the gate electrode (3) lies in a first lateral direction (L1) between the first contact region (14) and the second contact region (15) and between the first base region (12) and the second base region (13).

Images