SEMICONDUCTOR DEVICE, METHOD FOR DESIGNING THE SAME AND METHOD FOR MANUFACTURING THE SAME

Abstract

According to one embodiment, a semiconductor device comprises a first cell. The first cell comprises a first PMOS transistor, a second PMOS transistor arranged side-by-side with the first PMOS transistor, a first NMOS transistor, a second NMOS transistor arranged side-by-side with the first NMOS transistor, and a seventh interconnection that is not electrically coupled to the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor.

Description

AREA

[0001] The embodiments described herein generally relate to a semiconductor device, a method of designing the same, and a method of manufacturing the same. STATE OF THE ART

[0002] In a semiconductor device array design, an automatic placement and routing technique can be used to automatically perform cell placement and coupling. CITATION LISTPATENT LITERATURE

[0003] Patent Literature 1: Japanese Patent Application KOKAI Publication No. 2012-43894 SUMMARYTECHNICAL PROBLEM

[0004] An embodiment of the present invention provides a semiconductor device capable of suppressing an increase in development costs and a prolongation of the development work period. SOLUTION TO THE PROBLEM

[0005] A semiconductor device according to one embodiment comprises a first cell. The first cell comprises a first PMOS transistor, a second PMOS transistor arranged side by side with the first PMOS transistor in a first direction and configured to share one end with one end of the first PMOS transistor, a first NMOS transistor arranged side by side with the first PMOS transistor in a second direction crossing the first direction, a second NMOS transistor arranged side by side with the first NMOS transistor in the first direction and configured to share one end with one end of the first NMOS transistor, a first interconnection electrically connected to another end of the first PMOS transistor, a second interconnection electrically connected to one end of the first PMOS transistor and one end of the second PMOS transistor, a third interconnection,which is electrically connected to another end of the second PMOS transistor, a power supply voltage connection extending in the second direction, provided over the first connection, the second connection, and the third connection, and electrically connected to the first connection, the second connection, and the third connection, a fourth connection electrically connected to another end of the first NMOS transistor, a fifth connection electrically connected to one end of the first NMOS transistor and one end of the second NMOS transistor, a sixth connection electrically connected to the other end of the second NMOS transistor, a ground voltage connection extending in the second direction, provided over the fourth connection, the fifth connection, and the sixth connection, and electrically connected to the fourth connection,the fifth connection and the sixth connection, and a seventh connection provided in the same layer as the first to sixth connections and not electrically connected to the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram illustrating the overall configuration of a semiconductor device according to a first embodiment. Fig. 2 is a circuit diagram of a memory cell array included in the semiconductor device according to the first embodiment. Fig. 3 is a cross-sectional view of a PMOS transistor included in the semiconductor device according to the first embodiment. Fig. 4 is a cross-sectional view of an NMOS transistor included in the semiconductor device according to the first embodiment. Fig. 5 is a plan view of a standard cell of a NAND circuit included in the semiconductor device according to the first embodiment. Fig. 6 is a plan view of a standard cell of a NOR circuit included in the semiconductor device according to the first embodiment. Fig. 7 is a plan view of a standard cell of an inverter circuit included in the semiconductor device according to the first embodiment. Fig. 8 is a plan view of a standard cell of a buffer circuit included in the semiconductor device according to the first embodiment. Fig. 9 is a plan view of a transistor of an ECO basic cell included in the semiconductor device according to the first embodiment. Fig. 10 is a plan view of an ECO basic cell in which a decoupling capacitor included in the semiconductor device according to the first embodiment is configured. Fig. 11 is an equivalent circuit diagram of the ECO basic cell in which the decoupling capacitor included in the semiconductor device according to the first embodiment is configured. Fig. 12 is a plan view of an ECO basic cell in which the NAND circuit included in the semiconductor device according to the first embodiment is configured. Fig. 13 is a plan view of an ECO basic cell in which the NOR circuit included in the semiconductor device according to the first embodiment is configured. Fig. 14 is a plan view of an ECO basic cell in which the inverter circuit included in the semiconductor device according to the first embodiment is configured. Fig. 15 is a plan view of an ECO basic cell in which the buffer circuit included in the semiconductor device according to the first embodiment is configured. Fig. 16 is a plan view of an ECO basic cell in which a through cell included in the semiconductor device according to the first embodiment is configured. Fig. 17 is an equivalent circuit diagram of the ECO basic cell in which the pass cell included in the semiconductor device according to the first embodiment is configured. Fig. 18 is a plan view of a fill cell included in the semiconductor device according to the first embodiment. Fig. 19 is a plan view illustrating a specific example of using the through cell in the semiconductor device according to the first embodiment. Fig. 20 is a flowchart of a method for manufacturing the semiconductor device according to the first embodiment. Fig. 21 is a flowchart of the method for manufacturing the semiconductor device according to the first embodiment. Fig. 22 is a diagram illustrating an example of a planar arrangement after placement of the standard cell in a layout design of the semiconductor device according to the first embodiment. Fig. 23 is a diagram illustrating an example of the planar arrangement after placement of the ECO basic cell in which the decoupling capacitor is configured in the arrangement design of the semiconductor device according to the first embodiment. Fig. 24 is a diagram illustrating an example of the planar arrangement after placement of the fill cell in the arrangement design of the semiconductor device according to the first embodiment. Fig. 25 is a diagram illustrating an example of the planar arrangement after changing an ECO logic cell in the arrangement design of the semiconductor device according to the first embodiment. Fig. 26 is a diagram illustrating an example of the planar arrangement after changing the via cell in the arrangement design of the semiconductor device according to the first embodiment. Fig. 27 is a plan view illustrating a specific example of using a through cell in a semiconductor device according to a first modification of the first embodiment. Fig. 28 is a plan view illustrating a specific example of using the through cell in the semiconductor device according to the first modification of the first embodiment. Fig. 29 is a plan view illustrating a specific example of using the through cell in the semiconductor device according to the first modification of the first embodiment. Fig. 30 is a plan view of a transistor of an ECO basic cell included in a semiconductor device according to a second modification of the first embodiment. Fig. 31 is a plan view of the transistor of the ECO basic cell included in the semiconductor device according to the second modification of the first embodiment. Fig. 32 is a plan view of an ECO basic cell in which a through cell including a decoupling capacitor through an NMOS transistor included in a semiconductor device according to a third modification of the first embodiment is configured. Fig. 33 is an equivalent circuit diagram of the ECO basic cell in which the through cell including the decoupling capacitor through the NMOS transistor included in the semiconductor device according to the third modification of the first embodiment is configured. Fig. 34 is a plan view of an ECO basic cell in which a through cell comprising a decoupling capacitor through a PMOS transistor included in the semiconductor device according to the third modification of the first embodiment is configured. Fig. 35 is an equivalent circuit diagram of the ECO basic cell in which the pass cell including the decoupling capacitor is configured by the PMOS transistor included in the semiconductor device according to the third modification of the first embodiment. Fig. 36 is a flowchart of a method of manufacturing a semiconductor device according to a fourth modification of the first embodiment. Fig. 37 is a flowchart of the method of manufacturing the semiconductor device according to the fourth modification of the first embodiment. Fig. 38 is a block diagram illustrating an overall configuration of a semiconductor device according to a second embodiment. Fig. 39 is a block diagram illustrating an overall configuration of a semiconductor device according to a third embodiment. Fig. 40 is a block diagram illustrating an overall configuration of a semiconductor device according to a fourth embodiment. Fig. 41 is a block diagram illustrating an overall configuration of a semiconductor device according to a fifth embodiment. Fig. 42 is a circuit diagram of a memory cell array included in the semiconductor device according to the fifth embodiment. DETAILED DESCRIPTION

[0006] The embodiments will be described later with reference to the drawings. In the following description, components having substantially the same function and configuration are denoted by the same reference numerals. Redundant descriptions may be omitted where unnecessary. In addition, each of the embodiments described below illustrates an apparatus and a method for embodying the technical idea of the embodiment. The technical idea of the embodiments does not determine the materials, shapes, structures, placements, and the like of the components as follows. Various modifications can be made to the technical idea of the embodiments without departing from the gist of the invention. The embodiments and the r Modifications are included in the invention described in the claims and their equivalent scope. 1. First embodiment

[0007] A semiconductor device according to a first embodiment will be described. In the present embodiment, a case where the semiconductor device is a NAND flash memory will be described. Note that a semiconductor device 1 may be a non-volatile semiconductor memory device other than a NAND flash memory. For example, the semiconductor device 1 may be a ferroelectric random access memory (FeRAM). Furthermore, the semiconductor device 1 may be a device other than the semiconductor memory device. 1.1 Overall configuration of the semiconductor device

[0008] First, an example of an overall configuration of the semiconductor device 1 will be described with reference to Fig. 1 described. Fig. 1 is a block diagram illustrating the overall configuration of the semiconductor device 1. In Fig. 1, part of the coupling between components is shown by an arrow line, but the coupling between components is not limited to this.

[0009] The semiconductor device 1 is, for example, a NAND flash memory. The NAND flash memory includes a plurality of non-volatile memory cell transistors (also referred to as memory cells).

[0010] The semiconductor device 1 is coupled to a controller (not shown) provided externally. The semiconductor device 1 operates based on an instruction from an external controller.

[0011] The semiconductor device 1 includes a memory cell array 10, an input / output circuit 11, an instruction register 12, an address register 13, a sequencer 14, a voltage generator 15, a driver 16, a row control circuit 17, and a sense amplifier 18.

[0012] The memory cell array 10 is a set of a plurality of arranged memory cell transistors. The memory cell array 10 comprises a plurality of blocks BLK. In the example of Fig. 1, the memory cell array 10 includes four blocks BLK0, BLK1, BLK2, and BLK3. The BLK blocks are, for example, a set of a plurality of memory cell transistors from which data is collectively erased. Each memory cell transistor is connected to a row and a column. More specifically, the memory cell array 10 includes a plurality of bit lines and a plurality of word lines. Each memory cell is connected to, for example, a bit line and a word line. A detailed configuration of the memory cell array 10 will be described later.

[0013] The input / output circuit 11 is a circuit that inputs and outputs signals to and from an external controller. That is, the input / output circuit 11 functions as an interface circuit on the semiconductor device 1 side between the semiconductor device 1 and the external controller.

[0014] The input / output circuit 11 transmits and receives a signal DQ and clock signals DQS and DQSn to and from the external controller. For example, the signal DQ is data DT, address information ADD, or a command CMD. For example, the command CMD includes an instruction that causes the sequencer 14 to execute a read operation, a write operation, an erase operation, and the like. The clock signals DQS and DQSn are clock signals used at the time of inputting and outputting the data DT. The clock signal DQSn is an inverted signal of the clock signal DQS.

[0015] The input / output circuit 11 is coupled to the instruction register 12, the address register 13, and the sense amplifier 18. The input / output circuit 11 sends the instruction CMD to the instruction register 12. The input / output circuit 11 sends the information ADD to the address register 13. The input / output circuit 11 sends the data DT (write data) to the sense amplifier 18. In addition, the input / output circuit 11 receives the data DT (read data) from the sense amplifier 18.

[0016] The input / output circuit 11 receives various control signals from the external controller. For example, the semiconductor device 1 receives an instruction latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, and a read enable signal REn from the external controller. The instruction latch enable signal CLE is a signal indicating that the signal DQ received from the external controller is the instruction CMD. The address latch enable signal ALE is a signal indicating that the signal DQ received from the external controller is the address information ADD. The write enable signal WEn is a signal instructing the semiconductor device 1 to input the signal DQ. The read enable signal REn is a signal instructing the semiconductor device 1 to output the signal DQ.

[0017] The input / output circuit 11 sends a ready / busy signal RBn to the external controller. The ready / busy signal RBn is a signal indicating whether the semiconductor device 1 is in a busy state or a ready state. The busy state is a state in which the semiconductor device 1 cannot receive the DQ signal from the external controller. The ready state is a state in which the semiconductor device 1 can receive the DQ signal from the external controller.

[0018] For example, the input / output circuit 11 functions as a digital signal control circuit (also called a “logic circuit”) that processes digital signals such as the DQ signal and the control signal received from the external controller.

[0019] Instruction register 12 temporarily stores the CMD instruction. Instruction register 12 is coupled to sequencer 14. Instruction register 12 sends the CMD instruction to sequencer 14.

[0020] The instruction register 12 has the function of a digital signal control circuit that processes the received digital signal (instruction CMD).

[0021] The address register 13 temporarily stores the address information ADD. For example, the address information ADD includes a block address, a page address (word row address), and a column address. The block address, the page address, and the column address are used to select the BLK block, the word line, and the bit line in the memory cell array 10. The address register 13 is coupled to the driver 16, the row control circuit 17, and the sense amplifier 18. For example, the address register 13 sends the page address to the driver 16. The address register 13 sends the block address to the row control circuit 17. The address register 13 sends the column address to the sense amplifier 18. Hereinafter, the BLK block selected based on the block address is referred to as the selected BLK block. The word line selected based on the page address is referred to as the selected word line.

[0022] The address register 13 has the function of a digital signal control circuit that processes the received digital signal (address information ADD).

[0023] The sequencer 14 controls the entire operation of the semiconductor device 1. The sequencer 14 is coupled to, for example, the voltage generator 15, the driver 16, the row control circuit 17, and the sense amplifier 18. The sequencer 14 controls the voltage generator 15, the driver 16, the row control circuit 17, the sense amplifier 18, and the like. For example, the sequencer 14 executes the read operation, the write operation, the erase operation, and the like based on the CMD instruction.

[0024] The sequencer 14 functions as a digital signal control circuit that processes the received digital signal (for example, the CMD instruction).

[0025] The voltage generator 15 generates various voltages under the control of the sequencer 14. The voltage generator 15 is coupled to the driver 16. The voltage generator 15 supplies the generated voltages to the driver 16.

[0026] The voltage generator 15 includes a digital signal control circuit 15a. The digital signal control circuit 15a is a circuit that processes the received digital signal (control signal received from the sequencer 14).

[0027] Driver 16 is a circuit that supplies voltages to row control circuit 17 and sense amplifier 18. Driver 16 is coupled to row control circuit 17 and sense amplifier 18. More specifically, driver 16 supplies a variety of voltages used in read, write, and erase operations, and the like, to row control circuit 17 and sense amplifier 18 based on the control of sequencer 14. Driver 16 is coupled to row control circuit 17 via a variety of interconnections (or interconnections) CGI. For example, driver 16 applies a predetermined voltage to each of the interconnections CGI based on the page address.

[0028] The driver 16 includes a digital signal control circuit 16a. The digital signal control circuit 16a is a circuit that processes the received digital signal (address information ADD and control signal received from the sequencer 14).

[0029] The row control circuit 17 is a circuit that controls connections (word lines and select gate lines) in the row direction of the memory cell array 10. The row control circuit 17 is coupled to the memory cell array 10. For example, the row control circuit 17 selects a block BLK in the memory cell array 10 based on the block address. For example, the row control circuit 17 transmits a voltage applied to the connection CGI corresponding to the selected word line to the selected word line in the selected block BLK.

[0030] The row control circuit 17 includes a digital signal control circuit 17a. The digital signal control circuit 17a is a circuit that processes the received digital signal (address information ADD and control signal received from the sequencer 14).

[0031] The sense amplifier 18 is a circuit that controls connections (bit lines) in the column direction of the memory cell array 10. The sense amplifier 18 is coupled to the memory cell array 10. During the write operation, the sense amplifier 18 applies a voltage to each bit line of the memory cell array 10 based on the write data DT. In addition, during the read operation, the sense amplifier 18 determines the data stored in the memory cell transistor based on the bit line voltage and transmits a determination result to the input / output circuit 11 as read data DT.

[0032] The sense amplifier 18 includes a digital signal control circuit 18a. The digital signal control circuit 18a is a circuit that processes the received digital signal (address information ADD and control signal received from the sequencer 14). 1.2 Circuit configuration of the memory cell array

[0033] Next, an example of a circuit configuration of the memory cell array 10 will be described with reference to Fig. 2 described. Fig. 2 is a circuit diagram of the memory cell array 10. It should be noted that the example in Fig. 2 illustrates a circuit configuration of a block BLK.

[0034] As in Fig. 2, the block BLK contains a plurality of string units SU. The string unit SU comprises a plurality of NAND strings NS. In the example of Fig. 2, each BLK block comprises four string units SU0 to SU3. The SU string unit, for example, is a set of multiple NAND strings that are collectively selected during a write or read operation. Note that the number of BLK blocks in the memory cell array 10 and the number of SU string units in the BLK block are arbitrary.

[0035] The NAND string NS comprises a plurality of memory cell transistors MC and selection transistors ST1 and ST2. In the example of Fig. 2, the NAND string NS comprises eight memory cell transistors MC0 to MC7. Note that the number of memory cell transistors MC contained in the NAND string NS is arbitrary.

[0036] The memory cell transistor MC is a memory element that stores data non-volatilely. The memory cell transistor MC comprises a control gate and a charge storage film. The memory cell transistor MC can be of the metal oxide nitride oxide silicon (MONOS) or floating gate (FG) type. The MONOS type uses an insulating layer for the charge storage film. The FG type uses a conductor for the charge storage film.

[0037] The selection transistors ST1 and ST2 are switching elements. The selection transistors ST1 and ST2 are each used to select the string unit SU during different operations. The number of selection transistors ST1 and ST2 included in the NAND string NS is arbitrary. At least one of the selection transistors ST1 and ST2 must be included in the NAND string NS.

[0038] The current paths of the selection transistor ST2, the memory cell transistors MC0 to MC7, and the selection transistor ST1 in the NAND string NS are connected in series. A drain of the selection transistor ST1 is connected to the bit line BL. A source of the selection transistor ST2 is connected to a source line SL.

[0039] The control gates of the transistors of memory cells MC0 to MC7 in the same BLK block are generally connected to the word lines WL0 to WL7. More specifically, the control gates of the transistors of memory cells MC0 in the BLK block are generally connected to a word line WL0. The same applies to the transistors of memory cells MC1 to MC7.

[0040] The gates of a plurality of selection transistors ST1 in the string unit SU are generally coupled to a select gate line SGD. More specifically, the gates of the selection transistors ST1 in the string unit SU0 are generally coupled to a select gate line SGD0. The gates of the selection transistors ST1 in the string unit SU1 are generally coupled to a select gate line SGD1. The gates of the selection transistors ST1 in the string unit SU2 are generally connected to a select gate line SGD2. The gates of the selection transistors ST1 in the string unit SU3 are generally connected to a select gate line SGD3.

[0041] The gates of a plurality of selection transistors ST2 in block BLK are generally coupled to a selection gate line SGS. Note that, as with the selection gate line SGD, a different selection gate line SGS can be provided for each string unit SU.

[0042] The word lines WL0 to WL7, the select gate lines SGD0 to SGD3 and the select gate line SGS are coupled to the row control circuit 17.

[0043] The bit line BL is generally coupled to a NAND string NS in each string unit SU of each block BLK. The NAND strings NS coupled to a bit line BL are assigned the same column address. Each bit line BL is coupled to the sense amplifier 18.

[0044] For example, the source line SL is shared by the blocks BLK.

[0045] For example, a set of memory cell transistors MC coupled to the common word line WL in a string unit SU is referred to as a "cell unit CU." For example, the write and read operations are performed in units of the cell unit CU. 1.3 Automatic placement and routing

[0046] Next, automatic placement and routing will be described. In the present embodiment, an automatic placement and routing technique of a standard cell method is applied to the layout design of various digital control circuits included in the semiconductor device 1. In the automatic placement and routing of the standard cell method, the layout design is created by placing various cells (circuit blocks) side by side without gaps on a semiconductor substrate. For example, the circuit may be changed after the layout design. If the layout is corrected while suppressing the change from the original layout data as much as possible, this is called an engineering change order (ECO).The change order includes a device change order (also referred to as pre-mask ECO) and a metal change order (also referred to as post-mask ECO). The device change order makes a change encompassing the layout (hereinafter also referred to as "device layout") of various cells (transistors / circuit blocks). The metal change order changes the interconnect arrangement without changing the device layout.

[0047] For example, a standard cell (also called a "logic cell"), an ECO base cell, and a filler cell are used for automatic location and routing. If it is not specified below whether a cell is a standard cell, an ECO base cell, or a filler cell, the cell is simply referred to as a "cell."

[0048] The standard cell and the ECO base cell comprise a plurality of p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) (hereinafter referred to as "PMOS transistors") and n-channel MOSFETs (hereinafter referred to as "NMOS transistors"). If it is not specified below whether the transistor is a PMOS transistor or an NMOS transistor, the transistor will be referred to simply as a "transistor."

[0049] The transistors in the cell are coupled together by an M1 interconnect of a bottom layer. An M2 interconnect is provided above the M1 interconnect. A power supply voltage VDD or a ground voltage VSS is provided to the transistor via the M2 interconnect. That is, the M2 interconnect functions as a power supply voltage connection or ground voltage connection. An M3 interconnect is provided above the M2 interconnect. An M4 interconnect is provided above the M3 interconnect. For example, the M3 interconnect and the M4 interconnect are used for coupling between cells. The number of layers of interconnections used for automatic placement and routing is not limited to four. The number of layers of interconnections used for automatic placement and routing only needs to be three or more.

[0050] A standard cell is a cell in which a NAND (exclusive AND) circuit, a NOR (exclusive OR) circuit, an inverter circuit, a buffer circuit, or the like are configured in advance. In a standard cell, the placement of the transistor, the M1 interconnect, and the M2 interconnect connected to it are designed in advance. The type and number of transistors included in a standard cell are based on the circuit to be configured. The placement of the standard cell and the M3 and M4 interconnects connected to the standard cell are determined by automatic placement and routing.

[0051] The ECO basic cell is a cell equivalent to the metal ECO. In the ECO basic cell, the function of the circuit can be changed by changing the coupling between the transistors placed in the ECO basic cell, that is, the arrangement of the M1 connection by the metal ECO. In automatic placement and routing, the ECO basic cell is placed in a gap after the standard cell is placed. For example, a change in the circuit design may occur after the cell placement is completed. If this happens, the change in the circuit design can be handled by performing the metal ECO of the ECO basic cell without changing the cell placement.

[0052] In the ECO base cell, the location of the transistor is determined in advance. For example, the ECO base cell includes two PMOS transistors and two NMOS transistors. The location of the ECO base cell and the interconnects M1 to M4 connected to the corresponding transistors of the ECO base cell are designed through automatic placement and routing.

[0053] The ECO basic cell can configure the decoupling capacitor, NAND circuit, NOR circuit, inverter circuit, or buffer circuit according to the arrangement of the M1 connection. For example, the decoupling capacitor is configured in the ECO basic cell when the transistor is not used for the circuit configuration of the semiconductor device 1, that is, in a phase where metal ECO is not performed. The potential of each terminal of the transistor is determined by the configuration of the decoupling capacitor. When metal ECO is performed, the configuration of the ECO basic cell can be changed from the decoupling capacitor to the NAND circuit, NOR circuit, inverter circuit, or buffer circuit. Hereinafter, the ECO basic cell in which the NAND circuit, NOR circuit, inverter circuit, or buffer circuit is configured is also referred to as an "ECO logic cell."

[0054] Additionally, the ECO basic cell of the present embodiment can configure a pass-through cell by implementing metal ECO. The pass-through cell includes an M1 junction coupled to a transistor in the pass-through cell and an M1 junction used for coupling between two cells adjacent to the pass-through cell. The M1 junction used for coupling the adjacent cell is not connected to the transistor in the pass-through cell.

[0055] The filler cell is a cell arranged in a gap after the standard cell and the ECO basic cell. The filler cell includes an M2 junction and an n-type region corresponding to the PMOS transistor. The filler cell is not provided with a transistor. For example, a gap between the cells in a direction in which the M2 junction extends, if present, brings the M2 junctions into a state where the power supply and ground voltage connections are disconnected. By inserting the filler cell into the gap, the M2 junction is coupled between the adjacent cells. Likewise, an N-type well region between the adjacent cells is coupled by inserting the filler cell. 1.3.1 Cross-sectional configurations of PMOS transistor and NMOS transistor

[0056] Next, an example of cross-sectional configurations of the PMOS transistor and the NMOS transistor will be described with reference to the Fig. 3 and Fig. 4 described. Fig. 3 is a cross-sectional view of the PMOS transistor. Fig. 4 is a cross-sectional view of the NMOS transistor. In the examples of Fig. 3 and Fig. 4, an insulating film is omitted between the layers. In the following description, a direction parallel to a surface of the semiconductor substrate is referred to as the X direction. A direction parallel to the surface of the semiconductor substrate that intersects the X direction is defined as the Y direction. A direction that intersects the semiconductor substrate and the X direction and the Y direction is defined as the Z direction.

[0057] First, the configuration of the cross-section of a PMOS transistor TP is described. As in Fig. As shown in Figure 3, an n-type well region 101 is provided near a surface of a semiconductor substrate 100. The n-type recess region 101 is doped with, for example, phosphorus (P). In the n-type recess region 101, an area isolated by an element isolation region STI functions as the active region (AA) 102 of the PMOS transistor TP. For example, silicon oxide (SiO) is used for the element isolation region STI.

[0058] Two p + -Impurity diffusion regions 103 are provided near a surface of the active region 102. The p + -Impurity diffusion region 103 is doped with boron (B), for example. The two p + -Impurity diffusion regions 103 function as the source and drain of the PMOS transistor TP.

[0059] For example, the two p +-Impurity diffusion regions 103 are spaced apart in the X-direction. A gate insulating film 110 is formed on the active region 102 between the two p + -Impurity diffusion regions 103 are provided. The insulating film of the gate contains, for example, a metal oxide such as silicon oxide (SiO), silicon oxynitride (SiON), hafnium oxide (HfO), or hafnium oxynitride silicate (HfSiON).

[0060] A gate electrode 111 is provided on the gate insulating film. For example, the gate electrode 111 includes a conductive material such as polysilicon, tungsten (W), tungsten silicide (WSi), or titanium nitride (TiN). For example, the gate electrode 111 includes polysilicon or a stack of polysilicon and silicides such as nickel silicide (NiSi), nickel-platinum silicide (NiPtSi), and cobalt silicide (CoSi). For example, the gate electrode 111 includes a stack of silicon nitride (SiN), polysilicon and tungsten (W), and tungsten silicide (WSi). For example, the gate electrode 111 includes aluminum (Al), titanium (Ti), and tantalum (Ta). For example, the gate electrode 111 includes a stack of aluminum oxide (AlO), aluminum cobalt copper (AlCoCu), aluminum titanium nitride (AlTiN), aluminum titanium oxynitride (AlTiON), tantalum nitride (TaN), and titanium nitride (TiN).For example, electrode 111 includes a stack of silicides such as nickel silicide (NiSi), nickel platinum silicide (NiPtSi), and cobalt silicide (CoSi), polysilicon, and titanium nitride (TiN). For example, gate electrode 111 includes a stack of tungsten (W), tungsten silicon nitride (WSiN), tungsten (W), titanium nitride (TiN), polysilicon, and titanium nitride (TiN). The stacks described herein may not include all of the layers, but only some of the layers.

[0061] A contact plug 120 is placed on the p + impurity diffusion region 103 and the gate electrode 111. For example, the contact plug 120 has a columnar shape extending in the Z direction.

[0062] An M1 connection 130 is provided on the contact plug 120.

[0063] A contact plug 140 is provided on the M1 connector 130. For example, the contact plug 140 has a columnar shape extending in the Z direction.

[0064] An M2 connection 150 is provided on the contact plug 140. For example, the M2 connection 150 extends in the X direction.

[0065] A contact plug 160 is provided on the M2 connection 150. For example, the contact plug 160 has a columnar shape extending in the Z direction.

[0066] An M3 connection 170 is provided on the contact plug 160. For example, the M3 connection 170 extends in the Y direction.

[0067] A contact 180 is provided on the M3 connection 170. For example, the contact 180 has a columnar shape extending in the Z direction.

[0068] An M4 connection 190 is provided on contact 180. For example, M4 connection 190 extends in the X direction.

[0069] The M1 interconnect 130 and the M2 interconnect 150 contain, for example, tungsten (W). The M3 interconnect 170 and the M4 interconnect 190 contain, for example, tungsten (W), copper (Cu), or aluminum (Al). The M1 interconnect 130, the M2 interconnect 150, the M3 interconnect 170, and the M4 interconnect 190 contain a barrier metal such as titanium nitride (TiN), tantalum nitride (TaN), or a stack of tantalum nitride (TaN) and tantalum (Ta).

[0070] Next, the cross-sectional configuration of an NMOS transistor TN is described. As in Fig. As illustrated in Figure 4, a P-well region is provided near the surface of the semiconductor substrate 100 in a region surrounded by the element isolation region STI. The P-well region functions as the active region 104 of the NMOS transistor TN.

[0071] Two n + Impurity diffusion regions 105 are provided near a surface of the active region 104. The n + -Impurity diffusion region 105 is doped with phosphorus (P), for example. The two n + -Impurity diffusion regions 105 function as the source and drain of the NMOS transistor TN.

[0072] For example, the two n + -Impurity diffusion regions 105 are arranged apart from each other in the X-direction. A gate insulating film 110 is formed on the active region 104 between the two n + -Impurity diffusion regions 103 are provided. A gate electrode 111 is provided on the gate insulating film.

[0073] A contact plug 120 is on the area 105 of the n +-Impurity diffusion and the gate electrode 111. The configurations of the connections and the contact plugs above the contact plug 120 are similar to those described with respect to Fig. 3 were described. 1.3.2 Planar configuration of the standard cell

[0074] Next, an example of a planar configuration of the standard cell is described. The standard cells of the NAND circuit, the NOR circuit, the inverter circuit, and the buffer circuit are described below. 1.3.2.1 NAND circuit

[0075] First, an example of the planar configuration of the standard cell of the NAND circuit is shown with reference to Fig. 5 described. Fig. Figure 5 is a top view of the standard cell of the NAND circuit. In the example of Fig. 5, the insulating film between the layers is omitted. In the following description, either the source or drain of the transistor is referred to as one end of the transistor. The other end of the transistor is referred to as the other end of the transistor.

[0076] As in Fig. For example, as illustrated in Figure 5, the standard cell has a rectangular shape with one long side running in the Y direction and one short side running in the X direction. The same applies to the ECO base cell and the filler cell, which are described later.

[0077] For example, the lengths of the long sides of the corresponding cells (standard cell, ECO basic cell, and filler cell) are the same because they are compatible with automatic location and routing. The lengths of the short sides of the corresponding cells vary depending on the configuration of the cells. In addition, the positions of the M2 interconnections 150 and the N-type recess areas 101 of the standard cell, the ECO basic cell, and the filler cell are the same in the Y direction. When the corresponding cells are arranged side by side in the Y direction, the M2 interconnection 150 and the N-type recess area 101 between the cells are connected to each other.

[0078] A standard cell 1001 of the NAND circuit comprises an n-type recess region 101, PMOS transistors TP1 and TP2, NMOS transistors TN1 and TN2, M1 connections 130, M2 connections 150, and contacts 120 and 140.

[0079] In the example of Fig. 5, the n-type region 101 is provided on the top side, on the drawing sheet, of the standard cell 1001 of the NAND circuit.

[0080] The PMOS transistors TP1 and TP2 and the NMOS transistors TN1 and TN2 are arranged side by side in the Y direction. The PMOS transistors TP1 and TP2 are provided in the N-type recess region 101. In other words, in the N-type recess region 101, the active region 102 corresponding to the PMOS transistor TP1 and the active region 102 corresponding to the PMOS transistor TP2 are arranged side by side in the Y direction. In addition, the active region 104 corresponding to the NMOS transistor TN1 and the active region 104 corresponding to the NMOS transistor TN2 are arranged side by side in the Y direction.

[0081] The standard cell 1001 is equipped with four M2 connections 150_1 to 150_4 extending in the X direction. For example, the M2 connections 150_1 and 150_2 provided above the n-type region 101 (PMOS transistor TP) function as power supply voltage connections. The M2 connections 150_3 and 150_4 provided above the NMOS transistor TN function as ground voltage connections. Note that the number of M2 connections 150 serving as power supply voltage connections and ground voltage connections can be one, three, or more.

[0082] One ends of the PMOS transistors TP1 and TP2 are generally connected to the M2 connections 150_1 and 150_2 (power supply voltage connections) via an M1 connection 130_1.

[0083] One ends of the NMOS transistors TN1 and TN2 are generally connected via an M1 connection 130_2.

[0084] The other ends of the PMOS transistors TP1 and TP2 and the other end of the NMOS transistor TN1 are generally connected via an M1 connection 130_3. The M1 connection 130_3 functions as the output (OUT) connection of the NAND circuit.

[0085] The other end of the NMOS transistor TN2 is connected to the M2 connection 150_4 (ground voltage connection) via an M1 connection 130_4.

[0086] The gate electrode 111 of the PMOS transistor TP1 is connected to the gate electrode 111 of the NMOS transistor TN2 via an M1 connection 130_5. The M1 connection 130_5 functions as a signal input connection (IN1) of the NAND circuit.

[0087] The gate electrode 111 of the PMOS transistor TP2 is connected to the gate electrode 111 of the NMOS transistor TN1 via an M1 connection 130_6. The M1 connection 130_6 acts as the other connection for inputting signals (IN2) to the NAND circuit. 1.3.2.2 NOR circuit

[0088] Next, an example of the planar configuration of the standard cell of the NOR circuit is shown with reference to Fig. 6 described. Fig. Figure 6 is a top view of the standard cell of the NOR circuit. In the example of Fig. 6 the insulating film between the layers is omitted.

[0089] As in Fig. 6, a standard cell 1002 of the NOR circuit includes an N-type recess region 101, PMOS transistors TP3 and TP4, NMOS transistors TN3 and TN4, M1 connections 130, M2 connections 150, and contacts 120 and 140.

[0090] Similar to the standard cell 1001, the standard cell 1002 is provided with the n-type recess region 101 and the M2 interconnections 150_1 to 150_4. The positions of the n-type recess region 101 and the M2 interconnections 150_1 to 150_4 in the Y direction are similar to those of the standard cell 1001. The four M2 interconnections 150_1 to 150_4 each extend in the X direction.

[0091] The PMOS transistors TP3 and TP4 and the NMOS transistors TN3 and TN4 are arranged side by side in the Y direction. The PMOS transistors TP3 and TP4 are provided in the n-type recess region 101. In the n-type recess region 101, the active region 102 corresponding to the PMOS transistor TP3 and the active region 102 corresponding to the PMOS transistor TP4 are arranged side by side in the Y direction. In addition, the active region 104 corresponding to the NMOS transistor TN3 and the active region 104 corresponding to the NMOS transistor TN4 are arranged side by side in the Y direction.

[0092] One ends of the PMOS transistors TP3 and TP4 are generally connected via an M1 connection 130_10.

[0093] One ends of the NMOS transistors TN3 and TN4 are generally connected to the M2 connections 150_3 and 150_4 (ground voltage connections) via an M1 connection 130_11.

[0094] The other end of the PMOS transistor TP3 is connected to the M2 connections 150_1 and 150_2 (power supply voltage connections) via an M1 connection 130_12.

[0095] The other end of PMOS transistor TP4 and the other ends of NMOS transistors TN3 and TN4 are generally connected via an M1 connection 130_13. The M1 connection 130_13 serves as the output signal (OUT) connection of the NOR circuit.

[0096] The gate electrode 111 of the PMOS transistor TP3 is connected to the gate electrode 111 of the NMOS transistor TN4 via an M1 connection 130_14. The M1 connection 130_14 functions as a signal input connection (IN1) of the NOR circuit.

[0097] The gate electrode 111 of the PMOS transistor TP4 is connected to the gate electrode 111 of the NMOS transistor TN3 via an M1 connection 130_15. The M1 connection 130_15 acts as the other connection for inputting signals (IN2) to the NOR circuit. 1.3.2.3 Inverter circuit

[0098] Next, an example of the planar configuration of the standard cell of the inverter circuit is shown with reference to Fig. 7 described. Fig. Figure 7 is a top view of the standard cell of the inverter circuit. In the example of Fig. 7 the insulating film between the layers is omitted.

[0099] As in Fig. 7, the standard cell 1003 of the inverter circuit comprises an n-type region 101, a PMOS transistor TP5, an NMOS transistor TN5, M1 connections 130, M2 connections 150, and contacts 120 and 140.

[0100] Similar to the standard cell 1001, the standard cell 1003 is provided with the n-type recess region 101 and the M2 interconnections 150_1 to 150_4. The positions of the n-type recess region 101 and the M2 interconnections 150_1 to 150_4 in the Y direction are similar to those of the standard cell 1001. The four M2 interconnections 150_1 to 150_4 each extend in the X direction.

[0101] The PMOS transistor TP5 and the NMOS transistor TN5 are arranged side by side in the Y direction. The PMOS transistor TP5 is provided in the n-type recess region 101. The active region 102 corresponding to the PMOS transistor TP5 and the active region 104 corresponding to the NMOS transistor TN5 are arranged side by side in the Y direction.

[0102] One end of the PMOS transistor TP5 is connected to the M2 connections 150_1 and 150_2 (power supply voltage connections) via an M1 connection 130_20.

[0103] One end of the NMOS transistor TN5 is connected to the M2 connections 150_3 and 150_4 (ground voltage connections) via an M1 connection 130_21.

[0104] The other end of the PMOS transistor TP5 is connected to the other end of the NMOS transistor TN5 via an M1 connection 130_22. The M1 connection 130_22 serves as the connection for the output signal (OUT) of the inverter circuit.

[0105] The gate electrode 111 of the PMOS transistor TP5 is connected to the gate electrode 111 of the NMOS transistor TN5 via an M1 connection 130_23. The M1 connection 130_23 serves as a connection for the input signals (IN) of the inverter circuit. 1.3.2.4 Buffer circuit

[0106] Next, an example of the planar configuration of the standard cell of the buffer circuit is explained with reference to Fig. 8 described. Fig. Figure 8 is a top view of the standard cell of the buffer circuit. In the example of Fig. 8 the insulating film between the layers is omitted.

[0107] As in Fig. 8, a standard cell 1004 of the buffer circuit includes an N-type recess region 101, PMOS transistors TP6 and TP7, NMOS transistors TN6 and TN7, M1 interconnections 130, M2 interconnections 150, and contacts 120 and 140.

[0108] Similar to the standard cell 1001, the standard cell 1004 is provided with the N-type recess region 101 and the M2 interconnections 150_1 to 150_4. The positions of the N-type recess region 101 and the M2 interconnections 150_1 to 150_4 in the Y direction are similar to those in the standard cell 1001. The four M2 interconnections 150_1 to 150_4 each extend in the X direction.

[0109] PMOS transistors TP6 and TP7 are provided in the n-type recess region 101. PMOS transistors TP6 and TP7 are provided in an active region 102. PMOS transistors TP6 and TP7 are arranged side by side in the X direction. PMOS transistors TP6 and TP7 share a source or drain.

[0110] NMOS transistors TN6 and TN7 are provided in an active region 104. NMOS transistors TN6 and TN7 are arranged side by side in the X direction. NMOS transistors TN6 and TN7 share a source or drain.

[0111] One end of the PMOS transistor TP6 is connected to one end of the NMOS transistor TN6 via an M1 connection 130_30. The M1 connection 130_30 serves as the output connection (OUT) of the buffer circuit.

[0112] One end shared by PMOS transistors TP6 and TP7 (the other ends of PMOS transistors TP6 and TP7) is generally connected to M2 connections 150_1 and 150_2 (power supply voltage connections) via an M1 connection 130_31.

[0113] One end shared by NMOS transistors TN6 and TN7 (the other ends of NMOS transistors TN6 and TN6) is generally connected to M2 connections 150_3 and 150_4 (ground voltage connections) via an M1 connection 130_32.

[0114] One end of the PMOS transistor TP7, one end of the NMOS transistor TN7, the gate electrode 111 of the PMOS transistor TP6 and the gate electrode 111 of the NMOS transistor TN6 are generally connected via an M1 connection 130_33.

[0115] The gate electrode 111 of the PMOS transistor TP7 and the gate electrode 111 of the NMOS transistor TN7 are generally connected via an M1 connection 130_34. The M1 connection 130_34 functions as a connection for the input signals (IN) of the buffer circuit. 1.3.3 Planar configuration of the ECO basic cell

[0116] Next, an example of the planar configuration of the ECO basic cell is described. The following mainly describes the differences from the standard cell. 1.3.3.1 Planar configuration of the transistor of the ECO basic cell

[0117] First, an example of the planar configuration of the transistor of the ECO basic cell is presented with reference to Fig. 9 described. Fig. Figure 9 is a top view of the transistor of the ECO basic cell. In the example of Fig. 9, the insulating film between the layers, the M1 connection 130, the M2 connection 150 and the contact plugs 120 and 140 are omitted.

[0118] As in Fig. 9, an ECO basic cell 1010 includes an N-type recess region 101, PMOS transistors TP10 and TP11, and NMOS transistors TN10 and TN11.

[0119] Similar to the standard cell 1001, the N-type recessed region 101 is provided on the top surface of the ECO base cell 1010 on the drawing sheet. The position of the N-type recessed region 101 in the Y direction is similar to that of the standard cell 1001. Note that the positions of the M2 connections 150_1 to 150_4 (not shown) are also similar to those in the standard cell 1001.

[0120] PMOS transistors TP10 and TP11 are provided in the n-type recess region 101. PMOS transistors TP10 and TP11 are provided in an active region 102. PMOS transistors TP10 and TP11 are arranged side by side in the X direction. PMOS transistors TP10 and TP11 share a source or drain.

[0121] The NMOS transistors TN10 and TN11 are provided in an active region 104. The NMOS transistors TN10 and TN11 are arranged side by side in the X direction. The NMOS transistors TN10 and TN11 share a source or drain.

[0122] In the example of Fig. 9, a coupling portion 111a having a contact plug 120 (not illustrated) is provided at an end portion of the gate electrode 111 of each transistor. A width of the coupling portion 111a in the X direction is larger than a connection width (length in the X direction) of the gate electrode 111. Specifically, the coupling portion 111a is provided at the end portion of the gate electrode 111 extending in the Y direction so that both sides protrude in the X direction. Note that the shape of the coupling portion 111a is arbitrary. The width of the coupling portion 111a in the X direction may be the same as the connection width of the gate electrode 111. In other words, the coupling portion 111a may be eliminated. 1.3.3.2 Decoupling capacitor

[0123] Next, an example of a planar configuration of the ECO basic cell 1010 (ECO_C) in which the decoupling capacitor is configured is shown with respect to the Fig. 10 and Fig. 11 described. Fig. Figure 10 is a top view of the ECO base cell 1010 (ECO_C) in which the decoupling capacitor is configured. Fig. Figure 11 is an equivalent circuit diagram of the ECO basic cell 1010 (ECO_C) in which the decoupling capacitor is configured. In the example of Fig. 10 the insulating film between the layers is omitted.

[0124] As in Fig. 10, one end of the PMOS transistor TP10 and the gate electrodes 111 of the NMOS transistors TN10 and TN11 are generally coupled to the M2 connections 150_1 and 150_2 (power supply voltage connections) via an M1 connection 130_40.

[0125] One end shared by the PMOS transistors TP10 and TP11 (the other ends of the PMOS transistors TP10 and TP11) is generally connected to the M2 connections 150_1 and 150_2 (power supply voltage connections) via an M1 connection 130_41.

[0126] One end of the PMOS transistor TP11 is connected to the M2 connections 150_1 and 150_2 (power supply voltage connections) via an M1 connection 130_42.

[0127] One end of the NMOS transistor TN10 is connected to the M2 connections 150_3 and 150_4 (ground voltage connections) via an M1 connection 130_43.

[0128] One end shared by the NMOS transistors TN10 and TN11 (the other ends of the NMOS transistors TN10 and TN11) is generally connected to the M2 connections 150_3 and 150_4 (ground voltage connections) via an M1 connection 130_44.

[0129] One end of the NMOS transistor TN11 and the gate electrodes 111 of the PMOS transistors TP10 and TP11 are generally connected to the M2 connections 150_3 and 150_4 (ground voltage connections) via an M1 connection 130_45.

[0130] As in Fig. As illustrated in Figure 11, the power supply voltage VDD is applied to the source and drain of each of the PMOS transistors TP10 and TP11. The gate of each of the PMOS transistors TP10 and TP11 is grounded (the ground voltage VSS is applied). The source and drain of each of the NMOS transistors TN10 and TN11 are grounded. The power supply voltage VDD is applied to the gate of each of the NMOS transistors TN10 and TN11. As a result, each transistor acts as a decoupling capacitor between the power supply voltage VDD and the ground voltage VSS. 1.3.3.3 NAND circuit

[0131] Next, an example of a planar configuration of an ECO basic cell 1010 (ECO_NAND) in which the NAND circuit is configured will be described with reference to Fig. 12. Fig. Figure 12 is a top view of the ECO basic cell 1010 (ECO_NAND) in which the NAND circuit is configured. In the example of Fig. 12 the insulating film between the layers is omitted.

[0132] As in Fig. As illustrated in Figure 12, one end of the PMOS transistor TP10 is connected to the M2 connections 150_1 and 150_2 (power supply voltage connections) via an M1 connection 130_50.

[0133] One end of the NMOS transistor TN10 is connected to the M2 connections 150_3 and 150_4 (ground voltage connections) via an M1 connection 130_51.

[0134] One end shared by PMOS transistors TP10 and TP11 (the other ends of PMOS transistors TP10 and TP11) and one end of NMOS transistor TN11 are generally connected via an M1 connection 130_52. The M1 connection 130_52 functions as the signal output (OUT) connection of the NAND circuit.

[0135] One end shared by the NMOS transistors TN10 and TN11 (the other ends of the NMOS transistors TN10 and TN11) is not connected to the M1 interconnection 130.

[0136] One end of the PMOS transistor TP11 is connected to the M2 connections 150_1 and 150_2 (power supply voltage connections) via an M1 connection 130_53.

[0137] The gate electrode 111 of the PMOS transistor TP10 and the gate electrode 111 of the NMOS transistor TN10 are generally connected via an M1 interconnection 130_54. The M1 interconnection 130_54 functions as a connection for the input signals (IN1) of the NAND circuit.

[0138] The gate electrode 111 of the PMOS transistor TP11 and the gate electrode 111 of the NMOS transistor TN11 are generally connected via an M1 connection 130_55. The M1 connection 130_55 functions as the other signal input connection (IN2) of the NAND circuit. 1.3.3.4 NOR circuit

[0139] Next, an example of a planar configuration of an ECO basic cell 1010 (ECO_NOR) in which the NOR circuit is configured will be described with reference to Fig. 13. Fig. Figure 13 is a top view of the ECO basic cell 1010 (ECO_NOR) in which the NOR circuit is configured. In the example of Fig. 13 the insulating film between the layers is omitted.

[0140] As in Fig. As illustrated in Figure 13, one end of the PMOS transistor TP10 is connected to the M2 connections 150_1 and 150_2 (power supply voltage connections) via an M1 connection 130_60.

[0141] One end of the NMOS transistor TN10 is connected to the M2 connections 150_3 and 150_4 (ground voltage connections) via an M1 connection 130_61.

[0142] One end shared by the PMOS transistors TP10 and TP11 (the other ends of the PMOS transistors TP10 and TP11) is not connected to the M1 connection 130.

[0143] One end of PMOS transistor TP11 and one end shared by NMOS transistors TN10 and TN11 (the other ends of NMOS transistors TN10 and TN11) are generally connected via an M1 interconnection 130_62. The M1 interconnection 130_62 serves as the NOR circuit's output (OUT) connection.

[0144] One end of the NMOS transistor TN11 is connected to the M2 connections 150_3 and 150_4 (ground voltage connections) via an M1 connection 130_63.

[0145] The gate electrode 111 of the PMOS transistor TP10 and the gate electrode 111 of the NMOS transistor TN10 are generally connected via an M1 connection 130_64. The M1 connection 130_64 functions as a signal input connection (IN1) of the NOR circuit.

[0146] The gate electrode 111 of the PMOS transistor TP11 and the gate electrode 111 of the NMOS transistor TN11 are generally connected via an M1 connection 130_65. The M1 connection 130_65 acts as the other connection for inputting signals (IN2) to the NOR circuit. 1.3.3.5 Inverter circuit

[0147] Next, an example of a planar configuration of an ECO basic cell 1010 (ECO_I) in which the inverter circuit is configured will be described with reference to Fig. 14. Fig. Figure 14 is a top view of the ECO base cell 1010 (ECO_I) in which the inverter circuit is configured. In the example of Fig. 14 the insulating film between the layers is omitted.

[0148] As in Fig. As illustrated in Figure 14, one end of the PMOS transistor TP10 is connected to the M2 connections 150_1 and 150_2 (power supply voltage connections) via an M1 connection 130_70.

[0149] One end of the NMOS transistor TN10 is connected to the M2 connections 150_3 and 150_4 (ground voltage connections) via an M1 connection 130_71.

[0150] One end shared by PMOS transistors TP10 and TP11 (the other ends of PMOS transistors TP10 and TP11) is generally connected to one end shared by NMOS transistors TN10 and TN11 (the other ends of NMOS transistors TN10 and TN11) via an M1 connection 130_72. The M1 connection 130_72 functions as the output signal connection (OUT) of the inverter circuit.

[0151] One end of the PMOS transistor TP11 is coupled to the M2 connections 150_1 and 150_2 (connections for the power supply voltage) via an M1 connection 130_73.

[0152] One end of the NMOS transistor TN11 is connected to the M2 connections 150_3 and 150_4 (ground voltage connections) via an M1 connection 130_74.

[0153] The gate electrodes 111 of the PMOS transistors TP10 and TP11 and the gate electrodes 111 of the NMOS transistors TN10 and TN11 are generally connected via an M1 connection 130_75. The M1 connection 130_75 functions as the signal input (IN) connection of the inverter circuit. 1.3.3.6 Buffer circuit

[0154] Next, an example of a planar configuration of an ECO basic cell 1010 (ECO_B) in which the buffer circuit is configured will be described with reference to Fig. 15. Fig. Figure 15 is a top view of the ECO basic cell 1010 (ECO_B) in which the buffer circuit is configured. In the example of Fig. 15 the insulating film between the layers is omitted.

[0155] As in Fig. 15, one end of the PMOS transistor TP10, one end of the NMOS transistor TN10, the gate electrode 111 of the PMOS transistor TP11, and the gate electrode 111 of the NMOS transistor TN11 are generally connected via an M1 connection 130_80.

[0156] One end, shared by PMOS transistors TP10 and TP11 (the other ends of PMOS transistors TP10 and TP11), is connected to M2 connections 150_1 and 150_2 (power supply voltage connections) via an M1 connection 130_81.

[0157] One end, which is shared by the NMOS transistors TN10 and TN11 (the other ends of the NMOS transistors TN10 and TN11), is connected to the M2 connections 150_3 and 150_4 (ground voltage connections) via an M1 connection 130_82.

[0158] One end of the PMOS transistor TP11 and one end of the NMOS transistor TN11 are generally connected via an M1 connection 130_83. The M1 connection 130_83 serves as the connection for the output signal (OUT) of the buffer circuit.

[0159] The gate electrode 111 of the PMOS transistor TP10 and the gate electrode 111 of the NMOS transistor TN10 are generally connected via an M1 connection 130_84. The M1 connection 130_84 functions as a connection for the input signals (IN) of the buffer circuit. 1.3.3.7 Transit cell (or through cell)

[0160] Next, an example of a planar configuration of an ECO basic cell 1010 (ECO_T) in which the through cell is configured is shown with respect to the Fig. 16 and Fig. 17 described. Fig. 16 is a top view of the ECO base cell 1010 (ECO_T) in which the pass-through cell is configured. Fig. 17 is an equivalent circuit diagram of the pass-through cell. In the example of Fig. 16, the insulating film between the layers is omitted. In the example of Fig. Figure 16 describes a case where two M1 connections 130a (130a_1 and 130a_2) are provided that pass through the through cell in the Y direction. The M1 connections 130a are not electrically connected to the through cell. Note that the number of M1 connections 130a can be one.

[0161] As in Fig. As illustrated in Figure 16, one end of the PMOS transistor TP10 is connected to the M2 connections 150_1 and 150_2 (power supply voltage connections) via an M1 connection 130_90.

[0162] One end shared by the PMOS transistors TP10 and TP11 (the other ends of the PMOS transistors TP10 and TP11), the gate electrode 111 of the PMOS transistor TP10 and the gate electrode 111 of the PMOS transistor TP11 are connected to the M2 connections 150_1 and 150_2 (power supply voltage connections) via an M1 connection 130_91.

[0163] One end of the PMOS transistor TP11 is connected to the M2 connections 150_1 and 150_2 (power supply voltage connections) via an M1 connection 130_92.

[0164] One end of the NMOS transistor TN10 is connected to the M2 connections 150_3 and 150_4 (ground voltage connections) via an M1 connection 130_93.

[0165] One end shared by the NMOS transistors TN10 and TN11 (the other ends of the NMOS transistors TN10 and TN11), the gate electrode 111 of the NMOS transistor TN10 and the gate electrode 111 of the NMOS transistor TN11 are connected to the M2 connections 150_3 and 150_4 (ground voltage connections) via an M1 connection 130_94.

[0166] One end of the NMOS transistor TN11 is connected to the M2 connections 150_3 and 150_4 (ground voltage connections) via an M1 connection 130_95.

[0167] Between the M1 interconnect 130_90 and the M1 interconnect 130_91, and between the M1 interconnect 130_93 and the M1 interconnect 130_94, the M1 interconnect 130a_1 is arranged, passing through the through cell in the Y direction. The M1 interconnect 130a_1 is not electrically connected to each transistor of the through cell. The M1 interconnect 130a_1 passes above the n-type recess region 101, the active region 102, the element isolation region STI surrounding the active region 102, the active region 104, the element isolation region STI surrounding the active region 104, the gate electrode 111 of the PMOS transistor TP10, and above the gate electrode 111 of the NMOS transistor TN10 in the Y direction.

[0168] Between the M1 interconnection 130_91 and the M1 interconnection 130_92, and between the M1 interconnection 130_94 and the M1 interconnection 130_95, the M1 interconnection 130a_2 is arranged, passing through the through cell in the Y direction. The M1 interconnection 130a_2 is not electrically connected to each transistor of the through cell. The interconnection 130a_2 passes above the N-type recess region 101, the active region 102, the element isolation region STI surrounding the active region 102, the active region 104, the element isolation region STI surrounding the active region 104, the gate electrode 111 of the PMOS transistor TP11, and above the gate electrode 111 of the NMOS transistor in the Y direction.

[0169] As in Fig. As illustrated in Figure 17, the power voltage VDD is applied to the gate, source, and drain of each of the PMOS transistors TP10 and TP11. The gate, source, and drain of each of the NMOS transistors TN10 and TN11 are grounded. As a result, the potential of each terminal of the transistor is fixed. 1.3.4 Planar configuration of the filling cell

[0170] Next, an example of a planar configuration of the filling cell is described with reference to Fig. 18 described. Fig. Figure 18 is a top view of the filling cell. The following mainly describes the differences between the standard cell and the ECO basic cell.

[0171] As in Fig. As illustrated in Figure 18, a fill cell 1020 includes an N-type well region 101 and M2 interconnections 150_1 to 105_4. The positions of the N-type well region 101 and the M2 interconnections 150_1 to 150_4 in the Y direction are similar to those of the standard cell 1001. The fill cell 1020 does not include a transistor. The N-type well region 101 and the M2 interconnections 150_1 to 105_4 of the fill cell 1020 are connected to the N-type well region 101 and the M2 interconnections 150_1 to 105_4 of a cell (not shown) adjacent in the X direction. 1.3.5 Specific examples of the use of transit cells

[0172] Next, a specific example of the use of the transit cell in relation to Fig. 19 described. Fig. Fig. 19 is a plan view illustrating a specific example of using the through cell in the semiconductor device according to the first embodiment. In the example of Fig. 19, the insulating film between the layers, the connection M3 170, the connection M4 190 and the contacts 160 and 180 are omitted.

[0173] As in Fig. For example, as illustrated in FIG. 19, a standard cell 1004a of the buffer circuit, ECO basic cells 1010a and 1010b, a filler cell 1020, and a standard cell 1004b of the buffer circuit are arranged adjacently along the X direction by automatic placement and routing. The N-type recess regions 101 of the cells arranged in the X direction are connected to each other. Likewise, the M2 connections 150_1 to 150_4 of the cells arranged in the X direction are connected to each other. The ECO basic cells 1010c and 1010d are arranged adjacent to each other, so that the ECO basic cell 1010a is enclosed along the Y direction from the lower side of the drawing sheet.

[0174] If the metallic ECO is not used, the decoupling capacitor in the ECO base cells 1010a to 1010d is configured to set the potential of each terminal of the transistor.

[0175] In the above arrangement, a case is described in which an OR circuit (logical sum) is configured by the metal ECO using the ECO basic cells 1010a, 1010c and 1010d.

[0176] For example, a pass cell is configured through the metal ECO in the ECO basic cell 1010a. A NOR circuit is configured in the ECO basic cell 1010c. An inverter circuit is configured in the ECO basic cell 1010d. Then, the M1 connection 130_62 of the ECO basic cell 1010c (ECO_NOR) and the M1 connection 130_75 of the ECO basic cell 1010d (ECO_I) are electrically connected via the M1 connection 130a of the ECO basic cell 1010a (ECO_T), which is a pass cell. That is, an OR circuit is configured by coupling the signal output connection of the NOR circuit and the signal input connection of the inverter circuit. 1.4 Method for manufacturing a semiconductor device

[0177] Next, an example of the flow of a method for manufacturing a semiconductor device will be explained with reference to Fig. 20 to 26 described. Fig. 20 and Fig. 21 are flowcharts of the method for manufacturing a semiconductor device. Fig. Figure 22 is an example of a planar arrangement after placement of a standard cell. Fig. Figure 23 is an example of the planar arrangement after placement of the ECO base cell 1010 (ECO_C) in which the decoupling capacitor is configured. Fig. 24 is an example of the planar arrangement after placement of the fill cell 1020. Fig. Figure 25 is an example of the planar arrangement after changing the ECO logic cell. Fig. Figure 26 is an example of the planar arrangement after switching to the through cell. In the examples of Fig. 22 to 26, to describe the placement position of each cell, grids of 5 rows (Y = 5) × 7 columns (X = 7) are illustrated based on a cell size of the standard cell 1004 of the buffer circuit. The position of each grid is indicated by coordinates (X, Y). In addition, in the examples of Fig. 22 to 26, the standard cell 1001 of the NAND circuit, the standard cell 1002 of the NOR circuit, and the standard cell 1003 of the inverter circuit have the same size and are indicated by the same hatching for ease of description. The cell sizes of the standard cell 1004 of the buffer circuit and the ECO basic cell are indicated in the same cell size. It should be noted that in the examples of Fig. 22 to 26, the top view is hatched accordingly to improve visibility of the individual cells. The hatching in the top view is not related to any material or characteristic of the component to which the hatching was added.

[0178] The following mainly describes an array design and processes up to interconnect formation in semiconductor device manufacturing processes.

[0179] As in Fig. As illustrated in Figure 20, after the circuit design, a layout design is first performed as in S1 to S5. Specifically, standard cells are first placed based on the circuit design data (S1). This step corresponds to the "location" in automatic placement and routing.

[0180] As in Fig. 22, in step S1, in which the standard cells are placed, empty areas (areas where no cell is placed) remain in the planar arrangement. In the example of Fig. 22, the coordinate ranges (4, 2), (4, 3), (4, 4), (4, 5), (5, 1), (5, 2), and (7, 1) are empty. Furthermore, part of the coordinate ranges (3, 2), (3, 3), and (7, 3) are empty.

[0181] As in Fig. As illustrated in Figure 20, the standard cells are coupled using the M3 connections 170 and the M4 connections 190 (S2). This step corresponds to "routing" in automatic placement and routing.

[0182] The ECO basic cells 1010 (ECO_C), in which the decoupling capacitor is configured, are inserted into the column areas after the standard cells have been placed (S3).

[0183] As in Fig. 23, the ECO basic cells 1010 (ECO_C) according to S3 are placed, for example, on the planar array in the areas of coordinates (4, 2), (4, 3), (4, 4), (4, 5), (5, 1), (5, 2), and (7, 1). Four ECO basic cells (ECO_C) are placed adjacent to each other in the Y direction at X = 4, two ECO basic cells 1010 (ECO_C) are placed adjacent to each other in the Y direction at X = 5, and one ECO basic cell (ECO_C) is placed alone at X = 7. Further, two ECO basic cells 1010 (ECO_C) are arranged adjacent to each other in the X direction at Y = 2. That is, two or more ECO basic cells 1010 (ECO_C) are arranged adjacent to each other in the X direction or the Y direction.

[0184] As in Fig. 20, the filler cells 1020 are inserted into the column areas after the standard cells and the ECO base cells 1010 (ECO_C) are placed (S4).

[0185] As in Fig. 24, for example, according to S4, the fill cells 1020 are placed on the planar array in empty sections in the ranges of the coordinates (3, 2), (3, 3) and (7, 3).

[0186] As in Fig. As illustrated in Figure 20, a device arrangement is determined (S5). That is, the placement of each cell (transistor) is determined.

[0187] Once the device layout is determined, the semiconductor device manufacturing processes illustrated in S6 to S7 are performed. Note that, in this example, the layout design processes S8 to S14, described later, are performed after the semiconductor device manufacturing processes S6 to S7 are described, but the present invention is not limited thereto. The semiconductor device manufacturing process of S6 to S7 and the layout design process of S8 to S14 can be performed in parallel. First, various masks (hereinafter referred to as "device masks") relating to a photolithography process of the element isolation regions and the well (diffusion layer) regions of the semiconductor substrate 100 and the transistors are prepared (S6).

[0188] The transistors are fabricated on the substrate 100 based on the device mask (S7).

[0189] As in Fig. As illustrated in Figure 21, the arrangement design (metal ECO) is executed as shown in S8 to S14. If there is a change in the circuit design (S8_Yes), the metal ECO is executed. Specifically, the configuration of some ECO basic cells 1010 is changed from decoupling capacitors to ECO logic cells (S9). That is, the arrangement of the interconnect layer (here, the M1 interconnect 130) of the ECO basic cell 1010 is changed.

[0190] As in Fig. 25, for example, according to S9, the ECO basic cells of coordinates (4, 5) and (5, 1) are changed into ECO logic cells on the planar array.

[0191] As in Fig. As illustrated in Figure 21, it is confirmed whether coupling of the ECO logic cell is possible (S10). Specifically, in the arrangement of the M2 interconnection 150, the M3 interconnection 170, and the M4 interconnection 190, it is confirmed whether there is a space in which the M3 interconnection 170 and the M4 interconnection 190 can be connected to the ECO logic cell.

[0192] If coupling of the ECO logic cell is possible (S10_Yes), the ECO logic cell is connected using the M2 connection 150, the M3 connection 170, and the M4 connection 190 (S11). The ECO logic cells can be connected to each other, or the ECO logic cell and the standard cell can be connected to each other.

[0193] The interconnect arrangement is checked (S12). For example, if the congestion levels of the M3 interconnects 170 and the M4 interconnects 190 are high, the interconnect connected to the ECO logic cell may not meet a design rule or a condition such as signal transmission timing.

[0194] If the ECO logic cell's connections cannot be coupled (S10_No) or if the arrangement determination fails the check (S12_No), the metal ECO is performed again. Specifically, an unused ECO base cell 1010 (ECO_C) that has not been converted to the ECO logic cell is searched for near the ECO logic cell where coupling is not possible or the arrangement is NG. Then, the configuration of the ECO base cell 1010 (ECO_C) is changed from the decoupling capacitor to the pass-through cell (S13).

[0195] As in Fig. For example, as illustrated in Figure 26, according to S13, to couple the ECO logic cells of coordinates (4, 5) and (5, 1) on the planar array, the ECO basic cells in the areas of coordinates (4, 2), (4, 3), (4, 4), and (5, 2) are changed into pass-through cells. For example, the pass-through cell is adjacent to the ECO logic cell in the Y direction.

[0196] As in Fig. As shown in Figure 21, after changing the through cell, the process proceeds to S10 to confirm whether the coupling of the ECO logic cell is possible. If the coupling is possible (S10_Yes), the coupling is connected to the ECO logic cell in which the coupling is NG, with the M1 coupling 130a passing through the through cell. In the planar arrangement shown in Fig. 26, the ECO logic cells of coordinates (4, 5) and (5, 1) are connected via the through cells of coordinates (4, 2), (4, 3), (4, 4) and (5, 2).

[0197] If the circuit design remains unchanged (S8_Yes) or if the layout check determination has been passed (S12_Yes), the connection layout is determined (S14). The layout design is then complete.

[0198] Once the arrangement of the interconnections is determined, the processes illustrated in S15 to S16 are performed to fabricate the semiconductor device. First, various masks (hereinafter referred to as "interconnection masks") related to the photolithographic process for forming the interconnections are prepared (S15).

[0199] Based on the connection masks, various connections are established (S16). Specifically, for example, the contact plug 120, the M1 connection 130, the contact plug 140, the M2 connection 150, the contact plug 160, the M3 connection 170, the contact plug 180, and the M4 connection 190 are formed sequentially. 1.5 Effect according to existing design

[0200] With the configuration according to the present embodiment, it is possible to suppress an increase in development costs and a prolongation of the development work period. The effects are described in detail.

[0201] For example, the circuit design may be changed after the mask of the semiconductor device 1 has been fabricated. In such a case, if the process is restarted from the transistor arrangement, the device mask would be fabricated again, resulting in an increase in development costs and a prolongation of development work.

[0202] On the other hand, with the configuration according to the present embodiment, the ECO basic cell can be placed in an empty space where the standard cell is placed in automatic placement and automatic routing. The function of the ECO basic cell circuit can be changed by changing the arrangement of the M1 interconnection through the metal ECO. Therefore, it is possible to edit the circuit by performing the metal ECO without changing the cell (transistor) placement, even if the circuit design is changed after the device mask is created.

[0203] However, even if the ECO base cell is changed to an ECO logic cell, linking the connection to the ECO logic cell may not be possible. Additionally, in some cases, the layout determination may not be passed if the link congestion level is high due to the link increase associated with the addition of the ECO logic cell, even if link coupling can be performed.

[0204] On the other hand, in the configuration according to the present embodiment, the via cell can be configured in the ECO basic cell. In the via cell, the M1 interconnection, which is not coupled to the transistor in the via cell and couples the cells adjacent to the via cell, can be provided. By providing the via cell, an arrangement of the M1 interconnection can be increased. As a result, interconnect congestion can be alleviated, and the metallic ECO can be performed. Therefore, by providing the via cell, the coupling of the ECO logic cell can be facilitated. Therefore, only a change in the interconnection mask in the interconnection process can cope with the change in the circuit without changing the device mask corresponding to the semiconductor formation process including the transistor.

[0205] Therefore, the increase in development costs and the extension of the development work period can be suppressed.

[0206] The transistor terminal in the pass-through cell is coupled to the power supply voltage connection or ground voltage connection. Therefore, no charge accumulates in the transistor terminal, contributing to stable operation. 1.6. Modification of the first embodiment

[0207] Next, a modification of the first embodiment will be described. The following mainly describes the differences from the first embodiment. 1.6.1 First modification

[0208] First, a first modification of the first embodiment will be described. In the first modification, a case is described in which an M1 connection 130a passes through two adjacent cells in the X direction. Fig. 27 to 29 are plan views of a semiconductor device 1 illustrating specific examples of using a continuous cell. The examples in Fig. 27 to 29 differ in the arrangement of the M1 connection 130a. In the examples in Fig. 27 to 29, the insulating film between the layers, the M3 connection 170, the M4 connection 190 and the contact plugs 160 and 180 are omitted.

[0209] As in Fig. For example, as illustrated in Figure 27, a buffer circuit standard cell 1004a, ECO basic cells 1010a and 1010b, a filler cell 1020, and a buffer circuit standard cell 1004b are arranged adjacently by automatic placement and routing along the X direction. ECO basic cells 1010c are placed adjacently on the lower side of the drawing sheet of the ECO basic cell 1010a. ECO basic cells 1010d are placed adjacently on the higher side of the drawing sheet of the ECO basic cell 1010b.

[0210] In the above arrangement, for example, a continuous cell is configured through the metal ECO in the ECO basic cells 1010a and 1010b. A NOR circuit is configured in the ECO basic cell 1010c. An inverter circuit is configured in the ECO basic cell 1010d. Then, an M1 connection 130_62 of the ECO basic cell 1010c (ECO_NOR) and an M1 connection 130_75 of the ECO basic cell 1010d (ECO_I) are electrically connected via the M1 connection 130a passing through the ECO basic cells 1010a (ECO_T) and 1010b (ECO_T). Specifically, the M1 interconnect 130a passes through an N-type recess region 101 of the ECO basic cell 1010b (ECO_T), an active region 102, an element isolation region STI surrounding the active region 102, and a gate electrode 111 of a PMOS transistor TP10 in the Y direction. The M1 interconnect 130a, which has passed through the active region 102 in the Y direction, is bent in the X direction on the left side of the drawing sheet.Then, the M1 interconnect 130a in the ECO basic cell 1010b (ECO_T) is bent and extends in the Y direction on the lower side of the drawing sheet. The M1 interconnect 130a, which extends in the Y direction, is bent in the X direction on the left side of the drawing sheet and extends into the ECO basic cell 1010a (ECO_T) before reaching an active region 104 of the ECO basic cell 1010b (ECO_T). Further, the M1 interconnect 130a is bent in the Y direction on the lower side of the drawing sheet and passes above the active region 104 of the ECO basic cell 1010a (ECO_T), an element isolation region STI surrounding the active region 104, and a gate electrode 111 of an NMOS transistor TN11 in the Y direction.

[0211] It should be noted that the arrangement of the M1 connection 130a is not limited to that shown above. Two examples of different arrangements of the M1 connection 130a are described.

[0212] As in Fig. For example, as illustrated in Figure 28, the M1 interconnect 130a, which has been routed through the active area 102 of the ECO basic cell 1010b (ECO_T) in the Y direction, is bent in the X direction on the left side of the drawing sheet and extends into the ECO basic cell 1010a (ECO_T). Then, in the ECO basic cell 1010a (ECO_T), the M1 interconnect 130a is bent and extends in the Y direction on the lower side of the drawing sheet. The M1 interconnect 130a, which extends in the Y direction, is bent in the X direction on the left side of the drawing sheet before reaching the active area 104 of the ECO basic cell 1010a (ECO_T). The M1 connection 130a is bent in the Y direction on the lower side of the drawing sheet and extends in the Y direction over the gate electrode 111 of the NMOS transistor TN11.

[0213] As in Fig. As illustrated in Figure 29, a portion of the M1 interconnect 130a may branch into two parts. For example, the M1 interconnect 130a extending through the active area 102 of the ECO base cell 1010b (ECO_T) in the Y direction is bent in the X direction on the left side of the drawing sheet. The M1 interconnect 130a extending in the X direction is branched into two.

[0214] One of the two is bent and extends in the Y direction on the lower side of the drawing sheet in the ECO base cell 1010b (ECO_T), as shown in Fig. 27. The M1 connection 130a extending in the Y direction is bent in the X direction on the left side of the drawing sheet and extends into the ECO base cell 1010b (ECO_T) before reaching the active region 104 of the ECO base cell 1010b (ECO_T).

[0215] The other extends into the ECO base cell 1010a (ECO_T), as described with respect to Fig. 28. Then, in the ECO base cell 1010a (ECO_T), the M1 connection 130a is bent and extends in the Y direction on the lower side of the drawing sheet. The M1 connections 130a extending in the Y direction merge into one of the branching M1 connections 130a before reaching the active region 104 of the ECO base cell 1010a (ECO_T). 1.6.2 Second modification

[0216] Next, a second modification of the first embodiment will be described. In the second modification, two examples of a structure of a coupling portion 111a of a gate electrode 111, which is different from that of the first embodiment, will be described. Fig. 30 and Fig. 31 are top views of a transistor of an ECO basic cell 1010. In the examples of Fig. 30 and Fig. 31, the insulating film between the layers, the M1 connection 130, the M2 connection 150 and the contacts 120 and 140 are omitted.

[0217] As in Fig. 30, the configuration of each transistor of the ECO basic cell 1010 is similar to that shown in Fig. 9 of the first embodiment.

[0218] In the example of Fig. 30, the coupling portion 111a is provided at an end portion of the gate electrode 111 of each transistor. A width of the coupling portion 111a in the X direction is larger than a connection width of the gate electrode 111. In the example of Fig. 30, the coupling portion 111a is provided to protrude from the gate electrode 111 in one of the X directions.

[0219] As in Fig. 31, the configuration of each transistor of the ECO basic cell 1010 is similar to that shown in Fig. 9 of the first embodiment.

[0220] In the example of Fig. 31, the coupling portion 111a is eliminated. In other words, the coupling portion 111a, which has the same length as the width of the connection of the gate electrode 111, is provided at the end portion of the gate electrode 111.

[0221] In the present modification, the coupling portion 111a of the gate electrode 111 of the ECO basic cell has been described, but the gate electrode of the standard cell may have a similar structure. 1.6.3 Third modification

[0222] Next, a third modification of the first embodiment will be described. In the third modification, two examples of a through cell configuration different from that of the first embodiment will be described. 1.6.3.1 First example of a transit cell

[0223] First, an example of a planar configuration of an ECO basic cell 1010 (ECO_T) in which a pass cell comprising a decoupling capacitor through an NMOS transistor is configured is described with respect to the Fig. 32 and Fig. 33. Fig. 32 is a top view of the ECO basic cell 1010 (ECO_T) in which the pass cell including the decoupling capacitor is configured by the NMOS transistor. Fig. Figure 33 is an equivalent circuit diagram of the pass-through cell including the decoupling capacitor through the NMOS transistor. In the example of Fig. 32, the insulating film between the layers is omitted. In the example of Fig. Figure 32 describes a case where two M1 connections 130a (130a_1 and 130a_2) are provided, extending in the Y direction through the through cell. The M1 connection 130a is not electrically coupled to each transistor of the through cell. Note that the number of M1 connections 130a can be one.

[0224] As in Fig. As illustrated in Figure 32, one end of a PMOS transistor TP10 is connected to the M2 connections 150_1 and 150_2 (power supply voltage connections) via an M1 connection 130_100.

[0225] One end is connected by the PMOS transistors TP10 and TP11 (the other end of the PMOS transistors TP10 and TP11), a gate electrode 111 of the PMOS transistor TP10, a gate electrode 111 of the PMOS transistor TP11, a gate electrode 111 of an NMOS transistor TN10 and a gate electrode 111 of an NMOS transistor TN11 are connected via an M1 connection 130_101.

[0226] One end of the PMOS transistor TP11 is connected to the M2 connections 150_1 and 150_2 (power supply voltage connections) via an M1 connection 130_102.

[0227] One end of the NMOS transistor TN10 is connected to the M2 connections 150_3 and 150_4 (ground voltage connections) via an M1 connection 130_103.

[0228] One end, which is shared by the NMOS transistors TN10 and TN11 (the other ends of the NMOS transistors TN10 and TN11), is connected to the M2 connections 150_3 and 150_4 (ground voltage connections) via an M1 connection 130_104.

[0229] One end of the NMOS transistor TN11 is connected to the M2 connections 150_3 and 150_4 (ground voltage connections) via an M1 connection 130_105.

[0230] Between M1 connection 130_100 and M1 connection 130_101, as well as between M1 connection 130_103 and M1 connection 130_104, is M1 connection 130a_1, which passes through the pass cell in the Y direction. M1 connection 130a_1 is not electrically connected to any transistor of the pass cell.

[0231] Between M1 connection 130_101 and M1 connection 130_102, and between M1 connection 130_104 and M1 connection 130_105, is M1 connection 130a_2, which passes through the through cell in the Y direction. M1 connection 130a_2 is not electrically coupled to any transistor of the through cell.

[0232] As in Fig. As illustrated in Figure 33, the power supply voltage VDD is applied to the gate, source, and drain of each of the PMOS transistors TP10 and TP11. The power supply voltage VDD is applied to the gate of each of the NMOS transistors TN10 and TN11. The source and drain of each of the NMOS transistors TN10 and TN11 are grounded. As a result, the potential of each terminal of the transistor is fixed. The NMOS transistors TN10 and TN11 act as decoupling capacitors between the power supply voltage VDD and the ground voltage VSS. 1.6.3.2 Second example of a transit cell

[0233] First, an example of a planar configuration of an ECO basic cell 1010 (ECO_T) in which a pass cell comprising a decoupling capacitor through a PMOS transistor is configured will be described with reference to the Fig. 34 and Fig. 35. Fig. 34 is a top view of the ECO basic cell 1010 (ECO_T) in which the pass cell including the decoupling capacitor is configured by the PMOS transistor. Fig. Figure 35 is an equivalent circuit diagram of the pass-through cell including the decoupling capacitor through the PMOS transistor. In the example of Fig. 34, the insulating film between the layers is omitted. In the example of Fig. Figure 34 describes a case where two M1 connections 130a (130a_1 and 130a_2) are provided that extend through the through cell in the Y direction. The M1 connection 130a is not electrically coupled to each transistor of the through cell. Note that the number of M1 connections 130a can be one.

[0234] As in Fig. 34, one end of a PMOS transistor TP10 is connected to the M2 connections 150_1 and 150_2 (power supply voltage connections) via an M1 connection 130_110.

[0235] One end, shared by PMOS transistors TP10 and TP11 (the other ends of PMOS transistors TP10 and TP11), is connected to M2 connections 150_1 and 150_2 (power supply voltage connections) via an M1 connection 130_111.

[0236] One end of the PMOS transistor TP11 is connected to the M2 connections 150_1 and 150_2 (power supply voltage connections) via an M1 connection 130_112.

[0237] One end of the NMOS transistor TN10 is connected to the M2 connections 150_3 and 150_4 (ground voltage connections) via an M1 connection 130_113.

[0238] One end shared by NMOS transistors TN10 and TN11 (the other end of NMOS transistors TN10 and TN11), a gate electrode 111 of a PMOS transistor TP10, a gate electrode 111 of a PMOS transistor TP11, a gate electrode 111 of NMOS transistor TN10, and a gate electrode 111 of NMOS transistor TN11 are connected to M2 connections 150_3 and 150_4 (ground voltage connections) via M1 connection 130_114.

[0239] One end of the NMOS transistor TN11 is connected to the M2 connections 150_3 and 150_4 (ground voltage connections) via an M1 connection 130_115.

[0240] Between M1 connection 130_110 and M1 connection 130_111, as well as between M1 connection 130_113 and M1 connection 130_114, is M1 connection 130a_1, which passes through the pass cell in the Y direction. M1 connection 130a_1 is not electrically connected to any transistor of the pass cell.

[0241] Between M1 connection 130_111 and M1 connection 130_112, and between M1 connection 130_114 and M1 connection 130_115, is M1 connection 130a_2, which passes through the through cell in the Y direction. M1 connection 130a_2 is not electrically coupled to any transistor of the through cell.

[0242] As in Fig. As illustrated in Figure 35, the gate of each of the PMOS transistors TP10 and TP11 is grounded. The power voltage VDD is applied to the source and drain of each of the PMOS transistors TP10 and TP11. The gate, source, and drain of each of the NMOS transistors TN10 and TN11 are grounded. As a result, the potential of each terminal of the transistor is fixed. The PMOS transistors TP10 and TP11 act as decoupling capacitors between the power supply voltage VDD and the ground voltage VSS. 1.6.4 Fourth modification

[0243] Next, a fourth modification of the first embodiment will be described. In a fourth modification, a method for manufacturing a semiconductor device different from that of the first embodiment will be described. Fig. 36 and Fig. 37 are flowcharts of the method for manufacturing a semiconductor device. The following mainly explains differences from Fig. 20 and Fig. 21 of the first embodiment.

[0244] As in Fig. 36, the processes S1 to S7 are similar to those in Fig. 20 of the first embodiment.

[0245] As in Fig. 37, the metal ECO is executed when the circuit is changed (S8_Yes). In this example, the change to the ECO logic cell in S9 and the change to the pass cell in S13, which are made with reference to Fig. 21 are executed jointly (S21). More specifically, according to S21, the planar arrangement of the semiconductor device 1 is changed, for example, from that shown in Fig. 24 of the first embodiment to the planar arrangement shown in Fig. 26 illustrated planar arrangement.

[0246] Next, the ECO logic cell is connected using the M1 interconnect 130, the M2 interconnect 150, the M3 interconnect 170, and the M4 interconnect 190 using the through cell (S22).

[0247] The connection alignment check is executed (S23). In this example, if the alignment check determination has not been passed (S23_No), the process proceeds to S21 and the metal ECO is executed again.

[0248] If the circuit is not changed (S8_Yes) or if the layout check determination has been passed (S23_Yes), the connection layout is determined (S14). This completes the layout design.

[0249] Once the interconnection arrangement is determined, the processes shown in S15 to S16 are carried out to manufacture the semiconductor device as in the first embodiment. 1.6.5 Effect of the modification of the first embodiment

[0250] The structures according to the modifications of the first embodiment have the same effect as those of the first embodiment.

[0251] The first modification, the second modification, the third modification and the fourth modification can be combined. 2. Second embodiment

[0252] Next, a second embodiment will be described. In the second embodiment, a case where the semiconductor device 1 is a NOR flash memory will be described. The following mainly describes the differences from the first embodiment. 2.1 General configuration of the semiconductor device

[0253] An example of a configuration of the semiconductor device 1 will be described with reference to Fig. 38 described. Fig. 38 is a block diagram illustrating the configuration of the semiconductor device 1. In Fig. 38, part of the coupling between components is indicated by an arrow line, but the coupling between components is not limited to this.

[0254] As in Fig. 38, the semiconductor device 1 is a NOR flash memory.

[0255] The semiconductor device 1 includes a memory cell array 31, a row control circuit 32, a column control circuit 33, an address register 34, a buffer 35, an input / output shift register 36, a voltage generator 37, and a sequencer 38.

[0256] The memory cell array 31 includes a plurality of memory cells (memory cell transistors) MTx. In the memory device 1, a gate of each memory cell MTx is coupled to a corresponding one of a plurality of word lines WL. One end of a current path of each memory cell MTx is coupled to a corresponding one of a plurality of bit lines BL. The other end of the current path of each memory cell MTx is coupled to a source line and connected to, for example, ground. The memory cells MTx are arranged in a two-dimensional array or a three-dimensional array.

[0257] The MTx memory cell is a field-effect transistor with a stacked-gate structure containing a charge storage layer. The charge storage layer can be a floating electrode or a charge-trapping film.

[0258] The row control circuit 32 selects the word line WL corresponding to the address information among the word lines WL. The row control circuit 32 applies a predetermined voltage to the selected word line WL (and the unselected word lines WL) in a write operation, a read operation, an erase operation, and the like.

[0259] The row control circuit 32 includes a digital control signal circuit 32a that processes the received digital signal.

[0260] The column control circuit 33 selects the bit line BL corresponding to the address information among the bit lines BL. The row control circuit 32 applies a predetermined voltage to the selected bit line BL (and the unselected bit lines BL) in the write operation, the read operation, the erase operation, and the like.

[0261] The column control circuit 33 includes a digital signal control circuit 33a which processes the received digital signal.

[0262] The address register 34 temporarily stores the address information from the input / output shift register 36. The address register 34 transfers the address information to the row control circuit 32 and the column control circuit 33.

[0263] The address register 34 has the function of a digital control signal circuit that processes the received digital signal (address information).

[0264] The buffer 35 temporarily stores read data from the memory cell array 31 and write data from the input / output shift register 36.

[0265] The input / output shift register 36 temporarily stores data (signal DQ) transferred between the memory cell array 31 and the outside of the semiconductor device 1. The data (signal DQ) may include read data, write data, and / or address information. The input / output shift register 36 transfers the address information to the address register 34. The input / output shift register 36 transfers the write data to the buffer 35. The input / output shift register 36 transfers the read data supplied from the memory cell array 31 to the outside of the semiconductor device 1. The input / output shift register 36 may perform parallel-to-serial conversion of the data (signal DQ).

[0266] The input / output shift register 36 contains a digital signal control circuit 36a which processes the received digital signal.

[0267] The voltage generator 37 generates a plurality of voltages, each used for the write operation, the read operation, and the erase operation. The voltage generator 37 supplies the generated voltages to the row control circuit 32, the column control circuit 33, and the like.

[0268] The voltage generator 37 includes a digital signal control circuit 37a which processes the received digital signal.

[0269] The sequencer 38 controls the entire operation of the semiconductor device 1 based on various control signals such as a reset signal RESETn, a hold signal HOLDn and a write protect signal Wn.

[0270] The sequencer 38 functions as a digital signal control circuit that processes the received digital signals (various control signals).

[0271] Note that the semiconductor device 1 may include other components such as a status register. The status register temporarily stores a status signal indicating an operating status within the semiconductor device 1 and an execution result of the operation.

[0272] Similar to the first embodiment, an automatic placement and routing technique is used for the layout design of various digital signal control circuits included in the semiconductor device 1. 2.2 Effect according to the present embodiment

[0273] The configuration according to the present embodiment provides the same effects as those of the first embodiment. 3. Third embodiment

[0274] Next, a third embodiment will be described. In the third embodiment, a case where the semiconductor device 1 is a dynamic random access memory (DRAM) will be described. Note that the semiconductor device 1 may be a volatile semiconductor memory device other than DRAM. For example, the semiconductor device 1 may be a static random access memory (SRAM). The following mainly describes the differences from the first and second embodiments. 3.1 Overall configuration of the semiconductor device

[0275] An example of a configuration of the semiconductor device 1 will be described with reference to Fig. 39 described. Fig. 39 is a block diagram illustrating the configuration of the semiconductor device 1. In Fig. 39, part of the coupling between components is indicated by an arrow line, but the coupling between components is not limited to this.

[0276] As in Fig. 39, the semiconductor device 1 is a DRAM.

[0277] The semiconductor device 1 includes a memory cell array 51, a row decoder 52, a column decoder 53, an instruction decoder 54, an address decoder 55, an instruction / address input circuit 56, a sense amplifier circuit 57, a transfer gate 58, a read / write amplifier (RWAMP) circuit 59, an input / output circuit 60, a clock input circuit 61, an internal clock generator 62, a voltage generator 63, and the like.

[0278] The memory cell array 51 includes a plurality of memory cells MC. Each of the memory cells MC of the DRAM 51 includes a cell capacitor CC and a memory cell transistor CT. A gate of the cell transistor CT is connected to a corresponding one of a plurality of word lines WL. One end of a current path of the cell transistor CT is connected to a bit line BL. The other end of the current path of the cell transistor CT is connected to one end of the cell capacitor CC. The other end of the cell capacitor CC is connected to ground. The cell capacitor CC can store an amount of charge corresponding to the data to be stored. The memory cell transistor CT switches the conduction / non-conductivity (selection / non-selection of the memory cell MC) between the cell capacitor CC and the bit line BL. The memory cells MC are arranged in a two-dimensional array or a three-dimensional array in the memory cell array 51.

[0279] For example, memory cell array 51 includes a plurality of banks. Each bank is a control unit that includes a plurality of memory cells. The banks are independently operable.

[0280] The row decoder 52 controls the selection / de-selection of a row (for example, word line WL) of the memory cell array 51 based on a decoding result of address information and a decoding result of an instruction.

[0281] The column decoder 53 controls the selection / de-selection of a column (e.g., bit line BL) of the memory cell array 51 based on the decoding result of the address information and the decoding result of the instruction.

[0282] The instruction decoder 54 decodes the instruction from the instruction / address input circuit 56. The instruction decoder 54 transmits the decoding result of the instruction to the row decoder 52 and the column decoder 53.

[0283] The address decoder 55 decodes the address information from the instruction / address input circuit 56. The address decoder 55 transmits the decoding result of the address information to the row decoder 52 and the column decoder 53.

[0284] The instruction / address input circuit 56 receives an instruction / address signal CA provided externally. The instruction / address signal CA includes an instruction and address information. The instruction / address input circuit 56 transmits the instruction to the instruction decoder 54. The instruction / address input circuit 56 transmits the address information to the address decoder 55.

[0285] The sense amplifier circuit 57 detects and amplifies a signal from the memory cell MC during the read operation. The sense amplifier circuit 57 transmits the signal from the memory cell MC as read data to the input / output circuit 60 via the transfer gate 58 and the read / write amplifier circuit 59. The sense amplifier circuit 57 receives write data from the input / output circuit 60 via the transfer gate 58 and the read / write amplifier circuit 59. The sense amplifier circuit 57 outputs a signal corresponding to the write data to the bit line BL.

[0286] The transfer gate 58 controls the data transfer between the sense amplifier circuit 57 and the read / write amplifier circuit 59.

[0287] The read / write amplifier circuit 59 amplifies a level (signal value) of the signal corresponding to the read data and a level of the signal corresponding to the write data.

[0288] The input / output circuit 60 functions as an interface circuit for data (signal DQ) transferred between the memory cell array 51 and the outside of the DRAM 50. The input / output circuit 60 transfers the write data to the memory cell array 51 at a timing synchronized with an internal clock CLK2. The input / output circuit 60 transfers the read data to a device outside the DRAM 50 at a timing synchronized with the internal clock CLK2. For example, the input / output circuit 60 receives a data mask signal DM. As a result, the input / output circuit 60 performs mask processing on the data (signal DQ).

[0289] The input / output circuit 60 includes a digital signal control circuit 60a that processes the received digital signal.

[0290] The clock input circuit 61 receives a clock (hereinafter referred to as external clock) CLK1 from the outside. The clock input circuit 61 sends the external clock CLK1 to the internal clock generator 62.

[0291] The internal clock generator 62 generates the internal clock CLK2 based on the external clock CLK1. The internal clock generator 62 transmits the generated internal clock CLK2 to the input / output circuit 60 and the like.

[0292] The voltage generator 63 generates a variety of voltages used for various operations of the DRAM 50 using the external power supply voltage VDD and the ground voltage VSS. The voltage generator 63 transmits the generated voltages to another circuit (e.g., the read / write amplifier circuit 59).

[0293] Similar to the first embodiment, an automatic placement and routing technique is used for the layout design of digital control circuits included in the semiconductor device 1. 3.2 Effect according to the present embodiment

[0294] The configuration according to the present embodiment offers the same effects as those of the first embodiment. 4. Fourth embodiment

[0295] Next, a fourth embodiment will be described. In the fourth embodiment, a case where the semiconductor device 1 is an image sensor will be described. The following mainly describes the differences between the first and third embodiments. 4.1 Overall configuration of the semiconductor device

[0296] An example of an overall configuration of the semiconductor device 1 will be described with reference to Fig. 40 described. Fig. 40 is a block diagram illustrating the overall configuration of the semiconductor device 1. In Fig. 40, part of the coupling between components is indicated by an arrow line, but the coupling between components is not limited to this.

[0297] As in Fig. 40, the semiconductor device 1 is an image sensor.

[0298] The semiconductor device 1 includes a pixel array 71, a line scanning circuit 72, a column processing circuit 73, a column scanning circuit 74, a system control circuit 75, and a signal processing circuit 76.

[0299] The pixel array 71 includes a plurality of pixels PX. The pixels PX are arranged in a two-dimensional lattice shape along a row direction and a column direction. Each pixel PX includes a photoelectric conversion element. The photoelectric conversion element generates a charge corresponding to an amount of received light and stores the generated charge. In the pixel array 71, a filter may be provided with respect to a light incident surface of each pixel PX. For example, array patterns of a plurality of the filters are, for example, Bayer patterns.

[0300] In the pixel array 71, the pixels PX arranged in the row direction are generally connected to a pixel drive line PDL. In the pixel array 71, the pixels PX arranged in the column direction are generally connected to a corresponding one of a plurality of vertical signal lines VSL.

[0301] The line scanning circuit 72 is connected to one end of a plurality of pixel drive lines PDL. The line scanning circuit 72 generates a drive signal for reading out the signal from the pixel PX. The line scanning circuit 72 drives all pixels PX of the pixel array 71 simultaneously or line by line via the pixel drive lines PDL.

[0302] The line scanning circuit 72 includes a digital control signal circuit 72a that processes the received digital signal.

[0303] The output signals from the pixels PX driven by the line scanning circuit 72 are supplied to the column processing circuit 73 via each of the vertical signal lines VSL for each of the pixels PX arranged in the row direction. The column processing circuit 73 performs predetermined signal processing on the signal supplied via the vertical signal line VSL. Thus, the column processing circuit 73 generates a pixel signal. The column processing circuit 73 may temporarily store the generated pixel signal. For example, the column processing circuit 73 performs a noise removal process, an analog-to-digital conversion (AD conversion) process, and the like. The digital signal obtained by the AD conversion is output to the signal processing circuit 76.

[0304] The column processing circuit 73 includes a digital signal control circuit 73a that processes the received digital signal.

[0305] The column scanning circuit 74 sequentially selects a read circuit corresponding to an array of the pixel signals of the column processing circuit 73. Through selective scanning by the column scanning circuit 74, a pixel signal subjected to signal processing for each pixel in the column processing circuit 73 is output based on a predetermined order.

[0306] The column scanning circuit 74 includes a digital control circuit 74a that processes the received digital signal.

[0307] The system control circuit 75 receives a system clock signal and the like via a controller (not illustrated) external to the image sensor 70. The system control circuit 75 includes a timer and the like. The timer generates various timing signals based on the system clock signal. As a result, the system control circuit 75 controls the line scanning circuit 72, the column processing circuit 73, the column scanning circuit 74, and the like based on the generated various control signals.

[0308] The system control circuit 75 has a function as a digital signal control circuit that processes a received digital signal.

[0309] The signal processing circuit 76 has at least one arithmetic processing function. The signal processing circuit 76 performs various types of signal processing, such as arithmetic processing of the pixel signal output from the column processing circuit 73.

[0310] The signal processing circuit 76 functions as a digital control circuit that processes the received digital signal.

[0311] Note that the digital signal output from the signal processing circuit 76 is output to an image processing circuit 79 external to the image sensor 70. The image processing circuit 79 performs predetermined processing on the digital signal. As a result, an image signal for displaying an image on a predetermined display device is generated.

[0312] Similar to the first embodiment, an automatic placement and routing technique is used for the layout design of digital circuits for signal control included in the semiconductor device 1. 4.2 Effect according to this embodiment

[0313] The configuration according to the present embodiment provides the same effects as those of the first embodiment. 5. Fifth embodiment

[0314] Next, a fifth embodiment will be described. In the fifth embodiment, a case will be described where the semiconductor device 1 is a magnetoresistive random access memory (MRAM) using a resistance change element as a memory element. In the case of the MRAM, an element (also called an MTJ element) having a magnetoresistive effect through a magnetic tunnel junction (MTJ) is included as the resistance change element. The following mainly describes the differences between the first and fourth embodiments. Note that the semiconductor device using the resistance change element as a memory element may be, for example, a resistive RAM (ReRAM), a phase change RAM (PCRAM), or the like. 5.1 Overall configuration of the semiconductor device

[0315] An example of an overall configuration of the semiconductor device 1 will be described with reference to Fig. 41 described. Fig. 41 is a block diagram illustrating the overall configuration of the semiconductor device 1. In Fig. 41, part of the coupling between components is indicated by an arrow line, but the coupling between the components is not limited to this.

[0316] As in Fig. 41, the semiconductor device 1 includes a memory cell array 91, a row decoder 92, a sense amplifier and write driver (SA / WD) 93, a page buffer 94, an input / output circuit 95, and a control circuit 96.

[0317] The memory cell array 91 includes a plurality of memory cells MC connected to a row and a column. Then, the memory cells MC in the same row are coupled to the same word line WL, and both ends of the memory cells MC in the same column are coupled to the same bit line BL. The bit line BL includes, for example, a local bit line and a global bit line. The memory cell MC includes a resistance changing element. The resistance element functions as a storage element that can write data by changing its resistance state, store the written data in a non-volatile manner, and read the data.

[0318] The row decoder 92 is coupled to the memory cell array 91 via the word line WL. The row decoder 92 decodes a row address indicating a row direction of the memory cell array 91. Then, the word line WL is selected according to a decoding result, and a voltage required for an operation such as writing and reading data is applied to the selected word line WL.

[0319] The row decoder 92 includes a digital signal control circuit 92a that processes the received digital signal.

[0320] The SA / WD93 is coupled to the memory cell array 91 via the bit line BL. The SA / WD93 supplies voltage to the memory cell MC, which is driven via the bit line BL, and writes and reads data to and from the memory cell MC. Specifically, a driver WD of the SA / WD93 writes data to the memory cell MC. Additionally, a sense amplifier SA of the SA / WD93 reads data from the memory cell MC.

[0321] The SA / WD93 includes a digital signal control circuit 93a that processes the received digital signal.

[0322] The buffer 94 temporarily stores data to be written into the memory cell array 91 and data to be read from the memory cell array 91 in data units called a page.

[0323] The buffer 94 contains a digital signal control circuit 94a that processes the received digital signal.

[0324] The input / output circuit 95 sends various signals received from the outside of the semiconductor device 1 to the control circuit 96 and the page buffer 94, and sends various information from the control circuit 96 and the page buffer 94 to the outside of the semiconductor device 1.

[0325] The input / output circuit 95 includes a digital signal control circuit 95a that processes the received digital signal.

[0326] The control circuit 96 is coupled to the row decoder 92, the SA / WD 93, the page buffer 94, and the input / output circuit 95. The control circuit 96 controls the row decoder 92, the SA / WD 93, and the page buffer 94 according to various signals received by the input / output circuit 95 from outside the semiconductor device 1.

[0327] The control circuit 96 functions as a digital signal control circuit that processes the received digital signal.

[0328] Similar to the first embodiment, an automatic placement and routing technique is used for the layout design of the digital signal control circuits included in the semiconductor device 1. 5.2 Circuit configuration of the memory cell array

[0329] Next, an example of a configuration of the memory cell array 91 will be described with reference to Fig. 42 described. Fig. 42 is a circuit diagram of the memory cell array 91. In the example of Fig. 42, the memory cell MC, the word line WL and the bit line BL are classified by indices containing an index (“<>”).

[0330] As in Fig. 42, the memory cells MC are arranged in a matrix in the memory cell array 91. Each memory cell MC is connected to a set of one of the bit lines BL (BL <0> , BL <1> ,..., BL <n>) and one of the word lines WL (WL <0> , WL <1> ,..., WL <m>) (M and N are arbitrary integers). That is, a memory cell MC<i, j> (0 ≤ i ≤ M, 0 ≤ j ≤ N) is between a word line WL and a bit line BL <j>tied together.

[0331] The memory cell MC<i, j> includes a selector SEL<i, j> and an element with magnetoresistive effect MTJ<i, j> . The selector SEL<i, j> and the element with magnetoresistive effect MTJ<i, j> are connected in series. For example, one end of the selector SEL<i, j> with a word line WL and the other end is connected to one end of the magnetoresistive element MTJ<i, j> The other end of the magnetoresistive element MTJ<i, j> is equipped with a bit line BL <j>coupled.

[0332] The selector SEL (hereinafter also referred to as "switching element") functions as a switch that controls the power supply to a corresponding magnetoresistive element MTJ during the write operation and the read operation to the magnetoresistive element MTJ. Specifically, for example, in a case where the voltage applied to the memory cell MC is less than a preset threshold voltage, the selector SEL in the memory cell MC interrupts the current flow by acting as an insulator with a high resistance value (and enters an off state). On the other hand, if the voltage applied to the memory cell MC is equal to or higher than the threshold voltage, the selector SEL causes the current to flow as a conductor with a small resistance value (enters the on state).That is, the selector SEL has the function of allowing or interrupting the current flow depending on the magnitude of the voltage applied to the memory cell MC, regardless of the direction of the flowing current.

[0333] For example, the selector SEL can be a two-terminal switching element. When the voltage applied between the two terminals is less than the threshold voltage, the selector SEL is in a high-resistance or non-conducting state, providing almost no current. When the voltage applied between the two terminals is equal to or higher than the threshold voltage, the selector SEL is in a low-resistance, electrically conductive state. The switching element can perform this function regardless of the voltage polarity.

[0334] The magnetoresistive element (MTJ) functions as a memory element that stores data in a non-volatile manner. The magnetoresistive element (MTJ) can be switched to a low-resistance or high-resistance state by a current supplied by the selector (SEL). The magnetoresistive element (MTJ) can write data by changing its resistance state. 5.3 Effect according to this embodiment

[0335] The configuration according to the present embodiment provides the same effects as those of the first embodiment. 6. Variation and the like

[0336] The semiconductor devices according to the above embodiments include a first cell (1010). The first cell includes a first PMOS transistor (TP10), a second PMOS transistor (TP11) arranged side by side with the first PMOS transistor in a first direction (X direction) and configured to share one end with one end of the first PMOS transistor, a first NMOS transistor (TN10) arranged side by side with the first PMOS transistor in a second direction (Y direction) that crosses the first direction, a second NMOS transistor (TN11) arranged side by side with the first NMOS transistor in the first direction and configured to share one end with one end of the first NMOS transistor, a first interconnection (130_90) electrically connected to another end of the first PMOS transistor, a second interconnection (130_91),which is electrically connected to one end of the first PMOS transistor and one end of the second PMOS transistor, a third connection (130_92) electrically connected to another end of the second PMOS transistor, a power supply voltage connection (150_1) extending in the second direction, over the first connection, the second connection, and the third connection, and electrically connected to the first connection, the second connection, and the third connection, a fourth connection (130_93) electrically connected to another end of the first NMOS transistor, a fifth connection (130_94) electrically connected to one end of the first NMOS transistor and one end of the second NMOS transistor, a sixth connection (130_95) electrically connected to another end of the second NMOS transistor, a ground voltage connection (150_3) extending in the second direction,provided above the fourth connection, the fifth connection, and the sixth connection and electrically connected to the fourth connection, the fifth connection, and the sixth connection, and a seventh connection (130a) provided in the same layer as the first to sixth connections and not electrically coupled to the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor.

[0337] By applying the above embodiments, it is possible to provide a semiconductor device capable of suppressing an increase in development costs and a lengthening of the development work period.

[0338] The embodiment is not limited to the embodiments described above, and various variations are possible.

[0339] For example, the semiconductor device 1 may be any semiconductor device to which the automatic placement and routing technique can be applied. The automatic placement and routing technique may be used for purposes other than the layout of the digital control circuit.

[0340] For example, in the first embodiment, as a specific example of using the through cell, the case where the M1 interconnection 130 of the ECO basic cell 1010 (ECO_NOR) in which the NOR circuit is configured and the M1 interconnection 130 of the ECO basic cell 1010 (ECO_I) in which the inverter circuit is configured are coupled via the ECO basic cell 1010 (ECO_T) in which the through cell is configured is described, but the present invention is not limited to this.For example, the M1 connection 130 of the ECO basic cell 1010 (ECO_NOR) in which the NOR circuit is configured and the M1 connection 130 of any one of the ECO basic cells 1010 (ECO_NAND) in which the NAND circuit is configured, the ECO basic cell 1010 (ECO_NOR) in which another NOR circuit is configured, the ECO basic cell 1010 (ECO_B) in which the buffer circuit is configured, the standard cell 1001 of the NAND circuit, the standard cell 1002 of the NOR circuit, the standard cell 1003 of the inverter circuit, or the standard cell 1004 of the buffer circuit may be connected via the ECO basic cell 1010 (ECO_T) in which the through cell is configured.For example, the M1 connection 130 of the ECO basic cell 1010 (ECO_NAND) in which the NAND circuit is configured and the M1 connection 130 of any ECO basic cell 1010 (ECO_NAND) in which another NAND circuit is configured, the ECO basic cell 1010 (ECO_I) in which the inverter circuit is configured, the ECO basic cell 1010 (ECO_B) in which the buffer circuit is configured, the standard cell 1001 of the NAND circuit, the standard cell 1002 of the NOR circuit, the standard cell 1003 of the inverter circuit, or the standard cell 1004 of the buffer circuit are connected via the ECO basic cell 1010 (ECO_T) in which the through cell is configured.For example, the M1 connection 130 of the ECO basic cell 1010 (ECO_I) in which the inverter circuit is configured and the M1 connection 130 of any ECO basic cell 1010 (ECO_I) in which another inverter circuit is configured, the ECO basic cell 1010 (ECO_B) in which the buffer circuit is configured, the standard cell 1001 of the NAND circuit, the standard cell 1002 of the NOR circuit, the standard cell 1003 of the inverter circuit, or the standard cell 1004 of the buffer circuit are coupled via the ECO basic cell 1010 (ECO_T) in which the pass-through cell is configured.For example, the M1 connection 130 of the ECO basic cell 1010 (ECO_B) in which the buffer circuit is configured and the M1 connection 130 of any ECO basic cell 1010 (ECO_B) in which another buffer circuit is configured, the standard cell 1001 of the NAND circuit, the standard cell 1002 of the NOR circuit, the standard cell 1003 of the inverter circuit, or the standard cell 1004 of the buffer circuit may be coupled via the ECO basic cell 1010 (ECO_T) in which the pass-through cell is configured.

[0341] For example, the through cells in the areas of coordinates (4, 2) and (5, 2) in the planar arrangement ( Fig. 26) of the first embodiment, the ECO base cells 1010a and 1010b in the Fig. 27 to 29. The transit cell in the area of coordinates (5, 2) in the planar arrangement ( Fig. 26) may have the M1 connection 130a_2 in the through cell, which is in the Fig. 16, Fig. 32 and Fig. 34. The ECO logic cell in the area of coordinates (5, 1) in the planar arrangement ( Fig. 26) can be connected to one of the standard cells 1001 of the NAND circuit, the standard cell 1002 of the NOR circuit and the standard cell 1003 of the inverter circuit in the area above the coordinates (5, 3) and (6, 3) in Fig. 26 are connected via the M1 connection 130a_2 in the through cell in the area of coordinates (5, 2). 26 are connected via the M1 connection 130a_2 in the through cell in the area of coordinates (5, 2). The through cells in the areas of coordinates (4, 3) and (4, 4) in the planar arrangement ( Fig. 26) may have the M1 connection 130a_2 in the through cell, which is in the Fig. 16, Fig. 32 and Fig. 34 is shown.

[0342] For example, the case where the standard cell and the ECO base cell are planar cells was described in the first embodiment, but the present invention is not limited to this. The standard cell and the ECO base cell may have a configuration of FinFETs, nanosheets, or the like.

[0343] In FinFETs, a gate electrode faces two or more surfaces of a channel region. The channel region is formed in a convex shape on a surface of the semiconductor substrate. A plurality of channels can be provided in one transistor.

[0344] In the nanosheets, the gate electrodes are arranged opposite each other, enclosing a channel region. The channel region is formed in a flat, plate-shaped semiconductor layer. A plurality of flat, plate-shaped semiconductor layers can be stacked one on top of the other.

[0345] Furthermore, the "coupling" in the above embodiments also includes a state in which the coupling is made indirectly with, for example, a transistor or a resistor arranged between two components.

[0346] Although specific embodiments have been described, these embodiments have been presented only as examples and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; further, various omissions, substitutions, and changes may be made to the methods and systems described herein without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications that would fall within the scope and spirit of the inventions. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2012-43894

[0003] < / j> < / j> < / m> < / n>

Claims

[1] A semiconductor device comprising a first cell (1010), the first cell comprising: a first PMOS transistor (TP10); a second PMOS transistor (TP11) arranged side by side with the first PMOS transistor in a first direction (X direction) and configured to share one end with one end of the first PMOS transistor; a first NMOS transistor (TN10) arranged side by side with the first PMOS transistor in a second direction (Y direction) crossing the first direction; a second NMOS transistor (TN11) arranged side by side with the first NMOS transistor in the first direction and configured to share one end with one end of the first NMOS transistor; a first connection (130_90) electrically coupled to another end of the first PMOS transistor; a second connection (130_91) electrically coupled to one end of the first PMOS transistor and one end of the second PMOS transistor; a third connection (130_92) electrically coupled to another end of the second PMOS transistor; a power supply voltage connection (150_1) extending in the second direction, provided over the first connection, the second connection and the third connection, and electrically coupled to the first connection, the second connection and the third connection; a fourth connection (130_93) electrically coupled to another end of the first NMOS transistor; a fifth connection (130_94) electrically coupled to one end of the first NMOS transistor and one end of the second NMOS transistor; a sixth connection (130_95) electrically coupled to another end of the second NMOS transistor; a ground voltage connection (150_3) extending in the second direction, provided above the fourth connection, the fifth connection, and the sixth connection, and electrically coupled to the fourth connection, the fifth connection, and the sixth connection; and a seventh interconnection (130a_1) provided in the same layer as the first to sixth interconnections and not electrically coupled to the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor. [2] A semiconductor device according to claim 1, wherein a gate of the first PMOS transistor and a gate of the second PMOS transistor are electrically coupled to the power supply voltage connection via the second connection, and a gate of the first NMOS transistor and a gate of the second NMOS transistor are electrically coupled to the ground voltage connection via the fifth connection. [3] The semiconductor device according to claim 1, wherein a gate of the first PMOS transistor, a gate of the second PMOS transistor, a gate of the first NMOS transistor, and a gate of the second NMOS transistor are electrically coupled to the power supply voltage connection via the second connection. [4] The semiconductor device according to claim 1, wherein a gate of the first PMOS transistor, a gate of the second PMOS transistor, a gate of the first NMOS transistor, and a gate of the second NMOS transistor are electrically connected to the ground voltage connection via the fifth connection. [5] The semiconductor device according to claim 1, wherein the seventh interconnection is formed over a gate of the first PMOS transistor and a gate of the first NMOS transistor, over a first element isolation region surrounding an active region (102) of the first PMOS transistor and the second PMOS transistor, and over a second element isolation region surrounding an active region (104) of the first NMOS transistor and the second NMOS transistor. [6] A semiconductor device according to claim 2, further comprising: a second cell (1010) adjacent to one end of the first cell in the second direction; and a third cell (1010) adjacent to another end of the first cell in the second direction, wherein the second cell and the third cell are electrically coupled via the seventh connection. [7] A semiconductor device according to claim 6, wherein each of the second and third cells is a NAND circuit (ECO_NAND), a NOR circuit (ECO_NOR), an inverter circuit (ECO_I) and a buffer circuit (ECO_B). [8] The semiconductor device according to claim 1, wherein the first cell further comprises an eighth interconnection (130a_2) passing through the first cell in the second direction, provided in the same layer as the first to seventh interconnections, and not electrically coupled to the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, the second NMOS transistor, and the seventh interconnection. [9] A semiconductor device according to claim 8, wherein the eighth interconnection passes over a gate of the second PMOS transistor and a gate of the second NMOS transistor, over a first element isolation region surrounding an active region (102) of the first PMOS transistor and the second PMOS transistor, and over a second element isolation region surrounding an active region (104) of the first NMOS transistor and the second NMOS transistor. [10] The semiconductor device according to claim 1, further comprising a fourth cell (1010) adjacent to the first cell in the first direction, the fourth cell comprising: a third PMOS transistor (TP10) adjacent to the second PMOS transistor in the first direction; a fourth PMOS transistor (TP11) arranged side by side with the third PMOS transistor in the first direction and configured to share one end with one end of the third PMOS transistor; a third NMOS transistor (TN10) arranged adjacent to the second NMOS transistor in the first direction and side by side with the third PMOS transistor in the second direction; a fourth NMOS transistor (TN11) arranged side by side with the third NMOS transistor in the first direction and configured to share one end with one end of the third NMOS transistor; a ninth connection (130_90) electrically coupling another end of the third PMOS transistor to the power supply voltage connection; a tenth connection (130_91) electrically coupling one end of the third PMOS transistor and one end of the fourth PMOS transistor to the power supply voltage connection; an eleventh connection (130_92) electrically coupling another end of the fourth PMOS transistor to the power supply voltage connection; a twelfth connection (130_93) electrically coupling another end of the third NMOS transistor to the ground voltage connection; a thirteenth connection (130_94) electrically coupling one end of the third NMOS transistor and one end of the fourth NMOS transistor to the ground voltage connection; and a fourteenth connection (130_95) electrically coupling another end of the fourth NMOS transistor to the ground voltage connection. [11] The semiconductor device according to claim 10, wherein the seventh interconnection passes through the first cell and the fourth cell in the second direction and is not electrically coupled to the first to fourth PMOS transistors and the first to fourth NMOS transistors. [12] The semiconductor device according to claim 11, wherein the seventh interconnection passes over a gate of the third PMOS transistor and a gate of the second NMOS transistor, over a third element isolation region surrounding an active region (102) of the third PMOS transistor and the fourth PMOS transistor, and over a second element isolation region surrounding an active region (104) of the first NMOS transistor and the second NMOS transistor. [13] A semiconductor device according to claim 1, wherein one end, the other end and a gate of the first PMOS transistor are electrically coupled to the power supply voltage connection, one end, the other end and a gate of the second PMOS transistor are electrically coupled to the power supply voltage connection, one end, the other end and a gate of the first NMOS transistor are electrically coupled to the ground voltage connection, and one end, the other end and a gate of the second NMOS transistor are electrically coupled to the ground voltage connection. [14] A semiconductor device according to claim 1, wherein one end, the other end and a gate of the first PMOS transistor are electrically coupled to the power supply voltage connection, one end, the other end and a gate of the second PMOS transistor are electrically coupled to the power supply voltage connection, one end and the other end of the first NMOS transistor are electrically coupled to the ground voltage connection and a gate of the first NMOS transistor is electrically coupled to the power supply voltage connection, and one end and the other end of the second NMOS transistor are electrically coupled to the ground voltage connection and a gate of the second NMOS transistor is electrically coupled to the power supply voltage connection. [15] A semiconductor device according to claim 1, wherein one end and the other end of the first PMOS transistor are electrically coupled to the power supply connection and a gate of the first PMOS transistor is electrically coupled to the ground voltage connection, one end and the other end of the second PMOS transistor are electrically coupled to the power supply voltage connection and a gate of the second PMOS transistor is electrically coupled to the ground voltage connection, one end, the other end and a gate of the first NMOS transistor are electrically coupled to the ground voltage connection, and one end, the other end and a gate of the second NMOS transistor are electrically coupled to the ground voltage connection. [16] A method of designing a semiconductor device, the method comprising: Arranging a plurality of first cells (1001, 1002, 1003 or 1004) (S1); Coupling of the first cells by connections (S2); Arranging a plurality of second cells (1010(ECO_C)) in an area in which the first cells are not arranged (S3); Changing at least one of the second cells into a logic cell (S9) and changing at least one other of the second cells into a third cell (1010(ECO_T)) (S13); and Coupling the logic cell to a first connection (130a) passing through the third cell and not electrically coupled to the third cell (S11). [17] A method of designing a semiconductor device according to claim 16, wherein each of the first cells is a NAND circuit (1001), a NOR circuit (1002), an inverter circuit (1003) or a buffer circuit (1004), each of the second cells is a decoupling capacitor, and the logic cell is one of a NAND circuit (ECO_NAND), a NOR circuit (ECO_NOR), an inverter circuit (ECO_I) and a buffer circuit (ECO_B). [18] A method of designing a semiconductor device according to claim 16, wherein when the logic cell cannot be coupled by connection in the change, at least the other of the second cells is changed to the third cell. [19] A method of manufacturing a semiconductor device, the method comprising: Arranging a plurality of first cells (1001, 1002, 1003 or 1004) (S1); Connection of the first cells (S2); Arranging a plurality of second cells (1010(ECO_C)) in an area in which the first cells are not arranged (S3); Creating a mask used in the formation of a transistor (S6); Manufacturing a transistor based on the mask (S7); Changing at least one of the second cells into a logic cell (S9) and changing at least one other of the second cells into a third cell (1010(ECO_T)) (S13); and coupling the logic cell to a first connection (130a) passing through the third cell and not electrically coupled to the third cell (S11), where the creation of the mask and the coupling of the logic cell and the first connection are carried out in parallel. [20] A method of manufacturing a semiconductor device according to claim 19, wherein the fabrication of the transistor and the coupling of the logic cell to the first interconnection are carried out in parallel.

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