Device and method for processing receive data in a receive data path including parallel FEC decoding

Abstract

A device comprises a data width converter and a forward error correction (FEC) decoder. The data width converter includes an input for receiving an input data stream having an input bit width, a first output for generating a first output data stream having a first output bit width, and a second output for generating a second output data stream having at least a second output bit width. The FEC decoder includes an input for receiving the second output data stream having the at least second output bit width. The FEC decoder includes an error correction output for generating one or more error correction values based at least in part on one or more FEC codewords in the second output data stream.The one or more error correction values are used to correct one or more symbols, one or more subsymbols, or both in the first output data stream having the first output bit width. In one or more examples, the data width converter is located in a receive data path, and at least a portion of the FEC decoder is located parallel to the receive data path.

Description

PRIORITY CLAIM

[0001] This application claims the benefit of the filing date of U.S. Provisional Patent Application No. 63 / 378,690, filed October 7, 2022, for "FEC DECODER IMPLEMENTATION FOR LOW AND CONSTANT LATENCY," the disclosure of which is hereby incorporated by reference in its entirety. TECHNICAL FIELD

[0002] This disclosure relates generally to transceivers, and more particularly to transceivers that process data for communication, including encoding and / or decoding for error correction of data. Additionally, devices and methods are disclosed. BACKGROUND

[0003] Various applications require communication at high data rates over relatively short distances. For example, on-board systems in vehicles, certain industrial systems, and smart home systems would benefit from this type of communication. Various types of protocols and communication media have been proposed and developed for such applications. Adapting functional components to these developments often requires innovative, efficient design solutions. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] While this disclosure concludes with claims that particularly point out and distinctly claim particular examples, various features and advantages of examples within the scope of this disclosure may be more readily appreciated from the following description when read in conjunction with the accompanying drawings, in which: Fig. 1 is a schematic block diagram of a transmit physical layer (PHY) of a transmitter known to the inventor of this disclosure. Fig. 2 is a schematic block diagram of a transmit PHY of a transmitter according to one or more examples of the disclosure. Fig. 3A is a flowchart illustrating a process for processing transmit data in a transmit data path that includes parallel forward error correction (FEC) coding, according to one or more examples. Fig. 3B is an apparatus for processing transmit data in a transmit data path including parallel FEC encoding, according to one or more examples. Fig. Figure 4 is a table of the number of data bits transmitted per clock cycle corresponding to the operation of a data width converter in the transmit PHY of Fig. 2, according to one or more examples. Fig. 5A is a schematic block diagram of a receive physical layer (PHY) of a receiver known to the inventor of this disclosure. Fig. Figure 5B is a schematic block diagram of an FEC decoder of the receive PHY of Fig. 5A, which is known to the inventor of this disclosure. Fig. 6A is a schematic block diagram of a receive PHY of a receiver according to one or more examples of the disclosure. Fig. 6B is a block diagram of a receive PHY of a circuit section in Fig. 6A, according to one or more examples. Fig. Figure 6C is a block diagram of an FEC decoder of Fig. 6A, according to one or more examples. Fig. 7A is a flowchart illustrating a process for processing receive data in a receive data path including parallel FEC decoding, according to one or more examples. Fig. 7B is an apparatus for processing receive data in a receive data path including parallel FEC decoding, according to one or more examples. Fig. Figure 8 is a table of the number of data bits transmitted per clock cycle corresponding to the operation of a data width converter in the receive PHY of Fig. 6A-6C, according to one or more examples. Fig. 9 is a lookup table (LUT) for a latency predictor associated with the receive PHY, according to one or more examples. Fig. 10 is a syndrome calculator that provides the FEC decoder of the receiving PHY of Fig. 6A-6C, according to one or more examples. Fig. 11 is an example of an error locator polynomial (ELP) algorithm coupled to the receive PHY's FEC decoder, according to one or more examples. Fig. Figure 12 is a timing diagram for the communication processing associated with the receive data path and including an integrated FEC decoding approach. Fig. Figure 13 is a timing diagram for the communication processing associated with the receive data path and having a parallel FEC decoding approach. Fig. 14A and Fig. 14B are timing diagram portions of a timing diagram for communication processing associated with using a first clock rate for the receive data path and a second clock rate (i.e., a higher clock rate) for the ELP algorithm. Fig. 15A and Fig. 15B are timing diagram sections of a timing diagram for communication processing associated with variable symbol syndrome calculation. Fig. 16 is a block diagram of circuit logic that may be used, in some examples, to implement various functions, operations, acts, processes, and / or methods disclosed herein. MODE(S) FOR CARRYING OUT THE INVENTION

[0005] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific examples in which the present disclosure may be practiced. These examples are described in sufficient detail to enable those skilled in the art to practice the present disclosure. However, other examples contemplated herein may be utilized, and changes in structure, material, and process may be made without departing from the scope of the disclosure.

[0006] The illustrations presented herein are not intended to be actual views of any particular method, system, device, or structure, but are merely idealized representations used to describe the examples of the present disclosure. In some cases, similar structures or components may retain the same or similar numbering in the various drawings for the convenience of the reader; however, similarity in numbering does not necessarily imply that the structures or components are identical in size, composition, configuration, or any other characteristic.

[0007] The following description may include examples to enable those skilled in the art to practice the disclosed examples. The use of the terms "exemplary," "as an example," and "for example" means that the accompanying description is illustrative, and while the scope of the disclosure is intended to include the examples and their legal equivalents, the use of these terms is not intended to limit the scope of the examples or this disclosure to the specified components, steps, features, functions, or the like.

[0008] It should be understood that the components of the examples, as generally described herein and illustrated in the drawings, may be arranged and configured in a variety of different configurations. Thus, the following description of various examples is not intended to limit the scope of the present disclosure, but is merely representative of various examples. While the various aspects of the examples may be illustrated in the drawings, the drawings are not necessarily drawn to scale unless expressly indicated.

[0009] Furthermore, the specific implementations shown and described are only examples and should not be construed as the only way to implement the present disclosure unless otherwise stated herein. Elements, circuits, and functions may be shown in block diagram form in order not to obscure the present disclosure with unnecessary detail. Conversely, specific implementations shown and described are only examples and should not be construed as the only way to implement the present disclosure unless otherwise stated herein. Furthermore, block definitions and the partitioning of logic between different blocks are exemplary of a specific implementation. It will be readily apparent to those skilled in the art that the present disclosure may be practiced using numerous other partitioning solutions.Details of timing considerations and the like have largely been omitted to the extent that such details are not necessary for a complete understanding of the present disclosure and are within the capabilities of those skilled in the art.

[0010] Those of ordinary skill in the art will understand that information and signals may be represented using a variety of different technologies and techniques. Some drawings may illustrate signals as a single signal for clarity of illustration and description. Those of ordinary skill in the art will understand that the signal may represent a bus of signals, where the bus may have a variety of bit widths, and the present disclosure may be implemented with any number of data signals, including a single data signal.

[0011] The various illustrative logic blocks, modules, and circuits described in connection with the examples disclosed herein may be implemented or performed using a general-purpose processor, a special-purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof configured to perform the functions described herein. A general-purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but alternatively, it may be any conventional processor, control unit, microcontroller, or state machine.A processor may also be implemented as a combination of data processing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. A general-purpose computer including a processor is considered a special-purpose computer, while the general-purpose computer is used to execute computational instructions (e.g., software code) related to examples of the present disclosure.

[0012] The examples may be described with respect to a process represented as a flowchart, a flow sheet, a structure diagram, or a block diagram. Although a flowchart may describe operational acts as a sequential process, many of these acts may be performed in a different sequence, in parallel, or substantially concurrently. Furthermore, the order of the acts may be changed. A process may correspond to a method, a thread, a function, a procedure, a subroutine, a subprogram, another structure, or combinations thereof. Furthermore, the methods disclosed herein may be implemented in hardware, software, or both. When implemented in software, the functions may be stored or dispatched as one or more instructions or as code on computer-readable media.Computer-readable media includes both computer storage media and communications media, including any media that supports the transfer of a computer program from one location to another.

[0013] Any reference to an element herein using a label such as "first," "second," etc., does not limit the quantity or order of those elements unless such a limitation is expressly stated. Rather, these labels may be used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, a reference to a first and a second element does not imply that only two elements may be employed or that the first element must precede the second element in any way. Furthermore, unless otherwise stated, a set of elements may include one or more elements.

[0014] As used herein, the term "substantially" with respect to a given parameter, property, or condition means, and includes, to the extent understood by one skilled in the art, that the given parameter, property, or condition is satisfied with a small degree of variance, such as within acceptable manufacturing tolerances. By way of example, depending on the specified parameter, property, or condition that is substantially satisfied, the parameter, property, or condition may be at least 90% satisfied, at least 95% satisfied, or even at least 99% satisfied.

[0015] In a traditional approach to designing an Ethernet physical layer (PHY) transceiver, when a forward error correction (FEC) block is integrated into or downstream of the datapath, much of the datapath operates at integer multiples of the FEC symbol width. However, the outgoing data width is generally not an integer multiple of the FEC symbol width, and therefore one or more additional data width converters (e.g., gearing) and read-pause mechanisms may be employed. For example, in the Institute of Electrical and Electronics Engineers (IEEE) 802.3ch, 2.5GT1 Automotive Ethernet PHY, the FEC symbol width is ten (10) bits, the datapath width can be either seventy (70) bits or eighty (80) bits, and the output data width is sixty-five (65) bits.

[0016] Such an approach introduces latency into Ethernet packet communication. This latency is a data-dependent latency that can change from one packet to the next and is therefore a variable latency. Ethernet packets are timestamped to synchronize network time according to IEEE 1588. A packet's timestamp point (sometimes referred to as the "reference plane") is set at the edge of a device A, typically a point corresponding to the media-dependent interface (MDI). Tracking a packet at the edge of a device can be challenging, so IEEE 802.3 specifies that an initial timestamp is generated when a packet traverses the media-independent interface (MII) and then adjusted by an amount representing the path data delay to calculate a second, final timestamp corresponding to the MDI reference plane.

[0017] For proper timestamping, a fixed latency should be guaranteed in the PHY, or alternatively, predictor logic should be provided to calculate the amount of variable latency incurred per packet to adjust the timing discussed above. For example, a first packet might have an adjustment of three (3) clock cycles, a second packet might have an adjustment of ten (10) clock cycles, and so on.

[0018] Predictor logic tends to be relatively complex, as it must estimate packet delay by accurately predicting the beginning of the Ethernet packet, which is blocked by, for example, two data width converters and the FEC blocker. This complex predictor logic becomes even more complex when modules are configured to stall the data path. Furthermore, it is often desirable to reduce the overall latency of packets in the PHY, for example, for compliance with, but not limited to, Time-Sensitive Networking (TSN) and real-time communication standards.

[0019] Therefore, the traditional approach may use multiple data width converters. In some implementations of the traditional approach, certain modules may pause communication. This pause introduces latency that can further complicate the predictor logic. In a transmit data path, the latency of a frame is determined at least in part by the number of data width converters and the FEC block. The traditional approach therefore includes multiple sources of variable latency. In a receive data path, the latency of a frame is determined at least in part by the depth of the first-in, first-out (FIFO) buffer, which in turn is determined by the time it takes for the FEC decoder to correct the frame. The time it takes for the FEC decoder to correct a frame is determined by an error localization polynomial (ELP) algorithm.Furthermore, the width of the FIFO buffer in the FEC decoder should match the width of the FEC symbol, which results in several unwanted flops being used even though only a single FEC frame needs to be stored.

[0020] One or more examples generally relate to reducing latency and latency variation. One or more examples relate to a transmitter section of a PHY transceiver capable of reducing latency and latency variation. In one or more examples, the transmitter section is capable of reducing latency and latency variation to comply with TSN and IEEE 1588. In one or more examples, the transmitter section includes a latency predictor to determine a latency value that can be used to represent a predicted latency. In one or more examples, the latency predictor can be or include a lookup table (LUT). In one or more examples, the transmitter section has a relatively reduced area compared to the conventional approach.

[0021] In one or more examples, the transmitter section includes an FEC encoder parallel to the transmit data path. In one or more examples, the FEC encoder is at least substantially separate and operable independently of the transmit data path. In one or more examples, the FEC encoder is operable at a symbol width (“symbol width” is the data width in terms of the number of symbols) that is different from a symbol width associated with the data path. In one or more examples, the number of data width converters in the transmit data path is one (1) data width converter, which reduces latency in the transmit data path otherwise caused by additional data width converters. In one or more examples, the transmit data path provides a guaranteed fixed latency in (e.g., most or all, but not limited to) modules of the transmitter section of the PHY transceiver, except for (e.g.,single, but not limited to, data width converters.

[0022] One or more examples relate to a receiver section of a PHY transceiver capable of reducing latency and latency variation. In one or more examples, the receiver section is capable of reducing latency and latency variation to comply with TSN and IEEE 1588. In one or more examples, the receiver section includes a latency predictor to determine latency. In one or more examples, the latency predictor may be or include a lookup table (LUT). In one or more examples, the receiver section of the PHY transceiver has a relatively reduced area compared to the conventional approach.

[0023] In one or more examples, the receiver section includes an FEC decoder in parallel with the receive data path. In one or more examples, the FEC decoder is at least substantially separate and operable independently of the receive data path. In one or more examples, the FEC encoder is operable at a symbol width that is different from a symbol width associated with the receive data path. In one or more examples, the number of data width converters in the receiver data path is one (1) data width converter. In one or more examples, the receive data path provides a guaranteed fixed latency in (e.g., most or all, but not limited to) modules of the receiver section of the PHY transceiver, except for (e.g., any, but not limited to) the data width converter.

[0024] In one or more examples, the parallel FEC decoder processing may include a symbol error corrector for correcting subsymbols and an error magnitude generator for selecting the number of error magnitude bits to provide to the symbol error corrector. Further, in one or more examples, a syndrome calculator of the parallel FEC decoder may be one that operates on a variable number of symbols (e.g., seven (7) or eight (8) FEC symbols per clock). Further, in one or more examples, an ELP algorithm of the FEC decoder may be set to execute at a different clock rate (e.g., higher, but not limited to) than the clock rate of the receive data path.

[0025] Fig. Figure 1 shows a schematic block diagram of a transmit physical layer (PHY) of a transmitter (referred to herein as "transmitter section 100") known to the inventor of this disclosure. The transmitter section 100 may be at least part of an Ethernet physical layer (Ethernet PHY) transceiver for transmitting transmit data or Ethernet frames. For example, the transmitter section 100 may be compliant with the Institute of Electrical and Electronics Engineers (IEEE) 802.3ch, 2.5GT1 Automotive Ethernet PHY, and in particular, the "IEEE Standard for Ethernet - Amendment 8: Physical Layer Specifications and Management Parameters for 2.5 Gb / s, 5 Gb / s, and 10 Gb / s Automotive Electrical Ethernet," IEEE 802.3ch-2020, June 2020, for incorporating the next generation of onboard vehicle networks.

[0026] The transmitter section 100 includes (from left to right in the figure) a media access control (MAC) interface (I / F) (MAC-I / F) 102, timestamp control circuitry 104, a physical coding sublayer encoder (PCS encoder) 106, a data width converter 108 (which may also be referred to herein as "transmission 108"), an FEC encoder 110, a data width converter 112 (which may also be referred to herein as "transmission 112"), a scrambler 114, a precoder and mapper 116, and a transmitter multiplexer (MUX) 118. The scrambler 114 may include an output 158 to a training top module 120 coupled to transmit MUX 118 for training path selection.

[0027] As in Fig. 1, many of the modules of transmitter section 100 are connected downstream (e.g., serially, sequentially, or both, without limitation) to a transmit data path 101 for communicating data from a link layer to a transmission medium (e.g., a shared transmission medium such as twisted pair, without limitation). In particular, FEC encoder 110 is integrated with or downstream of transmit data path 101. FEC encoder 110 operates (e.g., processes symbols, without limitation) at an FEC symbol width. The FEC symbol width of FEC encoder 110 is ten (10) bits.

[0028] Most of the transmit data path 101 operates at integer multiples of the FEC symbol width. However, the subsequently requested or outgoing data width (e.g., seventy-two (72) bits) is not an integer multiple of the FEC symbol width. Because the outgoing data width is not an integer multiple of the FEC symbol width, one or more additional data width converters and read pause mechanisms are employed. For example, the transmit data path 101 includes (e.g., the additional) data width converter 112, and the FEC encoder 110 can generate a "read pause" for the data width converter 108 via an output 132 if necessary.

[0029] As in Fig. 1, the data width converter 108 includes an input to receive a data stream 150 having a first bit width and an output to generate a data stream 152 having a second bit width. The FEC encoder 110 includes an input to receive the data stream 152 having the second bit width and an output to generate a data stream 154 having the (same) second bit width. The data width converter 112 includes an input to receive a data stream 154 having the second bit width and an output to generate a data stream 156 having a third bit width.

[0030] To support 2.5GT1, the FEC symbol width is ten (10) bits, the first bit width of data stream 150 is sixty-five (65) bits (e.g., @ 25.6 ns), the second bit width of data streams 152 and 154 (e.g., to and from FEC encoder 110) is seventy (70) bits (e.g., @ 25.6 ns), and the third bit width of data stream 156 is seventy-two (72) bits (e.g., @ 25.6 ns).

[0031] Before being processed by the FEC encoder 110, Ethernet packets may be time-stamped by the time-stamping logic 104 (in Fig. 1 referred to as "TS 1588 104"). Time-stamping of Ethernet packets provides network chronological synchronization for IEEE 1588 compliance (e.g., but not limited to, Precision Time Protocol (PTP). Specifically, time-stamping circuitry 104 receives and timestamps Ethernet packets from MAC I / F 102 in a sixty-four (64)-bit 10 Gigabit Media Independent Interface (XGMII) data stream. XGMII is a high-speed serial data system interface for communication between the voting sublayer (RS) and the PCS for 10 gigabits per second (Gbps) operation.

[0032] The modules and the arrangement of the modules in the transmitter section 100 result in latency in the communication of Ethernet packets. This latency is a variable latency that changes from one packet to the next. To comply with Time-Sensitive Networking (TSN) and real-time Ethernet communication standards, it is desirable to reduce the overall latency of the packets in the PHY. For correct time stamping by the time stamping logic 104, a guaranteed fixed latency should be present in the PHY, or alternatively, predictor logic should be provided to calculate a variable latency incurred per packet to correctly adjust the timing.

[0033] The transmitter section 100 includes a latency predictor 122 having an output 130 operatively coupled to the timestamp circuitry 104 for timing adjustment. However, the latency predictor 122 includes complex predictor logic ("1588 predictor logic") to generate a predicted variable latency at an output 130 based on multiple sources of variable latency, as indicated in the figure. Generally, the latency in the transmit data path 101 is determined by the number of transmissions and the FEC block. The latency predictor 122 includes relatively complex logic to estimate the delay of the Ethernet packet by determining the beginning of the packet transmitted through the two (2) data width converters 108 and 112 and the FEC encoder 110. The latency predictor 122 becomes even more complex when the FEC encoder 110 stops the transmit data path 101 at the data width converter 108 via the output 132.

[0034] Fig. 2 is a schematic block diagram of a transmit physical layer (PHY) of a transmitter (referred to herein as "transmitter section 200") according to one or more examples of the disclosure. In one or more examples, transmitter section 200 may be at least part of an Ethernet physical layer (Ethernet PHY) transceiver for transmitting transmit data (e.g., one or more symbols, without limitation), such as Ethernet frames (e.g., an Ethernet frame is transmitted as a series of symbols at a physical layer, without limitation). In one specific non-limiting example, transmitter section 200 is compliant with the IEEE 802.3ch, 2.5GT1 Automotive Ethernet PHY, as described above.

[0035] The transmitter section 200 may include a transmit data path 201 for communicating data from a link layer to a transmission medium. The transmitter section 200 includes (from left to right in the figure) a MAC I / F 202, a timestamp circuit 204, a PCS encoder 206, a data width converter 208 (or "gearbox"), an FEC encoder 212, a scrambler 214, a precoder and mapper 216, and a transmit MUX 218. The precoder and mapper 216 generates pulse amplitude modulated (PAM) (e.g., 2-level) (PAM-2) signals based on the received data stream. For training, the scrambler 214 includes an output to a training top module 222 coupled to a selectable input of the transmit MUX 218 (a selectable input for selecting a training path).A control signal 220 (“PHY control 220”) from a PHY control unit (control unit not shown) is transmitted to the MUX 218 to select the data or training path.

[0036] As in Fig. 2, the data width converter 208 is located in the transmit data path 201, and the FEC encoder 212 is parallel to the transmit data path 201. As an illustrative example, the FEC encoder 212 may be arranged in a parallel path 203 that is parallel to at least a portion of the transmit data path 201 and / or the data width converter 208. The FEC encoder 212 may operate at least substantially separately and independently of the transmit data path 201. Due to this arrangement, the transmit data path 201 provides a fixed latency for data transmission.

[0037] In one or more examples, transmit data path 201 includes (e.g., only) a single data width converter (i.e., data width converter 208). Although "single" within transmit data path 201, data width converter 208 may consist of two or more separate data width converter circuits to generate the two respective output data streams (first and second output data streams 252 and 256), or alternatively, use shared circuitry to generate the different streams.

[0038] In particular, as in Fig. 2, an input of the data width converter 208 maps at least partially to an output of the PCS encoder 206. The data width converter 208 includes an input for receiving an input data stream 250 (e.g., the input data stream 250 is based at least partially on an output of the PCS encoder 206) having an input bit width, a first output for generating a first output data stream 252 having a first output bit width, and a second output for generating a second output data stream 256 having a second output bit width. In one or more examples, the input bit width, the first output bit width, and the second output bit width are different from one another.

[0039] The scrambler 214 includes an input for receiving the first output data stream 252 at the first output bit, and an output for generating a scrambled output data stream 254 based at least in part on the first output data stream 252. The scrambled output data stream 254 is provided for subsequent processing by the precoder and mapper 216 and transmitted via the transmit MUX 218. The FEC encoder 212 includes an input for receiving the second output data stream 256 having the second output bit width, and an output for generating parity bits 258 based at least in part on a plurality of received symbols of the second output data stream 256. The parity bits 258 are for insertion into the first output data stream 252 having the first output bit width.The first output data stream 252 received at the input of the scrambler 214 includes the inserted parity bits from the parity bits 258 generated by the FEC encoder 212.

[0040] In particular, the output of the FEC encoder 212 generates parity bits 258 for the respective ones of the plurality of received symbols of the second output data stream 256 for insertion at respective intervals of the first output data stream 252. A parity insertion circuit 210 may insert the parity bits 258. In one or more examples, the parity insertion circuit 210 may be part of the data width converter 208 or separate from it (e.g., an input of the parity insertion circuit 210 may receive an output of the data width converter 208, insert corresponding parity bits 258 into the received output of the data width converter 208, and generate the second output data stream 256 including, but not limited to, corresponding parity bits). In one or more examples, the parity insertion circuit 210 inserts the generated parity bits into the respective intervals of the first output data stream 252.

[0041] The output of FEC encoder 212 generates parity bits 258 based on the multiple symbols received (e.g., k symbols, where k = 360) over a number of clock cycles, each of the k symbols having a symbol width of s bits (e.g., s = 10 bits). Thus, FEC encoder 212 operates at a symbol width different from the requirements of transmit data path 201 and keeps its generated parity bits ready for insertion before the next FEC frame begins. In one or more examples, the second output bit width of the second output data stream 256 is an integer multiple of the symbol width of the FEC encoder 212. In one or more examples, the input bit width of the input data stream 250 is not an integer multiple of the symbol width and / or the first output bit width of the first output data stream 252 is not an integer multiple of the symbol width.

[0042] In one or more examples, little to no latency is introduced by the FEC encoder 212 disposed in the parallel path 203. In one or more examples, the modules and the arrangement of the modules in the transmitter section 200 reduce the latency in communicating Ethernet packets (e.g., by one clock cycle) and / or reduce or eliminate the variability of the latency in the transmit data path 201.

[0043] In one or more examples, the transmitter section 200 of the PHY transceiver is configured according to IEEE 802.3ch 2.5GT1. To comply with 2.5GT1, the symbol width is ten (10) bits, the input bit width of the input data stream 250 is sixty-five (65) bits (e.g., @ 25.6 ns), the first output bit width of the first output data stream 252 (e.g., to scrambler 214) is seventy-two (72) bits (e.g., @ 25.6 ns), and the second output bit width of the second output data stream 256 (e.g., to FEC encoder 212) is seventy (70) bits (e.g., at 25.6 ns). The scrambler 214 outputs the scrambled output data stream 254 at the first output, also with a bit width of seventy-two (72) bits (e.g., at 25.6 ns). Each IEEE 802.3ch FEC frame runs for fifty (50) clock cycles.

[0044] In one or more examples, the FEC encoder 212 is a Reed-Solomon (RS) FEC encoder that uses an RS code (e.g., but not limited to, parity bits are an RS code). In one or more examples, the FEC encoder 212 uses an RS code of RS(360,326). In one or more examples, an RS code may be represented by RS(n, k), where n = the total number of symbols in the FEC codeword, k = the number of data symbols for data, and (nk) = the number of parity symbols for parity.

[0045] In one or more other examples, the transmitter section 200 is configured according to one or more different standards, bit rates, bit widths, speeds, and / or codes.

[0046] In one or more examples, the FEC encoder 212 may be an FEC encoder that processes distributed symbols, for example, an FEC encoder that operates on a variable number of symbols from one clock (e.g., one or more first clocks) to the next (e.g., one or more second clocks) to adjust the incoming data rate. As an example, the FEC encoder 212 may operate on seven (7) symbols for one or more first clocks, followed by eight (8) symbols for one or more second clocks. As an example, the FEC encoder 212 may operate on six (6) symbols for one or more first clocks, followed by seven (7) symbols for one or more second clocks.

[0047] In one or more examples, the data width converter 208 may stop the FEC encoder 212 (e.g., regularly or periodically) if and as desired or required, without introducing variable latency into the transmit data path 201. For example, the data width converter 208 may stop the FEC encoder 212 every five (5) or six (6) cycles (e.g., for 2.5GT1). In the traditional approach (i.e., using the integrated FEC encoder in Fig. 1) Any pause towards the FEC encoder would halt the transmission of data downstream or not provide sufficient bandwidth for the insertion of the parity bits.

[0048] The timestamp circuit 204 is located in the transmit data path 201 to time-stamp the data stream communication (e.g., according to TSN, IEEE 1588 (PTP)). Specifically, the timestamp circuit 204 receives Ethernet packets from the MAC I / F 202 in a sixty-four (64) bit-width data stream according to XGMII and timestamps them. For any latency adjustments, a latency predictor 224 is operatively coupled to the data width converter 208, and the timestamp circuit 204 is operatively coupled to the latency predictor 224. Additionally, in one or more examples, the latency predictor 224 receives a start-of-packet (SOP) indication at an output 262 of the PCS encoder 206. The latency predictor 224 selects a latency value in response to a clock count value provided at an output 260 of the data width converter 208.In one or more examples, the latency predictor 224 includes a lookup table (LUT) with latency values each associated with clock count values.

[0049] The time stamp circuit 204 receives a latency value 264 (in Fig. 2 as a “predicted latency value 264”) from the latency predictor 224 and adjusts a timing of the timestamp circuit 204 based at least in part on the latency value 264. In one or more examples, the latency values in the lookup table are fixed latency values or predetermined latency values that depend on the (e.g., current, relative) clock count. The current, relative clock count may refer to a repeating cycle of clock counts, for example, a repeating cycle of 1 to 50 clock counts or another clock count range. A specific, non-limiting example of such a lookup table for the latency predictor associated with the receiver section of the PHY transceiver is described later with respect to Fig. 9 shown and described.

[0050] With reference to the specific, non-limiting example of Fig. 4, a table 400 is displayed with the numbers of transferred data bits per clock cycle, which corresponds to the operation of the data width converter 208 of Fig. 2. The number of data bits transmitted per clock cycle includes the number of data bits transmitted from the data width converter to the scrambler (“converter-to-scrambler”) and the number of data bits transmitted from the data width converter to the FEC encoder (“converter-to-FEC encoder”). The “Converter-to-Scrambler” column in Table 400 is associated with the first output data stream 252, which has the first output bit width ( Fig. 2) (e.g., seventy-two (72) bits); and the “Converter-to-FEC Encoder” column in table 400 is associated with the second output data stream 256 having the second output bit width ( Fig. 2) (e.g. seventy (70) bits or seven (7) symbols).

[0051] The values in the "Clock Count" column each indicate a current clock count associated with a repeating cycle of clock counts, for example, a repeating cycle of 1 to 50 clock counts or another clock count range. Here, the FEC encoder receives seven (7) symbols per clock cycle with a symbol width of ten (10) bits, for a total of seventy (70) bits per clock cycle. Using the RS code RS(360, 326), the FEC encoder operates to generate three hundred forty (340) parity bits (or thirty-four (34) parity symbols for a 10-bit symbol width) every fifty (50) clock cycles, based on 3260 data bits or 326 10-bit data symbols (i.e., 70 data bits x 46 clock cycles + 40 data bits x 1 clock cycle = 3260 data bits or 326 10-bit data symbols). The "P" in the "Converter-to-FEC Encoder" column indicates the insertion of the generated parity bits of the (e.g., first) FEC frame and / or FEC codeword.In the clock cycle preceding the insertion of the parity bit "P," the FEC encoder receives only forty (40) bits or four (4) symbols. The "Second FEC Frame Begins" indication in the "Converter-to-Scrambler" column indicates the beginning of the next (e.g., second) FEC frame.

[0052] Fig. 3A is a flowchart illustrating a process 300 for processing transmit data in a system including parallel FEC encoding, according to one or more examples.

[0053] In one or more examples, process 300 may include converting an input data stream having an input bit width into a first output data stream having a first output bit width and into a second output data stream having a second output bit width in an operation 302. In one or more examples, the input bit width, the first output bit width, and the second output bit width are different from one another. In one or more examples, operation 302 may include multiple conversion acts.

[0054] In one or more examples, process 300 may include performing FEC encoding on a plurality of received symbols of the second output data stream having the second output bit width to generate parity bits in an operation 304.

[0055] In one or more examples, process 300 may include inserting the generated parity bits into the first output data stream in an operation 306. In one or more examples, process 300 may include generating parity bits for respective ones of the plurality of received symbols of the second output data stream for insertion at respective intervals of the first output data stream.

[0056] In one or more examples, the conversion (e.g., in operation 302) of the input data stream having the input bit width to the first output data stream having the first output bit width is performed in a transmit data path, and the performance (e.g., in operation 304) of at least a portion of the FEC encoding is performed in parallel with the transmit data path. In one or more examples, the transmit data path provides a fixed latency in the communication of the first output data stream.

[0057] In one or more examples, the input data stream having the input bit width may be received by a PCS encoder. In one or more examples, the first output data stream having the first output bit width may include the inserted parity bits and may subsequently be scrambled (e.g., by, but not limited to, a scrambler).

[0058] In one or more examples, performing FEC encoding (e.g., in operation 304) may include performing FEC encoding on the plurality of received symbols comprising k symbols (e.g., received over multiple clock cycles), where each of the k symbols comprises a symbol width of s bits. Where "k" is an integer greater than or equal to 1. In one or more examples, the second output bit width is a multiple of the symbol width of s bits. In one or more examples, the symbol width is ten (10) bits. In one or more examples, the input bit width is sixty-five (65) bits, the first output bit width is seventy-two (72) bits, and the second output bit width is seventy (70) bits.

[0059] In one or more examples, process 300 may include signaling a latency predictor with a clock count value. The latency predictor includes a lookup table with latency values each associated with clock count values. In one or more examples, process 300 may include adjusting a timing of a timestamp process for timestamping data stream communications based at least in part on a latency value received from the latency predictor, wherein the latency value is responsive to the clock count value.

[0060] Fig. 3B is a device 350 for processing transmit data in a transmit data path that includes parallel FEC encoding, according to one or more examples. In one or more examples, device 350 includes a data width converter 352 and an FEC encoder 354. In one or more examples, data width converter 352 is located in a transmit data path 380, and the FEC encoder is located parallel to the transmit data path 380 (e.g., in a parallel path 382).

[0061] The data width converter 352 includes an input for receiving an input data stream 360 having an input bit width, a first output for generating a first output data stream 362 having a first output bit width, and a second output for generating a second output data stream 364 having a second output bit width. FEC encoder 354 includes an input for receiving the second output data stream 364 having the second output bit width. FEC encoder 354 includes an output 366 for generating parity bits based at least in part on a plurality of received symbols of the second output data stream 364 having the second output bit width. The parity bits are for insertion into the first output data stream 362 having the first output bit width.

[0062] Fig. 5A is a schematic block diagram of a receive physical layer (PHY) of a receiver 500A (referred to herein as "receiver section 500A"), which is known to the inventor of this disclosure. The receiver section 500A may be at least part of an Ethernet physical layer (Ethernet PHY) transceiver for receiving data or Ethernet frames. For example, the receiver section 500A may be compliant with IEEE 802.3ch, 2.5GT1 Automotive Ethernet PHY, and in particular, with the "IEEE Standard for Ethernet - Amendment 8: Physical Layer Specifications and Management Parameters for 2.5 Gb / s, 5 Gb / s, and 10 Gb / s Automotive Electrical Ethernet," IEEE 802.3ch-2020, June 2020, for incorporating the next generation of onboard vehicle networks.

[0063] The receiver section 500A includes (from right to left in the figure) a receiver MUX 504, a symbol decoder 506, a data width converter 510 ("gearbox 510"), an FEC decoder 512, a data width converter 514 ("gearbox 514"), a PCS decoder 516, a timestamp circuit 518, and a MAC I / F 520. Pulse amplitude modulated (PAM) (e.g., 4-level) (PAM-4) signals (per clock) are received from the receiver MUX 504 for processing (e.g., via the symbol decoder 506, which is a PAM symbol decoder). A training top module 508 is coupled to receive the signals from the receiver MUX 504 for scrambling / descrambling training. A PHY control 502 is input to the receiver MUX 504 for data or training path selection.

[0064] As in Fig. As shown in Figure 5A, many of the modules of receiver section 500A are positioned downstream of a receive data path 501 to process the incoming data stream from the transmission medium to a link layer for further processing. Specifically, FEC decoder 512 is integrated with or positioned downstream of receive data path 501. Note that FEC decoder 512 operates at an FEC symbol width. In one or more examples, the FEC symbol width is ten (10) bits.

[0065] In view of this, the receive data path 501 largely operates at integer multiples of the symbol width. However, the subsequently desired data width (e.g., sixty-five (65) bits) is not an integer multiple of the symbol width. Since the subsequently desired data width is not an integer multiple of the symbol width, one or more additional data width converters and read pause mechanisms may be employed. For example, the receive data path 501 may include (the additional) data width converter 514. The data width converter 514 may further generate a "pause seek" signal to the FEC decoder 512 at an output 532, if desired. For example, the data width converter 514 may generate a pause seek signal to pause the seek every 9 / 10 / 18 clock cycles, but is not limited to this.

[0066] In particular, data width converter 510 includes an input for receiving a data stream 550 having a first bit width and an output for generating a data stream 552 having a second bit width. FEC decoder 512 includes an input for receiving the data stream 552 having the second bit width and an output for generating a data stream 554 having the (same) second bit width or an alternative second bit width. Data width converter 514 includes an input for receiving the data stream 554 having the second bit width (or the alternative second bit width) and an output for generating a data stream 556 having a third bit width.

[0067] To support 2.5GT1, the FEC symbol width is ten (10) bits, the first bit width of data stream 550 is seventy-two (72) bits (e.g., @ 25.6 ns), the second bit width of data stream 552 is eighty (80) bits (e.g., @ 25.6 ns), the second bit width of data stream 554 is eighty (80) bits (e.g., @ 25.6 ns) (or the alternative second bit width of seventy (70) bits), and the third bit width of data stream 556 is sixty-five (65) bits (e.g., @ 25.6 ns).

[0068] In Fig. Figure 5B is a schematic block diagram of the FEC decoder 512 of Fig. 5A. The FEC decoder 512 of Fig. 5B includes a syndrome calculator 560, an error locator 562 (e.g., using an error locator polynomial (ELP) algorithm), a check search module 564, a synchronous first-in-first-out (FIFO) 566, and an error corrector 568 arranged as shown. An output of the syndrome calculator 560 is provided to an input of the error locator 562. In one or more examples, the error locator 562 runs for thirty-four (34) clock cycles (e.g., at 25.6 ns). Another output 570 from the syndrome calculator 560 is provided to the synchronous FIFO 566 for communication of the data stream. The check search module 564 generates correction values at an output 572 to the error corrector 568 for correcting symbols in the data stream. In one or more examples, the check-in search module 564 generates a fault location in one clock cycle. The check-in search module 564 is used to generate read enable signals with pauses to the synchronous FIFO 566.

[0069] With further reference to Fig. 5A, Ethernet packets can be timestamped by timestamping logic 518. Timestamping Ethernet packets enables time synchronization in the network for compliance with IEEE 1588 (e.g., but not limited to, PTP). Specifically, timestamping logic 518 receives Ethernet packets in data stream 556 (e.g., from PCS decoder 516) with a bit width of sixty-five (65) bits and timestams them.

[0070] Although timestamping is desirable, latency occurs in the communication of Ethernet packets due to the modules and the arrangement of the modules in the receiver section 500A. This latency is a variable latency that changes from one packet to the next. To comply with TSN standards and real-time Ethernet communication, it is desirable to reduce the overall latency of the packets in the PHY. For correct timestamping by the timestamping circuitry 518, a guaranteed fixed latency should be present in the PHY, or alternatively, predictor logic should be provided to calculate the amount of variable latency incurred per packet to correctly adjust the timing.

[0071] Accordingly, the receiver section 500A includes a latency predictor 522 with an output 534 operatively coupled to the timestamp logic 518 for timing adjustment. However, the latency predictor 522 includes complex predictor logic ("1588 predictor logic") to generate a predicted variable latency at an output 534 based on multiple sources of variable latency, as indicated in the figure.

[0072] The latency of the frame in the receive data path 501 can be determined by the depth of the synchronous FIFO 566 ( Fig. 5B). The FIFO depth is in turn determined by the time required by the FEC decoder 512 to correct the frame, which is determined by the ELP algorithm of the error locator 562 ( Fig. 5B). The ELP algorithm can be executed serially according to a number of clocks "P" (where, for example, P = number of FEC parity symbols). Due to the varying FIFO depth, it is difficult to predict the latency when the start of frame (SOF) is written to the synchronous FIFO 566. It is also difficult to track the SOF due to the different transmission conversions.

[0073] Furthermore, the area of the receive data path 501 is increased due to the flops used to align the path with the FEC symbol width. The width of the synchronous FIFO 566 should be aligned with the FEC symbol width, although most FIFO positions do not require such a large width. With the syndrome calculator 560 at the FEC symbol width, flops are used for data accumulation.

[0074] Fig. 6A is a schematic block diagram of a receiver physical layer (PHY) (referred to herein as receiver section 600A) according to one or more examples of the disclosure. In one or more examples, receiver section 600A may be at least part of an Ethernet physical layer (Ethernet PHY) transceiver for receiving data or Ethernet frames. In one specific, non-limiting example, receiver section 600A is compliant with the IEEE 802.3ch, 2.5GT1 Automotive Ethernet PHY, as described above.

[0075] The receiver section 600A includes (from right to left in the figure) a receiver MUX 604, a symbol decoder 606, a data width converter 610, a synchronous FIFO 614 (or FIFO, buffer, FIFO buffer, or synchronous FIFO buffer), a symbol error corrector 616, an FEC decoder 612, a PCS decoder 618, a timestamp circuit 620, and a MAC I / F 622. A training top module 608 is coupled to receive the incoming data stream from the receiver MUX 604 for training scrambling / descrambling. A PHY controller 602 is input to the receiver MUX 604 for data or training path selection.

[0076] As in Fig. As shown in Figure 6A, the data width converter 610 is located in the receive data path 601, and the FEC decoder 612 is parallel to the receive data path 601. For example, the FEC decoder 612 may be arranged in a parallel path 603 that runs parallel to at least a portion of the receive data path 601 and / or the synchronous FIFO 614. The FEC decoder 612 may operate at least substantially separately and independently of the receive data path 601. Due to this arrangement, the receive data path 601 provides a fixed latency for data transmission.

[0077] In one or more examples, receive data path 601 includes (e.g., only) a single data width converter (i.e., data width converter 610). Although "single" within receive data path 601, data width converter 610 may consist of two or more separate data width converter circuits to generate the two respective output data streams (first and second output data streams 652 and 654), or alternatively, use shared circuitry to generate the different streams.

[0078] In particular, the data width converter 610 includes an input for receiving an input data stream 650 having an input bit width, a first output for generating a first output data stream 652 having a first output bit width, and a second output for generating a second output data stream 654 having at least a second output bit width. In one or more examples, the input bit width, the first output bit width, and the at least second output bit width are different from one another.

[0079] In one or more examples, the synchronous FIFO 614 has an input to which the first output data stream 652 having the first bit width is written into the synchronous FIFO 614. The synchronous FIFO 614 has an output at which a first output data stream 656 having the first bit width is read from the synchronous FIFO 614. In one or more examples, the synchronous FIFO 614 serves as a pipeline stage in the receive data path 501. In one or more examples, the synchronous FIFO 614 may receive an "always active" read enable signal at an output 630 of the symbol error corrector 616.

[0080] In one or more examples, the symbol error corrector 616 includes a first input operatively coupled to the output of the synchronous FIFO 614 and a second input operatively coupled to an error correction output 655 of the FEC decoder 612. The symbol error corrector 616 includes an output for generating an error-corrected data stream 658 from the first output data stream 656 having the first bit width from the synchronous FIFO 614. The error-corrected data stream 658 is generated based at least in part on the one or more error correction values from the error correction output 655 that correct the one or more symbols, the one or more subsymbols, or both from the first output data stream 656.

[0081] The FEC decoder 612 includes an input for receiving the second output data stream 654 having at least the second output bit width. The FEC decoder 612 includes an error correction output 655 for generating one or more error correction values based at least in part on one or more FEC codewords in the second output data stream 654. The one or more error correction values are for correcting one or more symbols, one or more subsymbols, or both in the first output data stream 656 having the first bit width from the synchronous FIFO 614.

[0082] Specifically, in one or more examples, the error correction output of the FEC decoder 612 generates one or more error correction values for respective ones of the one or more FEC codewords in the second output data stream 654 to correct respective ones of the one or more symbols, the one or more subsymbols, or both in the first output data stream 652 having the first bit width.

[0083] In one or more examples, the receiver section 600A of the PHY transceiver is configured according to IEEE 802.3ch 2.5GT1. For 2.5GT1 compliance, the symbol width is ten (10) bits, the input bit width of the input data stream 650 is seventy-two (72) bits (e.g., @ 25.6 ns), the first output bit width of the first output data stream 652 (e.g., to the synchronous FIFO 614) is sixty-five (65) bits (e.g., @ 25.6 ns), and the second output bit width of the second output data stream 654 (e.g., to the FEC decoder 612) is seventy (70) or eighty (80) bits (e.g., @ 25.6 ns). Each IEEE 802.3ch FEC frame runs for fifty (50) clock cycles.

[0084] In one or more examples, the FEC decoder 612 is operable on k symbols (e.g., received over multiple clock cycles) in the second output data stream 654 having at least the second bit width. The respective k symbols have a symbol width of s bits. In one or more examples, the at least second output bit width is an integer multiple of the symbol width of s bits (e.g., ten (10) bits).

[0085] In one or more examples, FEC decoder 612 is an RS-FEC decoder. In one or more examples, FEC decoder 612 decodes based on an RS code of RS(360,326). In one or more examples, an RS code may be represented by RS(n, k), where n = the total number of symbols in the FEC codeword, k = the number of data symbols for data, and (nk) = the number of parity symbols for parity.

[0086] In one or more other examples, the receiver portion 600A is configured according to one or more different standards, bit rates, bit widths, speeds, and / or codes.

[0087] In one or more examples, symbol decoder 606 includes an output operatively coupled to the input of data width converter 610. The output of symbol decoder 606 generates the first input data stream 650 having the first bit width to data width converter 610. In one or more examples, PCS decoder 618 includes an input for receiving the error-corrected data stream having the first output bit width.

[0088] In Fig. 6B is a block diagram of a circuit portion 600B in the receive data path 601 of Fig. 6A, wherein circuit portion 600B includes a synchronous FIFO 614 and a symbol error corrector 616.

[0089] In Fig. 6C is a block diagram 600C of the FEC decoder 612 of Fig. 6A in a parallel path 603, the FEC decoder 612 includes a syndrome calculator 662, an error locator 664 (e.g., using an ELP algorithm), a check search module 666, and an error magnitude generator 668 arranged as shown.

[0090] The minimum second output bit width of the second output data stream 654 ( Fig. 6A and Fig. 6C) can be an integer multiple of the symbol width for FEC decoding. On the other hand, the first output bit width of the first output data stream 652 ( Fig. 6A and Fig. 6B) may not be an integer multiple of the symbol width.

[0091] In one or more examples of the disclosure, the symbol error corrector 616 ( Fig. 6A and Fig. 6B) is configured as a partial symbol error corrector, and the error magnitude generator 668 ( Fig. 6B and Fig. 6C) is configured as a variable length error size generator (not just a fixed symbol width error size generator).

[0092] With reference to Fig. 6B, the symbol error corrector 616 may receive one or more error correction values at the error correction output 655 for correcting one or more symbols, one or more subsymbols, or both in the first output data stream 656 from the synchronous FIFO 614. The output of the symbol error corrector 616 generates an error-corrected data stream 658 from the first output data stream 656 based at least in part on one or more error correction values.

[0093] Because the symbol error corrector 616 can correct both full symbols and partial symbols, the symbol error corrector 616 may also be referred to as a partial symbol error corrector. In one or more examples, the symbol width of a full symbol is ten (10) bits. In one or more examples, the partial symbol width of a partial symbol is five (5) bits. In one or more examples, the symbol error corrector 616 corrects both full symbols of ten (10) bits and partial symbols of five (5) bits, as needed.

[0094] In one or more examples, an error magnitude generator 668 of the FEC decoder in parallel path 603 generates a variable-length error magnitude for error correction at the symbol error corrector 616. In one or more examples, the error magnitude generator 668 selectively outputs error correction values depending on whether full or partial symbol correction is desired or required. In particular, the error magnitude generator 668 may selectively output a selected number of one or more error correction values (e.g., one or more error magnitude values) at the error correction output 655 for correcting the respective full or partial symbol.

[0095] In one or more examples, the symbol error corrector 616 includes an XOR circuit 660 for XORing the full / partial symbols in the first output data stream 656 with the error correction values.

[0096] The symbol error corrector 616 may also generate the always-active read enable signal at output 630 to the synchronous FIFO 614. In one or more examples, the always-active read enable signal may enable regular or continuous operation of the synchronous FIFO 614 during decoding. For example, compare the synchronous FIFO 566 of Fig. 5B, which receives read enable signals with pauses from the check search module 564.

[0097] Accordingly, the synchronous FIFO 614 can be Fig. 6A-6B serve as a pipeline stage in the receive data path 601.

[0098] In relation to Fig. 6C, in one or more examples, the error size generator 668 may regularly or periodically pause the FEC decoding logic (e.g., the check search module 666) as desired or necessary. Because the error size generator 668 is located in the parallel path 603, the pause would not introduce variable latency.

[0099] In continuation with Fig. 6C, the syndrome calculator 662 has an input for receiving a second output data stream 654 having at least a second output bit width and an output for generating one or more syndromes based at least in part on the one or more FEC codewords in the second output data stream 654. The error locator 664 is operatively coupled to the output of the syndrome calculator 662 and is provided at an input of the error locator 662. In one or more examples, the check search module 666 provides error position values to the error magnitude generator 668. In one or more examples, the syndrome calculator 660 may operate for fifty (50) clock cycles to generate a syndrome; the error locator 664 may run for seventeen (17) clock cycles (e.g., at 25.6 ns); and the check search module 666 provides seven (7) error position values in one (1) clock cycle.

[0100] In one or more examples, the syndrome calculator 662 is operable on k symbols of the second output data stream 654 having at least the second bit width. Each of the k symbols comprises a symbol width of s bits (e.g., ten (10) bits). In one or more examples, the at least second output bit width is an integer multiple of the symbol width.

[0101] In one or more examples, the syndrome calculator 662 may be, or be referred to as, a variable symbol syndrome calculator. In one or more examples, the second output data stream 654 having at least the second output bit width has a second output bit width in one or more first data transmissions and a third output bit width in one or more second data transmissions. In one or more examples, the syndrome calculator 662 is operable on a variable number of received symbols, including the second output bit width, where k = 7, and the third output bit width, where k = 8. In one or more examples comparing the current approach to the traditional approach where the syndrome calculator runs on a fixed eight (8) symbols, the buffer savings is between three hundred sixty (360) bits and eight (8) bits.A specific, non-limiting example of such a syndrome calculator is discussed later in relation to . Fig. 10 shown and described.

[0102] As previously described, the error locator 664 may operate according to an ELP algorithm. In one or more examples, the ELP algorithm is provided to perform control channel adjustments according to rIBM (Reformulated Inversion-less Berlekamp Massey algorithm). It should be noted that the ELP algorithm is a relatively independent process because it does not depend on the incoming receive data rate. Additionally, the ELP algorithm is not a time-critical function, but simply needs to be executed serially for P clocks to obtain the polynomial (P = number of parity symbols). To begin processing, the ELP algorithm merely needs to obtain a P-symbol syndrome. In one or more examples for 2.5GT1, P = thirty-four (34) symbols. A specific, non-limiting example of an ELP algorithm of the error locator 664 will be described later with respect to Fig. 11 shown and described.

[0103] According to one or more examples, the ELP algorithm of the error locator 664 is executed at a relatively higher clock frequency than that of the receive data path. Here, with respect to Fig. 6A, the data width converter 610 is located in the receive data path 601, and at least most of the receive data path 601 responds to a first clock signal 636 (CLK DATENPFAD ) with a first clock frequency. As in Fig. 6C, the error locator 664, which uses the ELP algorithm, may respond to a second clock signal 638 (CLK ELP ) at a second clock frequency. In one or more examples, the second clock frequency of the second clock signal 638 (CLK EL P) is greater than the first clock frequency of the first clock signal 636 (CLK DATENPFAD ).

[0104] In one or more examples, the ELP algorithm may run at a clock that is two (2) times the speed of the receive data path. In one or more examples (e.g., for 2.5GT1), the receive data path may operate at a clock of 25.6 ns, while the ELP algorithm may run at a clock of 12.8 ns (e.g., at two (2) times the speed of the receive data path). Here, the dwell time of each FEC frame is reduced from eighty-four (84) clocks to sixty-seven (67) clocks. In one or more other examples, a different ratio or percentage between the clocks (i.e., CLK ELP and CLK DATENPFAD ) used.

[0105] In one or more examples, latency predictor 624 is operatively coupled to data width converter 610, and timestamp circuitry 620 is operatively coupled to latency predictor 624. In one or more examples, latency predictor 624 selects a latency value in response to a clock count value provided at an output 632 of data width converter 610. In one or more examples, latency predictor 624 includes a lookup table (LUT) with latency values each associated with clock count values. Timestamp circuitry 620 is located in receive data path 601 to timestamp the error-corrected data stream. The timestamp circuit 620 receives a latency value at an output 634 of the latency predictor 624 and adjusts a timing of the timestamp circuit 620 based at least in part on the latency value.In one or more examples, the SOF can be predicted relatively easily using a lookup table.

[0106] In one or more examples related to latency savings, the frame's dwell time in the receive data path can be reduced from eighty-four (84) clock cycles to sixty-seven (67) clock cycles. This can reduce latency to 435.2 ns per FEC frame. By operating a clock at a speed two (2) times the receive data path speed, seventeen (17) clock cycles can be saved.

[0107] In one or more examples related to area savings, the FIFO size in the FEC decoder in the traditional approach can be 81 x 45 = 3645; whereas the FIFO size in the present approach can be 65 x 50 = 3250. The introduction of the syndrome calculator also allows the buffers used in the transmissions to be reduced in size (e.g., from 360 bits to 8 bits).

[0108] With further reference to Fig. 6A, the receiver section 600A may include an Operations, Management, and Maintenance (OAM) module 640. Generally, OAM data may be inserted into the data stream regularly or periodically, which may be referred to as in-band data exchange. In 2.5GT1, an OAM symbol of ten (10) bits is inserted at a fixed position in each FEC frame (e.g., at the 326th symbol). Here, the received OAM data may be analyzed to monitor link operation, such as PHY link health or other factors.

[0109] In one or more examples, the OAM module 640 may be coupled to the symbol error corrector 616 and / or the output of the FEC decoder 612. In one or more examples, OAM data via the parallel path 603 is processed separately from the processing in the receive data path 601. For example, the data width converter 610 may establish an OAM channel in the parallel path 603 so that the OAM data is routed via the parallel path 603 and not through the synchronous FIFO 614 of the receive data path 601. The one or more correction values of the error magnitude generator 668 may be applied directly to the last symbol to correct the OAM data.

[0110] Fig. 7A is a flowchart illustrating a process 700 for processing receive data in a receive data path including parallel FEC decoding, according to one or more examples.

[0111] In one or more examples, process 700 may include converting an input data stream having an input bit width into a first output data stream having a first output bit width and into a second output data stream having at least a second output bit width in an operation 702. In one or more examples, the input bit width, the first output bit width, and the at least second output bit width are different from one another. In one or more examples, operation 702 may include multiple conversion acts.

[0112] In one or more examples, process 700 may include performing an FEC decoding process on one or more FEC codewords of the second output data stream having the at least second output bit width to generate one or more error correction values in an operation 704.

[0113] In one or more examples, process 700 may include correcting one or more symbols, one or more subsymbols, or both in the first output data stream having the first output bit width based at least in part on the one or more error correction values in an operation 706.

[0114] In one or more examples, converting (e.g., in operation 702) the input data stream having the input bit width to the first output data stream having the first output bit width is processed in a receive data path, and performing (e.g., in operation 704) the FEC decoding process includes performing at least a portion of the FEC decoding process in parallel with the receive data path. In one or more examples, the receive data path provides a fixed latency in communicating the first output data stream.

[0115] In one or more examples, the first output data stream having the first bit width is written to a synchronous FIFO in the receive data path, and the first output data stream having the first bit width is read from the synchronous FIFO.

[0116] In one or more examples, performing (e.g., in operation 704) the at least a portion of the FEC decoding process comprises performing it on k symbols in the second output data stream having the at least second bit width, wherein each of the k symbols comprises a symbol width of ten (10) bits. In one or more examples, correcting (e.g., in operation 706) the one or more symbols, the one or more subsymbols, or both comprises correcting the one or more subsymbols. In one or more examples, correcting the one or more subsymbols includes correcting the one or more subsymbols having a subsymbol width of five (5) bits.

[0117] In one or more examples, performing (e.g., in operation 704) at least a portion of the FEC decoding process comprises generating one or more error magnitude values comprising the one or more error correction values. In one or more examples, generating the one or more error magnitude values comprises selectively providing a selected number of the one or more error magnitude values comprising the one or more error correction values.

[0118] In one or more examples, performing (e.g., in operation 704) the at least a portion of the FEC decoding process includes calculating one or more syndromes based at least in part on the one or more FEC codewords in the second output data stream having the at least second bit width. In one or more examples, the respective k symbols in the second output data stream comprise a symbol width of ten (10) bits. In one or more examples, the process 300 may include calculating the one or more syndromes with respect to k symbols of the second output data stream, where k=7, and calculating the one or more syndromes with respect to k symbols of the second output data stream, where k=8.

[0119] In one or more examples, process 700 may include signaling a latency predictor with a clock count value, wherein the latency predictor comprises a lookup table of latency values each associated with clock count values. In one or more examples, process 300 may include adjusting a timing of a timestamping process for timestamping based at least in part on a latency value received from the latency predictor, wherein the latency value is responsive to the clock count value.

[0120] Fig. 7B is an apparatus 750 for processing receive data in a receive data path including parallel FEC decoding, according to one or more examples. In one or more examples, apparatus 750 includes a data width converter 752 and an FEC decoder 754. In one or more examples, data width converter 752 is located in a receive data path 780, and at least a portion of FEC decoder 754 is parallel to receive data path 780 (e.g., in a parallel path 782).

[0121] The data width converter 752 includes an input for receiving an input data stream 760 having an input bit width, a first output for generating a first output data stream 762 having a first output bit width, and a second output for generating a second output data stream 764 having at least a second output bit width. The FEC decoder 754 includes an input for receiving the second output data stream 764 having the at least second output bit width. The FEC decoder 754 includes an error correction output 766 for generating one or more error correction values based at least in part on one or more FEC codewords in the second output data stream 764. The one or more error correction values are for correcting one or more symbols, one or more subsymbols, or both in the first output data stream 762 having the first output bit width.

[0122] With reference to the specific, non-limiting example of Fig. 8, a table 800 is displayed with the numbers of transferred data bits per clock cycle, which corresponds to the operation of the data width converter 610 of Fig. 6A are assigned. In Fig. 8, the clock count indicates a current, relative clock count that refers to a repeating cycle of clock counts, for example, a repeating cycle of 1 to 50 clock counts or another clock count range. The number of data bits transferred per clock cycle includes the number of data bits transferred from the data width converter to the synchronous FIFO (“converter-to-FIFO”) and the number of data bits transferred from the data width converter to the FEC decoder / syndrome calculator (“converter-to-syndrome calculator”). The “Converter-to-FIFO” column in Table 800 is assigned to the first output data stream 652 with the first output bit width ( Fig. 6A) (e.g., sixty-five (65) bits); and the "Converter-to-Syndrome Calculator" column in table 800 is assigned to the second output data stream 654, which has the second output bit width ( Fig. 6A) (e.g., seventy (70) bits or seven (7) symbols; or eighty (80) bits or eight (8) symbols).

[0123] As in the example of Fig. 8, the FEC decoder's syndrome calculator receives seven (7) symbols with a symbol width of ten (10) bits per clock cycle, for a total of seventy (70) bits per clock cycle. This occurs for one of every four (4) consecutive clock cycles. The syndrome calculator then receives eight (8) symbols with a symbol width of ten (10) bits for the next (single) clock cycle, for a total of eighty (80) bits for the clock cycle. This process is then repeated, with the syndrome calculator again receiving seventy (70) bits per clock cycle for four (4) consecutive clock cycles and then eighty (80) bits for the next clock cycle, and so on. The syndrome calculator can output one or more syndromes when a complete FEC codeword is received and processed.

[0124] Fig. 9 is a lookup table (LUT) 900 for a latency predictor associated with a receiver portion of a receive PHY, according to one or more examples. LUT 900 is a lookup table with latency values each associated with clock count values. In one or more examples, the latency values in LUT 900 are fixed or predetermined latency values that depend on the clock count. The clock count to be input is a current, relative clock count related to a repeating cycle of clock counts, for example, a repeating cycle of 1 to 50 clock counts or another clock count range.

[0125] The data width converter (or other component or mechanism) signals a (current, relative) clock count to the latency predictor using LUT 900. In response, LUT 900 outputs a selected latency value corresponding to the clock count. A timestamping circuit receives the selected latency value from LUT 900 and adjusts its timing based, at least in part, on the selected latency value.

[0126] It should be noted that a LUT for a transmitter section of a transmit PHY can be essentially the same as the LUT 900 in Fig. 9, according to one or more examples. In one or more examples, the latency predictor used in the transmit / receive PHY may be a pure lookup table (without additional circuitry or substantially additional circuitry).

[0127] One or more examples generally relate to determining variable latency and reducing complexity compared to the traditional approaches described above. In one or more examples, there is a fixed delay introduced by the modules in the transmit data path (e.g., by modules other than the data width converter). The variable latency introduced by the data width converter can therefore be reduced to a simple LUT, allowing the latency to be determined or selected based at least in part on a current, running clock count in the data width converter.

[0128] To better illustrate, a data width converter may maintain an internal clock count from 1 to 50 (e.g., each IEEE 802.3ch FEC frame runs for fifty (50) clocks). Furthermore, a pipeline depth may exist between the data width converter and the PCS decoder, for example, sixty-nine (69) clocks. When an SOF is received in the PCS decoder, the data width converter's internal clock count may indicate the nth clock. Within the data width converter, the clock count is (c = n - 69) clocks when it has output the SOF. Based on this relationship (c = n - 69), one can determine the variable delay introduced by the data width converter, which is sixty-nine (69) clocks ahead of the current clock count. Accordingly, a predictor LUT that outputs a variable latency value can be based on the relationship (c = n - 69).

[0129] Fig. 10 is a syndrome calculator 1000 for an FEC decoder of a receive PHY according to one or more examples. In one or more examples, the syndrome calculator 1000 may be Fig. 10 as syndrome calculator 662 of the in Fig. 6C specified FEC decoder 612 may be used.

[0130] In one or more examples, the syndrome calculator 1000 may be, or be referred to as, a variable symbol syndrome calculator. In the example shown, the syndrome calculator 1000 may include a plurality of input selectors 1004 having a plurality of inputs 1006 (alpha exponents), a plurality of multipliers 1008 for performing multiplications with respect to the selected inputs, an adder 1010, and a shift register array (DFF) 1012 arranged as shown. The syndrome calculator 1000 may generate a syndrome at an output 1014. As indicated in the figure, the syndrome calculator 1000 uses alpha exponents to calculate the syndrome, and these alpha exponents are manipulated (e.g., per clock cycle). A selector input 1002 is used (e.g. an incoming bit) to select between the number of symbols to be processed (e.g.the syndrome calculator 1000 manipulates the alpha exponents at least partially based on the incoming bit or selection).

[0131] Fig. 11 is an example of an error locator polynomial (ELP) algorithm 1100 of an error locator for an FEC decoder of a receive PHY, according to one or more examples. In one or more examples, such an ELP algorithm may be implemented in the error locator 664 of the FEC decoder 612 of Fig. 6C can be used. The Fig. The ELP algorithm 1100 shown in Figure 11 is one of many different standard algorithms and / or approaches (conventional or not) that can be used in an FEC decoder. As shown in Fig. 11, the ELP algorithm 1100 may include an input function 1102 associated with a syndrome polynomial 1104 and output functions 1106 associated with an error localization polynomial 1108 and an error magnitude polynomial 1110, respectively. Although in Fig. 11 specific parameters are displayed, these parameters are not to be understood as limiting and depend on the specific application and / or operating conditions.

[0132] In one or more examples, the ELP algorithm 1100 may be operated at a higher clock rate (e.g., a clock rate corresponding to the clock signal CLK ELP assigned clock rate) than the clock rate of the receive data path (e.g. a clock signal CLK DATENPFAD assigned clock rate). For example, the receive data path can be set to a first clock signal (e.g., the clock signal CLK DATENPFAD) with a first clock frequency, while the error locator with the ELP algorithm 1100 responds to a second clock signal (e.g. the clock signal CLK ELP ) can respond with a second clock frequency, wherein the second clock frequency is greater than the first clock frequency.

[0133] Fig. 12 is a timing diagram 1200 for the communication processing associated with the receive data path and having an integrated FEC decoding approach (see, e.g., Fig. 5A and Fig. 5B). The timing diagram 1200 shows different fill levels as a result of the required pause. The different fill levels result in complex predictor logic being used to predict latency.

[0134] Fig. 13 is a timing diagram 1300 for the communication processing associated with the receive data path with the parallel FEC decoding approach (see, e.g., Fig. 6A-6C). Compare Fig. 13 with the above Fig. 12. The timing diagram 1300 shows fixed FIFO fill levels that occur when no pause occurs.

[0135] Fig. 14A and Fig. 14B are timing diagram portions 1400A and 1400B of a timing diagram of the communication processing associated with using a first clock rate for the receive data path and a second clock rate (i.e., a higher clock rate) for the ELP algorithm (see, e.g., Fig. 6A-6C and 11). As described above, the ELP algorithm can run at a clock frequency that is twice (2) the speed (@12.8 ns) of the receive data path (@25.6 ns). From the time the syndrome is available to the time the ELP is provided, 486.4 ns elapses (486.4 / 25.6 ns = only 19 clock cycles). The FIFO fullness and the write / read enablements are fixed. From the above figure ( Fig. 13) shows that the maximum FIFO fill level was 66 (@81 bits). Fig. 14A and Fig. 14B the maximum FIFO fill level is 69 (@65 bits).

[0136] Fig. 15A and Fig. 15B are timing diagram sections 1500A and 1500B of a timing diagram for communication processing associated with variable symbol syndrome calculation (see, for example, Fig. 6A-6C and 10). The two (2) cursors indicate the boundaries of an FEC frame. "rx_data_x_i" marks the incoming data for the syndrome calculator. "Bit-80" indicates whether the valid input data is eighty (80) bits or seventy (70) bits. The syndrome calculator manipulates the alpha exponents based on this incoming bit, "Bit-80."

[0137] Fig. 16 is a block diagram of circuitry 1600 that, in some examples, may be used to implement various functions, operations, acts, processes, and / or methods disclosed herein. Circuitry 1600 includes one or more processors 1604 (sometimes referred to herein as "processors 1604") operatively coupled to one or more data storage devices (sometimes referred to herein as "storage 1606"). Memory 1606 includes machine-executable code 1608 stored thereon, and processors 1604 include logic circuitry 1610. Machine-executable code 1608 includes information describing functional elements that may be implemented (e.g., performed) by logic circuitry 1610. The logic circuit 1610 is adapted to implement (e.g., perform) the functional elements described by the machine-executable code 1608.Circuitry 1600, when executing the functional elements described by machine-executable code 1608, should be considered special-purpose hardware for executing functional elements disclosed herein. In some examples, processors 1604 may perform the functional elements described by machine-executable code 1608 sequentially, concurrently (e.g., on one or more different hardware platforms), or in one or more parallel process streams.

[0138] When implemented by the logic circuitry 1610 of the processors 1604, the machine-executable code 1608 adapts the processors 1604 to perform operations of examples disclosed herein. For example, the machine-executable code 1608 may be used to adapt the processors 1604 to perform at least a portion or all of the method of Fig. 3A and / or the procedure of Fig. 7A. As another example, machine-executable code 1608 may be used to adapt processors 1604 to execute at least a portion or all of the functions associated with transmitter portion 200 of Fig. 2 and the establishment of 350 Fig. 3B and / or the receiver section 600A of Fig. 6A and the facility 750 of Fig. Carry out the operations described in 7B.

[0139] Processors 1604 may include a general-purpose processor, a special-purpose processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, another programmable device, or any combination thereof configured to perform the functions disclosed herein. A general-purpose computer, including a processor, is considered a special-purpose computer, while the general-purpose computer executes functional elements corresponding to machine-executable code 1608 (e.g., software code, firmware code, hardware descriptions) related to examples of the present disclosure.It should be noted that a general-purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but processors 1604 may alternatively include any conventional processor, controller, microcontroller, or state machine. Processors 1604 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0140] In some examples, storage 1606 includes volatile data storage (e.g., random access memory (RAM)), non-volatile storage (e.g., flash memory, a hard disk drive, a solid-state drive, an erasable programmable read-only memory (EPROM), etc.). In some examples, processors 1604 and memory 1606 may be implemented in a single device (e.g., a semiconductor device product, a system-on-chip (SOC), etc.). In some examples, processors 1604 and memory 1606 may be implemented in separate devices.

[0141] In some examples, machine-executable code 1608 may include computer-readable instructions (e.g., software code, firmware code). As a non-limiting example, the computer-readable instructions may be stored by memory 1606, which may be directly accessible by processors 1604, and executed by processors 1604 using at least logic circuitry 1610. Also as a non-limiting example, the computer-readable instructions may be stored on memory 1606, transferred to a storage device (not shown) for execution, and executed by processors 1604 using at least logic circuitry 1610. Accordingly, in some examples, logic circuitry 1610 includes electrically configurable logic circuitry 1610.

[0142] In some examples, machine-executable code 1608 may describe hardware (e.g., circuit logic) to be implemented in logic circuitry 1610 to perform the functional elements. This hardware may be described at a variety of abstraction levels, from low-level transistor layouts to high-level description languages. At a high abstraction level, a hardware description language (HDL), such as an IEEE standard hardware description language (HDL), may be used. As non-limiting examples, VERILOG™, SYSTEMVERILOG™, or very large scale integration (VLSI) hardware description language (VHDL™) may be used.

[0143] HDL descriptions can be freely converted into descriptions at any of numerous other abstraction levels. As a non-limiting example, a high-level description can be converted into a logic-level description, such as a register transfer language (RTL), a gate-level description (GL), a layout-level description, or a mask-level description. As a non-limiting example, micro-operations performed by hardware logic circuits (e.g.,The operations to be performed (e.g., gates, flip-flops, registers, without limitation) of logic circuit 1610 may be described in an RTL and then converted into a GL description by a synthesis tool, and the GL description may be converted into a layout-level description by a placement and routing tool, corresponding to a physical layout of an integrated circuit, a programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. Accordingly, in some examples, machine-executable code 1608 may include an HDL, an RTL, a GL description, a mask-level description, another hardware description, or any combination thereof.

[0144] In examples where machine-executable code 1608 includes a hardware description (at any level of abstraction), a system (not shown, but including memory 1606) may implement the hardware description described by machine-executable code 1608. As a non-limiting example, processors 1604 may include a programmable logic device (e.g., an FPGA or PLC), and logic circuitry 1610 may be electrically controlled to implement circuitry corresponding to the hardware description in logic circuitry 1610. Also as a non-limiting example, logic circuitry 1610 may include hard-wired logic manufactured by a manufacturing system (not shown, but including memory 1606) according to the hardware description of machine-executable code 1608.

[0145] Regardless of whether the machine-executable code 1608 includes computer-readable instructions or a hardware description, the logic circuit 1610 is adapted to perform the functional elements described by the machine-executable code 1608 when implementing the functional elements of the machine-executable code 1608. It should be noted that although a hardware description may not directly describe functional elements, a hardware description indirectly describes functional elements that the hardware elements described by the hardware description can perform.

[0146] As used in this disclosure, the terms "module" or "component" may refer to specific hardware implementations for performing the actions of the module or component and / or software objects or software routines that may be stored on and / or executed by general-purpose hardware (e.g., computer-readable media, processing devices, etc.) of the computing system. In some examples, the various components, modules, engines, and services described in this disclosure may be implemented as objects or processes that execute on the computing system (e.g., as separate threads).Although some of the systems and methods described in the present disclosure are generally described as being implemented in software (stored on and / or executed by general purpose hardware), specific hardware implementations or a combination of software and specific hardware implementations are also possible and are contemplated.

[0147] As used in the present disclosure, the term "combination" with reference to a plurality of elements may include a combination of all of the elements or any of various different subcombinations of some of the elements. For example, the phrase "A, B, C, D, or combinations thereof" may refer to one of A, B, C, or D; the combination of each of A, B, C, and D; and any subcombination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0148] Terms used in the present disclosure, and in particular in the appended claims (e.g., contents of the appended claims), are generally intended to be "open" terms (e.g., the term "including" should be interpreted as "including, but not limited to," the term "comprising" should be interpreted as "at least comprising," the term "includes" should be interpreted as "includes, but not limited to," etc.).

[0149] Furthermore, where a specific number of an introduced claim statement is intended, that intention will be expressly stated in the claim, and in the absence of such reciting, no such intention exists. As an aid to understanding, for example, the following accompanying claims may include the use of the introductory phrases "at least one" and "one or more" to introduce claim statements. However, the use of such phrases should not be construed to imply that introducing a claim statement by the indefinite articles "a" or "an" limits a specified claim containing such an introduced claim statement to examples containing only one such statement, even if the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" and / or "an" (e.g.,"a" and / or "an" shall be interpreted to mean "at least one" or "one or more"; the same applies to the use of certain articles used to introduce claim particulars.

[0150] Furthermore, even if a particular number of introduced claim details is explicitly recited, those skilled in the art will recognize that such a recited number should be interpreted to mean at least the recited number (e.g., simply stating “two details” without other modifiers means at least two details or two or more details). Furthermore, where a convention analogous to “at least one of A, B, and C, etc.” or “one or more of A, B, and C, etc.” is used, such a construction is generally intended to include A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together, etc. Any disjunctive word or phrase whichthat presents two or more alternative terms, whether in the description, the claims, or the drawings, should be understood to contemplate the possibility of including either of the terms, one or the other, or both. For example, the phrase "A or B" should be understood to include the possibilities "A" or "B" or "A and B." Additional non-limiting examples of the disclosure include: Example 1: A device comprising: a data width converter, the data width converter including an input for receiving an input data stream having an input bit width, a first output for generating a first output data stream having a first output bit width, and a second output for generating a second output data stream having at least a second output bit width;and a forward error correction (FEC) decoder, the FEC decoder including an input for receiving the second output data stream having the at least second output bit width, the FEC decoder including an error correction output for generating one or more error correction values based at least in part on one or more FEC codewords in the second output data stream, the one or more error correction values for correcting one or more symbols, one or more subsymbols, or both in the first output data stream having the first output bit width.; Example 2: Device according to example 1, wherein: the data width converter is located in a receive data path and at least a portion of the FEC decoder is parallel to the receive data path. Example 3: The device according to examples 1 and 2, wherein the path for the received data provides a fixed latency in the communication of the first output data stream. Example 4: Device according to one of examples 1 to 3, wherein the input bit width, the first output bit width and the at least second output bit width differ from one another. Example 5: Device according to one of examples 1 to 4, comprising: a synchronous first-in-first-out (FIFO), wherein the synchronous FIFO has an input at which the first output data stream with the first bit width is written into the synchronous FIFO, wherein the synchronous FIFO has an output at which the first output data stream with the first bit width is read out of the synchronous FIFO. Example 6: The device of any one of examples 1 to 5, wherein the FEC decoder comprises: a symbol error corrector, the symbol error corrector having a first input operatively coupled to the output of the synchronous FIFO, a second input operatively coupled to the error correction output of the FEC decoder, and an output to generate an error-corrected data stream from the first output data stream having the first bit width based at least in part on the one or more error correction values that correct the one or more symbols, the one or more subsymbols, or both. Example 7: The device of any one of Examples 1 to 6, wherein the FEC decoder is operable on k symbols in the second output data stream having the at least second output bit width, wherein respective ones of the k symbols comprise a symbol width of s bits and the symbol width is ten (10) bits, and wherein: the output of the symbol error corrector to generate the error-corrected data stream is based at least in part on the one or more error correction values that correct the one or more subsymbols having a subsymbol width of five (5) bits. Example 8: The device of any one of examples 1 to 7, wherein the FEC decoder comprises: an error magnitude generator, wherein the error magnitude generator is operable to selectively output at the error correction output a selected number of the one or more error correction values for correcting the one or more symbols, the one or more sub-symbols, or both, wherein the one or more correction values comprise one or more error magnitude values. Example 9: The device of any one of examples 1 to 8, wherein the FEC decoder comprises: a syndrome calculator, the syndrome calculator having an input for receiving the second output data stream having the at least second output bit width and an output for generating one or more syndromes based at least in part on the one or more FEC codewords in the second output data stream. Example 10: The device according to any one of examples 1 to 9, wherein the syndrome calculator is operable on k symbols of the second output data stream having the at least second bit width, wherein respective ones of the k symbols comprise a symbol width of ten (10) bits and the at least second output bit width is an integer multiple of the symbol width of s bits. Example 11: The device of any one of examples 1 to 10, wherein the second output data stream having the at least second output bit width has a second output bit width in one or more first data transmissions and a third output bit width in one or more second data transmissions, and wherein: the syndrome calculator is operable on a variable number of symbols, including the second output bit width, where k=7, and the third output bit width, where k=8. Example 12: The device of any one of examples 1 to 11, wherein the data width converter is located in a receive data path and the receive data path is responsive to a first clock signal having a first clock frequency, the device comprising: an error locator polynomial generator, the error locator polynomial generator being responsive to a second clock signal having a second clock frequency, the second clock frequency being greater than the first clock frequency. Example 13: The device of any one of examples 1 to 12, wherein: the symbol error corrector comprises a further output to generate an always-active read enable signal for the synchronous FIFO. Example 14: The device of any one of examples 1 to 13, comprising: a latency predictor, wherein the latency predictor is operatively coupled to the data width converter, wherein the latency predictor comprises a lookup table of latency values each associated with clock count values. Example 15: The device of any one of examples 1 to 14, comprising: a timestamp circuit to timestamp the error-corrected data stream, wherein the timestamp circuit receives a latency value from the latency predictor and adjusts a timing of the timestamp circuit based at least in part on the latency value. Example 16: The device according to any one of examples 1 to 15, wherein: the error correction output of the FEC decoder generates one or more error correction values for respective one or more FEC codewords in the second output data stream for correcting respective one or more symbols, the one or more subsymbols, or both in the first output data stream having the first bit width. Example 17: The device according to any one of examples 1 to 16, wherein: the FEC decoder is operable on k symbols in the second output data stream having at least the second bit width, respective ones of the k symbols comprise a symbol width of s bits, and the at least second output bit width is an integer multiple of the symbol width of s bits. Example 18: The device of any one of Examples 1 to 17, wherein: the symbol width is ten (10) bits and the width of the at least second output bit is seventy (70) bits or eighty (80) bits. Example 19: The device of any one of examples 1 to 18, wherein: the input bit width is seventy-two (72) bits and the first output bit width is sixty-five (65) bits. Example 20: A method comprising: converting an input data stream having an input bit width into a first output data stream having a first output bit width and into a second output data stream having at least a second output bit width; performing a forward error correction (FEC) decoding process on one or more FEC codewords of the second output data stream having the at least second output bit width to generate one or more error correction values; and correcting one or more symbols, one or more subsymbols, or both in the first output data stream having the first output bit width based at least in part on the one or more error correction values. Example 21: The method of Example 20, wherein: converting the input data stream having the input bit width into the first output data stream having the first output bit width is performed in a receive data path, and performing the FEC decoding process comprises performing at least a portion of the FEC decoding process in parallel with the receive data path. Example 22: The method of examples 20 and 21, wherein the receive data path provides a fixed latency in communicating the first output data stream. Example 23: The method of any one of examples 20 to 22, wherein the input bit width, the first output bit width, and the second output bit width are different from each other. Example 24: The method of any one of examples 20 to 23, comprising: writing the first output data stream having the first bit width to a synchronous first-in-first-out (FIFO); and reading the first output data stream having the first bit width from the synchronous FIFO. Example 25: The method of any one of examples 20 to 24, wherein correcting the one or more symbols, the one or more sub-symbols, or both comprises correcting the one or more sub-symbols. Example 26: The method of any one of Examples 20 to 25, wherein: performing at least a portion of the FEC decoding process comprises performing it on k symbols in the second output data stream having the at least second output bit width, wherein respective ones of the k symbols comprise a symbol width of ten (10) bits, and correcting the one or more subsymbols comprises correcting the one or more subsymbols having a subsymbol width of five (5) bits. Example 27: The method of any one of examples 20 to 26, wherein performing at least a portion of the FEC decoding process comprises: generating one or more error magnitude values comprising the one or more error correction values. Example 28: The method of any one of examples 20 to 27, wherein generating comprises: selectively providing a selected number of the one or more error magnitude values comprising the one or more error correction values. Example 29: The method of any one of examples 20 to 28, wherein performing at least a portion of the FEC decoding process comprises: calculating one or more syndromes based at least in part on the one or more FEC codewords in the second output data stream having the at least second bit width. Example 30: The method of any one of Examples 20 to 29, wherein respective ones of the k symbols in the second output data stream have a symbol width of ten (10) bits, the method comprising: calculating the one or more syndromes with respect to k symbols of the second output data stream, where k = 7, and calculating the one or more syndromes with respect to k symbols of the second output data stream, where k = 8. Example 31: The method of any one of examples 20 to 30, comprising: signaling a latency predictor with a clock count value, wherein the latency predictor comprises a lookup table with latency values each associated with clock count values. Example 32: The method of any one of examples 20 to 31, comprising: adjusting a timing of a timestamping process for timestamping based at least in part on a latency value received from the latency predictor, the latency value responsive to the clock count value.Example 33: A device comprising: a data width converter in a receive data path, the data width converter including an input for receiving an input data stream having an input bit width, a first output for generating a first output data stream having a first output bit width, and a second output for generating a second output data stream having at least a second output bit width; a synchronous first-in-first-out (FIFO) in the receive data path, the synchronous FIFO having an input at which the first output data stream having the first bit width is written into the synchronous FIFO, and the synchronous FIFO having an output at which the first output data stream having the first bit width is read from the synchronous FIFO; at least a portion of a forward error correction (FEC) decoder parallel to the receive data path,wherein the at least one portion of the FEC decoder comprises an input for receiving the second output data stream having the at least second output bit width, wherein the at least one portion of the FEC decoder comprises an error correction output for generating one or more error correction values based at least in part on one or more FEC codewords in the second output data stream having the at least second output bit width; and a symbol error corrector in the receive data path, the symbol error corrector having a first input operatively coupled to the output of the synchronous FIFO, a second input operatively coupled to the error correction output of the FEC decoder, and an output for generating an error-corrected data stream from the first output data stream having the first bit width based at least in part on the one or more error correction values comprising one or more symbols,correct one or more subsymbols, or both, in the first output data stream. Example 34: The apparatus of Example 33, wherein: the at least one portion of the FEC decoder is operable on k symbols in the second output data stream having the at least second bit width, and respective ones of the k symbols comprise a symbol width of ten (10) bits, and the output of the symbol error corrector generates the error-corrected data stream based at least in part on the one or more error correction values for correcting the one or more subsymbols having a subsymbol width of five (5) bits. Example 35: The apparatus of examples 33 and 34, wherein the at least one portion of the FEC decoder comprises: an error magnitude generator, the error magnitude generator selectively outputting at the error correction output a selected number of the one or more correction values for correcting the one or more symbols or the one or more sub-symbols, the one or more correction values comprising one or more error magnitude values. Example 36: The apparatus of any one of examples 33 to 35, wherein the at least one portion of the FEC decoder comprises: a syndrome calculator, the syndrome calculator having an input for receiving the second output data stream having the at least second output bit width and an output for generating one or more syndromes based at least in part on the one or more FEC codewords. Example 37: Device according to one of examples 33 to 36, wherein the syndrome calculator is operable on k symbols of the second output data stream having the at least second bit width, respective ones of the k symbols comprise a symbol width of s bits, and the at least second output bit width is an integer multiple of the symbol width. Example 38: The device according to any one of examples 33 to 37, wherein the syndrome calculator is operable on a variable number of symbols. Example 39: The apparatus of any one of Examples 33 to 38, wherein the second output data stream having the at least second output bit width has a second output bit width in one or more first data transmissions and a third output bit width in one or more second data transmissions, the symbol width is ten (10) bits, and wherein: the syndrome calculator is operable on the variable number of symbols, including on the second output bit width when k=7 and on the third output bit width when k=8.

[0151] Although the present disclosure has been described herein with reference to certain illustrated examples, those of ordinary skill in the art will recognize and understand that the present invention is not limited thereto. Rather, many additions, omissions, and modifications may be made to the illustrated and described examples without departing from the scope of the invention as claimed below, along with their legal equivalents. Furthermore, features of one example may be combined with features of another example and still be included within the scope of the invention contemplated by the inventor. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 378,690

[0001] Cited non-patent literature

[0000] IEEE Standard for Ethernet - Amendment 8: Physical Layer Specifications and Management Parameters for 2.5 Gb / s, 5 Gb / s, and 10 Gb / s Automotive Electrical Ethernet", IEEE 802.3ch-2020, June 2020 [0025, 0062]

Claims

[1] Facility comprising: a data width converter, the data width converter including an input for receiving an input data stream having an input bit width, a first output for generating a first output data stream having a first output bit width, and a second output for generating a second output data stream having at least a second output bit width; and a forward error correction (FEC) decoder, the FEC decoder including an input for receiving the second output data stream having the at least second output bit width, the FEC decoder including an error correction output for generating one or more error correction values based at least in part on one or more FEC codewords in the second output data stream, the one or more error correction values for correcting one or more symbols, one or more subsymbols, or both in the first output data stream having the first output bit width. [2] Device according to claim 1, wherein: the data width converter is located in a receive data path, and at least one section of the FEC decoder is parallel to the receive data path. [3] The device of claim 2, wherein the received data path provides a fixed latency in the communication of the first output data stream. [4] The device according to claim 1, wherein the input bit width, the first output bit width and the at least second output bit width are different from each other. [5] Device according to claim 1, comprising: a synchronous first-in-first-out (FIFO), wherein the synchronous FIFO has an input at which the first output data stream with the first bit width is written into the synchronous FIFO, and wherein the synchronous FIFO has an output at which the first output data stream with the first bit width is read out of the synchronous FIFO. [6] The device of claim 5, wherein the FEC decoder comprises: a symbol error corrector, the symbol error corrector having a first input operatively coupled to the output of the synchronous FIFO, a second input operatively coupled to the error correction output of the FEC decoder, and an output for generating an error-corrected data stream from the first output data stream having the first bit width based at least in part on the one or more error correction values that correct the one or more symbols, the one or more subsymbols, or both. [7] The apparatus of claim 6, wherein the FEC decoder is operable on k symbols in the second output data stream having the at least second output bit width, wherein respective ones of the k symbols comprise a symbol width of s bits and the symbol width is ten (10) bits, and wherein: the output of the symbol error corrector generates the error-corrected data stream based at least in part on the one or more error correction values that correct the one or more subsymbols having a subsymbol width of five (5) bits. [8] The device of claim 7, wherein the FEC decoder comprises: an error magnitude generator, the error magnitude generator being operable to selectively output at the error correction output a selected number of the one or more error correction values for correcting the one or more symbols, the one or more sub-symbols, or both, the one or more correction values comprising one or more error magnitude values. [9] The device of claim 1, wherein the FEC decoder comprises: a syndrome calculator, the syndrome calculator having an input for receiving the second output data stream having the at least second output bit width and an output for generating one or more syndromes based at least in part on the one or more FEC codewords in the second output data stream. [10] The apparatus of claim 9, wherein the syndrome calculator is operable on k symbols of the second output data stream having the at least second bit width, wherein respective ones of the k symbols comprise a symbol width of ten (10) bits and the at least second output bit width is an integer multiple of the symbol width of s bits. [11] The device of claim 10, wherein the second output data stream having the at least second output bit width has a second output bit width in one or more first data transmissions and a third output bit width in one or more second data transmissions, and wherein: the syndrome calculator is operable on a variable number of symbols, including the second output bit width, where k=7, and the third output bit width, where k=8. [12] The device of claim 9, wherein the data width converter is located in a receive data path and the receive data path is responsive to a first clock signal having a first clock frequency, the device comprising: an error locator polynomial generator, the error locator polynomial generator responsive to a second clock signal having a second clock frequency, the second clock frequency being greater than the first clock frequency. [13] Device according to claim 6, wherein: the symbol error corrector includes a further output to generate an always-active read enable signal for the synchronous FIFO. [14] Device according to claim 1, comprising: a latency predictor, wherein the latency predictor is operatively coupled to the data width converter, wherein the latency predictor comprises a lookup table of latency values each associated with clock count values. [15] Device according to claim 14, comprising: a timestamp circuit for timestamping the error-corrected data stream, wherein the timestamp circuit receives a latency value from the latency predictor and adjusts a timing of the timestamp circuit based at least in part on the latency value. [16] Device according to claim 1, wherein: the error correction output of the FEC decoder generates one or more error correction values for respective one or more FEC codewords in the second output data stream for correcting respective one or more symbols that generate one or more subsymbols or both in the first output data stream having the first bit width. [17] Device according to claim 1, wherein: the FEC decoder is operable on k symbols in the second output data stream having at least the second bit width, respective ones of the k symbols comprise a symbol width of s bits, and the at least second output bit width is an integer multiple of the symbol width of s bits. [18] Device according to claim 17, wherein: the symbol width is ten (10) bits, and the minimum second output bits are seventy (70) bits or eighty (80) bits. [19] Device according to claim 18, wherein: the input bit width is seventy-two (72) bits, and the first output bit width is sixty-five (65) bits. [20] Method comprising: Converting an input data stream having an input bit width into a first output data stream having a first output bit width and into a second output data stream having at least a second output bit width; Performing a forward error correction (FEC) decoding process on one or more FEC codewords of the second output data stream having at least the second output bit width, to generate one or more error correction values; and Correcting one or more symbols, one or more subsymbols, or both in the first output data stream having the first output bit width based at least in part on the one or more error correction values. [21] The method of claim 20, wherein: converting the input data stream with the input bit width into the first output data stream with the first output bit width is performed in a receive data path, and performing the FEC decoding process comprises performing at least a portion of the FEC decoding process in parallel with the receive data path. [22] The method of claim 21, wherein the receive data path provides a fixed latency in the communication of the first output data stream. [23] The method of claim 20, wherein the input bit width, the first output bit width and the second output bit width are different from each other. [24] A method according to claim 20, comprising: Writing the first output data stream with the first bit width into a synchronous first-in-first-out (FIFO); and Reading the first output data stream with the first bit width from the synchronous FIFO. [25] The method of claim 20, wherein correcting the one or more symbols, the one or more sub-symbols, or both comprises correcting the one or more sub-symbols. [26] The method of claim 25, wherein: performing the at least part of the FEC decoding process comprises performing it on k symbols in the second output data stream having the at least second output bit width, wherein respective ones of the k symbols have a symbol width of ten (10) bits, and correcting the one or more subsymbols comprises correcting the one or more subsymbols having a subsymbol width of five (5) bits. [27] The method of claim 20, wherein performing at least part of the FEC decoding process comprises: Generating one or more error magnitude values comprising the one or more error correction values. [28] The method of claim 27, wherein generating comprises: selectively providing a selected number of the one or more error magnitude values comprising the one or more error correction values. [29] The method of claim 20, wherein performing at least part of the FEC decoding process comprises: Calculating one or more syndromes based at least in part on the one or more FEC codewords in the second output data stream having the at least second bit width. [30] The method of claim 29, wherein respective ones of the k symbols in the second output data stream comprise a symbol width of ten (10) bits, the method comprising: Calculating the one or more syndromes with respect to k symbols of the second output data stream, where k = 7, and Calculating the one or more syndromes with respect to k symbols of the second output data stream, where k = 8. [31] A method according to claim 20, comprising: Signaling a latency predictor with a clock count value, the latency predictor comprising a lookup table with latency values each associated with clock count values. [32] A method according to claim 31, comprising: Adjusting a timing of a timestamping process for timestamping based at least in part on a latency value received from the latency predictor, the latency value responsive to the clock count value. [33] Facility comprising: a data width converter in a receive data path, the data width converter including an input for receiving an input data stream having an input bit width, a first output for generating a first output data stream having a first output bit width, and a second output for generating a second output data stream having at least a second output bit width; a synchronous first-in-first-out (FIFO) in the receive data path, the synchronous FIFO having an input at which the first output data stream with the first bit width is written into the synchronous FIFO, and the synchronous FIFO having an output at which the first output data stream with the first bit width is read out of the synchronous FIFO; at least one portion of a forward error correction (FEC) decoder parallel to the receive data path, wherein the at least one portion of the FEC decoder comprises an input for receiving the second output data stream having the at least second output bit width, wherein the at least one portion of the FEC decoder comprises an error correction output for generating one or more error correction values based at least in part on one or more FEC codewords in the second output data stream having the at least second output bit width; and a symbol error corrector in the receive data path, the symbol error corrector having a first input operatively coupled to the output of the synchronous FIFO, a second input operatively coupled to the error correction output of the FEC decoder, and an output for generating an error-corrected data stream from the first output data stream having the first bit width based at least in part on the one or more error correction values that correct one or more symbols, one or more subsymbols, or both in the first output data stream. [34] Device according to claim 33, wherein: the at least portion of the FEC decoder is operable on k symbols in the second output data stream having the at least second bit width, and respective ones of the k symbols comprise a symbol width of ten (10) bits, and the output of the symbol error corrector generates the error-corrected data stream based at least in part on the one or more error correction values for correcting the one or more subsymbols having a subsymbol width of five (5) bits. [35] The device of claim 34, wherein the at least one portion of the FEC decoder comprises: an error magnitude generator, wherein the error magnitude generator selectively outputs at the error correction output a selected number of the one or more correction values for correcting the one or more symbols or the one or more sub-symbols, wherein the one or more the multiple correction values comprise one or more error size values. [36] The device of claim 33, wherein the at least one portion of the FEC decoder comprises: a syndrome calculator, the syndrome calculator having an input for receiving the second output data stream having the at least second output bit width and an output for generating one or more syndromes based at least in part on the one or more FEC codewords. [37] Apparatus according to claim 36, wherein the syndrome calculator is operable on k symbols of the second output data stream having the at least second bit width, respective ones of the k symbols comprise a symbol width of s bits, and the at least second output bit width is an integer multiple of the symbol width. [38] Apparatus according to claim 37, wherein the syndrome calculator is operable on a variable number of symbols. [39] The device of claim 38, wherein the second output data stream having the at least second output bit width has a second output bit width in one or more first data transmissions and a third output bit width in one or more second data transmissions, the symbol width is ten (10) bits, and wherein: the syndrome calculator is operable on the variable number of symbols, including the second output bit width when k=7 and the third output bit width when k=8.

Images