ASYNCHRONOUS DATA TRANSPORT

Abstract

A method includes obtaining source data from a data source, wherein the source data may correspond to a source clock and may be stored in a data buffer. The method may also include performing clock adjustment to a particular clock. The particular clock may be associated with a data stream output from the data buffer. The clock adjustment may be to align the source clock and the particular clock. The method may include identifying a symbol clock associated with a buffer device. The method may also include adjusting a set of null packets in the data stream in response to a number of elements in the buffer device satisfying a threshold in the buffer device. The method may include updating clock reference values in the source data so that a client device can be synchronized to the source data with minimal clock jitter.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This U.S. patent application claims priority to U.S. Provisional Patent Application No. 63 / 380,724, entitled "ASYNCHRONOUS VIDEO TRANSPORT," filed October 24, 2022, the disclosure of which is hereby incorporated by reference in its entirety. FIELD OF TECHNOLOGY

[0002] This disclosure relates generally to a distributed architecture with a remote device, and more particularly to asynchronous audio / video transport with a remote device. BACKGROUND

[0003] Unless otherwise stated herein, the contents described herein are not prior art within the meaning of the claims of the present application and are not recognized as prior art by inclusion in this section.

[0004] A remote device can be included in a system for transporting data within the system, e.g., between a data source and a client device. The remote device can be a remote physical layer (PHY; PHY device = RPD) and / or a remote medium access control layer (MAC layer (MAC = Medium Access Control) Layer PHY device (RMD)). The remote device can be included in a distributed access architecture (DAA) network, e.g., an HFC (Hybrid Fiber Cable) network, and can be used to transmit data between the data source and the client device. The data can be digital audio or video data, or a combination thereof. The MPEG transport stream format, as typically used in video transmission networks, can be used to transmit the data.

[0005] The subject matter claimed in the present disclosure is not limited to implementations that solve any disadvantages or operate only in environments such as those described above. Rather, this background is provided merely to illustrate an example of a technology area in which some of the implementations described in the present disclosure may be applied. SUMMARY

[0006] In one embodiment, a method comprises obtaining source data from a data source, wherein the source data may correspond to a source clock and may be stored in a data buffer. The method may also comprise performing a clock adjustment to a particular clock. The particular clock may be associated with a data stream output from the data buffer. The clock adjustment may be to align the source clock and the particular clock. The method may comprise identifying a symbol clock associated with a buffer device. The method may also comprise adjusting a set of null packets in the data stream in response to a number of elements in the buffer device satisfying a threshold in the buffer device, e.g., a buffer device being filled or emptied beyond one or more thresholds.The method may also include adjusting the clock reference in the data stream when it is sent to a downstream client device so that the client device can synchronize with the incoming data stream with minimal jitter.

[0007] The objects and advantages of the embodiments will be realized and attained by at least the elements, features, and combinations particularly pointed out in the claims.

[0008] Both the foregoing general description and the following detailed description are exemplary and are intended to illustrate and not to limit the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Exemplary implementations are described and explained in more detail using the attached drawings in which they are shown: Fig. 1 shows an exemplary system for asynchronous data transport; Fig. 2 shows an exemplary system for asynchronous data transport; Fig. 3 shows a flowchart of an exemplary method for asynchronous data transport; and Fig. 4 shows a schematic representation of a computer in the example form of a computing device that implements asynchronous data transport. DETAILED DESCRIPTION

[0010] A remote device, such as a remote physical device (RPD), may support asynchronous video. In such cases, a source clock associated with a data source may differ from an internal clock associated with a remote device, which in turn may differ from a device clock associated with a receiving device, such as a set-top box. The remote device may be forced to manage a clock difference between the source clock and the internal clock when acquiring the source data from the source device, and the remote device may be operated to output a data stream at a rate (according to the internal clock) that can be obtained from the receiving device.The receiving device (or client device) can synchronize with the data stream using clock references generated by the source device and updated by the remote device as needed, particularly to account for clock adjustments between the source and remote devices. Synchronization can be performed in such a way that minimal jitter is introduced into a clock synchronization process in the receiving / client device.

[0011] Managing the clock difference between the source clock and the internal clock can be addressed by inserting and / or deleting null packets from the data stream, which can lead to clock mismatches with the device clock (e.g., because the data stream may deviate from the internal clock due to the inserted / deleted null packets). Some previous approaches perform program clock reference correction (PCR) aimed at handling the clock mismatches, but can cause underflow or overflow of transport stream packets in the client device, resulting in dropped data packets and / or interruptions to a service associated with the data stream. Previous approaches may also cause excessive jitter in the clock synthesized by the client device.

[0012] Some aspects of the present disclosure may be directed to aligning an internal clock with a source clock by monitoring a rate at which source data is received from a data buffer in the remote device and subsequently transmitted from the data buffer in the remote device. Furthermore, the remote device may include a buffer device operable to insert and / or drop null packets into a data stream (e.g., the source data transmitted from the data buffer) such that the data rate of the data transmitted from the buffer device using the aligned internal clock matches the data transmission rate using a symbol clock driving the next block, e.g., a modulator.The symbol clock may be associated with a rate at which the data stream is read into the buffer device, and the internal clock may be associated with a rate at which the data stream is written out of the buffer device.

[0013] Further aspects of the present disclosure may include novel approaches for correcting clock reference values that may be affected by the insertion and / or dropping of null packets from the data stream. For example, a delta clock reference value may be determined using characteristics of the null packets in the data stream, and the delta clock reference value may be used to correct problems that may arise from the insertion and / or dropping of null packets. In another example, a frequency offset estimate, measured in parts per million (ppm), may be determined with respect to a number of elements in the buffer device and characteristics of the null packets in the data stream, viewed over a period of time.Alternatively or additionally, the techniques described here may distribute the corrections to the clock reference values over one or more data packets in the data stream so that an overflow or underflow of the clock reference value cannot occur and / or the device clock can be locked and / or remain locked to the internal clock of the remote device.

[0014] Fig. Figure 1 illustrates an example system 100 for asynchronous data transport according to at least one embodiment of the present disclosure. System 100 may include a remote device 110.

[0015] The remote device 110 may be referred to as remote because operations performed by the remote device 110 may be distributed (e.g., remotely) from a data source 105 that may have previously been performed by the data source 105. In some embodiments, the remote device 110 may be a remote physical layer (PHY) device (RPD). Alternatively or additionally, the remote device 110 may be a remote medium access control (MAC) physical layer (PHY) device of the middle access control layer (RMD). The data source may be a video core, a converged cable access platform (CCAP) core, and / or a video core integrated with a CCAP core used in the distributed access architecture (DAA) in the HFC network.

[0016] The remote device 110 can obtain source data from the data source 105. The data source 105 can be a video server, a video network, and / or any other system or device capable of generating and / or transmitting the source data to the remote device 110. The source data can be video data, digital audio data, and / or a combination of video data and digital audio data. For example, the source data can be Moving Picture Experts Group (MPEG) transport stream data (MPEG-1) and / or can conform to at least one of the elementary stream standards included in the transport stream data (e.g., MPEG-2, MPEG-4, Dolby Atmos, H.264, HEVC, AV1, VVC, Windows Media, DTS, etc.).

[0017] The data source 105 may transmit the source data to the remote device 110 at a data rate that may be associated with a source clock included in the data source 105. For example, in cases where the source clock is faster than a standard clock, an associated data rate may be higher than a standard data rate associated with the standard clock (e.g., the source data may be transmitted to the remote device 110 more quickly). In another example, in cases where the source clock is slower than the standard clock, an associated data rate may be lower than the standard data rate associated with the standard clock. Clock references for a receiving device 115 (to which the remote device 110 may be connected) may be included in the source data of the data source 105, and the clock references may be generated by the source device 105 using the source clock.

[0018] In general, the source clock may be defined to be within a predefined clock value, but the specifics of the source clock may vary. For example, the source clock of data source 105 may have a first frequency and / or a first phase, and a second source clock of a second data source (not shown) may have a second frequency and / or a second phase associated therewith. In the examples, both the source clock and the second source clock may be within a predefined clock value, but may also have deviations within an acceptable and / or predetermined threshold as defined by a standard (e.g., the MPEG-4 standard).

[0019] The remote device 110 may include one or more clocks that may be used as part of acquiring the source data from the data source 105 and transmitting the source data (or a variation of the source data, as described herein) to a receiving device 115. The remote device 110 may include at least a first clock, which may be the same as, or substantially the same as, the source clock. In some embodiments, the frequency of the source clock may differ from the frequency of the first clock and / or the source clock and the first clock may have different drift rates. For example, in cases where the source clock and the first clock have a substantially similar frequency at a particular time, the source clock may drift relative to the first clock, such that at a second time, the frequency of the source clock and the frequency of the first clock may be different.

[0020] In some embodiments, the remote device 110 may not have any characteristics of the source clock (e.g., a frequency and / or a phase). Alternatively or additionally, the remote device 110 may know that the characteristics of the source clock may be limited to the values defined by the standard. Therefore, the remote device 110 may apply one or more techniques (as described herein, e.g., with respect to Fig. 2) to determine the source clock (e.g., the frequency and / or phase) so that a particular clock (which may, for example, be the same as the first clock of the remote device 110 described herein) may be the same or a similar clock to the source clock.

[0021] The remote device 110 may be operable to receive the source data from the data source 105, reduce and / or remove any jitter that may be associated with the source data, and transmit a data stream to a receiving device 115. The receiving device 115 may be a set-top box and / or other consumer device capable of utilizing the source data. In some embodiments, the receiving device 115 may experience difficulty and / or be unable to receive the data stream (and / or the packets contained in the data stream) if a jitter value in the data stream reaches a threshold.For example, in cases where the jitter in the data stream of remote device 110 exceeds a threshold, one or more data packets of the data stream may not be received and / or recovered by the receiving device 115, causing the receiving device 115 to experience degraded service, service interruption, and / or other data loss-related problems. The jitter may be due to the burstiness of the input data that remote device 110 receives from data source 105, or to the insertion or deletion of null packets in the data stream to match the input rate to the symbol clock rate of the remote device.

[0022] As described herein, remote device 110 may be capable of reducing and / or removing jitter from the data stream. Remote device 110 may include one or more components operable to insert and / or drop null packets into the data stream, thereby reducing and / or removing jitter from the data stream. Alternatively or additionally, remote device 110 may be operable to spread effects associated with inserting and / or dropping null packets across portions of the data stream, which may contribute to reducing and / or removing jitter from the data stream.In general, the remote device 110 may manage the data stream such that a clock in the receiving device 115 may be locked and / or remain locked to a clock in the remote device 110 that is associated with the data stream, which may help the receiving device 115 receive the data stream from the remote device 110.

[0023] Changes, additions, or omissions may be made to the system 100 without departing from the scope of the present disclosure. The designations of the various elements as described are for example illustrative of the concepts described herein and are not limiting. Furthermore, the system 100 may include any number of other elements or be implemented in systems or contexts other than those described. For example, each of the components of Fig. 1 be divided into additional components or combined into fewer components.

[0024] Fig. Figure 2 shows an exemplary system 200 for asynchronous data transport according to at least one embodiment of the present disclosure. System 200 may include a remote device 210. Remote device 210 may include a data buffer 220, a clock adjustment device 225, a buffer device 230, and a clock reference correction device 235.

[0025] Some components of the system 200 may be the same as or similar to the components of the system 100 of Fig. 1 and / or may perform the same or similar operations unless otherwise described. For example, a data source 205, the remote device 210, and a receiving device 215 may be the same or similar to the data source 105, the remote device 110, and the receiving device 115 of Fig. 1.

[0026] The data buffer 220 may obtain source data from the data source 205 and store the source data therein. The data buffer 220 may be configured to store up to a certain amount of source data (e.g., the data buffer 220 may have a maximum data storage amount). In some embodiments, the data buffer 220 may be monitored by and / or interact with another device, such as the clock adjustment device 225, to determine an amount of source data stored in the data buffer 220 relative to a buffer data threshold. The buffer data threshold may be a predetermined value of the data buffer 220, e.g., half the maximum data storage amount in the data buffer 220. Alternatively or additionally, the data buffer threshold may be adjustable, e.g.,based on characteristics of the system 200, the data source 205 and / or the remote device 210 and / or in response to user input.

[0027] In cases where the amount of source data in data buffer 220 meets the buffer data threshold, clock adjuster 225 may begin performing operations relative to a particular clock. The particular clock may be a clock associated with remote device 210 and may be configured to match or substantially match a source clock of data source 205 associated with the source data. Alternatively or additionally, the particular clock may be associated with a data stream output from data buffer 220, e.g., to buffer device 230. Clock adjuster 225 may be a numerically controlled oscillator (NCO) with a loop filter.Alternatively or additionally, the clock adjustment device 225 may be other systems or devices (including hardware, software, firmware, and / or combinations thereof) capable of performing the operations described herein.

[0028] The particular clock may be limited by the specification associated with the source data and / or by other components of the remote device 210 and / or the receiving device 215. For example, in cases where the source data is an MPEG-1 transport stream, the frequency range of the particular clock may include a frequency requirement of ± 30 parts per million (ppm) and a frequency drift of the particular clock may include a drift requirement of 0.075 Hz / s (approximately 10 ppm / hour).

[0029] The particular clock may begin at a nominal rate, such as a rate within a specification associated with the source data. In cases where the source data is, for example, MPEG-1, MPEG-2, or MPEG-4, the nominal rate associated with the particular clock may be a rate defined in the MPEG-1, MPEG-2, or MPEG-4 specification. Once the source data in data buffer 220 meets the buffer data threshold, the particular clock may begin (at the nominal rate), and clock adjuster 225 may perform one or more operations to adjust the particular clock to match or substantially match the source clock. For example, clock adjuster 225 may determine a rate at which the source data is received in data buffer 220 and may make adjustments to the particular clock so that the data stream exits data buffer 220 at substantially the same rate.The clock adjustment device 225 is operable to adjust and / or substantially adjust the specific clock to the source clock. The clock adjustment device 225 is operable to establish a dynamic balance with the source clock such that the frequency offset between the specific clock and the source clock is canceled with very low frequency jitter.

[0030] In some embodiments, the source data may include fluctuations such as jitter, which may be due to the frequency of data traffic on the network between the data source 205 and the remote device 210 and / or lost packets during transmission from the data source 205 to the remote device 210 and / or bursty transmissions. The clock adjuster 225 may be operable to obtain measurements associated with the source data in the data buffer 220 (e.g., a source data rate) and / or to average the measurements. In some embodiments, the measurements may be taken at a preset interval. For example, the clock adjuster 225 may include an infinite impulse response (IIR) filter, a finite impulse response (FIR) filter, and / or an adaptive filter that averages the measurements based on the preset interval.A slope of change relative to the source data in data buffer 220 may be calculated using:. ppm=(buff_level1−buff_level0) / (t1−t0) where buff_level1 and buff_level0 describe the amount of source data in data buffer 220 at a second time t1 and a first time t0, respectively. Furthermore, buff_level1 and buff_level0 may be obtained from the IIR filtering of the source data in data buffer 220, and / or the times t1 and t0 may refer to the specific clock.

[0031] In some embodiments, the above equation relating to the slope of change of the source data in data buffer 220 may contain one or more outliers (which may be associated with omitted source data) that may corrupt the ppm calculation. Clock adjuster 225 may be operated to remove the outliers. Alternatively or additionally, clock adjuster 225 may be operated to average the calculated ppm values over a number of ppm data points and use the averaged ppm values to refine the determined clock (such that the determined clock is equal to, or substantially equal to, the source clock). The averaged ppm values may be adjusted by: n_ppm=ceil(scale*n_ppm0) where n_ppm0 is an initial number of average ppm values, n_ppm is an actual number of average ppm values, and scale is a scaling factor that can be calculated based on a slope of change associated with the ppm values.

[0032] The clock adjustment device 225 may be operated to determine a frequency offset and / or a phase offset for the particular clock, e.g., by using the ppm values as described above. The frequency offset may be determined using an average of the ppm values over a preset time interval and may be represented by: ppm_avg=1n_ppm∑i=1n_ppmppm(i)

[0033] The phase offset may comprise an average of the source data in the data buffer 220 over a preset time interval and may be represented by: buff_avg=1n_ppm∑i=1n_ppmbuff_sample(i)

[0034] The average amount of source data in data buffer 220 (buff_avg or buffer average) can be compared to a target amount of source data in data buffer 220 (buffer setpoint). In cases where the buffer average does not match the buffer setpoint, adjustments can be made by clock adjuster 225 to equalize the buffer average and the buffer setpoint. Such adjustments can help align the particular clock with the source clock. An equation associated with the particular clock adjustments may be: freq_adj=freq_adj*(1+beta*ppm_avg+phase_coef*buff_avg) where freq_adj is the adjusted frequency associated with the particular clock, beta is an attenuation factor (e.g., a value less than one), ppm_avg is the average ppm values (as determined above), phase_coef is a scaling factor associated with a phase adjustment (e.g., it may be 1 ppm or 1.0e-6 by default), and buff_avg is the phase adjustment (as determined above). In such cases, the calculated adjusted frequency may be used by the clock adjustment device 225 to update the particular clock. In some embodiments, the calculation of the adjusted frequency may be performed in firmware and transferred for implementation in hardware.

[0035] Buffer device 230 may include a symbol clock that may differ from the specific clock and / or the source clock. For example, the symbol clock may be connected to a symbol clock of a quadrature amplitude modulation (QAM) modulator assigned to buffer device 230. Buffer device 230 may use the symbol clock to read the data stream (e.g., one or more packets contained in the data stream received from data buffer 220), and buffer device 230 may use the specific clock to write the data stream, e.g., directly to receiving device 215.

[0036] In some embodiments, the symbol clock may deviate from the determined clock, so that a number of elements from the data stream in the buffer device 230 may drift over time. The buffer device 230 may be configured to attempt to hold a threshold number of elements from the data stream therein. For example, the buffer device 230 may provide space for a maximum number of elements (e.g., 256 bytes or slightly more than the size of an MPEG-1 transport stream packet, e.g., 188 bytes), and the buffer device 230 may begin performing operations when the number of elements in the buffer device 230 meets a threshold number of elements (e.g., approximately 94 bytes or half of an MPEG-1 transport stream packet).

[0037] As the buffer device 230 performs operations, in cases where the symbol clock is faster than the specified clock, the number of elements in the buffer device 230 may increase (e.g., the amount of data stream read into the buffer device 230 is greater than the amount of data stream written out of the buffer device 230). Alternatively or additionally, in cases where the symbol clock is slower than the specified clock, the number of elements in the buffer device 230 may decrease (e.g., the amount of data stream read into the buffer device 230 is less than the amount of data stream written out of the buffer device 230).

[0038] Buffer device 230 may be operable to adjust the amount of null packets in the data stream. Adjusting the amount of null packets in the data stream may help reduce and / or eliminate drift in the data stream associated with the difference between the symbol clock and the determined clock. In some embodiments, buffer device 230 may determine when to adjust the amount of null packets in the data stream. Alternatively or additionally, control logic hardware and / or control logic software may be included in remote device 210 and adjust the amount of null packets in the data stream.

[0039] In cases where the number of elements in buffer device 230 meets an upper threshold, one or more null packets may be dropped from the data stream. For example, the upper threshold may be 230 elements or more, and in cases where the number of elements in buffer device 230 is greater than 230 elements, one or more null packets may be dropped from the data stream.

[0040] In cases where the number of elements in buffer device 230 meets a lower threshold, one or more null packets may be inserted into the data stream. The lower threshold may be, for example, 20 elements or less, and in cases where the number of elements in buffer device 230 is less than 20 elements, one or more null packets may be inserted into the data stream. Buffer device 230 may continue to insert and / or discard null packets into the data stream so that the number of elements in buffer device 230 can be maintained between the upper and lower thresholds. Alternatively or additionally, a hysteresis loop may be used when inserting or deleting a packet.Packet insertion may begin when the lower threshold is reached, and packet insertion may continue until the buffer level builds up to a predetermined offset above the lower threshold. Similarly, packet deletion may begin when the higher threshold is reached, and packet deletion may continue until the buffer level builds up to a predetermined offset below the higher threshold.

[0041] In some embodiments, the adjustments to the number of null packets in the data stream may result in one or more clock reference values (e.g., program clock reference values (PCR values)) in the data stream being shifted in time. For example, there may be "n" transport stream packets between two clock reference values in the original data stream, but one or more null packets may be inserted, so that the effective time interval between the two clock reference values deviates from "n" transport stream packets. This may result in a large phase shift in the positive and / or negative direction each time null packets are inserted and / or deleted, and the phase shift may be reduced over time. The shifted clock reference values, and thus the large phase jitter, may affect how a clock connected to the receiving device 215 can be synchronized with the specific clock.In some cases, sudden corrections to the clock reference values may cause problems with the ability of the receiving device 215 to synchronize with the particular clock. The clock reference correction device 235 may be operated to perform a correction of the clock reference values and / or to distribute the correction of the clock reference values over multiple packets ( ), which may reduce the suddenness of the correction and help ensure that the clock contained in the receiving device 215 remains synchronized with the particular clock.

[0042] The corrections to the clock reference values by the clock reference correction device 235 due to adjustments to the amount of null packets in the data stream (e.g., insertion of null packets and / or discarding of null packets) may comply with an accuracy requirement defined in a specification such as ITU-T Rec. H.222.0. For example, a clock reference value tolerance may be ± 500 ns, whereby time shifts caused by adjustments to the amount of null packets in the data stream may exceed the clock reference tolerance.

[0043] In a first implementation, adjustments to the amount of null packets in the data stream can be corrected by determining a delta clock reference value based on whether a null packet is inserted or dropped. The generalized equation is: t_c0PRIOR=0 t_c=+ / −t_c0PRIOR+ / −[t_d*(1−t_dis / t_i)] t_c0NEXT=(t_i−t_dis) / t_i*t_d ◯ where t_c0NEXT the residual value of the t_c correction value at the time of the NULL event is and where: t_d ΔPCR ◯ Duration of an MPEG packet; based on baud rate, QAM modulation order, line coding ◯ Sign based on a zero event that is an insertion or deletion t_i Number of packets between the zero packets of the rate adaptation ◯ returns the frequency delta between the source clock of the source data and the specific clock t_dis MPEG PCR position ◯ Number of packets from the zero event to the MPEG PCR packet t_c PCR correction value ◯ This is a correction calculation based on the distance of the MPEG-PCR packet from the previous zero event with respect to t_d and t_i. t_c0 PCR correction carryover ◯ As mentioned above, t_i will change / shift over time. If a NULL event occurs, either before or after the expected t_i, t_c will have a residual value (or overflow) that must be carried over to the next t_c correction cycle. The t_c0 component indicates an error in t_d and / or t_i.

[0044] In cases where a null packet is inserted, the delta clock reference value can be determined as follows: • t_C INSERT = + / - t_c0 PRIOR-INSERT + [t_d * (1 - t_dis INSERT / t_i INSERT )] • t_c0 NEXT-INSERT = (t_i INSERT - t_dis INSERT ) / t_i INSERT * t_d (for event NULL)

[0045] In cases where a null packet is dropped, the delta value can be determined using: • t_c DELETE = + / - t_c0 PRIOR-DELETE - [t_d * (1 - t_dis DELETE / t_i DELETE )] • t_c0 NEXT-DELETE = (t_i DELETE - t_dis DELETE ) / t_i DELETE* t_d (at NULL event)

[0046] The sum of these two equations is added: • t_c = t_c INSERT + t_c (DELETE

[0047] Conventional techniques may determine the delta clock reference value using t_c → + / - m * t_d, where m is the total number of inserted / deleted null packets (cumulative), which may result in underflow / overflow of transport stream packets in the receiving device 215 when the receiving device 215 compares the presentation timestamp of the audio or video elementary stream packets with the local clock generated after updated program clock reference values, which are updated in the remote device 210 by simply adjusting the program clock reference values by the time corresponding to the aggregate number of inserted or deleted null packets. The present disclosure addresses these and other shortcomings of the conventional techniques by calculating the clock reference value using t_c → t_c + / - a * t_d; where a <2. Further, the clock reference value may be bounded by ~2 * t_d.Alternatively or additionally, the average time interval (e.g., t_i) may be updated with a moving average for the calculations described here.

[0048] In a second implementation, the number of elements in the buffer device 230 can be observed according to a number of times t(i), i = 1, 2, 3, ..., where the times can have a fixed time interval (e.g., t(i+1) - t(i) = t_i). In some embodiments, t_i can be constant and / or adjustable, e.g., via software. Adjustments to the number of null packets in the data stream can be determined as follows: ppm0=(B2−B1−tdel) / 188*t_d / t_i ppm=α*ppm0+(1+α)*ppm0 (as average) where B1 and B2 are the number of elements observed in the buffer 230 at time t(i) and t(i+1), respectively; t_del is equal to (n - m) * 188, where n is the total number of null packets inserted between t(i) and t(i+1) and m is the total number of null packets dropped between t(i) and t(i+1); t_d is the duration of the null packets; and α is an average forgetting factor.

[0049] In some embodiments, the above implementation may be performed using hardware. In such cases, a value (av_timed_rate_fifo_lvl_count_cnfg) may be a measure of the number of packets to be measured, the number of elements in the remote device (e.g., at a start time (av_timed_rate_fifo_lvl_start) and an end time (av_timed_rate_fifo_lvl_end)) may be measured, and / or a number of zero insertions and / or deletions may be determined. PPM=((av_timed_rate_fifo_lvl_end−av_timed_rate_fifo_lvl_start)+ / −188*nullcounts) / (av_timed_rate_fifo_lvl_count_cnfg*188)

[0050] In another embodiment, ppm could be tracked based on zero insertion / deletion events and monitoring the number of items in the remote device: PPM=((av_rate_fifo_lvl_end−av_rate_fifo_lvl_start)+188) / (av_rate_fifo_delta_num_pkt*188)

[0051] Another embodiment may count the number of bytes pushed into the remote device at the input rate and count the number of bytes read at the output rate over a given period of time. PPM=(mpt_rate_fifo_bytes_out−mpt_rate_fifo_bytes_in) / mpt_rate_fifo_bytes_out

[0052] In general, ppm can be measured by monitoring data in the form of running units, such as packets, to other units, such as discrete bits. Monitoring the data in conjunction with a measurement duration and / or other information, such as data addition / removal, can yield the ppm rate difference between input and output.

[0053] In the above equations, ppm may not be defined as a conventional frequency offset in units of ppm (parts per million), but may refer to a 1:1 slope (or part per one). In cases where the ppm value is greater than zero, it can be determined that a null packet may be discarded from the data stream. Alternatively, or additionally, in cases where the ppm value is less than zero, it can be determined that a null packet may be inserted into the data stream.

[0054] In some embodiments, the correction of the clock reference values may be associated with the null packet insertion / deletion events. The correction of the clock reference values may be rewritten in terms of changes due to ppm updates using the following equation: tc=const+tc0+tdel0+∑i=1Nt_dis(i)∗ppm(i) where t_c is the delta clock reference value, const is a constant (e.g., const = -t_d) to ensure that the clock reference value is smaller than the presentation timestamp, t_c0 is an uncompensated time shift that may be caused by a previous insertion / deletion of a null packet, t_del0 is equal to t_d when a null packet is inserted, and t_del0 is equal to -t_d when a null packet is dropped, t_dis(i) is the distance in the i-th observation interval, and ppm(i) is the ppm used in the i-th observation interval (e.g., from the equations above), i = 1, 2, ...N. In some embodiments, t_c0 may be the t_c determined as the residue of the clock reference value correction from a previous insertion / deletion of a null packet at a time when the current null packet is inserted / dropped.

[0055] In both the first and second implementations described above, the corrections to the clock reference values can be distributed in one or more individual packets in the data stream between the null packet events (e.g., the insertion or deletion of null packets in the data stream). Distributing the corrections can reduce jitter that may be introduced by the insertion / deletion of null packets in the data stream, which may cause the clock in the receiving device 215 to no longer match the specific clock in the remote device 210.

[0056] For example, the data stream may include clock reference values associated with individual data packets that may be distributed at a known interval. For example, a clock reference value may be included in data packets transmitted every 200 clock cycles. Using the equations described herein, it may be determined that a null packet may be inserted / dropped approximately every fourth clock reference value (e.g., approximately every 800 clock cycles). In response to the adjustment of null packets in the data stream, the clock reference values may be corrected using the equations described herein, and the corrections to the clock reference values may be distributed among the data packets with a clock reference value (e.g., the data packets that occur every 200 clock cycles in this example) that occur between the null packet events.

[0057] For example, using the above schedule, a first null packet event (e.g., inserting a null packet or deleting a null packet from the data stream) may occur at approximately 200 clock cycles, and a second null packet event may occur at approximately 1000 clock cycles. The corrections to the clock reference values may be distributed such that a first clock reference value in a data packet may include a portion of the correction at 200 clock cycles, a second clock reference value in a data packet may include a portion of the correction at 400 clock cycles, a third clock reference value in a data packet may include a portion of the correction at 600 clock cycles, and a fourth clock reference value in a data packet may include a portion of the correction at 800 clock cycles, so that the entirety of the correction may be distributed across multiple clock reference values (e.g., the first, second, third, and fourth clock reference values).By distributing the corrections to the clock reference values over several clock reference values in data packets in the data stream, the accuracy of the clock reference values may not exceed a threshold, so that the locking of the clock in the receiving device 215 with the specific clock in the remote device 210 may not be interrupted.

[0058] Fig. 3 shows an exemplary flow 300 of multiple packets through a network processing system using a distributed hardware architecture, in accordance with at least one embodiment of the present disclosure. The data flow 300 may be executed by processing logic that may include hardware (circuitry, dedicated logic, etc.), software (such as executing on a general-purpose computer system or a dedicated machine), or a combination of both, where the processing logic may be included in any computer system or device, such as the queue system 120 of Fig. 1. Implementation can also be done on application-specific integrated circuits (ASICs) or programmable hardware devices (e.g., FPGAs) or graphics processing units (GPUs) using dedicated hardware or a mix of software and hardware, or entirely in software.

[0059] For simplicity, the methods described herein are illustrated and described as a series of acts. However, the acts according to this disclosure may be performed in different orders and / or concurrently and with other acts not illustrated and described herein. Further, not all illustrated acts may be used to perform the methods according to the disclosed subject matter. Moreover, those skilled in the art will understand and appreciate that the methods may alternatively be represented as a series of interconnected states via a state diagram or events. Furthermore, the methods disclosed in this specification may be stored on an article of manufacture, such as a non-transitory computer-readable medium, to facilitate the transport and transfer of such methods to computers.As used herein, the term "article of manufacture" is intended to encompass a computer program accessible by any computer-readable device or storage medium. Although represented as individual blocks, various blocks may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation.

[0060] In block 302, source data corresponding to a source clock may be obtained from a data source. The source data may be stored in a data buffer. In some embodiments, the data source may be a video server, and the source data may be MPEG (Moving Picture Experts Group) data. The source data may originate from a video core or a CCAP core, or a video core integrated with a CCAP core, used in the DAA in the HFC network.

[0061] In block 304, a clock adjustment may be performed to a particular clock. The particular clock may be associated with a data stream output from the data buffer. The clock adjustment may be used to adjust the source clock and the particular clock. The clock adjustment may be determined to be performed in response to an amount of source data in the data buffer satisfying a buffer data threshold.

[0062] In some embodiments, clock adjustment may include monitoring an input buffer rate associated with the source data stored in the data buffer. Alternatively or additionally, clock adjustment may include monitoring an output buffer rate associated with the data stream output from the data buffer. Alternatively or additionally, clock adjustment may include adjusting the determined clock to cause the source data rate in the data buffer to converge to a predetermined threshold, wherein the input buffer rate and the output buffer rate may be adjusted.

[0063] In block 306, a symbol clock associated with the buffer device may be identified.

[0064] In block 308, a set of null packets in the data stream may be adjusted in response to a number of elements in the buffer device meeting a threshold in the buffer device. In some embodiments, a change in the number of elements in the buffer device may be caused by a difference between the symbol clock and the determined clock.

[0065] In some embodiments, one or more null packets may be removed from the data stream in response to the number of elements in the buffer device meeting an upper threshold in the buffer device. Alternatively or additionally, one or more null packets may be inserted into the data stream when the number of elements in the buffer device meeting a lower threshold in the buffer device.

[0066] Changes, additions, or omissions may be made to data stream 300 without departing from the scope of the present disclosure. For example, in some cases, one or more clock reference values located within individual data packets in the data stream may be corrected in response to the adjustment of the null packets in the data stream. In some embodiments, the one or more clock reference values may be corrected by a frequency offset estimate (in parts per million) determined using at least the number of elements in the buffer device and the characteristics of the null packets in the data stream over a time interval. The characteristics of the null packets may include a total number of inserted null packets, a total number of discarded null packets, and / or a duration associated with the null packets.Furthermore, the corrected clock reference values may be distributed between at least one data packet in the data stream associated with a first clock adjustment and a subsequent data packet in the data stream associated with a second clock adjustment.

[0067] Alternatively or additionally, the one or more clock reference values may be corrected by a delta clock reference value determined at least based on the characteristics of the null packets in the data stream. The characteristics of the null packets may include a duration associated with the null packets, an average time interval between the null packet adjustments, a first timestamp associated with the clock reference value correction, a second timestamp associated with a clock adjustment, and / or a time shift associated with a previous null packet adjustment. Furthermore, the corrected clock reference values may be distributed between at least one data packet in the data stream associated with a first null packet adjustment and a subsequent data packet in the data stream associated with a second null packet adjustment.

[0068] As another example, the names of the various elements in the manner described are intended to help explain the concepts described herein and are not limiting. Furthermore, the process 300 may include any number of other elements or be implemented in systems or contexts other than those described.

[0069] Fig.4 shows a schematic representation of a computer in the exemplary form of a computing device 400, in which a set of instructions may be executed to cause the computer to perform one or more of the methods discussed herein. The computing device 400 may include a mobile phone, a smartphone, a netbook computer, a rackmount server, a router computer, a server computer, a personal computer, a mainframe computer, a laptop computer, a tablet computer, a desktop computer, etc., in which a set of instructions may be executed to cause the computer to perform one or more of the methods discussed herein. In alternative embodiments, the computer may be connected (e.g., networked) to other computers on a LAN, an intranet, an extranet, or the Internet. The computer may operate in the capacity of a server in a client-server network environment.The computer may be a personal computer (PC), a set-top box (STB), a server, a network router, a switch or bridge, or any other computer capable of executing a set of instructions (sequential or otherwise) that specify the actions to be performed by that computer. Although only a single computer is illustrated, the term "computer" may also include any collection of computers that individually or collectively execute a set (or multiple sets) of instructions to perform one or more of the methods described herein.

[0070] The example computing device 400 includes a processing device (e.g., a processor) 402, a main memory 404 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM)), a static memory 406 (e.g., flash memory, static random access memory (SRAM)), and a data storage device 416 that communicate with each other via a bus 408.

[0071] Processing device 402 is one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. In particular, processing device 402 may include a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets or processors implementing a combination of instruction sets. Processing device 402 may also include one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. Processing device 402 is configured to execute instructions 426 to perform the operations and steps discussed herein.

[0072] Computing device 400 may also include a network interface 422 that can communicate with a network 418. Computing device 400 may also include a display device 410 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 412 (e.g., a keyboard), a cursor control device 414 (e.g., a mouse), and a signal generating device 420 (e.g., a speaker). In at least one embodiment, display device 410, alphanumeric input device 412, and cursor control device 414 may be combined into a single component or device (e.g., an LCD touchscreen).

[0073] The data storage device 416 may include a computer-readable storage medium 424 having stored thereon one or more sets of instructions 426 embodying one or more of the methods or functions described herein. The instructions 426 may also reside entirely or at least partially in the main memory 404 and / or the processing device 402 while being executed by the computing device 400, with the main memory 404 and the processing device 402 also representing computer-readable media. The instructions may further be transmitted or received over a network 418 via the network interface device 422.

[0074] While the computer-readable storage medium 426 is illustrated as a single medium in one embodiment, the term "computer-readable storage medium" may include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) that store the one or more instruction sets. The term "computer-readable storage medium" may also include any medium capable of storing, encoding, or carrying a set of instructions for execution by the computer, and that causes the computer to perform one or more of the methods of the present disclosure. Accordingly, the term "computer-readable storage medium" may include, but is not limited to, solid-state storage, optical media, and magnetic media.

[0075] While a number of implementations have been described, it should be understood that various changes may be made without affecting the spirit and scope of the disclosure. Accordingly, other embodiments are also within the scope of the following claims.

[0076] As is common practice, the various features illustrated in the drawings may not be drawn to scale. The illustrations presented in the present disclosure are not intended to be actual views of any particular apparatus (e.g., device, system, etc.) or method, but are merely idealized representations used to describe various embodiments of the disclosure. Accordingly, the dimensions of the various features may be arbitrarily expanded or reduced for clarity. In addition, some of the drawings may be simplified for clarity. For example, the drawings may not depict all components of a particular apparatus (e.g., device) or all acts of a particular method.

[0077] The terms used in the present disclosure, and particularly in the appended claims (e.g., in the body of the appended claims), should generally be understood as "open-ended terms" (e.g., the term "comprising" should be interpreted as "including, but not limited to").

[0078] If a specific number of introductory claims is intended, this intention will be expressly mentioned in the claim; if no such mention is made, there will be no intention. For clarity, in the following appended claims, the introductory phrases “at least one” and “one or more” may be used to introduce claim mentions. However, the use of such phrases should not be construed to mean that the introduction of a claim list by the indefinite articles “a” or “an” limits a particular claim containing such an introduced claim list to implementations containing only one such list, even if the same claim contains the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an” (e.g.,, "a" and / or "an" should be interpreted to mean "at least one" or "one or more"; the same applies to the use of certain articles used to introduce claims.

[0079] Even if a specific number of introduced claims is expressly recited, the skilled person will recognize that such a list is to be interpreted as meaning at least the recited number (e.g., the mere list "two lists" without other modifiers means at least two lists or two or more lists). In cases where the phrase "at least one of A, B, and C, etc." or "one or more of A, B, and C, etc." is used, such a construction is generally intended to include A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together, etc.

[0080] Furthermore, any disjunctive word or phrase preceding two or more alternative terms in the description, claims, or drawings should be understood to include the possibility of including exactly one of the terms, either of the terms, or both of the terms. For example, the phrase "A or B" should be understood to include the possibilities "A" or "B" or "A and B."

[0081] Furthermore, the terms "first," "second," "third," etc., are not necessarily used here to denote a specific order or number of elements. In general, the terms "first," "second," "third," etc., are used as generic labels to distinguish between different elements. Unless it is demonstrated that the terms "first," "second," "third," etc., denote a specific order, these terms should not be understood to denote a specific order. Unless it is demonstrated that the terms "first," "second," "third," etc., denote a specific number of elements, these terms should not be understood to denote a specific number of elements. For example, a first widget can be described as a first page, and a second widget can be described as a second page.The use of the term "second page" in reference to the second widget may serve to distinguish that page of the second widget from the "first page" of the first widget, and is not intended to imply that the second widget has two pages.

[0082] All examples and conditional expressions provided in the present disclosure are intended for educational purposes to facilitate the reader's understanding of the present disclosure and the concepts the inventor contributed to advancing the prior art, and are to be construed as not limiting to the specifically recited examples and conditions. Although implementations of the present disclosure have been described in detail, various changes, substitutions, and alterations may be made without departing from the spirit and scope of the present disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 380,724

[0001]

Claims

[1] A process comprising: Obtaining source data corresponding to a source clock from a data source, wherein the source data is stored in a data buffer; performing a clock adjustment to a specific clock, wherein the specific clock is associated with a data stream output from the data buffer and the clock adjustment is to align the source clock and the specific clock; identifying a symbol clock associated with a buffer device; and adjust a set of null packets in the data stream in response to a number of elements in the buffering means meeting a threshold in the buffering means. [2] The method of claim 1, further comprising correcting one or more clock reference values located in individual data packets in the data stream in response to the adjustment of the null packets in the data stream. [3] The method of claim 2, wherein the one or more clock reference values are corrected by a frequency offset estimate determined using at least the number of elements in the buffer device and the characteristics of the null packets in the data stream over a time interval. [4] The method of claim 3, wherein the characteristics of the null packets include a total number of inserted null packets, a total number of discarded null packets, and a duration associated with the null packets. [5] The method of claim 3, wherein the corrected clock reference values are distributed between at least one data packet in the data stream associated with a first zero packet adjustment and a subsequent data packet in the data stream associated with a second zero packet adjustment. [6] The method of claim 2, wherein the one or more clock reference values are corrected by a delta clock reference value determined using at least characteristics of the null packets in the data stream. [7] The method of claim 6, wherein the features of the null packets include: a duration associated with the zero packets, an average time interval between the zero packet adjustments, a first time stamp associated with the clock reference value correction, a second time stamp associated with a zero packet adjustment, and a time shift associated with a previous zero packet adjustment. [8] The method of claim 6, wherein the corrected clock reference values are distributed between at least one data packet in the data stream associated with a first zero packet adjustment and a subsequent data packet in the data stream associated with a second zero packet adjustment. [9] The method of claim 1, wherein the clock adjustment is determined to be performed in response to an amount of the source data in the data buffer satisfying a buffer data threshold. [10] The method of claim 1, wherein the clock adjustment further comprises: Monitoring an input buffer rate associated with the source data stored in the data buffer; monitoring an output buffer rate associated with the data stream output from the data buffer; and Adjusting the determined clock to cause the amount of source data in the data buffer to converge to a predetermined threshold, wherein the input buffer rate and the output buffer rate are equalized. [11] The method of claim 1, wherein a change in the number of elements in the buffer means is caused by a difference between the symbol clock and the determined clock. [12] The method of claim 1, wherein the data source is a video server, a video core, or a CCAP core with video transmission functionality integrated into a distributed access architecture (DAA) in a hybrid fiber optic cable (HFC) network, and the source data is MPEG (Moving Picture Experts Group) data. [13] The method of claim 1, wherein in response to the number of elements in the buffering means satisfying an upper threshold in the buffering means, one or more of the null packets are discarded from the data stream. [14] The method of claim 1, wherein in response to the number of elements in the buffer means satisfying a lower threshold in the buffer means, one or more of the null packets are inserted into the data stream. [15] A device comprising: a data buffer for storing source data from a data source, the source data corresponding to a source clock; a clock adjustment device for performing a clock adjustment to a specific clock to equalize the source clock and the specific clock; and a buffer means for adjusting a quantity of null packets in a data stream output from the data buffer, the buffer means adjusting the null packets in response to a number of elements in the buffer means satisfying a threshold in the buffer means. [16] The apparatus of claim 15, further comprising reference correction means for correcting one or more timing reference values located in individual data packets in the data stream in response to the adjustment of the null packets in the data stream. [17] The apparatus of claim 16, wherein the one or more clock reference values are corrected by a frequency offset estimate determined using at least the number of elements in the buffer device and the characteristics of the null packets in the data stream over a time interval. [18] The apparatus of claim 17, wherein the corrected clock reference values are distributed between at least one data packet in the data stream associated with a first zero packet match and a subsequent data packet in the data stream associated with a second zero packet match. [19] The apparatus of claim 15, wherein the data source is a video server and the source data is MPEG data (MPEG = Moving Picture Experts Group data). [20] The device according to claim 15, wherein: in response to the number of elements in the buffer device satisfying an upper threshold in the buffer device, one or more of the null packets are discarded from the data stream; and in response to the number of elements in the buffer device satisfying a lower threshold in the buffer device, inserting one or more of the null packets into the data stream.

Images