Drive circuit, display substrate and display device

Abstract

This disclosure relates to a drive circuit, a display substrate and a display device.The drive circuit comprises an input circuit, a reset circuit, a first node reset circuit, and a control node control circuit; the first node reset circuit controls a first node so that it is connected to or disconnected from a first voltage line under the control of an electrical potential of a second node; the control node control circuit controls a control node so that it is connected to or disconnected from a third voltage line under the control of an electrical potential of the first node; the channel width-to-length ratio of a transistor included in the first node reset circuit, whose gate electrode is electrically connected to the second node, to the channel width-to-length ratio of a transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24.This revelation enables a sensible layout of the transistors contained in the circuits and can effectively prevent leakage currents at the first node, improve the driving capability of the display product, prevent noise from the control node from entering the first node through leakage currents, improve the stability of the drive circuit, and prevent multiple outputs.

Description

AREA OF TECHNOLOGY The present disclosure relates to the field of display technology and in particular to a drive circuit, a display substrate and a display device. STATE OF THE ART As consumer demands for resolution and refresh rate of display devices have increased in recent years, the drive capability of display fields has also had to be improved accordingly, leading to the development of high-mobility oxide transistors. However, regarding the electrical characteristics of these oxide transistors, their threshold voltages are more negative than those of conventional transistors, meaning that some transistors in the drive circuit operate for extended periods with a gate-source voltage of 0 V, resulting in increased leakage current and power consumption. Furthermore, current technologies do not allow for the optimal arrangement of transistors in the drive circuit, leakage at the first node cannot be effectively prevented, and the drive capability of the display product cannot be improved.Conventional drive circuits cannot prevent noise from the control node from leaking into the first node, cannot improve the stability of the drive circuit, and cannot prevent multiple outputs. SUMMARY In one aspect, an embodiment of the present disclosure provides a drive circuit comprising an input circuit, a reset circuit, a first node reset circuit, and a control node control circuit; wherein the input circuit is electrically connected to an input control terminal, an input terminal, and a first node and serves to connect or disconnect the input terminal from the first node under the control of an input control signal provided by the input control terminal; the reset circuit is electrically connected to a reset terminal, the first node, and a first voltage line and serves to connect or disconnect the first node from the first voltage line under the control of a reset signal provided by the reset terminal;The first node reset circuit is electrically connected to a second node, the first node, and the first voltage line, and serves to connect or disconnect the first node from the first voltage line under the control of an electrical potential of the second node; the control node control circuit is electrically connected to the first node, a third voltage line, and a control node, and serves to connect or disconnect the control node from the third voltage line under the control of an electrical potential of the first node; a transistor contained in the input circuit, a transistor contained in the reset circuit, and a transistor contained in the first node reset circuit are arranged sequentially along a direction away from the display area;a ratio of the channel width-to-length ratio of a transistor included in the first node reset circuit, whose gate electrode is electrically connected to the second node, to a channel width-to-length ratio of a transistor included in the control node control circuit, is greater than or equal to 6 and less than or equal to 24. Optionally, the drive circuit according to at least one embodiment of the present disclosure further comprises a frame reset circuit; wherein the frame reset circuit is electrically connected to a frame reset line, the first node and a second voltage line and serves to connect or disconnect the first node from the second voltage line under the control of a frame reset signal provided by the frame reset line; a transistor contained in the frame reset circuit is arranged on a side of the transistor contained in the first node reset circuit that is remote from the display area. Optionally, the input circuit includes at least two input transistors connected in series, and the reset circuit includes at least two reset transistors connected in series. Optionally, the first node reset circuit comprises at least two transistors connected in series, whose gate electrodes are electrically connected to the second node; or the second node comprises a first second node and a second second node; the first node reset circuit comprises at least two transistors connected in series, whose gate electrodes are electrically connected to the first second node, and at least two transistors connected in series, whose gate electrodes are electrically connected to the second second node. Optionally, the frame reset circuit includes at least two frame reset transistors connected in series. Optionally, the transistor contained in the control node control circuit is located on a side of the transistor contained in the input circuit that is close to the display area. Optionally, the control node control circuit includes a control transistor; one gate electrode of the control transistor is electrically connected to the first node, one first electrode of the control transistor is electrically connected to the third voltage line, and one second electrode of the control transistor is electrically connected to the control node. Optionally, the drive circuit according to at least one embodiment of the present disclosure further comprises a shutdown-reset circuit; the shutdown-reset circuit is electrically connected to a fourth voltage line and a drive signal output terminal and serves to connect or disconnect the drive signal output terminal from the fourth voltage line under the control of a fourth voltage signal provided by the fourth voltage line. Optionally, a transistor included in the shutdown reset circuit is arranged on a side of the transistor included in the input circuit that is close to the display area. Optionally, the shutdown reset circuit includes a shutdown reset transistor; a gate electrode of the shutdown reset transistor and a first electrode of the shutdown reset transistor are electrically connected to the fourth voltage line, and a second electrode of the shutdown reset transistor is electrically connected to the drive signal output terminal. Optionally, the input circuit includes a first input transistor and a second input transistor; a gate electrode of the first input transistor is electrically connected to the input control terminal, a first electrode of the first input transistor is electrically connected to the input terminal, and a second electrode of the first input transistor is electrically connected to the control node; a gate electrode of the second input transistor is electrically connected to the input control terminal, a first electrode of the second input transistor is electrically connected to the control node, and a second electrode of the second input transistor is electrically connected to the first node. Optionally, the input control terminal is a transmission signal output terminal of a previous stage of the drive circuit, and the input terminal is a drive signal output terminal of the previous stage of the drive circuit; or both the input control terminal and the input terminal are the transmission signal output terminal of the previous stage of the drive circuit. Optionally, the reset circuit includes a first reset transistor and a second reset transistor; a gate electrode of the first reset transistor is electrically connected to the reset terminal, a first electrode of the first reset transistor is electrically connected to the first node, and a second electrode of the first reset transistor is electrically connected to the control node; a gate electrode of the second reset transistor is electrically connected to the reset terminal, a first electrode of the second reset transistor is electrically connected to the control node, and a second electrode of the second reset transistor is electrically connected to the first voltage line. Optionally, the channel width-to-length ratio of a transistor included in the control node control circuit is smaller than the channel width-to-length ratio of the second reset transistor. Optionally, the first node reset circuit includes a first pull-down transistor and a second pull-down transistor; a gate electrode of the first pull-down transistor is electrically connected to the second node, a first electrode of the first pull-down transistor is electrically connected to the first node, and a second electrode of the first pull-down transistor is electrically connected to the control node; a gate electrode of the second pull-down transistor is electrically connected to the second node, a first electrode of the second pull-down transistor is electrically connected to the control node, and a second electrode of the second pull-down transistor is electrically connected to the first voltage line. Optionally, the channel width-to-length ratio of the second pull-down transistor to the channel width-to-length ratio of a transistor included in the control node control circuit must be greater than or equal to 6 and less than or equal to 24. Optionally, the channel width-to-length ratio of the second pull-down transistor is larger than the channel width-to-length ratio of the first pull-down transistor. Optionally, the second node comprises a first second node and a second second node; wherein the first node reset circuit comprises a first pull-down transistor, a second pull-down transistor, a third pull-down transistor, and a fourth pull-down transistor; a gate electrode of the first pull-down transistor is electrically connected to the first second node, a first electrode of the first pull-down transistor is electrically connected to the first node, and a second electrode of the first pull-down transistor is electrically connected to the control node; a gate electrode of the second pull-down transistor is electrically connected to the first second node, a first electrode of the second pull-down transistor is electrically connected to the control node, and a second electrode of the second pull-down transistor is electrically connected to the first voltage line;a gate electrode of the third pull-down transistor is electrically connected to the second second node, a first electrode of the third pull-down transistor is electrically connected to the first node, and a second electrode of the third pull-down transistor is electrically connected to the control node; a gate electrode of the fourth pull-down transistor is electrically connected to the second second node, a first electrode of the fourth pull-down transistor is electrically connected to the control node, and a second electrode of the fourth pull-down transistor is electrically connected to the first voltage line. Optionally, the channel width-to-length ratio of the second pull-down transistor is larger than the channel width-to-length ratio of the first pull-down transistor, and the channel width-to-length ratio of the fourth pull-down transistor is larger than the channel width-to-length ratio of the third pull-down transistor. Optionally, the channel width-to-length ratio of the second pull-down transistor to the channel width-to-length ratio of the transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24; a channel width-to-length ratio of the fourth pull-down transistor to the channel width-to-length ratio of the transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24. Optionally, the frame reset circuit includes a first frame reset transistor and a second frame reset transistor; one gate electrode of the first frame reset transistor is electrically connected to the frame reset line, one first electrode of the first frame reset transistor is electrically connected to the first node, and one second electrode of the first frame reset transistor is electrically connected to the control node; one gate electrode of the second frame reset transistor is electrically connected to the frame reset line, one first electrode of the second frame reset transistor is electrically connected to the control node, and one second electrode of the second frame reset transistor is electrically connected to the second voltage line. Optionally, the drive circuit according to at least one embodiment of the present disclosure further comprises a transmission signal output circuit, a drive signal output circuit and an energy storage circuit; wherein the transmission signal output circuit is electrically connected to the first node, the second node, a transmission signal output terminal, a clock signal terminal and a second voltage line and serves to connect or disconnect the transmission signal output terminal to the clock signal terminal under control of the electrical potential of the first node and to connect or disconnect the transmission signal output terminal to the second voltage line under control of the electrical potential of the second node;The drive signal output circuit is electrically connected to the first node, the second node, a drive signal output terminal, the clock signal terminal, and a fourth voltage line, and serves to connect or disconnect the drive signal output terminal from the clock signal terminal under control of the electrical potential of the first node, and to connect or disconnect the drive signal output terminal from the fourth voltage line under control of the electrical potential of the second node; the energy storage circuit is electrically connected to the first node and the drive signal output terminal and serves to store electrical energy. Optionally, the fourth voltage line is used to provide a fourth voltage signal, and the second voltage line is used to provide a second voltage signal; a voltage value of the fourth voltage signal is equal to a voltage value of the second voltage signal, or the voltage value of the second voltage signal is less than the voltage value of the fourth voltage signal. Optionally, the drive circuit according to at least one embodiment of the present disclosure further comprises a second node control circuit; wherein the second node control circuit is electrically connected to the input control terminal, the first node, the second node and a second voltage line and serves to connect or disconnect the second node from the second voltage line under control of the input control signal provided by the input control terminal and to control the electrical potential of the second node under control of the electrical potential of the first node. In a second aspect, an embodiment of the present disclosure provides a display substrate comprising a base and the aforementioned drive circuitry arranged on the base. Optionally, the display substrate according to at least one embodiment of the present disclosure further comprises an electrostatic protection circuit arranged on the base; wherein a first terminal of the electrostatic protection circuit is electrically connected to a drive signal line, a second terminal of the electrostatic protection circuit is electrically connected to a common electrode voltage terminal via a short-circuit bridge, and the electrostatic protection circuit is used for electrostatic protection; the drive signal line comprises a DC voltage line, a clock signal line, a control voltage line, and a frame reset line. Optionally, the electrostatic protection circuit includes a first protection transistor, a second protection transistor, and a third protection transistor; both a gate electrode and a first electrode of the first protection transistor are electrically connected to the drive signal line, and a second electrode of the first protection transistor is electrically connected to a gate electrode of the second protection transistor; a first electrode of the second protection transistor is electrically connected to the gate electrode of the first protection transistor, and a second electrode of the second protection transistor is electrically connected to a gate electrode of the third protection transistor;both the gate electrode of the third protection transistor and a first electrode of the third protection transistor are electrically connected to the short-circuit bridge, and a second electrode of the third protection transistor is electrically connected to the gate electrode of the second protection transistor; the channel width-to-length ratio of the first protection transistor is greater than the channel width-to-length ratio of the second protection transistor, and the channel width-to-length ratio of the third protection transistor is greater than the channel width-to-length ratio of the second protection transistor. Optionally, the electrostatic protection circuit includes a first protection transistor, a second protection transistor, a third protection transistor, a fourth protection transistor, and a fifth protection transistor; both a gate electrode and a first electrode of the first protection transistor are electrically connected to the drive signal line, and a second electrode of the first protection transistor is electrically connected to a gate electrode of the second protection transistor; a first electrode of the second protection transistor is electrically connected to the gate electrode of the first protection transistor, and a second electrode of the second protection transistor is electrically connected to a gate electrode of the third protection transistor;a first electrode of the third protection transistor is electrically connected to the gate electrode of the second protection transistor, and a second electrode of the third protection transistor is electrically connected to a gate electrode of the fourth protection transistor; a first electrode of the fourth protection transistor is electrically connected to the gate electrode of the third protection transistor, and a second electrode of the fourth protection transistor is electrically connected to a gate electrode of the fifth protection transistor; both the gate electrode of the fifth protection transistor and a first electrode of the fifth protection transistor are electrically connected to the short-circuit bridge, and a second electrode of the fifth protection transistor is electrically connected to the gate electrode of the fourth protection transistor;the channel width-to-length ratio of the first protection transistor is greater than the channel width-to-length ratio of the second protection transistor, and the channel width-to-length ratio of the first protection transistor is greater than the channel width-to-length ratio of the fourth protection transistor; the channel width-to-length ratio of the third protection transistor is greater than the channel width-to-length ratio of the second protection transistor, and the channel width-to-length ratio of the third protection transistor is greater than the channel width-to-length ratio of the fourth protection transistor. In a third aspect, an embodiment of the present disclosure provides a display device comprising the above-mentioned display substrate. BRIEF DESCRIPTION OF THE FIGURES Fig. 1 is a structural diagram of a drive circuit according to at least one embodiment of the present disclosure; Fig. 2 is a structural diagram of a drive circuit according to at least one embodiment of the present disclosure; Fig. 3 is a structural diagram of a drive circuit according to at least one embodiment of the present disclosure; Fig. 4 is a structural diagram of a drive circuit according to at least one embodiment of the present disclosure; Fig. 5 is a circuit diagram of a drive circuit according to at least one embodiment of the present disclosure; Fig. 6 is a waveform diagram of the electrical potential of the first node PU when at least one embodiment of the drive circuit shown in Fig. 5 operates in the touch-sensing phase SC; Fig. 7 is a simulation waveform diagram of the electrical potential of the first node PU when at least one embodiment of the drive circuit shown in Fig. 6 operates in the touch-sensing phase SC.Fig. 5 is shown operating in a normal display state; Fig. 8 is a simulation waveform diagram of the electrical potential of the first node PU when at least one embodiment of the drive circuit shown in Fig. 5 is operating in the touch control phase; Fig. 9 is a timing diagram of the operation of at least one embodiment of the drive circuit shown in Fig. 5; Fig. 10 is a layout diagram of at least one embodiment of the drive circuit shown in Fig. 5; Fig. 11 is a layout diagram of the gate metal layer in Fig. 10; Fig. 12 is a layout diagram of the semiconductor layer in Fig. 10; Fig. 13 is a layout diagram of the conductive layer in Fig. 10; Fig. 14 is a layout diagram of the source-drain metal layer in Fig. 10; Fig. 15 is a circuit diagram of a drive circuit according to at least one embodiment of the present disclosure; Fig.Figure 16 is a circuit diagram of a drive circuit according to at least one embodiment of the present disclosure; Figure 17 is a circuit diagram of a drive circuit according to at least one embodiment of the present disclosure; Figure 18 is a circuit diagram of at least one embodiment of an electrostatic protection circuit; Figure 19 is a layout diagram of at least one embodiment of an electrostatic protection circuit; Figure 20 is a circuit diagram of at least one embodiment of an electrostatic protection circuit; Figure 21 is a layout diagram of at least one embodiment of an electrostatic protection circuit. DETAILED DESCRIPTION OF THE REVELATION The following section clearly and comprehensively describes technical solutions in embodiments of the present disclosure with reference to the drawings of those embodiments. It is understood that the described embodiments represent only a part and not all embodiments of the present disclosure. Based on the embodiments of the present disclosure, a person skilled in the art can, without creative effort, derive other embodiments that also fall within the scope of the present disclosure. The transistors used in all embodiments of the present disclosure can be thin-film transistors, field-effect transistors, or other devices with the same properties. In the embodiments of the present disclosure, to distinguish between two electrodes of the transistor other than the gate electrode, one of the two electrodes is designated as the first electrode and the other as the second electrode. In practice, the first electrode can be a drain electrode and the second electrode a source electrode if the transistor is a thin-film transistor or a field-effect transistor; or the first electrode can be a source electrode and the second electrode a drain electrode. As shown in Fig. 1, the drive circuit according to the embodiment of the present disclosure comprises an input circuit 11, a reset circuit 12, a first node reset circuit 13 and a control node control circuit 31; wherein the input circuit 11 is electrically connected to an input control terminal IK1, an input terminal I1 and a first node PU and serves to connect or disconnect the input terminal I1 from the first node PU under the control of an input control signal provided by the input control terminal IK1; the reset circuit 12 is electrically connected to a reset terminal R1, the first node PU and a first voltage line V1 and serves to connect or disconnect the first node PU from the first voltage line V1 under the control of a reset signal provided by the reset terminal R1;The first node reset circuit 13 is electrically connected to a second node PD, the first node PU, and the first voltage line V1, and serves to connect or disconnect the first node PU from the first voltage line V1 under control of the electrical potential of the second node PD; the control node control circuit 31 is electrically connected to the first node PU, a third voltage line V3, and a control node N0, and serves to connect or disconnect the control node N0 from the third voltage line V3 under control of the electrical potential of the first node PU; transistors contained in the input circuit 11, transistors contained in the reset circuit 12, and transistors contained in the first node reset circuit 13 are arranged sequentially along a direction away from the display area;a ratio of the channel width-to-length ratio of a transistor included in the first node reset circuit, whose gate electrode is electrically connected to the second node, to the channel width-to-length ratio of a transistor included in the control node control circuit, is greater than or equal to 6 and less than or equal to 24. Optionally, the first voltage line can be a first low-voltage line or a second low-voltage line, but the present disclosure is not limited to this. In a specific embodiment, the drive circuit according to the present disclosure can comprise an input circuit 11, a reset circuit 12, and a first node reset circuit 13. The input circuit 11 controls the input terminal I1 such that it is connected to or disconnected from the first node PU under the control of an input control signal. The reset circuit 12 controls the first node PU such that it is connected to or disconnected from the first voltage line V1 under the control of a reset signal. The first node reset circuit 13 controls the first node PU such that it is connected to or disconnected from the first voltage line V1 under the control of the electrical potential of the second node PD.The transistors contained in the input circuit 11, the transistors contained in the reset circuit 12, and the transistors contained in the first node reset circuit 13 can be arranged sequentially along a direction away from the display area in order to arrange the transistors contained in the circuits sensibly and to make good use of the lateral space of the bezel of the display substrate. Optionally, the third voltage line can be a high-voltage line. The drive circuit according to at least one embodiment of the present disclosure is provided with a control node control circuit 31. When the electrical potential of the first node PU is high, the electrical potential of the control node N0 is charged to a high voltage. At this time, the leakage current path of the first node PU runs from PU to N0 in order to effectively prevent leakage current at the first node PU and improve the drive capability of the display product. In a specific embodiment, by adjusting the ratio of the channel width-to-length ratio of the transistor contained in the first node reset circuit, whose gate electrode is electrically connected to the second node, and the channel width-to-length ratio of the transistor contained in the control node control circuit, it is possible to prevent the noise of the control node from leaking into the first node, thereby improving the stability of the drive circuit and preventing multiple outputs. Optionally, the channel width-to-length ratio of the transistor contained in the control node control circuit can be 5 / 12, the channel width-to-length ratio of the transistor contained in the first node reset circuit, whose gate electrode is electrically connected to the second node, can be 30 / 6, and the ratio between the channel width-to-length ratio of the transistor contained in the control node control circuit and the channel width-to-length ratio of the transistor contained in the first node reset circuit, whose gate electrode is electrically connected to the second node, can be 1:12, but the present disclosure is not limited thereto. In at least one embodiment of the present disclosure, the input circuit can be electrically connected to the input control terminal IK1 and the input terminal I1 and serves to connect or disconnect the input terminal I1 from the first node PU under the control of the input control signal provided by the input control terminal IK1. In a specific embodiment, the input control terminal IK1 and the input terminal I1 can be different signal terminals connected to different signals; or the input control terminal IK1 and the input terminal I1 can also be the same signal terminal receiving the same signal. In at least one embodiment of the present disclosure, the input circuit comprises at least two input transistors connected in series, and the reset circuit comprises at least two reset transistors connected in series. In a specific embodiment, the input circuit may comprise at least two transistors connected in series whose gate electrodes are electrically connected to the input control terminal, and the reset circuit may comprise at least two transistors connected in series whose gate electrodes are electrically connected to the reset terminal in order to replace the transistor whose first electrode or second electrode is electrically connected to the first node with at least two transistors connected in series in order to reduce the leakage current at the first node and improve the stability of the drive circuit. In at least one embodiment of the present disclosure, the first node reset circuit comprises at least two transistors connected in series, the gate electrodes of which are electrically connected to the second node; or the second node comprises a first second node and a second second node; the first node reset circuit comprises two transistors connected in series, the gate electrodes of which are electrically connected to the first second node, and at least two transistors connected in series, the gate electrodes of which are electrically connected to the second second node. In a specific embodiment, if the drive circuit uses a second node, the first node reset circuit may comprise at least two transistors whose gate electrodes are electrically connected to the second node; if the drive circuit uses two second nodes, the first node reset circuit may comprise two transistors connected in series whose gate electrodes are electrically connected to the first second node, and at least two transistors connected in series whose gate electrodes are electrically connected to the second second node. In at least one embodiment of the present disclosure, the transistor whose first electrode or second electrode is electrically connected to the first node is replaced by at least two transistors connected in series in order to reduce the leakage current at the first node and to improve the stability of the drive circuit. As shown in Fig. 2, the drive circuit according to at least one embodiment of the present disclosure, based on the embodiment of the drive circuit shown in Fig. 1, further comprises a frame reset circuit 21; the frame reset circuit 21 is electrically connected to the frame reset line STV0, the first node PU and the second voltage line V2 and serves to connect or disconnect the first node PU from the second voltage line V2 under the control of the frame reset signal provided by the frame reset line STV0; the transistor contained in the frame reset circuit 21 is arranged on a side of the transistor contained in the first node reset circuit 13 that is remote from the display area. Optionally, the second voltage line can be a second low-voltage line, but the present disclosure is not limited to this. In a specific embodiment, the drive circuit according to at least one embodiment of the present disclosure may further comprise a frame reset circuit 21. The frame reset circuit 21 controls the resetting of the electrical potential of the first node PU under the control of a frame reset signal during an idle period between two frames of the display time; the transistor contained in the frame reset circuit 21 is arranged on a side of the transistor contained in the first node reset circuit 13 that is remote from the display area, in order to arrange the transistors contained in the circuits efficiently and to make good use of the lateral space of the bezel of the display substrate. Optionally, the frame reset circuit includes at least two frame reset transistors connected in series. In at least one embodiment of the present disclosure, the frame reset circuit can comprise at least two transistors connected in series, the gate electrodes of which are electrically connected to the frame reset line. In at least one embodiment of the present disclosure, the transistor whose first electrode or whose second electrode is electrically connected to the first node is replaced by at least two transistors connected in series in order to reduce the leakage current at the first node and to improve the stability of the drive circuit. In at least one embodiment of the present disclosure, the transistor contained in the control node control circuit is arranged on a side of the transistor contained in the input circuit that is close to the display area. In a specific embodiment, the transistor contained in the control node control circuit can be located on a side of the transistor contained in the input circuit that is close to the display area, in order to arrange the transistors contained in each circuit in a sensible manner and to make good use of the lateral space of the bezel of the display substrate. Optionally, the control node control circuit includes a control transistor; one gate electrode of the control transistor is electrically connected to the first node, one first electrode of the control transistor is electrically connected to the third voltage line, and one second electrode of the control transistor is electrically connected to the control node. The drive circuit according to at least one embodiment of the present disclosure further comprises a shutdown-reset circuit; the shutdown-reset circuit is electrically connected to a fourth voltage line and a drive signal output terminal and serves to connect or disconnect the drive signal output terminal from the fourth voltage line under the control of a fourth voltage signal provided by the fourth voltage line. Optionally, the fourth voltage line can be a first low-voltage line. In a specific embodiment, the drive circuit may further include a shutdown-reset circuit, and the shutdown-reset circuit controls the drive signal output terminal to be connected to or disconnected from the fourth voltage line under the control of the fourth voltage signal. As shown in Fig. 3, the drive circuit according to at least one embodiment of the present disclosure, based on at least one embodiment of the drive circuit shown in Fig. 2, further comprises a shutdown-reset circuit 41; the shutdown-reset circuit 41 is electrically connected to the fourth voltage line V4 and the drive signal output terminal GT and serves to connect or disconnect the drive signal output terminal GT from the fourth voltage line V4 under the control of the fourth voltage signal provided by the fourth voltage line V4. In at least one embodiment of the present disclosure, in a case where the transistor included in the power-off reset circuit 41 is an n-type transistor, when the display is showing normally, the fourth voltage line V4 supplies a low-voltage signal, and when the display is ready to power off, the electrical potential of the voltage signal supplied by the fourth voltage line V4 is set to high. Under control of the fourth voltage signal, the power-off reset circuit 41 controls the drive signal output terminal GT so that it is connected to the fourth voltage line V4, such that the drive signal output terminal GT outputs a high-voltage signal that can release residual charges in the pixels and can effectively improve the power-on capability of the drive signal output terminal GT to avoid a poor afterimage. In the prior art, when the display is switched off, the electrical potential of the voltage signal provided by each DC line is raised to a high level, and the fourth voltage line, V4, passes the high-voltage signal via the output reset transistor in the drive circuit to the AA area (effective display area) to complete pixel discharge. However, due to the reliability of the display product, the drift output power of the output reset transistor decreases, leading to insufficient gate turn-on capability, incomplete release of pixel charges, and the formation of residual images.In view of this, in at least one embodiment of the present disclosure, the shutdown reset circuit 41, under the control of the fourth voltage signal, controls the drive signal output terminal GT to output a high voltage signal during shutdown in order to discharge the residual charges in the pixels, which can effectively improve the turn-on capability of the drive signal output terminal GT and avoid a poor residual image. In at least one embodiment of the present disclosure, a transistor included in the shutdown reset circuit is arranged on a side of the transistor included in the input circuit that is close to the display area. In a specific embodiment, a transistor included in the shutdown reset circuit is arranged on a side of the transistor included in the input circuit that is close to the display area, in order to arrange the transistors included in the circuits in a sensible manner and to make good use of the lateral space of the bezel of the display substrate. Optionally, the shutdown reset circuit includes a shutdown reset transistor; a gate electrode of the shutdown reset transistor and a first electrode of the shutdown reset transistor are electrically connected to the fourth voltage line, and a second electrode of the shutdown reset transistor is electrically connected to the drive signal output terminal. Optionally, the input circuit includes a first input transistor and a second input transistor; a gate electrode of the first input transistor is electrically connected to the input control terminal, a first electrode of the first input transistor is electrically connected to the input terminal, and a second electrode of the first input transistor is electrically connected to the control node; a gate electrode of the second input transistor is electrically connected to the input control terminal, a first electrode of the second input transistor is electrically connected to the control node, and a second electrode of the second input transistor is electrically connected to the first node. In at least one embodiment of the present disclosure, the input control terminal is a transmission signal output terminal of a previous stage of the drive circuit, and the input terminal is a drive signal output terminal of the previous stage of the drive circuit; or both the input control terminal and the input terminal are the transmission signal output terminal of the previous stage of the drive circuit. In a specific embodiment, the input control terminal can be the transmission signal output terminal of the previous stage of the drive circuit, and the input terminal can be the drive signal output terminal of the previous stage of the drive circuit; or both the input control terminal and the input terminal can be the transmission signal output terminal of the previous stage of the drive circuit. Optionally, the reset circuit includes a first reset transistor and a second reset transistor; a gate electrode of the first reset transistor is electrically connected to the reset terminal, a first electrode of the first reset transistor is electrically connected to the first node, and a second electrode of the first reset transistor is electrically connected to the control node; a gate electrode of the second reset transistor is electrically connected to the reset terminal, a first electrode of the second reset transistor is electrically connected to the control node, and a second electrode of the second reset transistor is electrically connected to the first voltage line. In at least one embodiment of the present disclosure, the channel width-to-length ratio of a transistor included in the control node control circuit is smaller than the channel width-to-length ratio of the second reset transistor. In a specific implementation, the channel width-to-length ratio of the transistor contained in the control node control circuit and the channel width-to-length ratio of the second reset transistor can be adjusted so that, upon arrival of the reset signal provided by the reset end, the competitiveness of the second reset transistor is improved to quickly lower the electrical potential of the control node and the electrical potential of the first node to a low voltage and to ensure that the electrical potential of the second node can be synchronously raised to a high voltage to start the noise suppression. For example, the channel width-to-length ratio of the transistor included in the control node control circuit may be 5 / 12 and the channel width-to-length ratio of the second reset transistor may be 5 / 6, but the present disclosure is not limited thereto. Optionally, the first node reset circuit includes a first pull-down transistor and a second pull-down transistor; a gate electrode of the first pull-down transistor is electrically connected to the second node, a first electrode of the first pull-down transistor is electrically connected to the first node, and a second electrode of the first pull-down transistor is electrically connected to the control node; a gate electrode of the second pull-down transistor is electrically connected to the second node, a first electrode of the second pull-down transistor is electrically connected to the control node, and a second electrode of the second pull-down transistor is electrically connected to the first voltage line. In at least one embodiment of the present disclosure, the ratio of the channel width-to-length ratio of the second pull-down transistor to the channel width-to-length ratio of a transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24. In a specific implementation, the channel width-to-length ratio of the second pull-down transistor can be adjusted to the channel width-to-length ratio of the transistor included in the control node control circuit to prevent the noise of the control node from being introduced into the first node through leakage, thereby improving the stability of the drive circuit and preventing multiple outputs. Optionally, the channel width-to-length ratio of the transistor included in the control node control circuit can be 5 / 12, the channel width-to-length ratio of the second pull-down transistor can be 30 / 6, and the ratio of the channel width-to-length ratio of the transistor included in the control node control circuit to the channel width-to-length ratio of the second pull-down transistor can be 1:12, but the present disclosure is not limited thereto. Optionally, the channel width-to-length ratio of the second pull-down transistor is larger than the channel width-to-length ratio of the first pull-down transistor. In a specific implementation, the channel width-to-length ratio of the second pull-down transistor can be larger than the channel width-to-length ratio of the first pull-down transistor. By adjusting the channel width-to-length ratio of the first pull-down transistor and the channel width-to-length ratio of the second pull-down transistor, it is possible to prevent noise from the control node from leaking into the first node, thereby improving the stability of the drive circuit and preventing multiple outputs. For example, the channel width-to-length ratio of the first pull-down transistor may be 15 / 6 and the channel width-to-length ratio of the second pull-down transistor may be 30 / 6, but the present disclosure is not limited thereto. Optionally, the second node comprises a first second node and a second second node; wherein the first node reset circuit comprises a first pull-down transistor, a second pull-down transistor, a third pull-down transistor, and a fourth pull-down transistor; a gate electrode of the first pull-down transistor is electrically connected to the first second node, a first electrode of the first pull-down transistor is electrically connected to the first node, and a second electrode of the first pull-down transistor is electrically connected to the control node; a gate electrode of the second pull-down transistor is electrically connected to the first second node, a first electrode of the second pull-down transistor is electrically connected to the control node, and a second electrode of the second pull-down transistor is electrically connected to the first voltage line;a gate electrode of the third pull-down transistor is electrically connected to the second second node, a first electrode of the third pull-down transistor is electrically connected to the first node, and a second electrode of the third pull-down transistor is electrically connected to the control node; a gate electrode of the fourth pull-down transistor is electrically connected to the second second node, a first electrode of the fourth pull-down transistor is electrically connected to the control node, and a second electrode of the fourth pull-down transistor is electrically connected to the first voltage line. In at least one embodiment of the present disclosure, the channel width-to-length ratio of the second pull-down transistor is larger than the channel width-to-length ratio of the first pull-down transistor, and the channel width-to-length ratio of the fourth pull-down transistor is larger than the channel width-to-length ratio of the third pull-down transistor. In at least one embodiment of the present disclosure, the channel width-to-length ratio of the second pull-down transistor is larger than the channel width-to-length ratio of the first pull-down transistor, and the channel width-to-length ratio of the fourth pull-down transistor is larger than the channel width-to-length ratio of the third pull-down transistor. In a specific implementation, the channel width-to-length ratio of the second pull-down transistor can be larger than the channel width-to-length ratio of the first pull-down transistor, and the channel width-to-length ratio of the fourth pull-down transistor can be larger than the channel width-to-length ratio of the third pull-down transistor. This setting prevents noise from the control node from leaking into the first node, thereby improving the stability of the drive circuit and preventing multiple outputs. For example, the channel width-to-length ratio of the first pull-down transistor and the channel width-to-length ratio of the third pull-down transistor may be 15 / 6, and the channel width-to-length ratio of the second pull-down transistor and the channel width-to-length ratio of the fourth pull-down transistor may be 30 / 6, but the present disclosure is not limited thereto. Optionally, the channel width-to-length ratio of the second pull-down transistor to the channel width-to-length ratio of a transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24; a channel width-to-length ratio of the fourth pull-down transistor to the channel width-to-length ratio of the control transistor is greater than or equal to 6 and less than or equal to 24. In a specific embodiment, the channel width-to-length ratio of the second pull-down transistor can be adjusted to the channel width-to-length ratio of the transistor included in the control node control circuit, and the channel width-to-length ratio of the fourth pull-down transistor can be adjusted to the channel width-to-length ratio of the transistor included in the control node control circuit to prevent the noise of the control node from leaking into the first node, thereby improving the stability of the drive circuit and preventing multiple outputs. Optionally, the channel width-to-length ratio of the transistor included in the control node control circuit can be 5 / 12, the channel width-to-length ratio of the second pull-down transistor and the channel width-to-length ratio of the fourth pull-down transistor can be 30 / 6, the ratio of the channel width-to-length ratio of the transistor included in the control node control circuit to the channel width-to-length ratio of the second pull-down transistor can be 1:12, and the ratio of the channel width-to-length ratio of the transistor included in the control node control circuit to the channel width-to-length ratio of the fourth pull-down transistor can be 1:12, but the present disclosure is not limited thereto. Optionally, the frame reset circuit includes a first frame reset transistor and a second frame reset transistor; one gate electrode of the first frame reset transistor is electrically connected to the frame reset line, one first electrode of the first frame reset transistor is electrically connected to the first node, and one second electrode of the first frame reset transistor is electrically connected to the control node; one gate electrode of the second frame reset transistor is electrically connected to the frame reset line, one first electrode of the second frame reset transistor is electrically connected to the control node, and one second electrode of the second frame reset transistor is electrically connected to the second voltage line. In at least one embodiment of the present disclosure, a frame reset circuit electrically connected to the first node can be configured to include a first frame reset transistor and a second frame reset transistor connected in series to reduce leakage currents at the first node. The drive circuit according to at least one embodiment of the present disclosure further comprises a transmission signal output circuit, a drive signal output circuit and an energy storage circuit; wherein the transmission signal output circuit is electrically connected to the first node, the second node, a transmission signal output terminal, a clock signal terminal and a second voltage line and serves to connect or disconnect the transmission signal output terminal to the clock signal terminal under control of the electrical potential of the first node and to connect or disconnect the transmission signal output terminal to the second voltage line under control of the electrical potential of the second node;The drive signal output circuit is electrically connected to the first node, the second node, a drive signal output terminal, the clock signal terminal, and a fourth voltage line, and serves to connect or disconnect the drive signal output terminal from the clock signal terminal under control of the electrical potential of the first node, and to connect or disconnect the drive signal output terminal from the fourth voltage line under control of the electrical potential of the second node; the energy storage circuit is electrically connected to the first node and the drive signal output terminal and serves to store electrical energy. Optionally, the second voltage line can be a second low-voltage line and the fourth voltage line a first low-voltage line. In at least one embodiment of the present disclosure, the fourth voltage line is used to provide a fourth voltage signal, and the second voltage line is used to provide a second voltage signal; a voltage value of the fourth voltage signal is equal to a voltage value of the second voltage signal, or the voltage value of the second voltage signal is less than the voltage value of the fourth voltage signal. In a specific embodiment, the drive circuit may further comprise a transmission signal output circuit and a drive signal output circuit.The transmission signal output circuit controls the drive signal output terminal so that it is connected to or disconnected from the clock signal terminal under the control of the electrical potential of the first node, and controls the drive signal output terminal so that it is connected to or disconnected from the third voltage line under the control of the electrical potential of the second node; the drive signal output circuit controls the drive signal output terminal so that it is connected to or disconnected from the clock signal terminal under the control of the electrical potential of the first node, and controls the drive signal output terminal so that it is connected to or disconnected from the third voltage line under the control of the electrical potential of the second node. In a specific embodiment, the voltage value of the second voltage signal can be lower than the voltage value of the fourth voltage signal. If the input control terminal is the transmission signal output terminal of the previous stage of the drive circuit, and the input terminal is the drive signal output terminal of the previous stage of the drive circuit, the gate-source voltage of the transistor used for the input is less than 0 V, the operating state of the transistor used for the input changes from the subthreshold region to the off state, and the leakage current is reduced as the electrical potential of the first node increases in two steps. The drive circuit according to at least one embodiment of the present disclosure further comprises a second node control circuit; wherein the second node control circuit is electrically connected to the input control terminal, the first node, the second node and a second voltage line and serves to connect or disconnect the second node from the second voltage line under control of the input control signal provided by the input control terminal and to control the electrical potential of the second node under control of the electrical potential of the first node. In a specific embodiment, the drive circuit can include a second node control circuit, wherein the second node control circuit connects or disconnects the second node to the fourth voltage line under the control of an input control signal and controls the electrical potential of the second node under the control of the electrical potential of the first node. As shown in Fig. 4, the drive circuit according to at least one embodiment of the present disclosure, based on at least one embodiment of the drive circuit shown in Fig. 3, comprises a first second node PD1, a second second node PD2, a second node control circuit 43, an energy storage circuit 40, a transmission signal output circuit 44, and a drive signal output circuit 45; wherein the first node reset circuit 13 is electrically connected to the first second node PD1, the second second node PD2, the first node PU, and the first voltage line V1, and serves to connect the first node PU to the first voltage line V1 under control of the electrical potential of the first second node PD1 and to connect the first node PU to the first voltage line V1 under control of the electrical potential of the second second node PD2;The second node control circuit 43 is electrically connected to the input control terminal IK1, the first node PU, the first second node PD1, the second second node PD2, and the second voltage line V2, and serves to connect the first second node PD1 to the second voltage line V2 and the second second node PD2 to the second voltage line V2 under the control of the input control signal provided by the input control terminal IK1, and to control the electrical potential of the first second node PD1 and the electrical potential of the second second node PD2 under the control of the electrical potential of the first node PU; a first terminal of the energy storage circuit 40 is electrically connected to the first node PU, a second terminal of the energy storage circuit 40 is electrically connected to the drive signal output terminal GT, and the energy storage circuit 40 serves to store electrical energy;the transmission signal output circuit 44 is electrically connected to the first node PU, the first second node PD1, the second second node PD2, the transmission signal output terminal OC, the clock signal terminal CLK and the second voltage line V2 and serves to connect the transmission signal output terminal OC to the clock signal terminal CLK under control of the electrical potential of the first node PU, to control the transmission signal output terminal OC so that it is connected to the second voltage line V2 under control of the electrical potential of the first second node PD1, and to control the transmission signal output terminal OC so that it is connected to the second voltage line V2 under control of the electrical potential of the second second node PD2;The propulsion signal output circuit 45 is electrically connected to the first node PU, the first second node PD1, the second second node PD2, the propulsion signal output terminal GT, the clock signal terminal CLK and the fourth voltage line V4 and serves to control the propulsion signal output terminal GT so that it is connected to the clock signal terminal CLK under control of the electrical potential of the first node PU, to control the propulsion signal output terminal GT so that it is connected to the fourth voltage line V4 under control of the electrical potential of the first second node PD1, and to control the propulsion signal output terminal GT so that it is connected to the fourth voltage line V4 under control of the electrical potential of the second second node PD2. As shown in Fig. 5, the shutdown-reset circuit based on at least one embodiment of the drive circuit shown in Fig. 4 comprises a shutdown-reset transistor M14; the gate electrode and the source electrode of the shutdown-reset transistor M14 are electrically connected to the first low-voltage line VGL, and the drain electrode of the shutdown-reset transistor M14 is electrically connected to the drive signal output terminal GT; the control node circuit comprises a control transistor M0; the gate electrode of the control transistor M0 is electrically connected to the first node PU, the source electrode of the control transistor M0 is electrically connected to the high-voltage line VGH, and the drain electrode of the control transistor M0 is electrically connected to the control node N0; the input circuit comprises a first input transistor M1A and a second input transistor M1B;The gate electrode of the first input transistor M1A is electrically connected to the input control terminal IK1, the source electrode of the first input transistor M1A is electrically connected to the input terminal I0, and the drain electrode of the first input transistor M1A is electrically connected to the control node N0; the gate electrode of the second input transistor M1B is electrically connected to the input control terminal IK1, the source electrode of the second input transistor M1B is electrically connected to the control node N0, and the drain electrode of the second input transistor M1B is electrically connected to the first node PU; the reset circuit comprises a first reset transistor M2A and a second reset transistor M2B;The gate electrode of the first reset transistor M2A is electrically connected to the reset terminal R1, the source electrode of the first reset transistor M2A is electrically connected to the first node PU, and the drain electrode of the first reset transistor M2A is electrically connected to the control node N0; the gate electrode of the second reset transistor M2B is electrically connected to the reset terminal R1, the source electrode of the second reset transistor M2B is electrically connected to the control node N0, and the drain electrode of the second reset transistor M2B is electrically connected to the first low-voltage line VGL; the first node reset circuit comprises a first pull-down transistor M8A, a second pull-down transistor M8C, a third pull-down transistor M8B, and a fourth pull-down transistor M8D;The gate electrode of the first pull-down transistor M8A is electrically connected to the first second node PD1, the source electrode of the first pull-down transistor M8A is electrically connected to the first node PU, and the drain electrode of the first pull-down transistor M8A is electrically connected to the control node N0; the gate electrode of the second pull-down transistor M8C is electrically connected to the first second node PD1, the source electrode of the second pull-down transistor M8C is electrically connected to the control node N0, and the drain electrode of the second pull-down transistor M8C is electrically connected to the first low-voltage line VGL;The gate electrode of the third pull-down transistor M8B is electrically connected to the second node PD2, the source electrode of the third pull-down transistor M8B is electrically connected to the first node PU, and the drain electrode of the third pull-down transistor M8B is electrically connected to the control node N0; the gate electrode of the fourth pull-down transistor M8D is electrically connected to the second node PD2, the source electrode of the fourth pull-down transistor M8D is electrically connected to the control node N0, and the drain electrode of the fourth pull-down transistor M8D is electrically connected to the first low-voltage line VGL; the frame reset circuit comprises a first frame reset transistor M15A and a second frame reset transistor M15B;The gate electrode of the first frame reset transistor M15A is electrically connected to the frame reset line STV0, the source electrode of the first frame reset transistor M15A is electrically connected to the first node PU, and the drain electrode of the first frame reset transistor M15A is electrically connected to the control node N0; the gate electrode of the second frame reset transistor M15B is electrically connected to the frame reset line STV0, the source electrode of the second frame reset transistor M15B is electrically connected to the control node N0, and the drain electrode of the second frame reset transistor M15B is electrically connected to the second low-voltage line LVGL; the second node control circuit comprises a first control transistor M5A, a second control transistor M6A, a third control transistor M16A, a fourth control transistor M5B, a fifth control transistor M6B, and a sixth control transistor M16B;Both the gate electrode and the source electrode of the first control transistor M5A are electrically connected to the first control voltage line VDDO, and the drain electrode of the first control transistor M5A is electrically connected to the first second node PD1; the gate electrode of the second control transistor M6A is electrically connected to the first node PU, the source electrode of the second control transistor M6A is electrically connected to the first second node PD1, and the drain electrode of the second control transistor M6A is electrically connected to the second low voltage line LVGL;The gate electrode of the third control transistor M16A is electrically connected to the input control terminal IK1, the source electrode of the third control transistor M16A is electrically connected to the first second node PD1, and the drain electrode of the third control transistor M16A is electrically connected to the second low-voltage line LVGL; both the gate electrode of the fourth control transistor M5B and the source electrode of the second control transistor M5B are electrically connected to the second control voltage line VDDE, and the drain electrode of the second control transistor M5B is electrically connected to the second second node PD2;The gate electrode of the fifth control transistor M6B is electrically connected to the first node PU, the source electrode of the fifth control transistor M6B is electrically connected to the second node PD2, and the drain electrode of the fifth control transistor M6B is electrically connected to the second low-voltage line LVGL; the gate electrode of the sixth control transistor M16B is electrically connected to the input control terminal IK1, the source electrode of the sixth control transistor M16B is electrically connected to the second node PD2, and the drain electrode of the sixth control transistor M16B is electrically connected to the second low-voltage line LVGL; the energy storage circuit includes a storage capacitor C0; the first pole plate of C0 is electrically connected to the first node PU, and the second pole plate of C0 is electrically connected to the drive signal output terminal GT;The transmission signal output circuit comprises a transmission output transistor M11, a first transmission reset transistor M12A, and a second transmission reset transistor M12B; and the drive signal output circuit comprises a drive output transistor M3, a first drive reset transistor M13A, a second drive reset transistor M13B, and an output reset transistor M4; the gate electrode of the transmission output transistor M11 is electrically connected to the first node PU, the source electrode of the transmission output transistor M11 is electrically connected to the clock signal terminal CLK, and the drain electrode of the transmission output transistor M11 is electrically connected to the transmission signal output terminal OC;The gate electrode of the first transmission reset transistor M12A is electrically connected to the first second node PD1, the source electrode of the first transmission reset transistor M12A is electrically connected to the transmission signal output terminal OC, and the drain electrode of the first transmission reset transistor M12A is electrically connected to the second low-voltage line LVGL; the gate electrode of the second transmission reset transistor M12B is electrically connected to the second second node PD2, the source electrode of the second transmission reset transistor M12B is electrically connected to the transmission signal output terminal OC, and the drain electrode of the second transmission reset transistor M12B is electrically connected to the second low-voltage line LVGL;The gate electrode of the drive output transistor M3 is electrically connected to the first node PU, the source electrode of the drive output transistor M3 is electrically connected to the clock signal terminal CLK, and the drain electrode of the drive output transistor M3 is electrically connected to the drive signal output terminal GT; the gate electrode of the first drive reset transistor M13A is electrically connected to the first second node PD1, the source electrode of the first drive reset transistor M13A is electrically connected to the drive signal output terminal GT, and the drain electrode of the first drive reset transistor M13A is electrically connected to the first low-voltage line VGL;The gate electrode of the second drive reset transistor M13B is electrically connected to the second node PD2, the source electrode of the second drive reset transistor M13B is electrically connected to the drive signal output terminal GT, and the drain electrode of the second drive reset transistor M13B is electrically connected to the first low-voltage line VGL; the gate electrode of the output reset transistor M4 is electrically connected to the reset control signal terminal R0, the source electrode of the output reset transistor M4 is electrically connected to the drive signal output terminal GT, and the drain electrode of the output reset transistor M4 is electrically connected to the first low-voltage line VGL. The input control terminal IK1 is a transmission signal output terminal of the previous stage of the drive circuit, and the input terminal I0 is a drive signal output terminal of the previous stage of the drive circuit. In at least one embodiment of the drive circuit shown in Fig. 5, all transistors are n-type transistors, but the present invention is not limited thereto. In at least one embodiment of the drive circuit shown in Fig. 5, a control transistor M0 is used to control the electrical potential of the control node N0. When the electrical potential of the first node PU is a high voltage, the electrical potential of the control node N0 is charged to a high voltage. At this point, the leakage current path of the first node PU runs from PU to N0, effectively preventing leakage current at the first node PU and improving the driving capability of the display product. The drain electrode of the first input transistor M1A is electrically connected to the control node N0; the source electrode of the second input transistor M1B is electrically connected to the control node N0; the drain electrode of the first reset transistor M2A is electrically connected to the control node N0; the source electrode of the second reset transistor M2B is electrically connected to the control node N0; the drain electrode of the first pull-down transistor M8A is electrically connected to the control node N0; the source electrode of the second pull-down transistor M8C is electrically connected to the control node N0; the drain electrode of the third pull-down transistor M8B is electrically connected to the control node N0; the source electrode of the fourth pull-down transistor M8D is electrically connected to the control node N0; the drain electrode of the first frame reset transistor M15A is electrically connected to the control node N0;The source electrode of the second frame reset transistor M15B is electrically connected to the control node N0; in at least one embodiment of the present disclosure, the transistor whose source electrode or drain electrode is electrically connected to the first node PU is configured as two transistors connected in series to reduce the leakage current at the first node PU. In at least one embodiment of the drive circuit shown in Fig. 5, M0, M2B, M8C, M8D, M15B, M16A, and M16B together form a PU voltage supply unit; when I1 provides a high-voltage signal to charge the first node PU of this stage of the drive circuit, M16A and M16B are switched on. At this time, the electrical potential of PD1 and the electrical potential of PD2 are rapidly pulled down, M8A, M8B, M8C, and M8D are switched off, and simultaneously the electrical potential of PU rises, M0 is switched on, and the electrical potential of N0 is charged to a high voltage. At this point, the leakage current path of PU PU-N0, and the drain-source voltage of M1A, the drain-source voltage of M2A, the drain-source voltage of M8A, the drain-source voltage of M8B, and the drain-source voltage of M15A are greatly reduced so that they are close to or equal to 0 V.This effectively prevents leakage currents at the first node PU and improves the drive capability of the display product. Simultaneously, the channel width-to-length ratio of M0 and the channel width-to-length ratio of M2B are adjusted to improve the competitiveness of M2B when the reset signal arrives. This ensures that the electrical potential of N0 and the voltage of the first node PU are quickly pulled down, guaranteeing that the electrical potential of the pull-down node can be synchronously raised to a high voltage, thus beginning to reduce the noise of the drive signal and the transmission signal. The channel width-to-length ratios of M0, M8C, and M8D are adjusted accordingly.that the ratio of the channel width-to-length ratio of M0 to the channel width-to-length ratio of M8C is 1 / 12 and the ratio of the channel width-to-length ratio of M0 to the channel width-to-length ratio of M8D is 1 / 12; The channel width-to-length ratio of M8A, M8B, M8C, and M8D is adjusted such that the ratio of the channel width-to-length ratio of M8A to the channel width-to-length ratio of M8C is set to 1 / 2, and the ratio of the channel width-to-length ratio of M8B to the channel width-to-length ratio of M8D is set to 1 / 2 to prevent noise from the control node N0 from leaking into the first node PU, thereby improving the stability of the drive circuit and preventing multiple outputs. In at least one embodiment of the drive circuit shown in Fig. 5, the channel width-to-length ratio of M0 can be 5 / 12, the channel width-to-length ratio of M2B can be 5 / 6, the channel width-to-length ratio of M8C can be 30 / 6, the channel width-to-length ratio of M8D can be 30 / 6, the channel width-to-length ratio of M8A and the channel width-to-length ratio of M8B can be 15 / 6; in at least one embodiment of the circuit shown in Fig.In the drive circuit shown in Figure 5, the drain electrode of the first transfer reset transistor M12A is electrically connected to the second low-voltage line LVGL; the drain electrode of the second transfer reset transistor M12B is electrically connected to the second low-voltage line LVGL; the drain electrode of the first drive reset transistor M13A is electrically connected to the first low-voltage line VGL; the drain electrode of the second drive reset transistor M13B is electrically connected to the first low-voltage line VGL; the first low-voltage line VGL is used to provide a first low-voltage signal, and the second low-voltage line LVGL is used to provide a second low-voltage signal; the voltage value of the second low-voltage signal can be lower than the voltage value of the first low-voltage signal.If the input control terminal is the transmission signal output terminal of the previous stage of the drive circuit and the input terminal is the drive signal output terminal of the previous stage of the drive circuit, the gate-source voltage of M1A and the voltage of M1B are less than 0 V, the operating state of M1A and the operating state of M1B change from the subthreshold range to the off state, and the leakage current is reduced when the electrical potential of the first node PU increases in two steps. In at least one embodiment of the drive circuit shown in Fig. 5, the drain electrode of M2B is electrically connected to the first low-voltage line VGL, the voltage value of the second low-voltage signal provided by the second low-voltage line is lower than the voltage value of the first low-voltage signal provided by the first low-voltage line, and the gate-source voltage of M2B, the gate-source voltage of M8C, and the gate-source voltage of M8D are all less than 0 V. At this point, the operating state of M2B, the operating state of M8C, and the operating state of M8D change from the sub-threshold region to the off state, and the leakage current is greatly reduced. As shown in Fig. 6, if at least one embodiment of the drive circuit shown in Fig. 5 operates in the touch scanning phase SC, the electrical potential of the first node PU can be kept at a high voltage, since the leakage current at the first node PU is low. In at least one embodiment of the drive circuit shown in Fig. 5, the first low-voltage line VGL supplies a low-voltage signal by adjusting M14 when the display is showing normally; when the display is ready to turn off, the electrical potential of the voltage signal supplied by the first low-voltage line LVGL is set to high, M14 is switched on, and the drive signal output terminal GT is controlled to output a high-voltage signal, thereby releasing residual charges in the pixels and effectively improving the turn-on capability of the drive signal output terminal GT to avoid a poor afterimage. Fig. 7 is a simulation waveform diagram of the electrical potential of the first node PU when at least one embodiment of the drive circuit shown in Fig. 5 is operating in a normal display state. Fig. 8 is a simulation waveform diagram of the electrical potential of the first node PU when at least one embodiment of the drive circuit shown in Fig. 5 is operating in the touch control phase; at this time the highest potential of PU can be around 16.95 V. Fig. 9 is an operating time diagram of at least one embodiment of the drive circuit shown in Fig. 5. In at least one embodiment of the drive circuit shown in Fig. 5, the channel width-to-length ratio of M14 can be selected according to the actual conditions. The channel width-to-length ratio of M14 is normally close to the channel width-to-length ratio of M4, thus ensuring that the electrical potential of the drive signal provided by GT can be raised sufficiently and quickly to a high level when the display is ready to be switched off. When at least one embodiment of the drive circuit shown in Fig. 5 of the present disclosure is in operation, the first control voltage provided by VDDO and the second control voltage provided by VDDE can be square wave signals, and the first control voltage and the second control voltage are phase-shifted, so that PD1 and PD2 operate alternately. Fig. 10 is a layout diagram of at least one embodiment of the drive circuit shown in Fig. 5, wherein the drive circuit is arranged on a base. Fig. 11 is a layout diagram of the gate metal layer in Fig. 10, Fig. 12 is a layout diagram of the semiconductor layer in Fig. 10, Fig. 13 is a layout diagram of the conductive layer in Fig. 10, and Fig. 14 is a layout diagram of the source-drain metal layer in Fig. 10. As shown in Fig. 10, the part designated CLKA is the first clock signal line, the part designated CLKB is the second clock signal line, the part designated CLKC is the third clock signal line, the part designated CLKD is the fourth clock signal line, the part designated STV is the start voltage line, the part designated VDDO is the first control voltage line, the part designated VDDE is the second control voltage line, the part designated STV0 is the frame reset line, the part designated LVGL is the second low voltage line, the part designated VGL1 is the first low voltage line, the part designated VGL2 is the second low voltage line, and the part designated VGH is the high voltage line; CLKA, CLKB, CLKC, CLKD, STV, VDDO, VDDE, STV0, LVGL, and VGL1 run in a vertical direction;CLKA, CLKB, CLKC, CLKD, STV, VDDO, VDDE, STV0, LVGL and VGL1 are arranged on a side of the drive circuit furthest from the display area; VGL2 and VGH run vertically; VGL2 and VGH are arranged on a side of the drive circuit close to the display area. As shown in Figs. 10, 11, 12, 13 to 14, the transistors in the input circuit, the transistors in the reset circuit, and the transistors in the first node reset circuit are arranged sequentially along a direction away from the display area; M14 is located on a side of M0 away from the display area, and M0 is located on a side of M1A and M1B away from the display area; the orthographic projection of the active pattern of M11 on the base, the orthographic projection of the first pole plate of C0 on the base, and the orthographic projection of the active pattern of M1A on the base are arranged sequentially in a vertical direction;The orthographic projection of the active pattern of M11 on the base, the orthographic projection of the first pole plate of C0 on the base, and the orthographic projection of the active pattern of M1B on the base are arranged vertically in succession to utilize a longitudinal space for the arrangement of M11, C0, M1A, and M1B, thus facilitating the realization of a narrow bezel; M1A and M1B are arranged side by side, M1A and M1B are arranged horizontally, and M1B is located on a side of M1A far from the display area; M14 and M4 are arranged vertically in succession to utilize the longitudinal space for the arrangement of M14 and M4, contributing to the realization of a narrow bezel; M3 and M0 are arranged vertically in succession to utilize the longitudinal space for the arrangement of M3 and M0, contributing to the realization of a narrow bezel; M3 is positioned between M14 and M11;M2A and M2B are arranged side by side, and M2B and M2A are arranged horizontally; M8D, M8B, and M7A are arranged vertically one behind the other, and M8D, M8B, and M7B are arranged vertically one behind the other to utilize the longitudinal space for the arrangement of M8D, M8B, M7A, and M7B, which contributes to achieving a narrow bezel; M8C and M8A are arranged vertically one after the other to utilize the longitudinal space for the arrangement of M8C and M8A, which contributes to achieving a narrow bezel; M8D and M8C are arranged side by side, M8B and M8A are arranged side by side, M8C and M8D are arranged horizontally, M8A and M8B are arranged horizontally, M8D is located on a side of M8C far from the display area, and M8B is located on a side of M8A far from the display area;M12B, M13B, M13A, and M12A are arranged vertically in a row to utilize the longitudinal space for the arrangement of M12B, M13B, M13A, and M12A, contributing to a narrow bezel; M13B is located on the side of M8D furthest from the display area; M6B, M15A, and M16A are arranged vertically in a row, and M6B, M15B, and M16A are arranged vertically in a row to utilize the longitudinal space for the arrangement of M6B, M15A, M15B, and M16A; M15A and M15B are arranged horizontally side by side; M6B is located on the side of M12B furthest from the display area; M5B and M5A are arranged vertically in a row; M5A is located on the side of M6A furthest from the display area. In Fig. 11, the part designated CLKA1 is a first clock signal line section contained in CLKA, the part designated CLKB1 is a first clock signal line section contained in CLKB, the part designated CLKC1 is a first clock signal line section contained in CLKC, and the part designated CLKD1 is a first clock signal line section contained in CLKD. In Fig. 12, the part designated A8D is an active pattern of M8D, the part designated A8C is an active pattern of M8C, the part designated A8B is an active pattern of M8B, and the part designated A8A is an active pattern of M8A. In Fig. 14, the part designated CLKA2 is a second clock signal line section contained in CLKA, the part designated CLKB2 is a second clock signal line section contained in CLKB, the part designated CLKC2 is a second clock signal line section contained in CLKC, and the part designated CLKD2 is a second clock signal line section contained in CLKD; CLKA2 can be electrically connected to CLKA1, CLKB2 can be electrically connected to CLKB1, CLKC2 can be electrically connected to CLKC1 and CLKD2 can be electrically connected to CLKD1. At least one embodiment of the drive circuit shown in Fig. 15 differs from at least one embodiment of the drive circuit shown in Fig. 5 in that: M0 and the control node N0 are not provided; the drain electrode of the first input transistor M1A is electrically connected to the source electrode of the second input transistor M1B; the drain electrode of the first reset transistor M2A is electrically connected to the source electrode of the second reset transistor M2B; the drain electrode of the first pull-down transistor M8A is electrically connected to the source electrode of the second pull-down transistor M8C; the drain electrode of the third pull-down transistor M8B is electrically connected to the source electrode of the fourth pull-down transistor M8D; the drain electrode of the first frame reset transistor M15A is electrically connected to the source electrode of the second frame reset transistor M15B. At least one embodiment of the drive circuit shown in Fig. 16 differs from at least one embodiment of the drive circuit shown in Fig. 15 in that: the gate electrode of M1A and the gate electrode of M1B are both electrically connected to I1; the drain electrode of M2B is electrically connected to the second low-voltage line LVGL, the drain electrode of M8C is electrically connected to the second low-voltage line LVGL, and the drain electrode of M8D is electrically connected to the second low-voltage line LVGL. At least one embodiment of the drive circuit shown in Fig. 17 differs from at least one embodiment of the drive circuit shown in Fig. 16 in that: the input circuit comprises an input transistor M1; the gate electrode of the input transistor M1 and the source electrode of the input transistor M1 are both electrically connected to the input terminal I0, and the drain electrode of the input transistor M1 is electrically connected to the first node PU; the reset circuit comprises a reset transistor M2; the gate electrode of the reset transistor M2 is electrically connected to the reset terminal R1, the source electrode of the reset transistor M2 is electrically connected to the first node PU, and the drain electrode of the reset transistor M2 is electrically connected to the first low-voltage line VGL; the first node reset circuit comprises a first pull-down transistor M8A and a third pull-down transistor M8B;the gate electrode of the first pull-down transistor M8A is electrically connected to the first second node PD1, the source electrode of the first pull-down transistor M8A is electrically connected to the first node PU, and the drain electrode of the first pull-down transistor M8A is electrically connected to the second low-voltage line LVGL; the gate electrode of the third pull-down transistor M8B is electrically connected to the second second node PD2, the source electrode of the third pull-down transistor M8B is electrically connected to the first node PU, and the drain electrode of the third pull-down transistor M8B is electrically connected to the second low-voltage line LVGL; the frame reset circuit includes a frame reset transistor M15;the gate electrode of the frame reset transistor M15 is electrically connected to the frame reset line STV0, the source electrode of the frame reset transistor M15 is electrically connected to the first node PU, and the drain electrode of the frame reset transistor M15 is electrically connected to the second low voltage line LVGL. The display substrate according to one embodiment of the present disclosure comprises a base and the aforementioned drive circuit arranged on the base. The display substrate according to at least one embodiment of the present disclosure further comprises an electrostatic protection circuit arranged on the base; wherein a first terminal of the electrostatic protection circuit is electrically connected to a drive signal line, a second terminal of the electrostatic protection circuit is electrically connected to a common electrode voltage terminal via a short-circuit bridge, and the electrostatic protection circuit is used for electrostatic protection; the drive signal line comprises a DC voltage line, a clock signal line, a control voltage line, and a frame reset line. In at least one embodiment of the present disclosure, the drive signal line is a metal conductor that runs through the entire display field and is located at the edge of the display field. The drive signal line is extremely susceptible to damage from high voltages when external static electricity is present. Therefore, an electrostatic protection circuit is arranged between the signal line and the short-circuit bridge to distribute the momentary high voltage and prevent the drive signal line from burning out. At least one embodiment of the present disclosure provides a specific structure for an electrostatic protection circuit that employs a design with a mixed arrangement of large and small thin-film transistors (TFTs). Based on ensuring electrostatic discharge performance, it can reduce the current between the signal lines and decrease crosstalk. Simultaneously, the footprint is smaller due to the small size of the TFTs. Optionally, the electrostatic protection circuit includes a first protection transistor, a second protection transistor, and a third protection transistor; both a gate electrode and a first electrode of the first protection transistor are electrically connected to the drive signal line, and a second electrode of the first protection transistor is electrically connected to a gate electrode of the second protection transistor; a first electrode of the second protection transistor is electrically connected to the gate electrode of the first protection transistor, and a second electrode of the second protection transistor is electrically connected to a gate electrode of the third protection transistor;both the gate electrode of the third protection transistor and a first electrode of the third protection transistor are electrically connected to the short-circuit bridge, and a second electrode of the third protection transistor is electrically connected to the gate electrode of the second protection transistor; the channel width-to-length ratio of the first protection transistor is greater than the channel width-to-length ratio of the second protection transistor, and the channel width-to-length ratio of the third protection transistor is greater than the channel width-to-length ratio of the second protection transistor. For example, the channel width-to-length ratio of the first protection transistor and the channel width-to-length ratio of the third protection transistor may be 3.5 / 8, and the channel width-to-length ratio of the second protection transistor may be 3.5 / 50, but the present disclosure is not limited thereto. In a specific embodiment, the channel width-to-length ratio of the first protection transistor and the channel width-to-length ratio of the third protection transistor may be greater than or equal to 3.5 / 12 and less than or equal to 3.5 / 6, and the channel width-to-length ratio of the second protection transistor may be greater than or equal to 3.5 / 80 and less than or equal to 3.5 / 30, but the present disclosure is not limited thereto. Optionally, the electrostatic protection circuit includes a first protection transistor, a second protection transistor, a third protection transistor, a fourth protection transistor, and a fifth protection transistor; both a gate electrode and a first electrode of the first protection transistor are electrically connected to the drive signal line, and a second electrode of the first protection transistor is electrically connected to a gate electrode of the second protection transistor; a first electrode of the second protection transistor is electrically connected to the gate electrode of the first protection transistor, and a second electrode of the second protection transistor is electrically connected to a gate electrode of the third protection transistor;a first electrode of the third protection transistor is electrically connected to the gate electrode of the second protection transistor, and a second electrode of the third protection transistor is electrically connected to a gate electrode of the fourth protection transistor; a first electrode of the fourth protection transistor is electrically connected to the gate electrode of the third protection transistor, and a second electrode of the fourth protection transistor is electrically connected to a gate electrode of the fifth protection transistor; both the gate electrode of the fifth protection transistor and a first electrode of the fifth protection transistor are electrically connected to the short-circuit bridge, and a second electrode of the fifth protection transistor is electrically connected to the gate electrode of the fourth protection transistor;the channel width-to-length ratio of the first protection transistor is greater than the channel width-to-length ratio of the second protection transistor, and the channel width-to-length ratio of the first protection transistor is greater than the channel width-to-length ratio of the fourth protection transistor; the channel width-to-length ratio of the third protection transistor is greater than the channel width-to-length ratio of the second protection transistor, and the channel width-to-length ratio of the third protection transistor is greater than the channel width-to-length ratio of the fourth protection transistor. For example, the channel width-to-length ratio of the first protection transistor, the channel width-to-length ratio of the third protection transistor, and the channel width-to-length ratio of the fifth protection transistor may be 3.5 / 8, and the channel width-to-length ratio of the second protection transistor and the channel width-to-length ratio of the fourth protection transistor may be 3.5 / 50, but the present disclosure is not limited thereto. In a specific embodiment, the channel width-to-length ratio of the first protection transistor, the channel width-to-length ratio of the third protection transistor, and the channel width-to-length ratio of the fifth protection transistor may be greater than or equal to 3.5 / 12 and less than or equal to 3.5 / 6, and the channel width-to-length ratio of the second protection transistor and the channel width-to-length ratio of the fourth protection transistor may be greater than or equal to 3.5 / 80 and less than or equal to 3.5 / 30, but the present disclosure is not limited thereto. As shown in Fig. 18, at least one embodiment of the electrostatic protection circuit can comprise a first protection transistor T1, a second protection transistor T2, a third protection transistor T3, a fourth protection transistor T4, and a fifth protection transistor T5; both the gate electrode and the source electrode of the first protection transistor T1 are electrically connected to the drive signal line QX, and the drain electrode of the first protection transistor T1 is electrically connected to the gate electrode of the second protection transistor T2; the source electrode of the second protection transistor T2 is electrically connected to the gate electrode of the first protection transistor T1, and the drain electrode of the second protection transistor T2 is electrically connected to the gate electrode of the third protection transistor T3;The source electrode of the third protection transistor T3 is electrically connected to the gate electrode of the second protection transistor T2, and the drain electrode of the third protection transistor T3 is electrically connected to the gate electrode of the fourth protection transistor T4; the source electrode of the fourth protection transistor T4 is electrically connected to the gate electrode of the third protection transistor T3, and the drain electrode of the fourth protection transistor T4 is electrically connected to the gate electrode of the fifth protection transistor T5; both the gate electrode and the source electrode of the fifth protection transistor T5 are electrically connected to the short-circuit bridge SR, the drain electrode of the fifth protection transistor T5 is electrically connected to the gate electrode of the fourth protection transistor T4; the gate electrode of T5 is electrically connected to the common electrode voltage terminal CM;The channel width-to-length ratio of the first protection transistor T1 is greater than the channel width-to-length ratio of the second protection transistor T2, and the channel width-to-length ratio of the first protection transistor T1 is greater than the channel width-to-length ratio of the fourth protection transistor T4; the channel width-to-length ratio of the third protection transistor T3 is greater than the channel width-to-length ratio of the second protection transistor T2, and the channel width-to-length ratio of the third protection transistor T3 is greater than the channel width-to-length ratio of the fourth protection transistor T4; the channel width-to-length ratio of the fifth protection transistor T5 is greater than the channel width-to-length ratio of the second protection transistor T2, and the channel width-to-length ratio of the fifth protection transistor T5 is greater than the channel width-to-length ratio of the second protection transistor T2. of the fourth protection transistor T4.; In at least one embodiment shown in Fig. 18, the channel width-to-length ratio of the first protection transistor, the channel width-to-length ratio of the third protection transistor, and the channel width-to-length ratio of the fifth protection transistor can be greater than or equal to 3.5 / 12 and less than or equal to 3.5 / 6, and the channel width-to-length ratio of the second protection transistor and the channel width-to-length ratio of the fourth protection transistor can be greater than or equal to 3.5 / 80 and less than or equal to 3.5 / 30. Fig. 19 is a layout diagram of at least one embodiment of an electrostatic protection circuit. In Fig. 19, the part labeled CLKA is a first clock signal line, the part labeled CLKB a second clock signal line, the part labeled CLKC a third clock signal line, and the part labeled CLKD a fourth clock signal line; the part labeled STV is a start voltage line, the part labeled VDDO is a first control voltage line, the part labeled VDDE is a second control voltage line, the part labeled STV0 is a frame reset line, the part labeled LVGL is a second low voltage line, and the part labeled VGL is a first low voltage line. The part labeled SR is a short-circuit bridge.The part designated E1 is the first electrostatic protection circuit, the part designated E2 is the second electrostatic protection circuit, the part designated E3 is the third electrostatic protection circuit, the part designated E4 is the fourth electrostatic protection circuit, the part designated E5 is the fifth electrostatic protection circuit, the part designated E6 is the sixth electrostatic protection circuit, the part designated E7 is the seventh electrostatic protection circuit, the part designated E8 is the eighth electrostatic protection circuit, the part designated E9 is the ninth electrostatic protection circuit, and the part designated E10 is the tenth electrostatic protection circuit. In Fig. 19, the first protection transistor in E5 is labelled T1, the second protection transistor in E5 is labelled T2, the third protection transistor in E5 is labelled T3, the fourth protection transistor in E5 is labelled T4, and the fifth protection transistor in E5 is labelled T5. As shown in Fig. 19, M2 and M4 are arranged next to each other in a horizontal direction, and M1, M3 and M5 are arranged next to each other in a horizontal direction. In Fig. 19, the part labelled CM is a common electrode voltage terminal. As shown in Fig. 20, at least one embodiment of the electrostatic protection circuit may comprise a first protection transistor T1 and a second protection transistor T2; the gate electrode of T1 and the source electrode of T1 are both electrically connected to the drive signal line QX, and the drain electrode of T1 is electrically connected to the gate electrode of T2; the source electrode of T2 is electrically connected to the gate electrode of T1, and the gate electrode of T1 is electrically connected to the common electrode voltage terminal CM. The channel width-to-length ratio of T1 and the channel width-to-length ratio of T2 can be 3.5 / 180. Fig. 21 is a layout diagram of at least one embodiment of an electrostatic protection circuit. In Fig. 21, the part designated CLKA is a first clock signal line, the part designated CLKB is a second clock signal line, the part designated CLKC is a third clock signal line, and the part designated CLKD is a fourth clock signal line; the part designated STV is a start voltage line, the part designated VDDO is a first control voltage line, the part designated VDDE is a second control voltage line, the part designated STV0 is a frame reset line, the part designated LVGL is a second low voltage line, and the part designated VGL is a first low voltage line. The part designated SR is a short-circuit bridge.The part designated E1 is the first electrostatic protection circuit, the part designated E2 is the second electrostatic protection circuit, the part designated E3 is the third electrostatic protection circuit, the part designated E4 is the fourth electrostatic protection circuit, the part designated E5 is the fifth electrostatic protection circuit, the part designated E6 is the sixth electrostatic protection circuit, the part designated E7 is the seventh electrostatic protection circuit, the part designated E8 is the eighth electrostatic protection circuit, the part designated E9 is the ninth electrostatic protection circuit, and the part designated E10 is the tenth electrostatic protection circuit. In Fig. 21, the first protection transistor in E5 is labelled T1, and the second protection transistor in E5 is labelled T2; in Fig. 21, the part labelled CM is a common electrode voltage terminal. The display device according to one embodiment of the present disclosure comprises the above-mentioned display substrate. The above descriptions merely describe optional embodiments of the present disclosure. It is understood that modifications and improvements can be made by a person skilled in the art without deviating from the principle of the present disclosure, and these modifications and improvements fall within the scope of the present disclosure.

Claims

A drive circuit comprising an input circuit, a reset circuit, a first node reset circuit, and a control node control circuit; wherein the input circuit is electrically connected to an input control terminal, an input terminal, and a first node and serves to control the input terminal, under the control of an input control signal provided by the input control terminal, to be connected to or disconnected from the first node; the reset circuit is electrically connected to a reset terminal, the first node, and a first voltage line and serves to control the first node, under the control of a reset signal provided by the reset terminal, to be connected to or disconnected from the first voltage line;The first node reset circuit is electrically connected to a second node, the first node, and the first voltage line, and serves to control the first node, under the control of an electrical potential of the second node, to be connected to or disconnected from the first voltage line; the control node control circuit is electrically connected to the first node, a third voltage line, and a control node, and serves to control the control node, under the control of an electrical potential of the first node, to be connected to or disconnected from the third voltage line; a transistor included in the input circuit, a transistor included in the reset circuit, and a transistor included in the first node reset circuit are arranged sequentially along a direction away from a display area;a ratio of a channel width-to-length ratio of a transistor contained in the first node reset circuit, whose gate electrode is electrically connected to the second node, to a channel width-to-length ratio of a transistor contained in the control node control circuit is greater than or equal to 6 and less than or equal to 24. Drive circuit according to claim 1, further comprising a frame reset circuit; wherein the frame reset circuit is electrically connected to a frame reset line, the first node and a second voltage line and serves to control the first node, under the control of a frame reset signal provided by the frame reset line, to be connected to or disconnected from the second voltage line; a transistor contained in the frame reset circuit is arranged on a side of the transistor contained in the first node reset circuit that is remote from the display area. Driving circuit according to claim 1, wherein the input circuit comprises at least two input transistors connected in series, and the reset circuit comprises at least two reset transistors connected in series. Driving circuit according to claim 1, wherein the first node reset circuit comprises at least two transistors connected in series, the gate electrodes of which are electrically connected to the second node; or the second node comprises a first second node and a second second node; the first node reset circuit comprises at least two transistors connected in series, the gate electrodes of which are electrically connected to the first second node, and at least two transistors connected in series, the gate electrodes of which are electrically connected to the second second node. Drive circuit according to claim 2, wherein the frame reset circuit comprises at least two frame reset transistors connected in series. Drive circuit according to claim 1, wherein the transistor contained in the control node control circuit is arranged on a side of the transistor contained in the input circuit that is close to the display area. Drive circuit according to claim 1, wherein the control node control circuit comprises a control transistor; a gate electrode of the control transistor is electrically connected to the first node, a first electrode of the control transistor is electrically connected to the third voltage line, and a second electrode of the control transistor is electrically connected to the control node. Drive circuit according to one of claims 1 to 7, further comprising a shutdown-reset circuit; wherein the shutdown-reset circuit is electrically connected to a fourth voltage line and a drive signal output terminal and serves to control the drive signal output terminal, to be connected to or disconnected from the fourth voltage line under the control of a fourth voltage signal provided by the fourth voltage line. Drive circuit according to claim 8, wherein a transistor included in the shutdown reset circuit is arranged on a side of the transistor included in the input circuit that is close to the display area. Driving circuit according to claim 8, wherein the turn-off reset circuit comprises a turn-off reset transistor; a gate electrode of the turn-off reset transistor and a first electrode of the turn-off reset transistor are electrically connected to the fourth voltage line, and a second electrode of the turn-off reset transistor is electrically connected to the drive signal output terminal. Drive circuit according to one of claims 1 to 7, wherein the input circuit comprises a first input transistor and a second input transistor; a gate electrode of the first input transistor is electrically connected to the input control terminal, a first electrode of the first input transistor is electrically connected to the input terminal, and a second electrode of the first input transistor is electrically connected to the control node; a gate electrode of the second input transistor is electrically connected to the input control terminal, a first electrode of the second input transistor is electrically connected to the control node, and a second electrode of the second input transistor is electrically connected to the first node. Drive circuit according to claim 11, wherein the input control terminal is a transmission signal output terminal of a previous stage of drive circuit, and the input terminal is a drive signal output terminal of the previous stage of drive circuit; or both the input control terminal and the input terminal are the transmission signal output terminal of the previous stage of drive circuit. Drive circuit according to one of claims 1 to 7, wherein the reset circuit comprises a first reset transistor and a second reset transistor; a gate electrode of the first reset transistor is electrically connected to the reset terminal, a first electrode of the first reset transistor is electrically connected to the first node, and a second electrode of the first reset transistor is electrically connected to the control node; a gate electrode of the second reset transistor is electrically connected to the reset terminal, a first electrode of the second reset transistor is electrically connected to the control node, and a second electrode of the second reset transistor is electrically connected to the first voltage line. Drive circuit according to claim 13, wherein a channel width-to-length ratio of a transistor included in the control node control circuit is smaller than a channel width-to-length ratio of the second reset transistor. A drive circuit according to any one of claims 1 to 7, wherein the first node reset circuit comprises a first pull-down transistor and a second pull-down transistor; a gate electrode of the first pull-down transistor is electrically connected to the second node, a first electrode of the first pull-down transistor is electrically connected to the first node, and a second electrode of the first pull-down transistor is electrically connected to the control node; a gate electrode of the second pull-down transistor is electrically connected to the second node, a first electrode of the second pull-down transistor is electrically connected to the control node, and a second electrode of the second pull-down transistor is electrically connected to the first voltage line. Drive circuit according to claim 15, wherein a channel width-to-length ratio of the second pull-down transistor to a channel width-to-length ratio of a transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24. Driving circuit according to claim 15, wherein a channel width-to-length ratio of the second pull-down transistor is greater than a channel width-to-length ratio of the first pull-down transistor. A drive circuit according to any one of claims 1 to 7, wherein the second node comprises a first second node and a second second node; wherein the first node reset circuit comprises a first pull-down transistor, a second pull-down transistor, a third pull-down transistor, and a fourth pull-down transistor; a gate electrode of the first pull-down transistor is electrically connected to the first second node, a first electrode of the first pull-down transistor is electrically connected to the first node, and a second electrode of the first pull-down transistor is electrically connected to the control node; a gate electrode of the second pull-down transistor is electrically connected to the first second node, a first electrode of the second pull-down transistor is electrically connected to the control node, and a second electrode of the second pull-down transistor is electrically connected to the first voltage line;a gate electrode of the third pull-down transistor is electrically connected to the second second node, a first electrode of the third pull-down transistor is electrically connected to the first node, and a second electrode of the third pull-down transistor is electrically connected to the control node; a gate electrode of the fourth pull-down transistor is electrically connected to the second second node, a first electrode of the fourth pull-down transistor is electrically connected to the control node, and a second electrode of the fourth pull-down transistor is electrically connected to the first voltage line. Driving circuit according to claim 18, wherein a channel width-to-length ratio of the second pull-down transistor is greater than a channel width-to-length ratio of the first pull-down transistor, and a channel width-to-length ratio of the fourth pull-down transistor is greater than a channel width-to-length ratio of the third pull-down transistor. Drive circuit according to claim 18, wherein a channel width-to-length ratio of the second pull-down transistor to a channel width-to-length ratio of the transistor contained in the control node control circuit is greater than or equal to 6 and less than or equal to 24; a channel width-to-length ratio of the fourth pull-down transistor to a channel width-to-length ratio of the transistor contained in the control node control circuit is greater than or equal to 6 and less than or equal to 24. Drive circuit according to claim 2, wherein the frame reset circuit comprises a first frame reset transistor and a second frame reset transistor; a gate electrode of the first frame reset transistor is electrically connected to the frame reset line, a first electrode of the first frame reset transistor is electrically connected to the first node, and a second electrode of the first frame reset transistor is electrically connected to the control node; a gate electrode of the second frame reset transistor is electrically connected to the frame reset line, a first electrode of the second frame reset transistor is electrically connected to the control node, and a second electrode of the second frame reset transistor is electrically connected to the second voltage line. Drive circuit according to one of claims 1 to 7, further comprising a transmission signal output circuit, a drive signal output circuit and an energy storage circuit; wherein the transmission signal output circuit is electrically connected to the first node, the second node, a transmission signal output terminal, a clock signal terminal and a second voltage line and serves to control the transmission signal output terminal, under control of the electrical potential of the first node, to be connected to or disconnected from the clock signal terminal, and to control the transmission signal output terminal, under control of the electrical potential of the second node, to be connected to or disconnected from the second voltage line;The drive signal output circuit is electrically connected to the first node, the second node, a drive signal output terminal, the clock signal terminal, and a fourth voltage line, and serves to control the drive signal output terminal, under the control of the electrical potential of the first node, to be connected to or disconnected from the clock signal terminal, and to control the drive signal output terminal, under the control of the electrical potential of the second node, to be connected to or disconnected from the fourth voltage line; the energy storage circuit is electrically connected to the first node and the drive signal output terminal and serves to store electrical energy. Drive circuit according to claim 22, wherein the fourth voltage line serves to provide a fourth voltage signal, and the second voltage line serves to provide a second voltage signal; a voltage value of the fourth voltage signal is equal to a voltage value of the second voltage signal, or the voltage value of the second voltage signal is less than the voltage value of the fourth voltage signal. Drive circuit according to one of claims 1 to 7, further comprising a second node control circuit; wherein the second node control circuit is electrically connected to the input control terminal, the first node, the second node and a second voltage line and serves to control the second node under the control of the input control signal provided by the input control terminal, to be connected to or disconnected from the second voltage line, and to control the electrical potential of the second node under the control of the electrical potential of the first node. Display substrate comprising a base and the drive circuit according to any one of claims 1 to 24, wherein the drive circuit is arranged on the base. Display substrate according to claim 25, further comprising an electrostatic protection circuit arranged on the base; wherein a first terminal of the electrostatic protection circuit is electrically connected to a drive signal line, a second terminal of the electrostatic protection circuit is electrically connected to a common electrode voltage terminal via a short-circuit bridge, and the electrostatic protection circuit is used for electrostatic protection; the drive signal line comprises a DC voltage line, a clock signal line, a control voltage line and a frame reset line. Display substrate according to claim 26, wherein the electrostatic protection circuit comprises a first protection transistor, a second protection transistor and a third protection transistor; both a gate electrode of the first protection transistor and a first electrode of the first protection transistor are electrically connected to the drive signal line, and a second electrode of the first protection transistor is electrically connected to a gate electrode of the second protection transistor; a first electrode of the second protection transistor is electrically connected to the gate electrode of the first protection transistor, and a second electrode of the second protection transistor is electrically connected to a gate electrode of the third protection transistor;both the gate electrode of the third protection transistor and a first electrode of the third protection transistor are electrically connected to the short-circuit bridge, and a second electrode of the third protection transistor is electrically connected to the gate electrode of the second protection transistor; a channel width-to-length ratio of the first protection transistor is greater than a channel width-to-length ratio of the second protection transistor, and a channel width-to-length ratio of the third protection transistor is greater than the channel width-to-length ratio of the second protection transistor. Display substrate according to claim 26, wherein the electrostatic protection circuit comprises a first protection transistor, a second protection transistor, a third protection transistor, a fourth protection transistor and a fifth protection transistor; both a gate electrode of the first protection transistor and a first electrode of the first protection transistor are electrically connected to the drive signal line, and a second electrode of the first protection transistor is electrically connected to a gate electrode of the second protection transistor; a first electrode of the second protection transistor is electrically connected to the gate electrode of the first protection transistor, and a second electrode of the second protection transistor is electrically connected to a gate electrode of the third protection transistor;a first electrode of the third protection transistor is electrically connected to the gate electrode of the second protection transistor, and a second electrode of the third protection transistor is electrically connected to a gate electrode of the fourth protection transistor; a first electrode of the fourth protection transistor is electrically connected to the gate electrode of the third protection transistor, and a second electrode of the fourth protection transistor is electrically connected to a gate electrode of the fifth protection transistor; both the gate electrode of the fifth protection transistor and a first electrode of the fifth protection transistor are electrically connected to the short-circuit bridge, and a second electrode of the fifth protection transistor is electrically connected to the gate electrode of the fourth protection transistor;a channel width-to-length ratio of the first protection transistor is greater than a channel width-to-length ratio of the second protection transistor, and the channel width-to-length ratio of the first protection transistor is greater than a channel width-to-length ratio of the fourth protection transistor; a channel width-to-length ratio of the third protection transistor is greater than the channel width-to-length ratio of the second protection transistor, and the channel width-to-length ratio of the third protection transistor is greater than the channel width-to-length ratio of the fourth protection transistor; a channel width-to-length ratio of the fifth protection transistor is greater than the channel width-to-length ratio of the second protection transistor, and the channel width-to-length ratio of the fifth protection transistor is greater than the channel width-to-length ratio of the fourth protection transistor. Display device comprising the display substrate according to any one of claims 25 to 28.

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