Display substrate and display device

Abstract

A display substrate and a display device are provided. The display substrate comprises a shift register including a first output transistor (OUT1) through a fifth output transistor (OUT5). The first output transistor (OUT1) is electrically connected to a cascade signal output terminal (GP) and a first power supply terminal (V1); the second output transistor (OUT2) is connected to the cascade signal output terminal (GP) and a second power supply terminal (V2); the third output transistor (OUT3) is connected to the fifth output transistor (OUT5) and the first power supply terminal (V1); the fourth output transistor (OUT4) is connected to a driver signal output terminal (OP) and the second power supply terminal (V2); and the fifth output transistor (OUT5) is connected to the driver signal output terminal (OP).A gate electrode (OUT12) of the first output transistor and a gate electrode (OUT32) of the third output transistor form an integrated structure, and a gate electrode (OUT22) of the second output transistor and a gate electrode (OUT42) of the fourth output transistor form an integrated structure.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and particularly to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, the present disclosure provides a display substrate having a display area and a non-display area, the display substrate comprising: a pixel driving circuit located in the display area and a gate driving circuit group located in the non-display area, the gate driving circuit group comprising at least a first driving circuit, the first driving circuit being connected to the pixel driving circuit, the first driving circuit comprising a plurality of cascaded shift registers; the shift registers comprising at least a first output transistor, a second output transistor, a third output transistor, a fourth output transistor, a fifth output transistor, a cascade signal output terminal, a driving signal output terminal, a first power supply terminal, and a second power supply terminal, the driving signal output terminal being electrically connected to the pixel driving circuit;

[0006] The first output transistor is electrically connected to the cascade signal output terminal and the first power supply terminal respectively, the second output transistor is electrically connected to the cascade signal output terminal and the second power supply terminal respectively, the third output transistor is electrically connected to the fifth output transistor and the first power supply terminal respectively, the fourth output transistor is electrically connected to the drive signal output terminal and the second power supply terminal respectively, and the fifth output transistor is electrically connected to the drive signal output terminal;

[0007] The gate electrode of the first output transistor and the gate electrode of the third output transistor are an integrated structure, and the gate electrode of the second output transistor and the gate electrode of the fourth output transistor are an integrated structure.

[0008] In an exemplary embodiment, the shift register further includes: a fifth capacitor;

[0009] The fifth capacitor is connected to the cascade signal output terminal and the second power supply terminal respectively.

[0010] In an exemplary embodiment, the capacitance of the fifth capacitor is less than or equal to 60 farads.

[0011] In an exemplary embodiment, any one of the third output transistor and the fourth output transistor is located on a side of any one of the first output transistor and the second output transistor that is close to the display area, the fifth output transistor is located on a side of any one of the third output transistor and the fourth output transistor that is close to the display area, and the fifth capacitor is located on a side of the second output transistor that is away from the display area.

[0012] The first output transistor and the third output transistor are arranged along a first direction, the second output transistor and the fourth output transistor are arranged along a first direction, the first output transistor and the second output transistor are arranged along a second direction, the third output transistor and the fourth output transistor are arranged along a second direction, and the first direction intersects the second direction.

[0013] In an exemplary embodiment, the transistor includes: an active pattern,

[0014] The length of the active pattern of the first output transistor along the first direction is shorter than the length of the active pattern of the third output transistor along the first direction;

[0015] A channel width of the active pattern of the first output transistor is smaller than a channel width of the active pattern of the third output transistor, and a channel length of the active pattern of the first output transistor is greater than a channel length of the active pattern of the third output transistor.

[0016] In an exemplary embodiment, the transistor includes: an active pattern, a length of the active pattern of the third output transistor along the first direction is greater than a length of the active pattern of the fourth output transistor along the first direction, and a length of the active pattern of the third output transistor along the second direction is less than a length of the active pattern of the fourth output transistor along the second direction.

[0017] In an exemplary embodiment, a channel width of the active pattern of the first output transistor ranges from 80 micrometers to 100 micrometers, and a channel length of the active pattern of the first output transistor ranges from 3.2 micrometers to 3.7 micrometers.

[0018] In an exemplary embodiment, a channel width of the active pattern of the third output transistor ranges from 250 micrometers to 300 micrometers, and a channel length of the active pattern of the third output transistor ranges from 2.9 micrometers to 3.2 micrometers.

[0019] In an exemplary embodiment, a transistor includes: an active pattern;

[0020] A length of the active pattern of the second output transistor along the first direction is shorter than a length of the active pattern of the fourth output transistor along the first direction;

[0021] A channel width of the active pattern of the second output transistor is smaller than a channel width of the active pattern of the fourth output transistor, and a channel length of the active pattern of the second output transistor is greater than a channel length of the active pattern of the fourth output transistor.

[0022] In an exemplary embodiment, a channel width of the active pattern of the second output transistor ranges from 80 micrometers to 100 micrometers, and a channel length of the active pattern of the second output transistor ranges from 3.2 micrometers to 3.7 micrometers.

[0023] In an exemplary embodiment, a channel width of the active pattern of the fourth output transistor ranges from 250 micrometers to 300 micrometers, and a channel length of the active pattern of the fourth output transistor ranges from 2.9 micrometers to 3.2 micrometers.

[0024] In an exemplary embodiment, a length of the active pattern of the fifth output transistor along the second direction is greater than a length of the active pattern of any one of the third output transistor and the fourth output transistor along the second direction;

[0025] A channel width of the active pattern of the fifth output transistor ranges from 250 micrometers to 300 micrometers, and a channel length of the active pattern of the fifth output transistor ranges from 2.9 micrometers to 3.2 micrometers.

[0026] In an exemplary embodiment, the transistor includes a gate electrode, and a length of the gate electrode of the third output transistor along the first direction is greater than a length of the gate electrode of the fourth output transistor along the first direction.

[0027] In an exemplary embodiment, the transistor includes a gate electrode, and a length of the gate electrode of the fifth output transistor along the second direction is greater than a length of a gate electrode of either the first output transistor or the second output transistor along the second direction.

[0028] In an exemplary embodiment, the shift register further includes: a fourth capacitor;

[0029] The fourth capacitor is connected to the fifth output transistor and the first power supply terminal respectively.

[0030] In an exemplary embodiment, the fourth capacitor is located between the second output transistor and the fourth output transistor.

[0031] In an exemplary embodiment, the shift register further includes: a twenty-fourth transistor;

[0032] The twenty-fourth transistor is connected to the fifth output transistor and the second power supply terminal respectively, and a transistor type of the twenty-fourth transistor is opposite to a transistor type of any transistor among the first to fifth output transistors.

[0033] In an exemplary embodiment, the twenty-fourth transistor is located on a side of the fifth output transistor close to the display area, and is arranged along a first direction with the first output transistor and the third output transistor.

[0034] In an exemplary embodiment, the shift register further includes: a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a reverse signal output terminal, and a mask signal terminal;

[0035] The twentieth transistor is respectively connected to the cascade signal output terminal, the fifth output transistor, and the twenty-first transistor; the twenty-first transistor is respectively connected to the reverse signal output terminal and the mask signal terminal of the previous stage shift register; the twenty-second transistor is respectively connected to the cascade signal output terminal, the reverse signal output terminal, and the second power supply terminal; and the twenty-third transistor is respectively connected to the cascade signal output terminal, the reverse signal output terminal, and the first power supply terminal;

[0036] The transistor type of the twenty-second transistor is opposite to the transistor type of any one of the first to third output transistors, the twentieth transistor, the twenty-first transistor, and the twenty-third transistor.

[0037] In an exemplary embodiment, the 20th to 23rd transistors are located on a side of the fifth output transistor close to the display area;

[0038] The 21st transistor and the 20th transistor are arranged along the second direction, and the 20th transistor is located on the side of the 21st transistor close to the 22nd transistor, and the 23rd transistor is located between the 22nd transistor and the fifth output transistor, and is located on the side of the 22nd transistor away from the 21st transistor.

[0039] In an exemplary embodiment, the shift register further includes: first to eighth transistors, eleventh to sixteenth transistors, first to third capacitors, a signal input terminal, a first clock signal terminal, a second clock signal terminal, and a third power supply terminal;

[0040] The first transistor is respectively connected to the signal input terminal, the first clock signal terminal, the second transistor, the eighth transistor, the twelfth transistor and the thirteenth transistor, the second transistor is respectively connected to the first clock signal line, the third transistor, the fifth transistor, the eighth transistor, the eleventh transistor, the twelfth transistor and the thirteenth transistor, the third transistor is respectively connected to the first clock signal terminal, the second power supply terminal, the fifth transistor and the eleventh transistor, the fourth transistor is respectively connected to the second clock signal terminal, the third capacitor, the fifth transistor, the fifteenth transistor and the sixteenth transistor, the fifth transistor is respectively connected to the first power supply terminal, the third capacitor and the eleventh transistor, the sixth transistor is respectively connected to the second clock signal terminal, the first capacitor, the seventh transistor and the eleventh transistor, the seventh transistor is respectively connected to the second clock signal terminal, the first capacitor, the second capacitor, the first output transistor, the third output transistor, and the eighth transistor are connected, the eighth transistor is connected to the first power supply terminal, the second capacitor, the first output transistor, the third output transistor, the twelfth transistor, and the thirteenth transistor, respectively; the eleventh transistor is connected to the second power supply terminal and the first capacitor, respectively; the twelfth transistor is connected to the second power supply terminal, the second output transistor, the fourth output transistor, the thirteenth transistor, and the sixteenth transistor, respectively; the thirteenth transistor is connected to the first power supply terminal and the third power supply terminal, respectively; the thirteenth transistor is connected to the first power supply terminal and the third power supply terminal, respectively; the fourteenth transistor is connected to the signal input terminal, the first clock signal terminal, and the fifteenth transistor, respectively; the fifteenth transistor is connected to the second power supply terminal, the third capacitor, and the sixteenth transistor, respectively; the sixteenth transistor is connected to the second output transistor, the fourth output transistor, and the third capacitor, respectively;

[0041] The capacitance value of the third capacitor is greater than the capacitance value of the second capacitor, and the capacitance value of the second capacitor is greater than the voltage value of the first capacitor;

[0042] The transistor type of any one of the first to eighth transistors and the eleventh to sixteenth transistors is the same as the transistor type of any one of the first to fifth output transistors;

[0043] Any one of the first to eighth transistors, the eleventh to sixteenth transistors, and the first to third capacitors is located on a side of any one of the first output transistor and the second output transistor away from the display area.

[0044] In an exemplary embodiment, the shift register includes: at least one P-type transistor, at least one N-type transistor, and at least one capacitor, wherein the capacitor includes: a first plate and a second plate; the at least one P-type transistor includes: the first output transistor to the fifth output transistor; the gate electrode of the N-type transistor includes: a first gate electrode and a second gate electrode;

[0045] The display substrate comprises: a base and a driving circuit layer provided on the base, the gate driving circuit group and the pixel driving circuit are provided on the driving circuit layer, and the driving circuit layer comprises a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer stacked in sequence;

[0046] The first semiconductor layer includes at least: an active pattern of a P-type transistor;

[0047] The first conductive layer at least includes: a gate electrode of a P-type transistor and a first plate of at least one capacitor;

[0048] The second conductive layer includes at least: a second plate of at least one capacitor and a first gate electrode of an N-type transistor

[0049] The second semiconductor layer includes at least: an active pattern of an N-type transistor;

[0050] The third conductive layer at least includes: a second gate electrode of the N-type transistor;

[0051] The fourth conductive layer at least includes: a first electrode and a second electrode of any one of a P-type transistor and an N-type transistor.

[0052] In an exemplary embodiment, the device further includes: an initial signal line, a first clock signal line, a second clock signal line, a first second power line, a third power line, a second second power line, and a first first power line, wherein the second second power line is connected to the second power terminal connected to the second output transistor, and the first first power line is connected to the first power terminal connected to the first output transistor;

[0053] Any one of the initial signal line, the first clock signal line, the second clock signal line, the first second power line, the third power line, the second second power line and the first first power line at least partially extends along the second direction;

[0054] The orthographic projections of the initial signal line, the first clock signal line, the second clock signal line, the first second power line, the third power line, the second second power line, and the first first power line on the substrate are arranged in sequence in a direction close to the display area, and no overlapping area exists between the orthographic projections of any two of the initial signal line, the first clock signal line, the second clock signal line, the first second power line, the second second power line, and the first first power line on the substrate;

[0055] The orthographic projection of the second clock signal line on the substrate is located on a side of the orthographic projection of any transistor in the shift register on the substrate away from the display area.

[0056] In an exemplary embodiment, the display substrate includes: a base and a driving circuit layer provided on the base, the gate driving circuit group and the pixel driving circuit are provided on the driving circuit layer, and the driving circuit layer includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer stacked in sequence;

[0057] The initial signal line, the first clock signal line, the second clock signal line and the third power line are located in the fourth conductive layer;

[0058] The first second power line, the second second power line, and the first first power line are located in the fifth conductive layer.

[0059] In an exemplary embodiment, an orthographic projection of the second second power line on the substrate at least partially overlaps with an orthographic projection of the third power line on the substrate;

[0060] The line width of the second second power line is greater than the line width of the third power line.

[0061] In an exemplary embodiment, the device further comprises: a third second power line, a fourth second power line, a second first power line, and a masking signal line, wherein the third second power line is connected to the second power terminal connected to the fourth output transistor, and the second first power line is connected to the first power terminal connected to the third output transistor;

[0062] Any one of the third second power line, the fourth second power line, the second first power line and the masking signal line at least partially extends along the second direction;

[0063] The orthographic projections of the third second power line, the second first power line, the masking signal line, and the fourth second power line on the substrate are arranged in sequence in a direction close to the display area, and there is no overlapping area between the orthographic projections of any two of the third second power line, the second first power line, the masking signal line, and the fourth second power line on the substrate.

[0064] In an exemplary embodiment, the display substrate includes: a base and a driving circuit layer provided on the base, the gate driving circuit group and the pixel driving circuit are provided on the driving circuit layer, and the driving circuit layer includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer stacked in sequence;

[0065] The third second power line, the fourth second power line, the second first power line and the masking signal line are located in the fifth conductive layer.

[0066] In an exemplary embodiment, the gate driving circuit group further includes: a second driving circuit, the second driving circuit being electrically connected to the pixel driving circuit, the first driving circuit and the second driving circuit being arranged along the first direction;

[0067] The second driving circuit is electrically connected to the fourth second power line.

[0068] In a second aspect, the present disclosure further provides a display device, comprising: the above-mentioned display substrate.

[0069] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0070] Summary of the Figures

[0071] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0072] FIG1 is a schematic structural diagram of a display device;

[0073] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0074] FIG3 is a second schematic diagram of a planar structure of a display substrate;

[0075] FIG4 is a third schematic diagram of a planar structure of a display substrate;

[0076] FIG5 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0077] FIG6 is a timing diagram of the operation of the pixel driving circuit provided in FIG5 ;

[0078] FIG7 is an equivalent circuit diagram of a shift register;

[0079] FIG8 is a timing diagram of the operation of a portion of a shift register;

[0080] FIG9 is a schematic structural diagram of a display substrate provided in an embodiment of the present disclosure;

[0081] FIG10A is a schematic diagram of a partial film layer of the display substrate provided in FIG9 ;

[0082] FIG10B is a schematic diagram of another portion of the film layer of the display substrate provided in FIG9 ;

[0083] FIG11 is a schematic diagram of a film layer where signal lines of the display substrate provided in FIG9 are located;

[0084] FIG12 is a schematic diagram of FIG9 after the first semiconductor layer pattern is formed;

[0085] FIG13 is a schematic diagram of the first conductive layer pattern in FIG9;

[0086] FIG14 is a schematic diagram of FIG9 after forming a first conductive layer pattern;

[0087] FIG15 is a schematic diagram of the second conductive layer pattern in FIG9 ;

[0088] FIG16 is a schematic diagram of FIG9 after forming a second conductive layer pattern;

[0089] FIG17 is a schematic diagram of a pattern of the second semiconductor layer in FIG9 ;

[0090] FIG18 is a schematic diagram of FIG9 after forming a second semiconductor layer pattern;

[0091] FIG19 is a schematic diagram of a third conductive layer pattern in FIG9 ;

[0092] FIG20 is a schematic diagram of FIG9 after forming a third conductive layer pattern;

[0093] FIG21 is a schematic diagram of FIG9 after forming a fifth insulating layer pattern;

[0094] FIG22 is a schematic diagram of a fourth conductive layer pattern in FIG9 ;

[0095] FIG23 is a schematic diagram of FIG9 after forming a fourth conductive layer pattern;

[0096] FIG24 is a schematic diagram of FIG9 after forming a first planar layer pattern;

[0097] FIG25 is a schematic diagram of the fifth conductive layer pattern in FIG9 ;

[0098] FIG. 26 is a schematic diagram of FIG. 9 after a fifth conductive layer pattern is formed.

[0099] Details

[0100] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design

[0101] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0102] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0103] In this specification, for convenience, terms such as "center," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate positions or positional relationships when describing the positional relationships of components with reference to the accompanying drawings. This is intended solely to facilitate the description of this specification and simplify the description, and is not intended to indicate or imply that the device or element referred to must have a specific position, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of the components may vary depending on the direction in which the components are described. Therefore, the terms are not limited to those described in this specification and may be appropriately replaced as appropriate.

[0104] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0105] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0106] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0107] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0108] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0109] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0110] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0111] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0112] Figure 1 is a schematic diagram of the structure of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a gate driver, and a pixel array. The timing controller is respectively connected to the data driver and the gate driver. The data driver is respectively connected to multiple data signal lines (D1 to Dn). The gate driver is respectively connected to multiple gate signal lines (G1 to Gm). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit. The pixel driving circuit may be respectively connected to the gate signal lines and the data signal lines.

[0113] In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light emitting driver to the light emitting driver. The data driver may use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3, ..., and Dn. For example, the data driver may sample the grayscale values ​​using the clock signal and apply data voltages corresponding to the grayscale values ​​to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number.

[0114] In an exemplary embodiment, the gate driver may generate a scan signal to be provided to the gate signal lines G1, G2, G3, ... to Gm by receiving a clock signal, a gate start signal, etc. from a timing controller. For example, the scan driver may sequentially provide a scan signal having an on-level pulse to the gate signal lines G1 to Gm. For example, the gate driver may be configured in the form of a shift register and may generate the scan signal by sequentially transmitting a scan start signal provided in the form of an on-level pulse to the next stage circuit under the control of a clock signal. m may be a natural number.

[0115] FIG2 is a schematic diagram of a planar structure of a display substrate (I), FIG3 is a schematic diagram of a planar structure of a display substrate (II), and FIG4 is a schematic diagram of a planar structure of a display substrate (III). As shown in FIG2 to FIG4, the display substrate may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P includes a first subpixel P1 that emits a first color light, a second subpixel P2 that emits a second color light, and a third subpixel P3 that emits a third color light. The first subpixel P1, the second subpixel P2, and the third subpixel P3 each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are respectively connected to a gate signal line and a data signal line. The pixel driving circuits are configured to receive a data voltage transmitted by the data signal line under the control of the gate signal line and output a corresponding current to the light-emitting device. The light-emitting devices in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are respectively connected to the pixel driving circuit of the subpixel. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the subpixel.

[0116] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) emitting red light, the second subpixel P2 may be a blue subpixel (B) emitting blue light, and the third subpixel P3 may be a green subpixel (G) emitting green light.

[0117] In an exemplary embodiment, the shape of the sub-pixel may be rectangular, diamond, pentagonal, or hexagonal, and the three sub-pixels may be arranged horizontally, vertically, or in a herringbone pattern, which is not limited in the present disclosure.

[0118] In an exemplary embodiment, a pixel unit may include three sub-pixels, which may be arranged horizontally, vertically, or in a herringbone pattern, etc., without limitation in this disclosure. Figures 2 and 3 illustrate an example of a pixel unit including three sub-pixels. The three sub-pixels in Figure 2 are arranged horizontally, while the three sub-pixels in Figure 3 are arranged in a herringbone pattern.

[0119] In an exemplary embodiment, a pixel unit may include four sub-pixels, which may be arranged horizontally, vertically, or in a square pattern, which is not limited in this disclosure. FIG4 illustrates an example in which a pixel unit includes four sub-pixels, and the four sub-pixels are arranged in a square pattern.

[0120] In the display market, most display substrates utilize low-temperature polysilicon (LTPS) technology, which boasts advantages such as high resolution, high response speed, high brightness, and a high aperture ratio. Despite its popularity, LTPS technology also has drawbacks, such as high production costs and high power consumption. This is where the low-temperature polycrystalline oxide (LTPO) technology solution comes in. Compared to LTPS technology, LTPO offers lower leakage current and faster pixel response. The addition of an oxide layer to the display substrate reduces the energy required to excite the pixels, thereby reducing power consumption during screen display.

[0121] In example embodiments, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure.

[0122] Figure 5 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in Figure 5, the pixel driving circuit in the LTPO display substrate may include 7 transistors (first transistor M1 to seventh transistor M7) and 1 capacitor C. Among them, the gate electrode of the first transistor M1 is electrically connected to the first reset signal line Reset1, the first electrode of the first transistor M1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor M1 is electrically connected to the first node N1 or the third node N3; the gate electrode of the second transistor M2 is electrically connected to the second scan signal line Gate2, the first electrode of the second transistor M2 is electrically connected to the first node N1, and the second electrode of the second transistor M2 is electrically connected to the third node N3; the gate electrode of the third transistor M3 is electrically connected to the first node N1, the first electrode of the third transistor M3 is electrically connected to the second node N2, and the second electrode of the third transistor M3 is electrically connected to the third node N3; the gate electrode of the fourth transistor M4 is electrically connected to the first scan signal line Gate1, and the first electrode of the fourth transistor M4 is electrically connected to the data signal line Data. The second electrode of the fourth transistor M4 is electrically connected to the second node N2; the gate electrode of the fifth transistor M5 is electrically connected to the light emitting signal line EM, the first electrode of the fifth transistor M5 is electrically connected to the high-level power supply line VDD, and the second electrode of the fifth transistor M5 is electrically connected to the second node N2; the gate electrode of the sixth transistor M6 is electrically connected to the light emitting signal line EM, the first electrode of the sixth transistor M6 is electrically connected to the third node N3, and the second electrode of the sixth transistor M6 is electrically connected to the fourth node N4; the gate electrode of the seventh transistor M7 is electrically connected to the second reset signal line Reset2, the first electrode of the seventh transistor M7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor M7 is electrically connected to the fourth node N4; the first plate of the capacitor C is electrically connected to the first node N1, and the second plate of the capacitor C is electrically connected to the high-level power supply line VDD. Figure 5 is explained by taking the second electrode of the first transistor M1 being electrically connected to the first node N1 as an example.

[0123] In an exemplary embodiment, the signal of the second reset signal line Reset2 may be the same as the signal of the first scan signal line Gate1 , or may also be the same as the signal of the first reset signal line Reset1 .

[0124] In an exemplary embodiment, the first transistor M1 to the seventh transistor M7 may be low-temperature polysilicon thin-film transistors, or may be oxide thin-film transistors, or may be low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active pattern of the low-temperature polysilicon thin-film transistor is low-temperature polysilicon (LTPS), and the active pattern of the oxide thin-film transistor is oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate to form an LTPO display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0125] In an exemplary embodiment, the first transistor M1 and the second transistor M2 are of opposite transistor types to the third transistor M3 to the seventh transistor M7. For example, the first transistor M1 and the second transistor M2 may be N-type transistors, and the third transistor M3 to the seventh transistor M7 may be P-type transistors.

[0126] In example embodiments, the first and second transistors M1 and M2 may be oxide transistors, and the third to seventh transistors M3 to M7 may be low-temperature polysilicon transistors.

[0127] In an exemplary embodiment, the voltage value of the signal of the first initial signal line INIT1 is constant and is a DC signal. The voltage value of the signal of the first initial signal line INIT1 may be -3V.

[0128] In an exemplary embodiment, the voltage value of the signal of the second initial signal line INIT2 is constant and is a DC signal. The voltage value of the signal of the second initial signal line INIT2 may be 0V.

[0129] In an exemplary embodiment, the light emitting device L′ may be electrically connected to the fourth node N4 and the low-level power line VSS, respectively.

[0130] In an exemplary embodiment, the high-level power line VDD continuously provides a high-level signal, and the low-level power line VSS continuously provides a low-level signal.

[0131] FIG6 is a timing diagram of the operation of the pixel driving circuit provided in FIG5 . The following illustrates an exemplary embodiment of the present disclosure through the operation process of the pixel driving circuit illustrated in FIG5 during the display phase. FIG6 is illustrated by taking the first transistor M1 and the second transistor M2 as N-type transistors, the third transistor M3 to the seventh transistor M7 as P-type transistors, and the signal of the second reset signal line Reset2 as the same as the signal of the first reset signal line Reset1 as an example. The pixel driving circuit in FIG5 includes the first transistor M1 to the seventh transistor M7, a capacitor C and 9 signal lines (data signal line Data, a first scanning signal line Gate1, a second scanning signal line Gate2, a first reset signal line Reset1, a second reset signal line Reset2, a first initial signal line INIT1, a second initial signal line INIT2, a light-emitting signal line EM and a high-level power line VDD).

[0132] 5 and 6 , the operation process of the pixel driving circuit may include:

[0133] The first stage P1 is called the initialization stage. The signals of the first reset signal line Reset1 and the second reset signal line Reset2 are high-level signals. The first transistor M1 is turned on. The signal of the first initial signal line INIT1 is written into the first node N1 or the third node N3 through the turned-on first transistor M1, and the first node N1 or the third node N3 is initialized (reset), and the pre-stored voltage inside it is cleared to complete the initialization. The seventh transistor M7 is turned on, and the signal of the second initial signal line INIT2 is written into the fourth node N4 through the turned-on seventh transistor M7, and the first electrode of the light-emitting device L is initialized (reset), and the pre-stored voltage inside it is cleared to complete the initialization.

[0134] In the second phase P2, also known as the data writing phase or threshold compensation phase, the signal on the first scan signal line Gate1 is a low-level signal, the signal on the second scan signal line Gate2 is a high-level signal, and the data signal line Data outputs a data voltage. During this phase, since the first node N1 is a low-level signal, the third transistor M3 is turned on. The signal on the first scan signal line Gate1 is a low-level signal, the fourth transistor M4 is turned on, the signal on the second scan signal line Gate2 is a high-level signal, and the second transistor M2 is turned on. The data voltage output by the data signal line Data is provided to the first node N1 via the turned-on fourth transistor M4, the second node N2, the turned-on third transistor M3, the third node N3, and the turned-on second transistor M2. The difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor M3 is charged into the capacitor C until the voltage at the first node N1 reaches Vd-|Vth|, where Vd is the data voltage output by the data signal line Data and Vth is the threshold voltage of the third transistor M3.

[0135] In the third stage P3, referred to as the light-emitting stage, the signal of the light-emitting signal line EM is a low-level signal, the fifth transistor M5 and the sixth transistor M6 are turned on, and the power supply voltage output by the high-level power line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor M5, the third transistor M3, and the sixth transistor M6, thereby driving the light-emitting device L to emit light.

[0136] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between the gate electrode and the first electrode. Since the voltage of the first node N1 is Vd-|Vth|, the driving current of the third transistor M3 is: I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*(Vdd-Vd) 2

[0137] Wherein, I is the driving current flowing through the third transistor M3, that is, the driving current driving the light-emitting device L, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor M3, Vth is the threshold voltage of the third transistor M3, Vd is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the high-level power supply line VDD.

[0138] In an exemplary embodiment, the light-emitting device L may include any one of an organic light-emitting diode (OLED), a quantum dot light-emitting diode, and an inorganic light-emitting diode. For example, the light-emitting device may be a micron-sized light-emitting device, such as a micro light-emitting diode (Micro LED), a sub-millimeter light-emitting diode (Mini LED), or a micro organic light-emitting diode (Micro OLED), etc., and the present disclosure is not limited to this. For example, taking the light-emitting device L as an organic light-emitting diode (OLED) as an example, the light-emitting device may include a stacked first electrode (e.g., serving as an anode), an organic light-emitting layer, and a second electrode (e.g., serving as a cathode).

[0139] In an exemplary embodiment, the organic light-emitting layer may include an emissive layer (EML) and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer of all sub-pixels may be a common layer connected together, and the emissive layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0140] In an exemplary embodiment, the gate signal line may include a first scan signal line, a second scan signal line, a light emitting signal line, a first reset signal line, and a second reset signal line.

[0141] In an exemplary embodiment, the gate driver includes at least one gate driver circuit. The number of gate driver circuits depends on the gate signal lines. Taking the display substrate including the pixel driver circuit shown in FIG. 5 as an example, the gate driver circuit includes a first scan driver circuit, a second scan driver circuit, and a light driver circuit. The first scan driver circuit is electrically connected to the first scan signal line, the first reset signal line, and the second reset signal line. The second scan driver circuit is electrically connected to the second scan signal line. The light driver circuit is electrically connected to the light signal line.

[0142] In an exemplary embodiment, any gate drive circuit in a gate driver may include multiple cascaded shift registers. FIG7 is an equivalent circuit diagram of a shift register. As shown in FIG7 , the shift register may include a shift subcircuit, an inverting output subcircuit, a selection output subcircuit, and a latch subcircuit.

[0143] In an exemplary embodiment, the shift subcircuit may have a circuit structure of 10T3C, 10T4C, 12T3C, 12T4C, 13T3C, 13T4C, 16T3C, or 16T4C, which is not limited in the present disclosure.

[0144] In an exemplary embodiment, as shown in FIG7 , the shift subcircuit may include: a first transistor T1 to a sixteenth transistor T16, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fifth capacitor C5. The gate electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK1, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the gate electrode of the second transistor T2 is electrically connected to the first node N1, the first electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK1, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the gate electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK1, the first electrode of the third transistor T3 is electrically connected to the second power supply terminal V2, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the gate electrode of the fourth transistor T4 is electrically connected to the third node N1. 3, a first electrode of the fourth transistor T4 is electrically connected to the second clock signal terminal CK2, and a second electrode of the fourth transistor T4 is electrically connected to the fourth node N4; a gate electrode of the fifth transistor T5 is electrically connected to the second node N2, a first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal V1, and a second electrode of the fifth transistor T5 is electrically connected to the fourth node N4; a gate electrode of the sixth transistor T6 is electrically connected to the fifth node N5, a first electrode of the sixth transistor T6 is electrically connected to the second clock signal terminal CK2, and a second electrode of the sixth transistor T6 is electrically connected to the sixth node N6; a gate electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CK2, and a first electrode of the seventh transistor T7 is electrically connected to the sixth node N6 is electrically connected, the second electrode of the seventh transistor T7 is electrically connected to the seventh node N7; the gate electrode of the eighth transistor T8 is electrically connected to the first node N1, the first electrode of the eighth transistor T8 is electrically connected to the first power supply terminal V1, and the second electrode of the eighth transistor T8 is electrically connected to the seventh node N7; the gate electrode of the ninth transistor T9 is electrically connected to the seventh node N7, the first electrode of the ninth transistor T9 is electrically connected to the first power supply terminal V1, and the second electrode of the ninth transistor T9 is electrically connected to the cascade signal output terminal GP(n); the gate electrode of the tenth transistor T10 is electrically connected to the eighth node N8, the first electrode of the tenth transistor T10 is electrically connected to the second power supply terminal V2, and the second electrode of the tenth transistor T10 is electrically connected to the cascade signal output terminal GP(n). The output terminal GP(n) is electrically connected; a gate electrode of the eleventh transistor T11 is electrically connected to the second power supply terminal V2, a first electrode of the eleventh transistor T11 is electrically connected to the second node N2, and a second electrode of the eleventh transistor T11 is electrically connected to the fifth node N5; a gate electrode of the twelfth transistor T12 is electrically connected to the second power supply terminal V2, a first electrode of the twelfth transistor T12 is electrically connected to the first node N1, and a second electrode of the twelfth transistor T12 is electrically connected to the eighth node N8; a gate electrode of the thirteenth transistor T13 is electrically connected to the third power supply terminal V3, a first electrode of the thirteenth transistor T13 is electrically connected to the first power supply terminal V1, and a second electrode of the thirteenth transistor T13 is electrically connected to the first node N1;A gate electrode of the fourteenth transistor T14 is electrically connected to the first clock signal terminal CK1, a first electrode of the fourteenth transistor T14 is electrically connected to the signal input terminal IN, and a second electrode of the fourteenth transistor T14 is electrically connected to a first electrode of the fifteenth transistor T15; a gate electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal V2, and a second electrode of the fifteenth transistor T15 is electrically connected to the third node N3; a gate electrode of the sixteenth transistor T16 is electrically connected to the third node N3, a first electrode of the sixteenth transistor T16 is electrically connected to the third node N3, and a second electrode of the sixteenth transistor T16 is electrically connected to the eighth node N8; The first plate C11 of the first capacitor C1 is electrically connected to the fifth node N5, the second plate of the first capacitor C1 is electrically connected to the sixth node N6, the first plate C21 of the second capacitor C2 is electrically connected to the seventh node N7, the second plate C22 of the second capacitor C2 is electrically connected to the first power supply terminal V1, the first plate C31 of the third capacitor C3 is electrically connected to the third node N3, the second plate C32 of the third capacitor C3 is electrically connected to the fourth node N4, the first plate C51 of the fifth capacitor C5 is electrically connected to the second power supply terminal V2, and the second plate C52 of the fifth capacitor C5 is electrically connected to the cascade signal output terminal GP(n). Figure 7 is illustrated using 16T4C as an example.

[0145] In an exemplary embodiment, when the shift sub-circuit has a circuit structure of 10T3C, the shift sub-circuit includes: first to tenth transistors T1 to T10 and first to third capacitors C1 to C3.

[0146] In an exemplary embodiment, when the shift sub-circuit has a 10T4C circuit structure, the shift sub-circuit includes: first to tenth transistors T1 to T10 , first to third capacitors C1 to C3 , and a fifth capacitor C5 .

[0147] In an exemplary embodiment, when the shift sub-circuit has a 12T3C circuit structure, the shift sub-circuit includes: first to twelfth transistors T1 to T12 and first to third capacitors C1 to C3.

[0148] In an exemplary embodiment, when the shift sub-circuit has a 12T4C circuit structure, the shift sub-circuit includes: first to twelfth transistors T1 to T12 , first to third capacitors C1 to C3 , and a fifth capacitor C5 .

[0149] In an exemplary embodiment, when the shift sub-circuit has a circuit structure of 13T3C, the shift sub-circuit includes: first to thirteenth transistors T1 to T13 and first to third capacitors C1 to C3.

[0150] In an exemplary embodiment, when the shift sub-circuit has a 13T4C circuit structure, the shift sub-circuit includes: first to thirteenth transistors T1 to T13 , first to third capacitors C1 to C3 , and a fifth capacitor C5 .

[0151] In an exemplary embodiment, when the shift sub-circuit has a 16T3C circuit structure, the shift sub-circuit includes: first to sixteenth transistors T1 to T16 and first to third capacitors C1 to C3.

[0152] In an exemplary embodiment, as shown in FIG. 7 , the selection output sub-circuit may include a seventeenth transistor T17 , an eighteenth transistor T18 , a nineteenth transistor T19 , a twenty-fourth transistor T24 , and a fourth capacitor C4 . In which, a gate electrode of the seventeenth transistor T17 is electrically connected to the eighth node N8, a first electrode of the seventeenth transistor T17 is electrically connected to the second power supply terminal V2, and a second electrode of the seventeenth transistor T17 is electrically connected to the drive signal output terminal OP(n). A gate electrode of the eighteenth transistor T18 is electrically connected to the seventh node N7, a first electrode of the eighteenth transistor T18 is electrically connected to the first power supply terminal V1, a second electrode of the eighteenth transistor T18 is electrically connected to the first electrode of the nineteenth transistor T19, a gate electrode of the nineteenth transistor T19 is electrically connected to the ninth node N9, and a second electrode of the nineteenth transistor T19 is electrically connected to the drive signal output terminal OP(n). A gate electrode of the twenty-fourth transistor T24 is electrically connected to the ninth node N9, a first electrode of the twenty-fourth transistor T24 is electrically connected to the second power supply terminal V2, and a second electrode of the twenty-fourth transistor T24 is electrically connected to the drive signal output terminal OP(n). A first plate C41 of the fourth capacitor C4 is electrically connected to the ninth node N9, and a second plate C42 of the fourth capacitor C4 is electrically connected to the first power supply terminal V1.

[0153] In an exemplary embodiment, as shown in FIG7 , the inverting output subcircuit may include a twenty-second transistor T22 and a twenty-third transistor T23 , wherein a gate electrode of the twenty-second transistor T22 is electrically connected to the cascade signal output terminal GP(n), a first electrode of the twenty-second transistor T22 is electrically connected to the second power supply terminal V2, a second electrode of the twenty-second transistor T22 is electrically connected to the reverse signal output terminal Anti-GP(n), a gate electrode of the twenty-third transistor T23 is electrically connected to the cascade signal output terminal GP(n), a first electrode of the twenty-third transistor T23 is electrically connected to the first power supply terminal V1, and a second electrode of the twenty-third transistor T23 is electrically connected to the reverse signal output terminal Anti-GP(n).

[0154] In an exemplary embodiment, as shown in FIG7 , the latch sub-circuit may include a twentieth transistor T20 and a twenty-first transistor T21. A gate electrode of the twentieth transistor T20 is electrically connected to the cascade signal output terminal GP(n), a first electrode of the twentieth transistor T20 is electrically connected to the ninth node N9, a second electrode of the twentieth transistor T20 is electrically connected to a second electrode of a twenty-first transistor T21, a gate electrode of the twenty-first transistor T21 is electrically connected to the reverse signal output terminal Anti-GP(n−1) of the previous-stage shift register, and a second electrode of the twenty-first transistor T21 is electrically connected to the mask signal terminal MS.

[0155] The above-mentioned shift register provided by the present disclosure can latch the control signal of the corresponding masking signal end in the selection output sub-circuit according to the refresh rate requirement of the display area, so as to realize the control of the signal output by the driving signal output end, and realize different refresh rates in different areas of the display panel, that is, high and low refresh rates can coexist in the same frame picture, and the embodiment of the present disclosure is not limited to realizing different refresh rates in fixed areas of the display panel, and can realize dynamic refresh of any area, thereby reducing the power consumption of the display panel; at the same time, the latch sub-circuit can use the phase difference of the cascade signals output by the front and rear stages of the shift sub-circuit to store the control signal of the masking signal end in each stage of the shift register, thereby realizing continuous and correct output of the shift register of this stage.

[0156] In an exemplary embodiment, any capacitor among the first capacitor C1 to the fifth capacitor C5 can be a capacitor device made by a process. For example, a capacitor device can be realized by making a special capacitor electrode, and multiple capacitor electrodes of the capacitor can be realized by a metal layer, a semiconductor layer (such as doped polysilicon), etc. Alternatively, any capacitor among the first capacitor C1 to the fifth capacitor C5 can be a parasitic capacitance between multiple devices, which can be realized by the transistor itself and other devices and circuits. The connection method of any capacitor among the first capacitor C1 to the fifth capacitor C5 includes but is not limited to the method described above, and can be other applicable connection methods, and the level of the corresponding node can be stored. Here, the exemplary embodiment of the present disclosure is not limited to this.

[0157] In an exemplary embodiment, transistors can be classified into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low voltage (e.g., 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high voltage (e.g., 5V, 10V, or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high voltage (e.g., 5V, 10V, or other suitable voltages), and the turn-off voltage is a low voltage (e.g., 0V, -5V, -10V, or other suitable voltages).

[0158] In an exemplary embodiment, the first to twentieth transistors T1 to T21 and the twenty-third transistor T23 are P-type transistors, and the twentieth transistor T22 and the twenty-fourth transistor T24 are N-type transistors.

[0159] In an exemplary embodiment, the signal at the mask signal terminal MS may be a low level signal or a high level signal. When the signal at the mask signal terminal MS is a low level signal, it may be -20V to -5V; when the signal at the mask signal terminal MS is a high level signal, it may be 5V to 20V.

[0160] In an exemplary embodiment, the signal of the first power terminal V1 may be a high-level signal, for example, 5V to 10V; the signal of the second power terminal V2 may be a low-level signal, for example, -10V to -5V.

[0161] In an exemplary embodiment, the signal at either the first clock signal terminal CK1 or the second clock signal terminal CK2 is a square wave signal that repeats a high voltage and a low voltage. For example, the signal at the first clock signal terminal CK1 and the second clock signal terminal CK2 may have the same period and may be configured as phase-shifted signals. Here, the signal at the second clock signal terminal CK2 may be phase-shifted by half a period compared to the signal at the first clock signal terminal CK1. The high voltage period in each period of the signal at either the first clock signal terminal CK1 or the second clock signal terminal CK2 may be set to be longer than the low voltage period.

[0162] In an exemplary embodiment, the third power supply terminal V3 provides a low-level signal during the power-on initialization phase to prevent the ninth transistor T9 and the tenth transistor T10 of the final-stage control shift register from being simultaneously turned on due to output signal delay. Alternatively, the third power supply terminal V3 provides a low-level signal during an abnormal shutdown phase to prevent the ninth transistor T9 and the tenth transistor T10 from being simultaneously turned on. The third power supply terminal V3 continuously provides a high-level signal during the normal display phase, meaning that the thirteenth transistor T13 is turned off during the normal display phase.

[0163] In an exemplary embodiment, the drive signal output terminal OP(n) of the shift register is primarily used to control at least one transistor (e.g., the second transistor M2) in the pixel drive circuit of the display substrate. When the display substrate is in a refresh frame, the drive signal output terminal OP(n) outputs a high-level signal for a period of time and a low-level signal for the remainder of the frame, thereby controlling the conduction of the second transistor M2 and refreshing the data voltage. When the display substrate is not in a refresh frame, the drive signal output terminal OP(n) continuously outputs a low-level signal, preventing the second transistor M2 from conducting.

[0164] FIG8 is a timing diagram of the operation of a portion of the shift register. The following describes the operating principle of the shift register provided by the present disclosure to control the display panel to achieve different refresh rates in different areas, using the shift register shown in FIG7 as an example, combined with the signal timing diagram shown in FIG8. FIG8 illustrates this using the first four stages of the shift register as an example.

[0165] The signal timing diagram shown in FIG8 is only an example of the input (IN) and output (OP(1), OP(2), OP(3), OP(4)) of the first four-stage shift register. For example, when the area corresponding to the second row of sub-pixels and the third row of sub-pixels in the display panel is a low refresh rate area, and the first row of sub-pixels and the fourth row of sub-pixels are a high refresh rate area, when the signal at the cascade signal output terminal GP(1) of the first stage shift register and the signal at the reverse signal output terminal Anti-GP(0) of the previous stage are both low-level signals (at time t1), the twentieth transistor T20 and the twenty-first transistor T21 are both turned on, that is, at time t1, the low-level signal of the mask signal terminal MS is latched in the fourth capacitor C4 of the selection output sub-circuit, and the signal at the first stage cascade signal output terminal GP(1) is turned on. When the output is high level (at the moment T1”), the eighteenth transistor T18 is turned on. Since the fourth capacitor C4 maintains the low level signal of the masking signal terminal MS at the moment t1, the nineteenth transistor T19 is turned on and the twenty-fourth transistor T24 is turned off. Then, at the moment T1”, the driving signal output terminal OP(1) of the first-stage shift register outputs a high level signal of the first power supply terminal V1, thereby realizing a high refresh rate of the first row of sub-pixels in the display area. The maintenance time of the high level signal outputted by the driving signal output terminal OP(1) of the first-stage shift register from the first power supply terminal V1 can be set according to actual needs. For example, the duration of the high level signal outputted by the driving signal output terminal OP(1) of the first-stage shift register from the first power supply terminal V1 can overlap with the duration of the high level signal outputted by the driving signal output terminal OP(4) of the fourth-stage shift register from the first power supply terminal V1, and the pixel driving circuit corresponding to the driving signal output terminal OP(4) of the fourth-stage shift register can be pre-charged. Similarly, the duration of the output level signal of the driving signal output terminal OP(n) of the other-stage shift register is similar and will not be described in detail.

[0166] As shown in FIG8 , when the signal of the cascade signal output terminal GP(2) of the second-stage shift register and the signal of the reverse signal output terminal Anti-GP(1) of the previous stage are both low-level signals (at time t2), the twentieth transistor T20 and the twenty-first transistor T21 are both turned on, that is, the high-level signal of the mask signal terminal MS is latched in the fourth capacitor C4 of the selection output sub-circuit at time t2; when the second-stage cascade signal output terminal GP(2) outputs a high-level signal (at time T2″), the eighteenth transistor T18 is turned on. Since the fourth capacitor C4 maintains the high-level signal of the mask signal terminal MS at time t2, the nineteenth transistor T19 is turned off and the twentieth transistor T20 is turned on. Then, at time T2″, the driving signal output terminal OP(2) of the second-stage shift register outputs the low-level signal of the second power supply terminal V2, thereby realizing a low refresh rate for the second row of sub-pixels in the display area.

[0167] When the signal of the cascade signal output terminal GP(3) of the third-stage shift register and the signal of the reverse signal output terminal Anti-GP(2) of the previous stage are both low-level signals (at time t3), the twentieth transistor T20 and the twenty-first transistor T21 are both turned on, that is, the high-level signal of the masking signal terminal MS is locked in the fourth capacitor C4 of the selection output sub-circuit at time T3; when the third-stage cascade signal output terminal GP(3) outputs a high-level signal (at time T3″), the eighteenth transistor T18 is turned on. Since the fourth capacitor C4 maintains the high-level signal of the masking signal terminal MS at time t3, the nineteenth transistor T19 is turned off and the twentieth transistor T20 is turned on. Then, at time T3″, the driving signal output terminal OP(3) of the third-stage shift register outputs a low-level signal of the second power supply terminal V2, thereby realizing a low refresh rate of the third row of sub-pixels in the display area;

[0168] When the signal of the cascade signal output terminal GP(4) of the fourth-stage shift register and the signal of the reverse signal output terminal Anti-GP(3) of the previous stage are both low-level signals (at time t4), the twentieth transistor T20 and the twenty-first transistor T21 are both turned on, that is, the low-level signal of the mask signal terminal MS is latched in the fourth capacitor C4 of the selection output sub-circuit at time t4. When the fourth-stage cascade signal output terminal GP(4) outputs a high-level signal (at time T4”), the eighteenth transistor T18 is turned on. Since the fourth capacitor C4 maintains the low-level signal of the mask signal terminal MS at time t4, the nineteenth transistor T19 is turned on and the twentieth transistor T20 is turned off. At time T4”, the drive signal output terminal OP(4) of the fourth-stage shift register outputs a high-level signal of the first power supply terminal V1, thereby achieving a high refresh rate of the fourth row of sub-pixels in the display area.

[0169] Therefore, when a low refresh rate is required in a certain area of ​​the display substrate, a high-level signal is input through the masking signal terminal MS, and the driving signal output terminal always outputs a low-level signal so that some transistors of the pixel driving circuit in the corresponding display substrate are cut off. The data voltage in the display substrate is not charged, and the state of the previous frame is maintained, thereby achieving a low refresh rate in this area.

[0170] In an exemplary embodiment, since the shift register provided in FIG. 7 includes a large number of transistors, the display substrate including the shift register provided in FIG. 7 cannot achieve a narrow frame.

[0171] FIG9 is a schematic diagram of the structure of a display substrate provided in an embodiment of the present disclosure, FIG10A is a schematic diagram of a partial film layer of the display substrate provided in FIG9, and FIG10B is a schematic diagram of another partial film layer of the display substrate provided in FIG9. The display substrate provided in an embodiment of the present disclosure has a display area and a non-display area, and the display substrate includes: a pixel driving circuit located in the display area and a gate driving circuit group located in the non-display area, the gate driving circuit group includes at least a first driving circuit, the first driving circuit is connected to the pixel driving circuit, and the first driving circuit includes a plurality of cascaded shift registers; the shift register includes at least: a first output transistor OUT1, a second output transistor OUT2, a third output transistor OUT3, a fourth output transistor OUT4, and a fifth output transistor OUT5, a cascade signal output terminal, a driving signal output terminal, a first power supply terminal and a second power supply terminal, and the driving signal output terminal is electrically connected to the pixel driving circuit. The first output transistor OUT1 is electrically connected to the cascade signal output terminal and the first power supply terminal, respectively. The second output transistor OUT2 is connected to the cascade signal output terminal and the second power supply terminal, respectively. The third output transistor OUT3 is connected to the fifth output transistor OUT5 and the first power supply terminal, respectively. The fourth output transistor OUT4 is connected to the drive signal output terminal and the second power supply terminal, respectively. The fifth output transistor OUT5 is connected to the drive signal output terminal.

[0172] In an exemplary embodiment, as shown in FIG. 10A , the gate electrode OUT12 of the first output transistor OUT1 and the gate electrode OUT32 of the third output transistor OUT3 are integrally formed, and the gate electrode OUT22 of the second output transistor OUT2 and the gate electrode OUT42 of the fourth output transistor OUT4 are integrally formed.

[0173] In an exemplary embodiment, the first driving circuit may be connected to the gate electrode of the second transistor of the pixel driving circuit through the second scan signal line.

[0174] In an exemplary embodiment, as shown in Figures 9, 10A and 10B, the first output transistor OUT1 is the ninth transistor T9 in Figure 7, the second output transistor OUT2 is the tenth transistor T10 in Figure 7, the third output transistor OUT3 is the eighteenth transistor T18 in Figure 7, the fourth output transistor OUT4 is the seventeenth transistor T17 in Figure 7, and the fifth output transistor OUT5 is the nineteenth transistor T19 in Figure 7.

[0175] In an exemplary embodiment, as shown in FIG10B , the shift register may further include a fifth capacitor C5 . The fifth capacitor C5 is connected to the cascade signal output terminal and the second power supply terminal, respectively. In an exemplary embodiment, in conjunction with FIG7 , the fifth capacitor C5 is configured to maintain the stability of the signal at the reverse signal output terminal.

[0176] In an exemplary embodiment, the capacitance of the fifth capacitor is less than or equal to 60 farads. The smaller capacitance of the fifth capacitor can increase the discharge speed of the fifth capacitor, ensuring the output of the reverse signal output terminal. The smaller capacitance of the fifth capacitor can reduce the area of ​​the plate in the fifth capacitor, reduce the area occupied by the shift register, and achieve a narrow frame of the display substrate.

[0177] In an exemplary embodiment, as shown in Figures 9, 10A and 10B, any one of the third output transistor OUT3 and the fourth output transistor OUT4 is located on a side of any one of the first output transistor OUT1 and the second output transistor OUT2 close to the display area, the fifth output transistor OUT5 is located on a side of any one of the third output transistor OUT3 and the fourth output transistor OUT4 close to the display area, and the fifth capacitor C5 is located on a side of the second output transistor OUT2 away from the display area.

[0178] In an exemplary embodiment, as shown in Figures 9, 10A and 10B, the first output transistor OUT1 and the third output transistor OUT3 are arranged along the first direction D1, the second output transistor OUT2 and the fourth output transistor OUT4 are arranged along the first direction D1, the first output transistor OUT1 and the second output transistor OUT2 are arranged along the second direction D2, and the third output transistor OUT3 and the fourth output transistor OUT4 are arranged along the second direction D2, and the first direction D1 intersects the second direction D2.

[0179] In an exemplary embodiment, a transistor includes an active pattern, a gate electrode, a first electrode, and a second electrode.

[0180] In an exemplary embodiment, as shown in FIG. 10A , the length of the active pattern OUT11 of the first output transistor OUT1 along the first direction D1 is smaller than the channel width of the active pattern OUT31 of the third output transistor OUT3 along the first direction D1 .

[0181] In an exemplary embodiment, as shown in FIG. 10A , the channel width of the active pattern OUT11 of the first output transistor OUT1 is smaller than the channel width of the active pattern OUT31 of the third output transistor OUT3 , and the channel length of the active pattern OUT11 of the first output transistor OUT1 is greater than the channel length of the active pattern OUT31 of the third output transistor OUT3 .

[0182] In an exemplary embodiment, the channel width of the active pattern OUT11 of the first output transistor OUT1 ranges from 80 micrometers to 100 micrometers. For example, the channel width of the active pattern OUT11 of the first output transistor OUT1 may be 90 micrometers.

[0183] In an exemplary embodiment, the channel length of the active pattern OUT11 of the first output transistor OUT1 ranges from 3.2 micrometers to 3.7 micrometers. Exemplarily, the channel length of the active pattern OUT11 of the first output transistor OUT1 may be 3.5 micrometers.

[0184] In an exemplary embodiment, a channel width-to-length ratio of the active pattern OUT11 of the first output transistor OUT1 may be in the range of 90 / 3.5.

[0185] In an exemplary embodiment, the channel width of the active pattern OUT31 of the third output transistor OUT3 ranges from 250 micrometers to 300 micrometers. For example, the channel width of the active pattern OUT311 of the third output transistor OUT3 may be 270 micrometers.

[0186] In an exemplary embodiment, the channel length of the active pattern OUT31 of the third output transistor OUT3 ranges from 2.9 micrometers to 3.2 micrometers. For example, the channel length of the active pattern OUT311 of the third output transistor OUT3 may be 3.1 micrometers.

[0187] In an exemplary embodiment, the channel width-to-length ratio of the active pattern OUT31 of the third output transistor OUT3 may be in the range of 270 / 3.1.

[0188] In an exemplary embodiment, as shown in FIG. 10A , a length of the active pattern OUT31 of the third output transistor OUT3 along the first direction D1 is greater than a length of the active pattern OUT41 of the fourth output transistor OUT4 along the first direction D1, and a length of the active pattern OUT31 of the third output transistor OUT3 along the second direction D2 is less than a length of the active pattern OUT41 of the fourth output transistor OUT4 along the second direction D2.

[0189] In an exemplary embodiment, as shown in FIG. 10A , the length of the active pattern OUT21 of the second output transistor OUT2 along the first direction D1 is smaller than the length of the active pattern OUT41 of the fourth output transistor OUT4 along the first direction D1 .

[0190] In an exemplary embodiment, as shown in FIG. 10A , the channel width of the active pattern OUT21 of the second output transistor OUT2 is smaller than the channel width of the active pattern OUT41 of the fourth output transistor OUT4 , and the channel length of the active pattern OUT21 of the second output transistor OUT2 is greater than the channel length of the active pattern OUT41 of the fourth output transistor OUT4 .

[0191] In an exemplary embodiment, the channel width of the active pattern OUT21 of the second output transistor OUT2 ranges from 80 micrometers to 100 micrometers. For example, the channel width of the active pattern OUT21 of the second output transistor OUT2 may be 90 micrometers.

[0192] In an exemplary embodiment, the channel length of the active pattern OUT21 of the second output transistor OUT2 ranges from 3.2 micrometers to 3.7 micrometers. For example, the channel length of the active pattern OUT21 of the second output transistor OUT2 may be 3.5 micrometers.

[0193] In an exemplary embodiment, a channel width-to-length ratio of the active pattern OUT21 of the second output transistor OUT2 may be in the range of 90 / 3.5.

[0194] In an exemplary embodiment, the channel width of the active pattern OUT41 of the fourth output transistor OUT4 ranges from 250 micrometers to 300 micrometers. For example, the channel width of the active pattern OUT411 of the fourth output transistor OUT4 may be 270 micrometers.

[0195] In an exemplary embodiment, the channel length of the active pattern OUT41 of the fourth output transistor OUT4 ranges from 2.9 micrometers to 3.2 micrometers. For example, the channel length of the active pattern OUT411 of the fourth output transistor OUT4 may be 3.1 micrometers.

[0196] In an exemplary embodiment, the channel width-to-length ratio of the active pattern OUT41 of the fourth output transistor OUT4 is 270 / 3.1.

[0197] In an exemplary embodiment, as shown in FIG. 10A , the length of the active pattern OUT51 of the fifth output transistor OUT5 along the second direction D2 is greater than the length of the active pattern of any one of the third and fourth output transistors OUT3 and OUT4 along the second direction D2 .

[0198] In an exemplary embodiment, as shown in FIG10A , the channel width of the active pattern OUT51 of the fifth output transistor OUT5 ranges from 250 μm to 300 μm. For example, the channel width of the active pattern OUT51 of the fifth output transistor OUT5 ranges from 270 μm.

[0199] 10A , the channel length of the active pattern OUT51 of the fifth output transistor OUT5 ranges from 2.9 μm to 3.2 μm. Exemplarily, the channel length of the active pattern OUT51 of the fifth output transistor OUT5 ranges from 3.1 μm.

[0200] In an exemplary embodiment, the channel width-to-length ratio of the active pattern OUT51 of the fifth output transistor OUT5 may be 270 / 3.1.

[0201] In an exemplary embodiment, as shown in FIG10A , the active pattern OUT51 of the fifth output transistor OUT5 extends along the second direction D2. Extending the active pattern OUT51 of the fifth output transistor OUT5 along the second direction D2 can reduce the width of the shift register along the first direction, thereby reducing the area occupied by the shift register and achieving a narrow frame. In an exemplary embodiment, the channel width of the active pattern of any of the third to fifth output transistors OUT3 to OUT5 is greater than the channel width of the active pattern of any of the first and second output transistors OUT1 to OUT2. The channel length of the active pattern of any of the third to fifth output transistors OUT3 to OUT5 is close to the channel length of the active pattern of any of the first and second output transistors OUT1 to OUT2. This results in a current amplification factor of the third to fifth output transistors OUT3 to OUT5 that is greater than the current amplification factor of any of the first and second output transistors OUT1 to OUT2. This can improve the drive capability of the output signal to the drive signal output terminal, enhance the performance of the shift register, and improve the reliability of the display substrate.

[0202] In an exemplary embodiment, as shown in FIG. 10A , the active pattern OUT11 of the first output transistor OUT1 and the active pattern OUT21 of the second output transistor OUT2 are the same active pattern.

[0203] In an exemplary embodiment, as shown in FIG. 10A , the length of the gate electrode OUT22 of the third output transistor OUT2 along the first direction D1 is greater than the length of the gate electrode OUT42 of the fourth output transistor OUT4 along the first direction D1 .

[0204] In an exemplary embodiment, as shown in FIG. 10A , the length of the gate electrode OUT52 of the fifth output transistor OUT5 along the second direction D2 is greater than the length of the gate electrode of either the first output transistor OUT1 or the second output transistor OUT2 along the second direction D2 .

[0205] In an exemplary embodiment, as shown in FIG10A , the integrated structure of the gate electrode OUT12 of the first output transistor OUT1 and the gate electrode OUT32 of the third output transistor OUT3 may include a first connecting segment 92A, a transition portion 92C, and a plurality of first branch segments 92B. The first branch segments 92B and the transition portion 92C are located on a side of the first connecting segment 92A closer to the display area. The first connecting segment 92A is electrically connected to each of the plurality of first branch segments 92B. One end of the transition portion 92C is electrically connected to the middle portion of one of the first branch segments 92B.

[0206] In an exemplary embodiment, as shown in FIG10A , the first connecting segment 92A extends at least partially along the second direction D2, the first branch segment 92B extends at least partially along the first direction D1, a plurality of first branch segments 92B are arranged along the second direction D2, and the transition portion 92C is in a broken line shape and extends partially along the first direction D1.

[0207] In an exemplary embodiment, as shown in FIG. 10A , the length of the first branch segment 92B along the first direction D1 is greater than the length of the transition portion 92C along the first direction D1 .

[0208] In an exemplary embodiment, as shown in FIG10A , the integrated structure of the gate electrode OUT22 of the second output transistor OUT2 and the gate electrode OUT42 of the fourth output transistor OUT4 may include: a second connecting segment 102A and a plurality of second branch segments 102B. The second branch segments 102B are located on a side of the second connecting segment 102A close to the display area, and the second connecting segment 102A is respectively connected to the plurality of second branch segments 102B.

[0209] In an exemplary embodiment, as shown in FIG. 10A , the second connecting segment 102A at least partially extends along the second direction D2 , the second branch segments 102B at least partially extend along the first direction D1 , and a plurality of second branch segments 102B are arranged along the second direction D2 .

[0210] In an exemplary embodiment, as shown in FIG. 10A , the length of the first branch segment 92B along the first direction D1 is greater than the length of the second branch segment 102B along the second direction D2 .

[0211] In an exemplary embodiment, as shown in FIG10B , the shift register may further include a fourth capacitor C4 , wherein the fourth capacitor C4 is connected to the fifth output transistor OUT5 and the first power supply terminal, respectively.

[0212] In an exemplary embodiment, the capacitance value of the fourth capacitor ranges from 120 farads to 130 farads. Exemplarily, the capacitance value of the fourth capacitor ranges from 125.6 farads.

[0213] In an exemplary embodiment, as shown in FIG. 10B , the fourth capacitor C4 is located between the second output transistor OUT2 and the fourth output transistor OUT4 .

[0214] In an exemplary embodiment, as shown in FIG10B , the shift register may further include a twenty-fourth transistor T24 . The twenty-fourth transistor T24 is connected to the fifth output transistor OUT5 and the second power supply terminal, respectively.

[0215] In an exemplary embodiment, the transistor type of the twenty-fourth transistor T24 is opposite to the transistor type of any one of the first to fifth output transistors OUT1 to OUT5 .

[0216] In an exemplary embodiment, as shown in FIG. 10B , the twenty-fourth transistor T24 is located on a side of the fifth output transistor OUT5 close to the display area, and is arranged along the first direction D1 with the first output transistor OUT1 and the third output transistor OUT3 .

[0217] In an exemplary embodiment, the shift register may further include: a 20th transistor T20, a 21st transistor T21, a 22nd transistor T22, a 23rd transistor T23, a reverse signal output terminal, and a mask signal terminal. The 20th transistor T20 is respectively connected to the cascade signal output terminal, the fifth output transistor OUT5, and the 21st transistor T21; the 21st transistor T21 is respectively connected to the reverse signal output terminal and the mask signal terminal of the previous-stage shift register; the 22nd transistor T22 is respectively connected to the cascade signal output terminal, the reverse signal output terminal, and the second power supply terminal; and the 23rd transistor T23 is respectively connected to the cascade signal output terminal, the reverse signal output terminal, and the first power supply terminal.

[0218] In an exemplary embodiment, the transistor type of the twenty-second transistor T22 is opposite to the transistor type of any one of the first to fifth output transistors OUT1 , the twentieth transistor T20 , the twenty-first transistor T21 , and the twenty-third transistor T23 .

[0219] In an exemplary embodiment, as shown in FIG10B , the twentieth to twenty-third transistors T20 to T23 are located on a side of the fifth output transistor OUT5 close to the display area; the twenty-first transistor T21 and the twentieth transistor T20 are arranged along the second direction D2, and the twentieth transistor T20 is located on a side of the twenty-first transistor T21 close to the twenty-second transistor T22, and the twenty-third transistor T23 is located between the twenty-second transistor T22 and the fifth output transistor OUT5, and on a side of the twenty-second transistor T22 away from the twenty-first transistor T21.

[0220] In an exemplary embodiment, as shown in FIG10B , the shift register may further include: first to eighth transistors T1 to T8, eleventh to sixteenth transistors T11 to T16, first to third capacitors C1 to C3, a signal input terminal, a first clock signal terminal, a second clock signal terminal, and a third power supply terminal. Among them, the first transistor T1 is respectively connected to the signal input terminal, the first clock signal terminal, the second transistor T2, the eighth transistor T8, the twelfth transistor T12 and the thirteenth transistor T13, the second transistor T2 is respectively connected to the first clock signal line, the third transistor T3, the fifth transistor T5, the eighth transistor T8, the eleventh transistor T11, the twelfth transistor T12 and the thirteenth transistor T13, the third transistor T3 is respectively connected to the first clock signal terminal, the second power supply terminal, the fifth transistor T5 and the eleventh transistor T11, the fourth transistor T4 is respectively connected to the second clock signal terminal, the third capacitor C3, the fifth transistor T5, the fifteenth transistor T15 and the sixteenth transistor T16, the fifth transistor T5 is respectively connected to the first power supply terminal, the third capacitor C3 and the eleventh transistor T11, the sixth transistor T6 is respectively connected to the second clock signal terminal, the first capacitor C1, the seventh transistor T7 and the eleventh transistor T11, the seventh transistor T7 is respectively connected to the second clock signal terminal, the first capacitor C1 , the second capacitor C2, the first output transistor, the third output transistor and the eighth transistor T8 are connected, the eighth transistor T8 is respectively connected to the first power supply terminal, the second capacitor C2, the first output transistor, the third output transistor, the twelfth transistor T12 and the thirteenth transistor T13, the eleventh transistor T11 is respectively connected to the second power supply terminal and the first capacitor C1, the twelfth transistor T12 is respectively connected to the second power supply terminal, the second output transistor, the fourth output transistor, the thirteenth transistor T13 and the sixteenth transistor T16, the thirteenth transistor T13 is respectively connected to the first power supply terminal and the third power supply terminal, the thirteenth transistor T13 is respectively connected to the first power supply terminal and the third power supply terminal, the fourteenth transistor T14 is respectively connected to the signal input terminal, the first clock signal terminal and the fifteenth transistor T15, the fifteenth transistor T15 is respectively connected to the second power supply terminal, the third capacitor C3 and the sixteenth transistor T16, and the sixteenth transistor T16 is respectively connected to the second output transistor, the fourth output transistor and the third capacitor C3.

[0221] In an exemplary embodiment, a transistor type of any one of the first to eighth transistors and the eleventh to sixteenth transistors is the same as a transistor type of any one of the first to fifth output transistors.

[0222] In an exemplary embodiment, the capacitance value of the third capacitor C3 is greater than the capacitance value of the second capacitor C2 , and the capacitance value of the second capacitor C2 is greater than the voltage value of the first capacitor C1 .

[0223] In an exemplary embodiment, the voltage value of the first capacitor C1 ranges from 47 farads to 50 farads. For example, the voltage value of the first capacitor C1 may be 48.7 farads.

[0224] In an exemplary embodiment, the voltage value of the second capacitor C2 ranges from 71 farads to 73 farads. For example, the voltage value of the second capacitor C2 may be 72.7 farads.

[0225] In an exemplary embodiment, the voltage value of the third capacitor C3 ranges from 119 farads to 121 farads. For example, the voltage value of the third capacitor C3 may be 120.2 farads.

[0226] In an exemplary embodiment, as shown in FIG10B , any one of the first to eighth transistors T1 to T8 , the eleventh to sixteenth transistors T11 to T16 , and the first to third capacitors C1 to C3 is located on a side of any one of the first output transistor OUT1 and the second output transistor OUT2 away from the display area.

[0227] In an exemplary embodiment, as shown in FIG9 , the display substrate further includes: an initial signal line STV, a first clock signal line CLK1, a second clock signal line CLK2, a first power line VGH, a second power line VGL, a third power line VEL, and a mask signal line MSL located in a non-display area. The initial signal line STV is electrically connected to the signal input terminals of some shift registers, the first clock signal line CLK1 is electrically connected to one of the first clock signal terminal and the second clock signal terminal of any shift register, the second clock signal line CLK2 is electrically connected to the other of the first clock signal terminal and the second clock signal terminal of any shift register, the first power line VGH is electrically connected to the first power terminal of any shift register, the second power line VGL is electrically connected to the second power terminal of any shift register, the third power line VEL is electrically connected to the third power terminal of any shift register, and the mask signal line MSL is electrically connected to the mask signal terminal of any shift register.

[0228] 9 , any one of the initial signal line STV, the first clock signal line CLK1, the second clock signal line CLK2, the first power line VGH, the second power line VGL, the third power line VEL and the masking signal line MSL at least partially extends along the second direction D2.

[0229] In an exemplary embodiment, the shift register includes at least one P-type transistor, at least one N-type transistor, and at least one capacitor, wherein the capacitor includes a first plate and a second plate. The at least one P-type transistor includes first to fifth output transistors OUT1 to OUT5.

[0230] In an exemplary embodiment, the gate electrode of the N-type transistor includes a first gate electrode and a second gate electrode disposed in different layers and connected to each other, and the first gate electrode is disposed in the same layer as the second plate of the at least one capacitor.

[0231] In an exemplary embodiment, the P-type transistors include the first to twenty-first transistors T1 to T21 and the twenty-third transistor T23 in FIG. 7 , and the N-type transistors include the twenty-second and twenty-fourth transistors T22 and T24 in FIG. 7 .

[0232] In an exemplary embodiment, the display substrate may further include: a base and a driving circuit layer disposed on the base, the gate driving circuit group and the pixel driving circuit being disposed on the driving circuit layer, the driving circuit layer including a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer stacked in sequence;

[0233] In an exemplary embodiment, the first semiconductor layer includes at least an active pattern of a P-type transistor.

[0234] In an exemplary embodiment, the first conductive layer includes at least: a gate electrode of a P-type transistor and a first plate of at least one capacitor.

[0235] In an exemplary embodiment, the second conductive layer includes at least: a second plate of at least one capacitor and a first gate electrode of the N-type transistor.

[0236] In an exemplary embodiment, the second semiconductor layer includes at least an active pattern of an N-type transistor.

[0237] In an exemplary embodiment, the third conductive layer includes at least a second gate electrode of the N-type transistor.

[0238] In an exemplary embodiment, the fourth conductive layer includes at least an initial signal line STV, a first clock signal line CLK1, a second clock signal line CLK2, a third power line VEL, and first and second electrodes of either a P-type transistor or an N-type transistor.

[0239] The fifth conductive layer at least includes two first power lines, four second power lines and a mask signal line MSL.

[0240] In an exemplary embodiment, as shown in Figures 9 and 11, the two first power lines include a first first power line VGH-1 and a second first power line VGH-2. The four second power lines include a first second power line VGL-1, a second second power line VGL-2, a third second power line VGL-3, and a fourth second power line VGL-4.

[0241] In an exemplary embodiment, the second second power line VGL-2 is connected to the second power terminal to which the second output transistor is connected, the third second power line VGL-2 is connected to the second power terminal to which the fourth output transistor is connected, the first first power line VGH-1 is connected to the first power terminal to which the first output transistor is connected, and the second first power line VGH-2 is connected to the first power terminal to which the third output transistor is connected.

[0242] In an exemplary embodiment, Figure 11 is a schematic diagram of the film layer where the signal lines of the display substrate provided in Figure 9 are located. As shown in Figures 9 and 11, the initial signal line STV, the first clock signal line CLK1, the second clock signal line CLK2, and the third power line VEL are arranged in sequence in a direction close to the display area.

[0243] In an exemplary embodiment, as shown in FIG9 , the initial signal line STV, the first clock signal line CLK1, and the second clock signal line CLK2 are located on a side of the first and second electrodes of all transistors in the shift register away from the display area, and the orthographic projection of the third power line VEL on the substrate partially overlaps with the orthographic projections of some transistors on the substrate.

[0244] In an exemplary embodiment, as shown in Figures 9 and 11, the first second power line VGL-1, the second second power line VGL-2, the first first power line VGH-1, the third second power line VGL-3, the second first power line VGH-2, the masking signal line MSL and the fourth second power line VGL-4 are arranged in sequence along a direction close to the display area.

[0245] In an exemplary embodiment, as shown in FIG. 9 and FIG. 11 , an orthographic projection of the second power line VGL- 2 on the substrate at least partially overlaps an orthographic projection of the third power line VEL on the substrate.

[0246] In an exemplary embodiment, as shown in FIG. 11 , the line width of the second power line VGL- 2 is greater than the line width of the third power line VEL.

[0247] In an exemplary embodiment, as shown in Figures 9 and 11, the orthographic projection of the second clock signal line CLK2 on the substrate is located on a side of the orthographic projection of any transistor in the shift register on the substrate away from the display area. That is, the initial signal line STV, the first clock signal line CLK1, and the second clock signal line CLK2 are located on a side of the shift register away from the display area, and do not overlap with the electrodes included in the transistors in the shift register. This reduces the overlapping area between all signal lines connected to the shift register and the electrodes included in the transistors in the shift register, avoids signal jumps on the electrodes included in the transistors in the shift register due to signal jumps on the clock signal lines, and improves the reliability of the display substrate.

[0248] In an exemplary embodiment, as shown in FIG11 , no overlapping region exists between the orthographic projections of any two of the initial signal line STV, the first clock signal line CLK1, the second clock signal line CLK2, the first second power line VGL-1, the second second power line VGL-2, and the first first power line VGH-1. No overlapping region exists between the orthographic projections of any two of the third second power line VGL-3, the second first power line VGH-2, the masking signal line MSL, and the fourth second power line VGL-4. The orthographic projection of the first second power line VGL-1 on the substrate is located between the orthographic projection of the second clock signal line CLK2 and the orthographic projection of the third power line VEL on the substrate. The orthographic projections of the first first power line VGH-1, the third second power line VGL-3, the second first power line VGH-2, the masking signal line MSL, and the fourth second power line VGL-4 on the substrate are located on a side of the orthographic projection of the third power line VEL on the substrate that is closer to the display area. The above signal line setting method disclosed in the present invention can ensure that multiple signal lines located in the fourth conductive layer (such as the initial signal line STV, the first clock signal line CLK1 and the second clock signal line CLK2) do not overlap with all signal lines located in the fifth conductive layer, which can reduce signal coupling between signal lines and improve the reliability of the display substrate.

[0249] In an exemplary embodiment, as shown in FIG11 , the line width of the first second power line VGL-1 is smaller than the line width of any signal line among the second second power line VGL-2 and the third second power line VGL-3, and the line width of the fourth second power line VGL-4 is smaller than the line width of any signal line among the second second power line VGL-2 and the third second power line VGL-3.

[0250] In an exemplary embodiment, as shown in FIG. 11 , the line width of the first first power line VGH- 1 is smaller than the line width of the second first power line VGH- 2 .

[0251] In an exemplary embodiment, as shown in FIG11 , the line width of the masking signal line MSL is greater than the line width of any one of the first second power line VGL-1, the fourth second power line VGL-4, and the first first power line VGH-1, and is smaller than the line widths of the second second power line VGL-2, the third second power line VGL-3, and the second first power line VGH-2.

[0252] In an exemplary embodiment, the gate driving circuit group further includes: a second driving circuit electrically connected to the pixel driving circuit, the first driving circuit and the second driving circuit are arranged along the first direction D1, and the second driving circuit is electrically connected to the fourth second power line VGL-4.

[0253] In an exemplary embodiment, the second driving circuit may be connected to the gate electrode of the first transistor of the pixel driving circuit through the first scan signal line.

[0254] In an exemplary embodiment, two driving circuits share one power line, which can reduce the area occupied by the entire gate driving circuit group in the non-display region and achieve a narrow frame of the display substrate.

[0255] In an exemplary embodiment, the display substrate further includes a light-emitting structure layer located on a side of the drive circuit layer away from the substrate. The light-emitting structure layer 103 may include an anode, a pixel definition layer, an organic light-emitting layer, and a cathode. The anode is connected to the pixel drive circuit via a via, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. Driven by the anode and cathode, the organic light-emitting layer emits light of a corresponding color.

[0256] In an exemplary embodiment, the display substrate may further include an encapsulation structure layer located on a side of the light-emitting structure layer away from the substrate. The encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer may be made of an organic material. The second encapsulation layer is disposed between the first and third encapsulation layers to prevent external moisture from entering the light-emitting structure layer.

[0257] In an exemplary embodiment, the display substrate may further include a touch structure layer located on a side of the encapsulation structure layer away from the base. The touch structure layer may include a first touch insulation layer disposed on the encapsulation structure layer, a first touch metal layer disposed on the first touch insulation layer, a second touch insulation layer covering the first touch metal layer, a second touch metal layer disposed on the second touch insulation layer, and a touch protection layer covering the second touch metal layer. The first touch metal layer may include a plurality of bridging electrodes, and the second touch metal layer may include a plurality of first touch electrodes and second touch electrodes. The first touch electrodes or the second touch electrodes may be connected to the bridging electrodes through vias.

[0258] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a gate driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0259] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0260] (1) Forming a first semiconductor layer pattern on a substrate. In an exemplary embodiment, forming the first semiconductor layer pattern on a substrate may include: depositing a first semiconductor thin film on the substrate, and patterning the first semiconductor thin film through a patterning process to form the first semiconductor layer pattern. As shown in FIG12 , FIG12 is a schematic diagram of FIG9 after the first semiconductor layer pattern is formed.

[0261] In an exemplary embodiment, as shown in FIG. 12 , the semiconductor layer pattern may include at least active patterns 11 to 211 of first to twenty-first transistors and a twenty-third transistor 231 at each stage of the shift register.

[0262] In an exemplary embodiment, as shown in FIG12 , the active pattern 51 of the fifth transistor, the active pattern 81 of the eighth transistor, and the active pattern 131 of the thirteenth transistor are integrally formed, the active pattern 91 of the ninth transistor and the active pattern 101 of the tenth transistor are integrally formed, the active pattern 121 of the twelfth transistor and the active pattern 161 of the sixteenth transistor are integrally formed, and the active pattern 201 of the twentieth transistor and the active pattern 211 of the twenty-first transistor are integrally formed. The active pattern 11 of the first transistor, the active pattern 21 of the second transistor, the active pattern 31 of the third transistor, the active pattern 41 of the fourth transistor, the active pattern 61 of the sixth transistor, the active pattern 71 of the seventh transistor, the active pattern 111 of the eleventh transistor, the active pattern 141 of the fourteenth transistor, the active pattern 151 of the fifteenth transistor, the active pattern 171 of the seventeenth transistor, the active pattern 181 of the eighteenth transistor, the active pattern 191 of the nineteenth transistor, and the active pattern 231 of the twenty-third transistor may be separately provided.

[0263] In an exemplary embodiment, as shown in FIG12 , the active pattern 11 of the first transistor and the active pattern 141 of the fourteenth transistor are arranged along a first direction D1, and the active pattern 11 of the first transistor is located on a side of the active pattern 141 of the fourteenth transistor close to the display area, and the active pattern 21 of the second transistor is located on a side of the active pattern 11 of the first transistor close to the display area. The active pattern 31 of the third transistor and the active pattern 11 of the first transistor are arranged along the second direction D2, and the active pattern 31 of the third transistor of the shift register at this level is located on the side of the active pattern 11 of the first transistor of the shift register at this level close to the shift register at the next level. The active pattern 111 of the eleventh transistor and the active pattern 151 of the fifteenth transistor are arranged along the first direction D1. The active pattern 111 of the eleventh transistor and the active pattern 11 of the first transistor are arranged along the second direction D2. The active pattern 151 of the fifteenth transistor and the active pattern 141 of the fourteenth transistor are arranged along the second direction D2. The active pattern 111 of the eleventh transistor is located on the side of the active pattern 151 of the fifteenth transistor of the shift register at this level close to the display area. The active pattern 111 of the eleventh transistor of the shift register at this level is located on the side of the active pattern 31 of the third transistor close to the shift register at the next level. The active pattern 41 of the fourth transistor of the current stage shift register is located on the side of the active pattern 111 of the eleventh transistor that is closer to the shift register of the next stage. The active pattern 61 of the sixth transistor is located on the side of the active pattern 21 of the second transistor that is closer to the display area. The active pattern 71 of the seventh transistor is located on the side of the active pattern 61 of the sixth transistor that is closer to the display area. The active pattern 51 of the fifth transistor (which is also the active pattern 81 of the eighth transistor and the active pattern 131 of the thirteenth transistor) is located on the side of the active pattern 21 of the second transistor and the active pattern 111 of the eleventh transistor close to the display area, and the active pattern 131 of the thirteenth transistor is located on the side of the active pattern 81 of the eighth transistor away from the display area, the active pattern 51 of the fifth transistor is located on the side of the active pattern 111 of the eleventh transistor close to the display area, the active pattern 71 of the seventh transistor, the active pattern 81 of the eighth transistor and the active pattern 51 of the fifth transistor are arranged in sequence along the second direction D2, and the active pattern 71 of the seventh transistor of the shift register at this level is located on the side of the active pattern 81 of the eighth transistor close to the previous level shift register, and the active pattern 51 of the fifth transistor of the shift register at this level is located on the side of the active pattern 81 of the eighth transistor close to the next level shift register.The active pattern 121 of the twelfth transistor (also the active pattern 161 of the sixteenth transistor) is located on a side of the active pattern 41 of the fourth transistor closer to the display area. The active pattern 121 of the twelfth transistor is located on a side of the active pattern 161 of the sixteenth transistor closer to the display area. The active pattern 51 of the fifth transistor and the active pattern 121 of the twelfth transistor are arranged along the second direction D2. The active pattern 121 of the twelfth transistor of the current stage shift register is located on a side of the active pattern 51 of the fifth transistor closer to the shift register of the next stage. The active pattern 91 of the ninth transistor (also the active pattern 101 of the tenth transistor) is located on a side of the active pattern 71 of the seventh transistor and the active pattern 51 of the fifth transistor (also the active pattern 81 of the eighth transistor and the active pattern 131 of the thirteenth transistor) closer to the display area. The active pattern 91 of the ninth transistor of the current stage shift register can be located on a side of the active pattern 101 of the tenth transistor closer to the shift register of the previous stage. The active pattern 171 of the seventeenth transistor and the active pattern 181 of the eighteenth transistor are arranged along the second direction D2 and are located on the side of the active pattern 91 of the ninth transistor (also the active pattern 101 of the tenth transistor) close to the display area. The active pattern 171 of the seventeenth transistor in the shift register of this level can be located on the side of the active pattern 181 of the eighteenth transistor close to the shift register of the next level. The active pattern 191 of the nineteenth transistor is located on a side of the active pattern 171 of the seventeenth transistor and the active pattern 181 of the eighteenth transistor close to the display area, the active pattern 201 of the twentieth transistor (also the active pattern 211 of the twenty-first transistor) is located on a side of the active pattern 191 of the nineteenth transistor close to the display area, and the active pattern 201 of the twentieth transistor of the current level shift register is located on a side of the active pattern 211 of the twenty-first transistor close to the next level shift register, the active pattern 231 of the twenty-third transistor is located between the active pattern 191 of the nineteenth transistor and the active pattern 201 of the twentieth transistor (also the active pattern 211 of the twenty-first transistor), and is arranged along the first direction D1 with the active pattern 171 of the seventeenth transistor.

[0264] In an exemplary embodiment, as shown in FIG12 , any one of the active pattern 11 of the first transistor, the active pattern 21 of the second transistor, the active pattern 31 of the third transistor, the active pattern 71 of the seventh transistor, the active pattern 91 of the ninth transistor (also the active pattern 101 of the tenth transistor), the active pattern 111 of the eleventh transistor, the active pattern 141 of the fourteenth transistor, the active pattern 151 of the fifteenth transistor, the active pattern 171 of the seventeenth transistor, the active pattern 181 of the eighteenth transistor, the active pattern 191 of the nineteenth transistor, the active pattern 201 of the twentieth transistor (also the active pattern 211 of the twenty-first transistor), and the active pattern 231 of the twenty-third transistor has a strip shape and extends along the second direction D2.

[0265] In an exemplary embodiment, as shown in FIG. 12 , any one of the active pattern 41 of the fourth transistor and the active pattern 61 of the sixth transistor has a stripe shape and extends along the first direction D1 .

[0266] In an exemplary embodiment, as shown in FIG. 12 , the active pattern 121 of the twelfth transistor (also the active pattern 161 of the sixteenth transistor) has an inverted “T” shape.

[0267] In an exemplary embodiment, the shape of the active pattern 51 of the fifth transistor may be The shape of the active pattern of the eighth transistor can be The shapes of the active pattern 51 of the fifth transistor and the active pattern 81 of the eighth transistor may be The active pattern 131 of the thirteenth transistor may be in the shape of a zigzag line extending at least partially along the first direction D1.

[0268] In an exemplary embodiment, the length of the active pattern 91 of the ninth transistor (also the active pattern 101 of the tenth transistor) along the first direction D1 is smaller than the length of the active pattern 171 of the seventeenth transistor along the first direction D1, and smaller than the length of the active pattern 181 of the eighteenth transistor along the first direction D1.

[0269] In an exemplary embodiment, the channel width of the active pattern 91 of the ninth transistor ranges from 80 micrometers to 100 micrometers, and the channel length of the active pattern 91 of the ninth transistor ranges from 3.2 micrometers to 3.7 micrometers.

[0270] In exemplary embodiments, the channel width-to-length ratio of the active pattern 91 of the ninth transistor may be 90 / 3.5.

[0271] In an exemplary embodiment, the channel width of the active pattern 101 of the tenth transistor ranges from 80 micrometers to 100 micrometers, and the channel length of the active pattern 101 of the tenth transistor ranges from 3.2 micrometers to 3.7 micrometers.

[0272] In example embodiments, the channel width-to-length ratio of the active pattern 101 of the tenth transistor may be 90 / 3.5.

[0273] In exemplary embodiments, the channel width of the active pattern 171 of the seventeenth transistor ranges from 250 micrometers to 300 micrometers, and the channel length of the active pattern 171 of the seventeenth transistor ranges from 2.9 micrometers to 3.2 micrometers.

[0274] In example embodiments, the channel width-to-length ratio of the active pattern 171 of the seventeenth transistor may be 270 / 3.1.

[0275] In exemplary embodiments, the channel width of the active pattern 181 of the eighteenth transistor ranges from 250 micrometers to 300 micrometers, and the channel length of the active pattern 181 of the eighteenth transistor ranges from 2.9 micrometers to 3.2 micrometers.

[0276] In exemplary embodiments, the channel width-to-length ratio of the active pattern 181 of the eighteenth transistor may be 270 / 3.1.

[0277] In exemplary embodiments, the channel width of the active pattern 191 of the nineteenth transistor ranges from 250 micrometers to 300 micrometers, and the channel length of the active pattern 191 of the nineteenth transistor ranges from 2.9 micrometers to 3.2 micrometers.

[0278] In example embodiments, the channel width-to-length ratio of the active pattern 191 of the nineteenth transistor may be 270 / 3.1.

[0279] In an exemplary embodiment, as shown in FIG12 , the active pattern of each transistor may include a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, the first region 51-1 of the active pattern 51 of the fifth transistor may serve as the first region 81-1 of the active pattern 81 of the eighth transistor and the first region 131-1 of the active pattern 131 of the thirteenth transistor. The second region 91-2 of the active pattern 91 of the ninth transistor may serve as the second region 101-2 of the active pattern 101 of the tenth transistor. The second region 121-2 of the active pattern 121 of the twelfth transistor may serve as the second region 161-2 of the active pattern 161 of the sixteenth transistor. The second region 201-2 of the active pattern 201 of the twentieth transistor may serve as the second region 211-2 of the active pattern 211 of the twenty-first transistor. the first area 11-1 and the second area 11-2 of the active pattern 11 of the first transistor, the first area 21-1 and the second area 21-2 of the active pattern 21 of the second transistor, the first area 31-1 and the second area 31-2 of the active pattern 31 of the third transistor, the first area 41-1 and the second area 41-2 of the active pattern 41 of the fourth transistor, the second area 51-2 of the active pattern 51 of the fifth transistor, the first area 61-1 and the second area 61-2 of the active pattern 61 of the sixth transistor, the first area 71-1 and the second area 71-2 of the active pattern 71 of the seventh transistor, the second area 81-2 of the active pattern 81 of the eighth transistor, the first area 91-1 of the active pattern 91 of the ninth transistor, the first area 101-1 of the active pattern 101 of the tenth transistor, the first area 111-1 and the second area 111-2 of the active pattern 111 of the eleventh transistor, and the first area 111-2 of the active pattern 111 of the twelfth transistor. The first region 121-1 of the pattern 121, the second region 131-2 of the active pattern 131 of the thirteenth transistor, the first region 141-1 and the second region 141-2 of the active pattern 141 of the fourteenth transistor, the first region 151-1 and the second region 151-2 of the active pattern 151 of the fifteenth transistor, the first region 161-1 of the active pattern 161 of the sixteenth transistor, the first region 171-1 and the second region 171-2 of the active pattern 171 of the seventeenth transistor, the first region 181-1 and the second region 181-2 of the active pattern 181 of the eighteenth transistor, the first region 191-1 and the second region 191-2 of the active pattern 191 of the nineteenth transistor, the first electrode 201-1 of the active pattern of the twentieth transistor, the first electrode 211-1 of the twenty-first transistor, and the first region 231-1 and the second region 231-2 of the active pattern of the twenty-third transistor are separately provided.

[0280] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a first insulating layer covering the first semiconductor layer pattern, and a first conductive layer pattern disposed on the first insulating layer, as shown in FIG13 and FIG14 , FIG13 is a schematic diagram of the first conductive layer pattern in FIG9 , and FIG14 is a schematic diagram of FIG9 after the first conductive layer pattern is formed. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0281] In an exemplary embodiment, as shown in Figures 13 and 14, the first conductive layer pattern may include at least: the gate electrode 12 of the first transistor to the gate electrode 212 of the twenty-first transistor, the gate electrode 232 of the twenty-third transistor, the first plate C11 of the first capacitor to the first plate C51 of the fifth capacitor, the first connecting line L1, the second connecting line L2 and the third connecting line L3.

[0282] In an exemplary embodiment, as shown in FIG13 and FIG14 , the gate electrode 12 of the first transistor and the gate electrode 142 of the fourteenth transistor are an integrated structure, and the integrated structure of the gate electrode 12 of the first transistor and the gate electrode 142 of the fourteenth transistor is strip-shaped and extends along the first direction D1.

[0283] In an exemplary embodiment, as shown in Figures 13 and 14, the gate electrode 22 of the second transistor and the gate electrode 82 of the eighth transistor are integrally formed. The gate electrode 22 of the second transistor may be in an "n" shape with an opening facing the display area, and the gate electrode 82 of the eighth transistor may be in a zigzag shape, extending at least partially along the first direction D1.

[0284] In an exemplary embodiment, as shown in FIG. 13 and FIG. 14 , the gate electrode 32 of the third transistor is provided separately and may be in a strip shape and extend along the first direction D1 .

[0285] In an exemplary embodiment, as shown in FIG13 and FIG14, the gate electrode 42 of the fourth transistor, the gate electrode 162 of the sixteenth transistor, and the C31 of the third capacitor are an integrated structure. The shape of the third capacitor C31 is rectangular. The gate electrode 42 of the fourth transistor of the current stage shift register is located on the side of the third capacitor C31 close to the next stage shift register, and the shape of the gate electrode 42 of the fourth transistor is strip-shaped and extends along the second direction D2. The gate electrode 162 of the sixteenth transistor is located on the side of the third capacitor C31 close to the display area, and the shape of the gate electrode 162 of the sixteenth transistor is rectangular. Font.

[0286] 13 and 14 , the gate electrode 52 of the fifth transistor is provided separately. The gate electrode 52 of the fifth transistor is shaped like a zigzag line and at least partially extends along the first direction D1.

[0287] In an exemplary embodiment, as shown in FIG13 and FIG14, the gate electrode 62 of the sixth transistor and the first plate C11 of the first capacitor are an integral structure. The gate electrode 62 of the sixth transistor of the current stage shift register is located on the side of the first plate C11 of the first capacitor close to the next stage shift register. The shape of the first plate C11 of the first capacitor can be The gate electrode 62 of the sixth transistor is in a zigzag shape and at least partially extends along the second direction D2.

[0288] In an exemplary embodiment, as shown in Figures 13 and 14 , the gate electrode 72 of the seventh transistor is provided separately. The gate electrode 72 of the seventh transistor is shaped like a broken line and extends at least partially along the first direction D1. The gate electrode 72 of the seventh transistor is at least partially located on one side of the first plate C11 surrounding the first capacitor.

[0289] In an exemplary embodiment, as shown in Figures 13 and 14, the gate electrode 92 of the ninth transistor, the gate electrode 182 of the eighteenth transistor, and the first plate C21 of the second capacitor are integrally structured. The gate electrode 92 of the ninth transistor (also the gate electrode 182 of the eighteenth transistor and the first plate C21 of the second capacitor) includes a first connecting segment 92A, a transition portion 92C, and at least one first branch segment 92B. The first plate C21 of the second capacitor is located on a side of the first connecting segment 92A away from the display area, the first branch segment 92B is located on a side of the first connecting segment 92A closer to the display area, and the transition portion 92C is located on a side of any of the first branch segments 92B in the current shift register that is closer to the next shift register. The first connecting segment 92A is electrically connected to the first plate C21 of the second capacitor and the at least one first branch segment 92B, respectively. One end of the transition portion 92C is electrically connected to the middle portion of the first branch segment 92B closer to the next shift register. The first connecting segment 92A is strip-shaped and extends along the second direction D2. The first branch segment 92B can be strip-shaped and extend along the first direction D1. The first connecting segment 92A and at least one first branch segment 92B can be comb-shaped, wherein the first connecting segment 92A can be equivalent to the "comb back" and the first branch segment 92B can be equivalent to the "comb teeth".

[0290] In an exemplary embodiment, as shown in Figures 13 and 14, the gate electrode 102 of the tenth transistor and the gate electrode 172 of the seventeenth transistor are integrally formed. The gate electrode 102 of the tenth transistor (also the gate electrode 172 of the seventeenth transistor) includes a second connecting segment 102A and at least one second branch segment 102B. The second branch segment 102B is located on the side of the second connecting segment 102A closer to the display area. The second connecting segment 102A extends along the second direction D2, and the second branch segments 102B extend along the first direction D1. The plurality of second branch segments 102B are arranged along the direction D2, and at least one second branch segment is electrically connected to the second connecting segment 102A. The gate electrode 102 of the tenth transistor (also the gate electrode 172 of the seventeenth transistor) has a comb-like structure, with the second connecting segment 102A acting as the "back" of the comb and the second branch segments 102B acting as the "teeth" of the comb.

[0291] In an exemplary embodiment, as shown in Figures 13 and 14, the gate electrode 112 of the eleventh transistor and the gate electrode 152 of the fifteenth transistor are an integrated structure, and the gate electrode 112 of the eleventh transistor (also the gate electrode 152 of the fifteenth transistor) is strip-shaped and extends along the first direction D1.

[0292] In an exemplary embodiment, as shown in Figures 13 and 14, the gate electrode 122 of the twelfth transistor and the first plate C51 of the fifth capacitor are integrally formed. The gate electrode 122 of the twelfth transistor is located on a side of the first plate C51 of the fifth capacitor that is closer to the next shift register stage and is electrically connected to the side of the first plate C51 of the fifth capacitor that is closer to the next shift register stage. The gate electrode 122 of the twelfth transistor has a zigzag shape and extends at least partially along the first direction D1. The first plate C51 of the fifth capacitor can be rectangular, and the corners of the rectangle can be chamfered.

[0293] 13 and 14 , the gate electrode 132 of the thirteenth transistor is separately provided. The gate electrode 132 of the thirteenth transistor is in the shape of a stripe and extends along the second direction D2.

[0294] In an exemplary embodiment, as shown in Figures 13 and 14, the gate electrode 192 of the nineteenth transistor and the first plate C41 of the fourth capacitor are integrally structured. The gate electrode 192 of the nineteenth transistor (also the first plate C41 of the fourth capacitor) includes a third connecting segment 192A and at least one third branch segment 192B. The third branch segment 192B is located on the side of the third connecting segment 192A closer to the display area. The gate electrode 192 of the nineteenth transistor (also the first plate C41 of the fourth capacitor) can have a comb-like structure. The third connecting segment 192A can be strip-shaped and extend along the second direction D2, equivalent to a "comb back." The third branch segments 192B can be strip-shaped and extend along the first direction D1, equivalent to "comb teeth." At least one third branch segment 192B is arranged along the second direction D2. The third connecting segment 192A is provided with a protrusion K away from the boundary of the display area, and one of the third branch segments 192B has a greater length in the first direction than the remaining branch segments.

[0295] In an exemplary embodiment, the length of the first branch segment 92B is greater than the length of the second branch segment 102B, and the length of any second branch segment 102B is greater than the length of any third branch segment 192B.

[0296] In an exemplary embodiment, as shown in FIG. 13 and FIG. 14 , the gate electrode 202 of the twentieth transistor is provided separately. The gate electrode 202 of the twentieth transistor may be in a strip shape and extend along the first direction D1 .

[0297] In an exemplary embodiment, as shown in FIG. 13 and FIG. 14 , the gate electrode 212 of the twenty-first transistor is separately provided, and the shape of the gate electrode 212 of the twenty-first transistor may be Font.

[0298] In an exemplary embodiment, as shown in FIG. 13 and FIG. 14 , the gate electrode 232 of the twenty-third transistor is separately provided, and the gate electrode 232 of the twenty-third transistor may be shaped like an “h” that is flipped leftward.

[0299] In an exemplary embodiment, as shown in FIG13 and FIG14, the first connection line L1 is located on the side of the gate electrode 42 of the fourth transistor (also the first plate C31 of the third capacitor and the gate electrode 162 of the sixteenth transistor) away from the display area. The shape of the first connection line L1 can be Font.

[0300] In an exemplary embodiment, as shown in Figures 13 and 14, the second connection line L2 is located between the gate electrode 42 of the fourth transistor (also the first plate C31 of the third capacitor and the gate electrode 162 of the sixteenth transistor) and the gate electrode 122 of the twelfth transistor (also the first plate C51 of the fifth capacitor). The second connection line L2 can be strip-shaped and extend along the second direction D2.

[0301] 13 and 14 , the third connection line L3 is located on a side of the gate electrode 232 of the twenty-third transistor close to the display area. The third connection line L3 may be in a strip shape and extend along the second direction D2.

[0302] In an exemplary embodiment, as shown in FIG13 and FIG14 , the gate electrode 12 of the first transistor (also the gate electrode 142 of the fourteenth transistor) is arranged across the active pattern of the first transistor and the active pattern of the fourteenth transistor, the gate electrode 22 of the second transistor (also the gate electrode 82 of the eighth transistor) is arranged across the active pattern of the second transistor and the active pattern of the eighth transistor, the gate electrode 32 of the third transistor is arranged across the active pattern of the third transistor, and the gate electrode 42 of the fourth transistor (also the first plate C31 of the third capacitor and the gate electrode of the sixteenth transistor) is arranged across the active pattern of the second transistor and the active pattern of the eighth transistor. 162) is arranged across the active pattern of the fourth transistor and the active pattern of the sixteenth transistor, the gate electrode 52 of the fifth transistor is arranged across the active pattern of the fifth transistor, the gate electrode 62 of the sixth transistor (also the first plate C11 of the first capacitor) is arranged across the active pattern of the sixth transistor, the gate electrode 72 of the seventh transistor is arranged across the active pattern of the seventh transistor, and any first branch segment of the gate electrode 92 of the ninth transistor (also the first plate C21 of the second capacitor and the gate electrode 182 of the eighteenth transistor) is arranged across the active pattern of the ninth transistor and the eighteenth transistor. The gate electrode 102 of the tenth transistor (also the gate electrode 172 of the seventeenth transistor) is arranged across the active pattern of the tenth transistor and the active pattern of the seventeenth transistor. The gate electrode 112 of the eleventh transistor (also the gate electrode 152 of the fifteenth transistor) is arranged across the active pattern of the eleventh transistor and the active pattern of the fifteenth transistor. The gate electrode 122 of the twelfth transistor (also the first plate C51 of the fifth capacitor) is arranged across the active pattern of the twelfth transistor. The gate electrode 132 of the thirteenth transistor is arranged across It is arranged on the active pattern of the thirteenth transistor, any third branch segment 192B of the gate electrode 192 of the nineteenth transistor (also the fourth capacitor) is arranged across the active pattern of the nineteenth transistor, the gate electrode 202 of the twentieth transistor is arranged across the active pattern of the twentieth transistor, the gate electrode 212 of the twenty-first transistor is arranged across the active pattern of the twenty-first transistor, and the gate electrode 232 of the twenty-third transistor is arranged across the active pattern of the twenty-third transistor. That is, the extension direction of the gate electrode of at least one transistor is perpendicular to the extension direction of the active pattern.

[0303] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform a conductorization process on the first semiconductor layer. The first semiconductor layer in the areas shielded by the first conductive layer forms the channel regions of the first through twenty-first transistors, as well as the twenty-third transistor. The first semiconductor layer in the areas not shielded by the first conductive layer is conductorized. That is, the first and second areas of the active pattern of any of the first through twenty-first transistors, as well as the twenty-third transistor, are both conductorized. As shown in FIG14 , after conductorization, the second area of ​​the active pattern of the twentieth transistor (also the second area of ​​the active pattern of the twenty-first transistor) in this disclosure serves as the second electrode 204 of the twentieth transistor (also the second electrode 214 of the twenty-first transistor).

[0304] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a second insulating film and a second conductive film on a substrate having the aforementioned pattern formed thereon, patterning the second conductive film through a patterning process to form a second insulating layer pattern covering the first conductive layer pattern and a second conductive layer pattern located on the second insulating layer pattern, as shown in FIG15 and FIG16 , FIG15 is a schematic diagram of the second conductive layer pattern in FIG9 , and FIG16 is a schematic diagram of FIG9 after the second conductive layer pattern is formed. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0305] In an exemplary embodiment, as shown in Figures 15 and 16, the second conductive layer pattern may include at least: a first gate electrode 222A of the twenty-second transistor located in each stage of the shift register, a first gate electrode 242A of the twenty-fourth transistor, the second plate C12 of the first capacitor to the second plate C52 of the fifth capacitor, a fourth connecting line L4 and a fifth connecting line L5.

[0306] In an exemplary embodiment, as shown in Figures 15 and 16, the first gate electrode 222A of the 22nd transistor is provided separately. The orthographic projection of the first gate electrode 222A of the 22nd transistor on the substrate is located on the side of the orthographic projection of the gate electrode of the 19th transistor on the substrate closer to the display area, and is located between the orthographic projection of the gate electrode of the 20th transistor on the substrate and the orthographic projection of the third connecting line on the substrate. The first gate electrode 222A of the 22nd transistor can be strip-shaped and extend along the first direction D1.

[0307] In an exemplary embodiment, as shown in Figures 15 and 16, the first gate electrode 242A of the 24th transistor is provided separately. The orthographic projection of the first gate electrode 242A of the 24th transistor on the substrate is located on the side of the orthographic projection of the gate electrode of the 19th transistor on the substrate closer to the display area, and is located between the orthographic projection of the first gate electrode 222A of the 22nd transistor on the substrate and the orthographic projection of the gate electrode of the 20th transistor on the substrate. The first gate electrode 242A of the 24th transistor can be strip-shaped and extend along the first direction D1.

[0308] In an exemplary embodiment, as shown in Figures 15 and 16, the orthographic projection of the second plate C12 of the first capacitor on the substrate at least partially overlaps the orthographic projection of the first plate of the first capacitor on the substrate. The area of ​​the second plate C12 of the first capacitor is smaller than the area of ​​the first plate of the first capacitor. The shape of the second plate C12 of the first capacitor is the same as the shape of the first plate of the first capacitor.

[0309] In an exemplary embodiment, as shown in Figures 15 and 16, the orthographic projection of the second plate C22 of the second capacitor on the substrate at least partially overlaps with the orthographic projection of the first plate of the second capacitor on the substrate, wherein the orthographic projection of the second plate C22 of the second capacitor on the substrate at least partially overlaps with the orthographic projection of the first branch segment on the substrate. The area of ​​the second plate C22 of the second capacitor is smaller than the area of ​​the first plate of the second capacitor. The second plate C22 of the second capacitor can be rectangular, the corners of the rectangle can be chamfered, and the second plate C22 extends along the second direction D2.

[0310] In an exemplary embodiment, as shown in Figures 15 and 16, the orthographic projection of the second plate C32 of the third capacitor on the substrate at least partially overlaps with the orthographic projection of the first plate of the third capacitor on the substrate. The area of ​​the second plate C32 of the third capacitor is smaller than the area of ​​the first plate of the third capacitor. The shape of the second plate C32 of the third capacitor can be rectangular. The orthographic projection of the second plate C32 of the third capacitor on the substrate and the orthographic projection of the first plate of the third capacitor on the substrate have two non-overlapping areas K1 and K2. The shape of the two non-overlapping areas K1 and K2 can be square, and the two non-overlapping areas K1 and K2 expose the first plate of the third capacitor. The shape of the second plate C32 of the third capacitor and the first plate of the third capacitor are not exactly the same. The second plate C32 of the third capacitor can be equivalent to a rectangle with two diagonally opposite corners missing.

[0311] In an exemplary embodiment, as shown in Figures 15 and 16, the orthographic projection of the second plate C42 of the fourth capacitor on the substrate at least partially overlaps with the orthographic projection of the first plate of the fourth capacitor on the substrate, wherein the orthographic projection of the second plate C42 of the fourth capacitor on the substrate at least partially overlaps with the orthographic projection of the protrusion of the third branch segment on the substrate. The shape of the second plate C42 of the fourth capacitor is the same as the shape of the first plate C41 of the fourth capacitor, and the area of ​​the second plate C42 of the fourth capacitor is smaller than the area of ​​the first plate of the fourth capacitor.

[0312] In an exemplary embodiment, as shown in Figures 15 and 16, the orthographic projection of the second plate C52 of the fifth capacitor on the substrate at least partially overlaps the orthographic projection of the first plate of the fifth capacitor on the substrate. The shape of the second plate C52 of the fourth capacitor is the same as the shape of the first plate C51 of the fifth capacitor, and the area of ​​the second plate C52 of the fifth capacitor is smaller than the area of ​​the first plate of the fourth capacitor.

[0313] In an exemplary embodiment, as shown in FIG15 and FIG16 , the orthographic projection of the fourth connection line L4 on the substrate is located between the orthographic projection of the gate electrode of the tenth transistor (also the gate electrode of the seventeenth transistor) on the substrate and the orthographic projection of the gate electrode of the fourth transistor (also the first plate of the third capacitor and the gate electrode of the sixteenth transistor) on the substrate, and is located on the side of the gate electrode of the twelfth transistor (also the first plate of the fifth capacitor) of the current stage shift register close to the next stage shift register. The shape of the fourth connection line L4 can be

[0314] In an exemplary embodiment, as shown in Figures 15 and 16, the orthographic projection of the fifth connection line L5 on the substrate is located between the orthographic projections of the gate electrode of the tenth transistor (also the gate electrode of the seventeenth transistor) and the orthographic projections of the gate electrode of the nineteenth transistor on the substrate, and is disposed around at least one side of the gate electrode of the tenth transistor (also the gate electrode of the seventeenth transistor). The fifth connection line L5 may be shaped like a zigzag line and extend at least partially along the first direction D1.

[0315] (4) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming the second semiconductor layer pattern may include: depositing a third insulating film and a second semiconductor film on the substrate having the aforementioned pattern formed thereon, patterning the second semiconductor film through a patterning process to form a third insulating layer covering the second conductive layer and a second semiconductor pattern disposed on the third insulating layer, as shown in Figures 17 and 18 , where Figure 17 is a schematic diagram of the second semiconductor layer pattern in Figure 9 , and Figure 18 is a schematic diagram of Figure 9 after the second semiconductor layer pattern is formed.

[0316] In example embodiments, as shown in FIG. 17 and FIG. 18 , the second semiconductor layer pattern may include at least an active pattern 221 of a twenty-second transistor and an active pattern 241 of a twenty-fourth transistor.

[0317] In an exemplary embodiment, as shown in FIG. 17 and FIG. 18 , the active pattern 221 of the 22nd transistor of the current stage shift register is located on a side of the active pattern 241 of the 24th transistor close to the next stage shift register.

[0318] 17 and 18, the active pattern 221 of the 22nd transistor is separately provided. The active pattern 221 of the 22nd transistor may be in a stripe shape and extend along the second direction D2.

[0319] 17 and 18, the active pattern 241 of the 24th transistor is separately provided. The active pattern 241 of the 24th transistor may be in a stripe shape and extend along the second direction D2.

[0320] 17 and 18 , the active pattern of each transistor may include a first region, a second region, and a channel region between the first region and the second region. In an exemplary embodiment, the first region 221-1 and the second region 221-2 of the active pattern 221 of the twenty-second transistor and the first region 241-1 and the second region 241-2 of the active pattern 241 of the twenty-fourth transistor are separately provided.

[0321] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a fourth insulating film and a third conductive film on the substrate having the aforementioned pattern formed thereon, patterning the third conductive film through a patterning process to form a fourth insulating layer pattern covering the second semiconductor layer pattern and a third conductive layer pattern located on the fourth insulating layer pattern, as shown in Figures 19 and 20, where Figure 19 is a schematic diagram of the third conductive layer pattern in Figure 9, and Figure 20 is a schematic diagram of Figure 9 after the third conductive layer pattern is formed. In an exemplary embodiment, the third conductive layer may be referred to as a second gate metal (GATE3) layer.

[0322] In exemplary embodiments, as shown in FIG. 19 and FIG. 20 , the third conductive layer pattern may include at least the second gate electrode 222B of the 22nd transistor and the second gate electrode 242B of the 24th transistor in each stage of the shift register, and a sixth connection line L6 .

[0323] In an exemplary embodiment, as shown in Figures 19 and 20, the second gate electrode 222B and the first gate electrode of the twenty-second transistor constitute the gate electrode of the twenty-second transistor. The orthographic projection of the second gate electrode 222B of the twenty-second transistor on the substrate partially overlaps with the orthographic projection of the first gate electrode of the twenty-second transistor on the substrate. The second gate electrode 222B of the twenty-second transistor can be shaped like a "[" and have an opening.

[0324] In an exemplary embodiment, as shown in Figures 19 and 20, the second gate electrode 242B and the first gate electrode of the twenty-fourth transistor constitute the gate electrode of the twenty-fourth transistor. The orthographic projection of the second gate electrode 242B of the twenty-fourth transistor on the substrate partially overlaps with the orthographic projection of the first gate electrode of the twenty-fourth transistor on the substrate and is located within the opening of the second gate electrode 222B of the twenty-second transistor. The second gate electrode 242B of the twenty-fourth transistor can be shaped like a zigzag line and extend at least partially along the first direction D1.

[0325] In an exemplary embodiment, as shown in Figures 19 and 20, the sixth connection line L6 is located within the opening of the second gate electrode 222B of the 22nd transistor and is located on a side of the second gate electrode 242B of the 24th transistor of the current stage that is close to the shift register of the next stage. The sixth connection line L6 is in a strip shape and extends in a direction that intersects the first direction D1 and the second direction D2.

[0326] In exemplary embodiments, as shown in FIG. 19 and FIG. 20 , the second gate electrode 222B of the 22nd transistor straddles the active pattern of the 22nd transistor, and the second gate electrode 242B of the 24th transistor straddles the active pattern of the 24th transistor.

[0327] In an exemplary embodiment, after the third conductive layer pattern is formed, the third conductive layer can be used as a shield to perform conductorization on the second semiconductor layer. The second semiconductor layer in the area blocked by the third conductive layer forms the channel area of ​​the twenty-second transistor and the twenty-fourth transistor, and the second semiconductor layer in the area not blocked by the third conductive layer is conductorized, that is, the first and second areas of the active pattern of any one of the twenty-second transistor and the twenty-fourth transistor are both conductorized.

[0328] (6) Forming a fifth insulating layer pattern. In an exemplary embodiment, forming the fifth insulating layer pattern may include: depositing a fifth insulating film on the substrate having the aforementioned pattern formed thereon, patterning the fifth insulating film through a patterning process to form a fifth insulating layer pattern covering the aforementioned structure, wherein the fifth insulating layer is provided with a plurality of via patterns, as shown in FIG. 21 , which is a schematic diagram of FIG. 9 after the fifth insulating layer pattern is formed.

[0329] In an exemplary embodiment, as shown in FIG. 21 , the fifth insulation layer pattern may include at least first to seventy-first via holes V1 to V11 located at each stage of the shift register.

[0330] In an exemplary embodiment, as shown in FIG21 , the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the first transistor on the substrate, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer within the first via hole V1 are etched away to expose the surface of the first area of ​​the active pattern of the first transistor, and the first via hole V1 is configured to connect the first electrode of the subsequently formed first transistor (also the first electrode of the fourteenth transistor) to the first area of ​​the active pattern of the first transistor through the via hole.

[0331] In an exemplary embodiment, as shown in FIG21 , the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the first transistor on the substrate, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer within the second via hole V2 are etched away to expose the surface of the second area of ​​the active pattern of the first transistor, and the second via hole V2 is configured to connect the second electrode of the subsequently formed first transistor to the second area of ​​the active pattern of the first transistor through the via hole.

[0332] In an exemplary embodiment, as shown in FIG21 , the orthographic projection of the third via V3 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the second transistor on the substrate, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer within the third via V3 are etched away to expose the surface of the first area of ​​the active pattern of the second transistor, and the third via V3 is configured to connect the first electrode of the subsequently formed second transistor to the first area of ​​the active pattern of the second transistor through the via.

[0333] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the fourth via V4 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the second transistor on the substrate, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the fourth via V4 are etched away to expose the surface of the second area of ​​the active pattern of the second transistor, and the fourth via V4 is configured to connect the second electrode of the subsequently formed second transistor (which is also the second electrode of the third transistor and the first electrode of the eleventh transistor) to the second area of ​​the active pattern of the second transistor through the via.

[0334] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the fifth via V5 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the third transistor on the substrate, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the fifth via V5 are etched away to expose the surface of the first area of ​​the active pattern of the third transistor, and the fifth via V5 is configured to connect the first electrode of the subsequently formed third transistor to the first area of ​​the active pattern of the third transistor through the via.

[0335] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the third transistor on the substrate, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the sixth via V6 are etched away to expose the surface of the second area of ​​the active pattern of the third transistor, and the sixth via V6 is configured to connect the second electrode of the subsequently formed second transistor (which is also the second electrode of the third transistor and the first electrode of the eleventh transistor) to the second area of ​​the active pattern of the third transistor through the via.

[0336] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the fourth transistor on the substrate, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the seventh via V7 are etched away to expose the surface of the first area of ​​the active pattern of the fourth transistor, and the seventh via V7 is configured to connect the first electrode of the subsequently formed fourth transistor to the first area of ​​the active pattern of the fourth transistor through the via.

[0337] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the fourth transistor on the substrate, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the eighth via V8 are etched away to expose the surface of the second area of ​​the active pattern of the fourth transistor, and the eighth via V8 is configured to connect the second electrode of the subsequently formed fourth transistor (which is also the second electrode of the fifth transistor) to the second area of ​​the active pattern of the fourth transistor through the via.

[0338] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the fifth transistor (also the first area of ​​the active pattern of the eighth transistor and the first area of ​​the active pattern of the thirteenth transistor) on the substrate, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the ninth via V9 are etched away to expose the surface of the second area of ​​the active pattern of the fourth transistor, and the ninth via V9 is configured to connect the first electrode of the subsequently formed fifth transistor (also the first electrode of the eighth transistor, the first electrode of the ninth transistor and the first electrode of the thirteenth transistor) to the first area of ​​the active pattern of the fifth transistor (also the first area of ​​the active pattern of the eighth transistor and the first area of ​​the active pattern of the thirteenth transistor) through the via.

[0339] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the tenth via V10 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the fifth transistor on the substrate, and the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the tenth via V10 are etched away to expose the surface of the second area of ​​the active pattern of the fifth transistor. The tenth via V10 is configured to connect the second electrode of the subsequently formed fourth transistor (which is also the second electrode of the fifth transistor) to the second area of ​​the active pattern of the fifth transistor through the via.

[0340] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the eleventh via V11 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the sixth transistor on the substrate, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the eleventh via V11 are etched away to expose the surface of the first area of ​​the active pattern of the sixth transistor, and the eleventh via V11 is configured to connect the first electrode of the subsequently formed sixth transistor to the first area of ​​the active pattern of the sixth transistor through the via.

[0341] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the twelfth via V12 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the sixth transistor on the substrate, and the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the twelfth via V12 are etched away to expose the surface of the second area of ​​the active pattern of the sixth transistor. The twelfth via V12 is configured to connect the second electrode of the subsequently formed sixth transistor (which is also the first electrode of the seventh transistor) to the second area of ​​the active pattern of the sixth transistor through the via.

[0342] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the thirteenth via V13 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the seventh transistor on the substrate, and the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the thirteenth via V13 are etched away to expose the surface of the first area of ​​the active pattern of the seventh transistor. The thirteenth via V13 is configured to connect the second electrode of the subsequently formed sixth transistor (which is also the first electrode of the seventh transistor) to the first area of ​​the active pattern of the seventh transistor through the via.

[0343] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the fourteenth via V14 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the seventh transistor on the substrate, and the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the fourteenth via V14 are etched away to expose the surface of the second area of ​​the active pattern of the seventh transistor. The fourteenth via V14 is configured to connect the second electrode of the subsequently formed seventh transistor (which is also the second electrode of the eighth transistor) to the second area of ​​the active pattern of the seventh transistor through the via.

[0344] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the fifteenth via V15 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the eighth transistor on the substrate, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the fifteenth via V15 are etched away to expose the surface of the second area of ​​the active pattern of the eighth transistor, and the fifteenth via V15 is configured to connect the second electrode of the subsequently formed seventh transistor (which is also the second electrode of the eighth transistor) to the second area of ​​the active pattern of the eighth transistor through the via.

[0345] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the sixteenth via V16 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the ninth transistor on the substrate, and the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the sixteenth via V16 are etched away to expose the surface of the first area of ​​the active pattern of the ninth transistor. The sixteenth via V16 is configured to connect the first electrode of the subsequently formed fifth transistor (which is also the first electrode of the eighth transistor, the first electrode of the ninth transistor and the first electrode of the thirteenth transistor) to the first area of ​​the active pattern of the ninth transistor through the via.

[0346] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the seventeenth via V17 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the ninth transistor (also the second area of ​​the active pattern of the tenth transistor) on the substrate, and the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the seventeenth via V17 are etched away to expose the surface of the second area of ​​the active pattern of the ninth transistor (also the second area of ​​the active pattern of the tenth transistor), and the seventeenth via V17 is configured to connect the second electrode of the subsequently formed ninth transistor (also the second electrode of the tenth transistor) to the second area of ​​the active pattern of the ninth transistor (also the second area of ​​the active pattern of the tenth transistor) through the via.

[0347] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the eighteenth via V18 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the tenth transistor on the substrate, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the eighteenth via V18 are etched away to expose the surface of the first area of ​​the active pattern of the tenth transistor, and the eighteenth via V18 is configured to connect the first electrode of the subsequently formed tenth transistor to the first area of ​​the active pattern of the tenth transistor through the via.

[0348] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the nineteenth via V19 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the eleventh transistor on the substrate, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the nineteenth via V19 are etched away to expose the surface of the first area of ​​the active pattern of the eleventh transistor, and the nineteenth via V19 is configured to connect the second electrode of the subsequently formed second transistor (which is also the second electrode of the third transistor and the first electrode of the eleventh transistor) to the first area of ​​the active pattern of the eleventh transistor through the via.

[0349] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the twentieth via V20 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the eleventh transistor on the substrate, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the twentieth via V20 are etched away to expose the surface of the second area of ​​the active pattern of the eleventh transistor, and the twentieth via V20 is configured to connect the second electrode of the subsequently formed eleventh transistor to the second area of ​​the active pattern of the eleventh transistor through the via.

[0350] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the twenty-first via V21 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the twelfth transistor on the substrate, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the twenty-first via V21 are etched away to expose the surface of the first area of ​​the active pattern of the twelfth transistor, and the twenty-first via V21 is configured to connect the first electrode of the subsequently formed twelfth transistor to the first area of ​​the active pattern of the twelfth transistor through the via.

[0351] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the twenty-second via V22 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the twelfth transistor (also the second area of ​​the active pattern of the sixteenth transistor) on the substrate, and the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the twenty-second via V22 are etched away to expose the surface of the second area of ​​the active pattern of the twelfth transistor (also the second area of ​​the active pattern of the sixteenth transistor), and the twenty-second via V22 is configured to connect the second electrode of the subsequently formed twelfth transistor (also the second electrode of the sixteenth transistor) to the second area of ​​the active pattern of the twelfth transistor (also the second area of ​​the active pattern of the sixteenth transistor) through the via.

[0352] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the twenty-third via V23 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the thirteenth transistor on the substrate, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the twenty-third via V23 are etched away to expose the surface of the second area of ​​the active pattern of the thirteenth transistor, and the twenty-third via V23 is configured to connect the second electrode of the subsequently formed thirteenth transistor to the second area of ​​the active pattern of the thirteenth transistor through the via.

[0353] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the twenty-fourth via V24 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the fourteenth transistor on the substrate, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the twenty-fourth via V24 are etched away to expose the surface of the first area of ​​the active pattern of the fourteenth transistor, and the twenty-fourth via V24 is configured to connect the first electrode of the subsequently formed first transistor (which is also the first electrode of the fourteenth transistor) to the first area of ​​the active pattern of the fourteenth transistor through the via.

[0354] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the twenty-fifth via V25 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the fourteenth transistor on the substrate, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the twenty-fifth via V25 are etched away to expose the surface of the second area of ​​the active pattern of the fourteenth transistor, and the twenty-fifth via V25 is configured to connect the second electrode of the subsequently formed fourteenth transistor (which is also the first electrode of the fifteenth transistor) to the second area of ​​the active pattern of the fourteenth transistor through the via.

[0355] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the twenty-sixth via V26 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the fifteenth transistor on the substrate, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the twenty-sixth via V26 are etched away to expose the surface of the first area of ​​the active pattern of the fifteenth transistor, and the twenty-sixth via V26 is configured to connect the second electrode of the subsequently formed fourteenth transistor (which is also the first electrode of the fifteenth transistor) to the first area of ​​the active pattern of the fifteenth transistor through the via.

[0356] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the twenty-seventh via V27 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the fifteenth transistor on the substrate, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the twenty-seventh via V27 are etched away to expose the surface of the second area of ​​the active pattern of the fifteenth transistor, and the twenty-seventh via V27 is configured to connect the second electrode of the subsequently formed fifteenth transistor to the second area of ​​the active pattern of the fifteenth transistor through the via.

[0357] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the twenty-eighth via V28 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the sixteenth transistor on the substrate, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the twenty-eighth via V28 are etched away to expose the surface of the first area of ​​the active pattern of the sixteenth transistor, and the twenty-eighth via V28 is configured to connect the first electrode of the subsequently formed sixteenth transistor to the first area of ​​the active pattern of the sixteenth transistor through the via.

[0358] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the twenty-ninth via V29 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the seventeenth transistor on the substrate, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the twenty-ninth via V29 are etched away to expose the surface of the first area of ​​the active pattern of the seventeenth transistor, and the twenty-ninth via V29 is configured to connect the first electrode of the subsequently formed seventeenth transistor to the first area of ​​the active pattern of the seventeenth transistor through the via.

[0359] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the 30th via V30 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the seventeenth transistor on the substrate, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the 30th via V30 are etched away to expose the surface of the second area of ​​the active pattern of the seventeenth transistor, and the 30th via V30 is configured to connect the second electrode of the subsequently formed seventeenth transistor (which is also the second electrode of the nineteenth transistor and the second electrode of the twenty-fourth transistor) to the second area of ​​the active pattern of the seventeenth transistor through the via.

[0360] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the thirty-first via V31 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the eighteenth transistor on the substrate, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the thirty-first via V31 are etched away to expose the surface of the first area of ​​the active pattern of the eighteenth transistor, and the thirty-first via V31 is configured to connect the first electrode of the subsequently formed eighteenth transistor to the first area of ​​the active pattern of the eighteenth transistor through the via.

[0361] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the thirty-second via V32 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the eighteenth transistor on the substrate, and the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the thirty-second via V32 are etched away to expose the surface of the second area of ​​the active pattern of the eighteenth transistor. The thirty-second via V32 is configured to connect the second electrode of the subsequently formed eighteenth transistor (which is also the first electrode of the nineteenth transistor) to the second area of ​​the active pattern of the eighteenth transistor through the via.

[0362] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the thirty-third via V33 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the nineteenth transistor on the substrate, and the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the thirty-third via V33 are etched away to expose the surface of the first area of ​​the active pattern of the nineteenth transistor. The thirty-third via V33 is configured to connect the second electrode of the subsequently formed eighteenth transistor (which is also the first electrode of the nineteenth transistor) to the first area of ​​the active pattern of the nineteenth transistor through the via.

[0363] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the thirty-fourth via V34 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the nineteenth transistor on the substrate, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the thirty-fourth via V34 are etched away to expose the surface of the second area of ​​the active pattern of the nineteenth transistor, and the thirty-fourth via V34 is configured to connect the second electrode of the subsequently formed seventeenth transistor (which is also the second electrode of the nineteenth transistor and the second electrode of the twenty-fourth transistor) to the second area of ​​the active pattern of the nineteenth transistor through the via.

[0364] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the thirty-fifth via V35 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the twentieth transistor on the substrate, and the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the thirty-fifth via V35 are etched away to expose the surface of the first area of ​​the active pattern of the twentieth transistor. The thirty-fifth via V35 is configured to connect the first electrode of the subsequently formed twentieth transistor to the first area of ​​the active pattern of the twentieth transistor through the via.

[0365] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the thirty-sixth via V36 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the twenty-first transistor on the substrate, and the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the thirty-sixth via V36 are etched away to expose the surface of the first area of ​​the active pattern of the twenty-first transistor. The thirty-sixth via V36 is configured to connect the first electrode of the subsequently formed twenty-first transistor to the first area of ​​the active pattern of the twenty-first transistor through the via.

[0366] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the thirty-seventh via V37 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the twenty-second transistor on the substrate, the fourth insulating layer in the thirty-seventh via V37 is etched away, exposing the surface of the first area of ​​the active pattern of the twenty-second transistor, and the thirty-seventh via V37 is configured to connect the first electrode of the subsequently formed twenty-second transistor to the first area of ​​the active pattern of the twenty-first transistor through the via.

[0367] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the thirty-eighth via V38 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the twenty-second transistor on the substrate, the fourth insulating layer in the thirty-eighth via V38 is etched away, exposing the surface of the second area of ​​the active pattern of the twenty-second transistor, and the thirty-eighth via V38 is configured to connect the second electrode of the subsequently formed twenty-second transistor (which is also the second electrode of the twenty-third transistor) to the second area of ​​the active pattern of the twenty-first transistor through the via.

[0368] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the thirty-ninth via V39 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the twenty-third transistor on the substrate, and the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the thirty-ninth via V39 are etched away to expose the surface of the first area of ​​the active pattern of the twenty-third transistor. The thirty-ninth via V39 is configured to connect the first electrode of the subsequently formed twenty-third transistor to the first area of ​​the active pattern of the twenty-third transistor through the via.

[0369] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the 40th via V40 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the twenty-third transistor on the substrate, the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer in the 40th via V40 are etched away to expose the surface of the second area of ​​the active pattern of the twenty-third transistor, and the 40th via V40 is configured to connect the second electrode of the subsequently formed twenty-second transistor (which is also the second electrode of the twenty-third transistor) to the second area of ​​the active pattern of the twenty-third transistor through the via.

[0370] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the forty-first via V41 on the substrate is located within the range of the orthographic projection of the first area of ​​the active pattern of the twenty-fourth transistor on the substrate, the fourth insulating layer in the forty-first via V41 is etched away, exposing the surface of the first area of ​​the active pattern of the twenty-fourth transistor, and the forty-first via V41 is configured to connect the first electrode of the subsequently formed twenty-fourth transistor to the first area of ​​the active pattern of the twenty-fourth transistor through the via.

[0371] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the forty-second via V42 on the substrate is located within the range of the orthographic projection of the second area of ​​the active pattern of the twenty-fourth transistor on the substrate, the fourth insulating layer in the forty-second via V42 is etched away to expose the surface of the second area of ​​the active pattern of the twenty-fourth transistor, and the forty-second via V42 is configured to connect the second electrode of the subsequently formed seventeenth transistor (which is also the second electrode of the nineteenth transistor and the second electrode of the twenty-fourth transistor) to the second area of ​​the active pattern of the twenty-fourth transistor through the via.

[0372] In an exemplary embodiment, as shown in FIG21 , the orthographic projection of the forty-third via V43 on the substrate is located within the range of the orthographic projection of the gate electrode of the first transistor (also the gate electrode of the fourteenth transistor) on the substrate. The second insulating layer, the third insulating layer, and the fourth insulating layer within the forty-third via V43 are etched away, exposing the surface of the gate electrode of the first transistor (also the gate electrode of the fourteenth transistor). The forty-third via V43 is configured to connect one of the subsequently formed first and second clock signal lines and the first electrode of the second transistor to the gate electrode of the first transistor (also the gate electrode of the fourteenth transistor) through the via. FIG21 is illustrative using the connection between the first clock signal line and the gate electrode of the first transistor (also the gate electrode of the fourteenth transistor) as an example.

[0373] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the forty-fourth via V44 on the substrate is located within the range of the orthographic projection of the gate electrode of the second transistor (also the gate electrode of the eighth transistor) on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the forty-fourth via V44 are etched away to expose the surface of the gate electrode of the second transistor (also the gate electrode of the eighth transistor), and the forty-fourth via V44 is configured to connect the second electrode of the first transistor and the second electrode of the thirteenth transistor formed subsequently to the gate electrode of the second transistor (also the gate electrode of the eighth transistor) through the via.

[0374] In an exemplary embodiment, as shown in FIG21 , the orthographic projection of the forty-fifth via V45 on the substrate is located within the orthographic projection of the gate electrode of the third transistor on the substrate. The second, third, and fourth insulating layers within the forty-fifth via V45 are etched away, exposing the surface of the gate electrode of the third transistor. The forty-fifth via V45 is configured to connect one of the subsequently formed first and second clock signal lines to the gate electrode of the third transistor through the via. FIG21 is illustrative using the first clock signal line as an example.

[0375] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the forty-sixth via V46 on the substrate is located within the range of the orthographic projection of the gate electrode of the fourth transistor (which is also the gate electrode of the sixteenth transistor and the first plate of the third capacitor) on the substrate, and the second insulating layer, the third insulating layer and the fourth insulating layer in the forty-sixth via V46 are etched away to expose the surface of the gate electrode of the fourth transistor (which is also the gate electrode of the sixteenth transistor and the first plate of the third capacitor), and the forty-sixth via V46 is configured to connect the second electrode of the fifteenth transistor and the first electrode of the sixteenth transistor formed subsequently to the gate electrode of the fourth transistor (which is also the gate electrode of the sixteenth transistor and the first plate of the third capacitor) through the via.

[0376] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the forty-seventh via V47 on the substrate is located within the range of the orthographic projection of the gate electrode of the fifth transistor on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the forty-seventh via V47 are etched away to expose the surface of the gate electrode of the fifth transistor, and the forty-seventh via V47 is configured to connect the second electrode of the subsequently formed second transistor (which is also the second electrode of the third transistor and the first electrode of the eleventh transistor) to the gate electrode of the fifth transistor through the via.

[0377] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the forty-eight via V48 on the substrate is located within the range of the orthographic projection of the gate electrode of the sixth transistor (the first plate of the first capacitor) on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the forty-eight via V48 are etched away to expose the surface of the gate electrode of the sixth transistor (the first plate of the first capacitor), and the forty-eighth via V48 is configured to connect the second electrode of the subsequently formed eleventh transistor to the gate electrode of the sixth transistor (the first plate of the first capacitor) through the via.

[0378] In an exemplary embodiment, as shown in FIG21 , the orthographic projection of the forty-ninth via V49 on the substrate is within the range of the orthographic projection of the gate electrode of the seventh transistor on the substrate. The second, third, and fourth insulating layers within the forty-ninth via V49 are etched away, exposing the surface of the gate electrode of the seventh transistor. The forty-ninth via V49 is configured to connect the other of the subsequently formed first and second clock signal lines and the first electrode of the sixth transistor to the gate electrode of the seventh transistor through the via. FIG21 is illustrated using the second clock signal line as an example.

[0379] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the fiftieth via V50 on the substrate is located within the range of the orthographic projection of the gate electrode of the ninth transistor (also the gate electrode of the eighteenth transistor and the first plate of the second capacitor) on the substrate, and the second insulating layer, the third insulating layer and the fourth insulating layer in the fiftieth via V50 are etched away to expose the surface of the gate electrode of the ninth transistor (also the gate electrode of the eighteenth transistor and the first plate of the second capacitor), and the fiftieth via V50 is configured to connect the second electrode of the subsequently formed seventh transistor (also the second electrode of the eighth transistor) to the gate electrode of the ninth transistor (also the gate electrode of the eighteenth transistor and the first plate of the second capacitor) through the via.

[0380] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the fifty-first via V51 on the substrate is located within the range of the orthographic projection of the gate electrode of the tenth transistor (also the gate electrode of the seventeenth transistor) on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the fifty-first via V51 are etched away to expose the surface of the gate electrode of the tenth transistor (also the gate electrode of the seventeenth transistor), and the fifty-first via V51 is configured to connect the second electrode of the subsequently formed twelfth transistor (also the second electrode of the sixteenth transistor) to the gate electrode of the tenth transistor (also the gate electrode of the seventeenth transistor) through the via.

[0381] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the fifty-second via V52 on the substrate is located within the range of the orthographic projection of the gate electrode of the eleventh transistor (also the gate electrode of the fifteenth transistor) on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the fifty-second via V52 are etched away to expose the surface of the gate electrode of the eleventh transistor (also the gate electrode of the fifteenth transistor), and the fifty-second via V52 is configured to connect the first electrode of the subsequently formed third transistor to the gate electrode of the eleventh transistor (also the gate electrode of the fifteenth transistor) through the via.

[0382] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the fifty-third via V53 on the substrate is located within the range of the orthographic projection of the gate electrode of the twelfth transistor (also the first plate of the fifth capacitor) on the substrate, and the second insulating layer, the third insulating layer and the fourth insulating layer in the fifty-third via V53 are etched away to expose the surface of the gate electrode of the twelfth transistor (also the first plate of the fifth capacitor), and the fifty-third via V53 is configured to connect the first electrode of the subsequently formed tenth transistor to the gate electrode of the twelfth transistor (also the first plate of the fifth capacitor) through the via.

[0383] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the fifty-fourth via V54 on the substrate is located within the range of the orthographic projection of the gate electrode of the thirteenth transistor on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the fifty-fourth via V54 are etched away to expose the surface of the gate electrode of the thirteenth transistor, and the fifty-fourth via V54 is configured to connect a subsequently formed third power line to the gate electrode of the thirteenth transistor through the via.

[0384] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the fifty-fifth via V55 on the substrate is located within the range of the orthographic projection of the gate electrode of the nineteenth transistor on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the fifty-fifth via V55 are etched away to expose the surface of the gate electrode of the nineteenth transistor, and the fifty-fifth via V55 is configured to connect the first electrode of the subsequently formed twentieth transistor to the gate electrode of the nineteenth transistor through the via.

[0385] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the fifty-sixth via V56 on the substrate is located within the range of the orthographic projection of the gate electrode of the twentieth transistor on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the fifty-sixth via V56 are etched away to expose the surface of the gate electrode of the twentieth transistor, and the fifty-sixth via V56 is configured to connect the subsequently formed seventh connecting portion to the gate electrode of the twentieth transistor through the via.

[0386] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the fifty-seventh via V57 on the substrate is located within the range of the orthographic projection of the first gate electrode of the twenty-second transistor on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the fifty-seventh via V57 are etched away to expose the surface of the first gate electrode of the twenty-second transistor, and the fifty-seventh via V57 is configured to connect the subsequently formed eighth connecting line to the first gate electrode of the twenty-second transistor through the via.

[0387] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the fifty-eighth via V58 on the substrate is located within the range of the orthographic projection of the second gate electrode of the twenty-second transistor on the substrate, the fifty-eighth via V58 exposes the surface of the second gate electrode of the twenty-second transistor, and the fifty-eighth via V58 is configured to connect the subsequently formed eighth connecting line and the seventh connecting line to the second gate electrode of the twenty-second transistor through the via.

[0388] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the fifty-ninth via V59 on the substrate is located within the range of the orthographic projection of the gate electrode of the twenty-third transistor on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the fifty-ninth via V59 are etched away to expose the surface of the gate electrode of the twenty-third transistor, and the fifty-ninth via V59 is configured to connect the subsequently formed eighth connecting line and the ninth connecting line to the gate electrode of the twenty-third transistor through the via.

[0389] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the 60th via V60 on the substrate is located within the range of the orthographic projection of the first gate electrode of the 24th transistor on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the 60th via V60 are etched away to expose the surface of the first gate electrode of the 24th transistor, and the 60th via V60 is configured to connect the first pole of the 20th transistor formed subsequently to the first gate electrode of the 24th transistor through the via.

[0390] In an exemplary embodiment, as shown in FIG21 , the orthographic projection of the sixty-first via V61 on the substrate is located within the range of the orthographic projection of the second gate electrode of the twenty-fourth transistor on the substrate, the sixty-first via V61 exposes the surface of the second gate electrode of the twenty-fourth transistor, and the sixty-first via V61 is configured to connect the first electrode of the subsequently formed twentieth transistor to the second gate electrode of the twenty-fourth transistor through the via.

[0391] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the sixty-second via V62 on the substrate is located within the range of the orthographic projection of the first connecting line on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the sixty-second via V62 are etched away to expose the surface of the first connecting line, and the sixty-second via V62 is configured to connect the subsequently formed first clock signal line and the other of the second clock signal lines and the first electrode of the fourth transistor to the first connecting line through the via.

[0392] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the sixty-third via V63 on the substrate is located within the range of the orthographic projection of the second connecting line on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the sixty-third via V63 are etched away to expose the surface of the second connecting line, and the sixty-third via V63 is configured to connect the first electrode of the twelfth transistor and the second electrode of the thirteenth transistor formed subsequently to the second connecting line through the via.

[0393] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the sixty-fourth via V64 on the substrate is located within the range of the orthographic projection of the third connecting line on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the sixty-fourth via V64 are etched away to expose the surface of the third connecting line, and the sixty-fourth via V64 is configured to connect the second electrode of the subsequently formed twenty-second transistor (which is also the second electrode of the twenty-third transistor) to the third connecting line through the via.

[0394] In an exemplary embodiment, as shown in FIG21 , the orthographic projection of the sixty-fifth via V65 on the substrate is located within the range of the orthographic projection of the second plate of the first capacitor on the substrate, the third insulating layer and the fourth insulating layer within the sixty-fifth via V65 are etched away to expose the surface of the second plate of the first capacitor, and the sixty-fifth via V65 is configured to connect the second electrode of the subsequently formed sixth transistor (which is also the first electrode of the seventh transistor) to the second plate of the first capacitor through the via.

[0395] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the sixty-sixth via V66 on the substrate is located within the range of the orthographic projection of the second plate of the second capacitor on the substrate, the third insulating layer and the fourth insulating layer in the sixty-sixth via V66 are etched away to expose the surface of the second plate of the second capacitor, and the sixty-sixth via V66 is configured to connect the first electrode of the subsequently formed fifth transistor (which is also the first electrode of the eighth transistor, the first electrode of the ninth transistor, and the first electrode of the thirteenth transistor) to the second plate of the second capacitor through the via.

[0396] In an exemplary embodiment, as shown in FIG21 , the orthographic projection of the sixty-seventh via V67 on the substrate is located within the range of the orthographic projection of the second plate of the third capacitor on the substrate, the third insulating layer and the fourth insulating layer within the sixty-seventh via V67 are etched away to expose the surface of the second plate of the third capacitor, and the sixty-seventh via V67 is configured to connect the second electrode of the subsequently formed fourth transistor (which is also the second electrode of the fifth transistor) to the second plate of the third capacitor through the via.

[0397] In an exemplary embodiment, as shown in FIG21 , the orthographic projection of the sixty-eighth via V68 on the substrate is located within the range of the orthographic projection of the second plate of the fourth capacitor on the substrate, the third insulating layer and the fourth insulating layer within the sixty-eighth via V68 are etched away to expose the surface of the second plate of the fourth capacitor, and the sixty-eighth via V68 is configured to connect the subsequently formed tenth connecting line to the second plate of the fourth capacitor through the via.

[0398] In an exemplary embodiment, as shown in FIG21 , the orthographic projection of the sixty-ninth via V69 on the substrate is located within the range of the orthographic projection of the second plate of the fifth capacitor on the substrate, the third insulating layer and the fourth insulating layer within the sixty-ninth via V69 are etched away to expose the surface of the second plate of the fifth capacitor, and the sixty-ninth via V69 is configured to connect the second electrode of the subsequently formed ninth transistor (which is also the second electrode of the tenth transistor) to the second plate of the fifth capacitor through the via.

[0399] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the seventieth via V70 on the substrate is located within the range of the orthographic projection of the fourth connecting line on the substrate, the third insulating layer and the fourth insulating layer in the seventieth via V70 are etched away to expose the surface of the fourth connecting line, and the seventieth via V70 is configured to connect the second electrode of the subsequently formed ninth transistor (which is also the second electrode of the tenth transistor) and the eleventh connecting line to the fourth connecting line through the via.

[0400] In an exemplary embodiment, as shown in Figure 21, the orthographic projection of the seventy-first via V71 on the substrate is located within the range of the orthographic projection of the fifth connecting line on the substrate, the third insulating layer and the fourth insulating layer in the seventy-first via V71 are etched away to expose the surface of the fifth connecting line, and the seventy-first via V71 is configured to connect the second electrode of the subsequently formed ninth transistor (which is also the second electrode of the tenth transistor) and the ninth connecting line to the fifth connecting line through the via.

[0401] In an exemplary embodiment, as shown in FIG21 , the orthographic projection of the seventy-second via V72 on the substrate is located within the range of the orthographic projection of the sixth connecting line on the substrate, the seventy-second via V72 exposes the surface of the sixth connecting line, and the seventy-second via V72 is configured to connect the second electrode of the subsequently formed seventeenth transistor (which is also the second electrode of the nineteenth transistor and the second electrode of the twenty-fourth transistor) to the sixth connecting line through the via.

[0402] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the fifth insulating layer, as shown in Figures 22 and 23, where Figure 22 is a schematic diagram of the fourth conductive layer pattern in Figure 9, and Figure 23 is a schematic diagram of Figure 9 after the fourth conductive layer pattern is formed. In an exemplary embodiment, the fourth conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0403] In an exemplary embodiment, as shown in Figures 22 and 23, the fourth conductive layer pattern may include at least: an initial signal line STV, a first clock signal line CLK1, a second clock signal line CLK2, a third power line VEL and the first electrode 13 and the second electrode 14 of the first transistor located in each stage of the shift register to the first electrode 193 and the second electrode 194 of the nineteenth transistor, the first electrode 203 of the twentieth transistor, the first electrode 213 of the twenty-first transistor, the first electrode 222 and the second electrode 224 of the twenty-second transistor to the first electrode 243 and the second electrode 244 of the twenty-fourth transistor, and the seventh connecting line L7 to the twelfth connecting line L12.

[0404] In an exemplary embodiment, as shown in Figures 22 and 23, the first electrode 13 of the first transistor and the first electrode 143 of the fourteenth transistor are integrally formed. The first electrode 13 of the first transistor (also the first electrode 143 of the fourteenth transistor) is shaped like a zigzag line and extends at least partially along the first direction D1. The first electrode 13 of the first transistor (also the first electrode 143 of the fourteenth transistor) is connected to the first region of the active pattern of the first transistor via a first via, and is connected to the first region of the active pattern of the fourteenth transistor via a twenty-fourth via.

[0405] In an exemplary embodiment, as shown in Figures 22 and 23, the second electrode 14 of the first transistor is provided separately. The second electrode 14 of the first transistor is strip-shaped and extends along the second direction D2. The second electrode 14 of the first transistor is connected to the second region of the active pattern of the first transistor through a second via hole, and is connected to the gate electrode of the second transistor (also the gate electrode of the eighth transistor) through a forty-fourth via hole.

[0406] In an exemplary embodiment, as shown in Figures 22 and 23, the first electrode 23 of the second transistor is provided separately. The first electrode 23 of the second transistor is strip-shaped and extends along the second direction D2. The first electrode 23 of the second transistor is connected to the first region of the active pattern of the second transistor through the third via hole, and is connected to the gate electrode of the first transistor (also the gate electrode of the fourteenth transistor) through the forty-third via hole.

[0407] In an exemplary embodiment, as shown in Figures 22 and 23, the second electrode 24 of the second transistor, the second electrode 34 of the third transistor, and the first electrode 113 of the eleventh transistor are integrally formed. The integral structure of the second electrode 24 of the second transistor, the second electrode 34 of the third transistor, and the first electrode 113 of the eleventh transistor is in the shape of a broken line and extends at least partially along the second direction D2. The second electrode 24 of the second transistor (also the second electrode 34 of the third transistor and the first electrode 113 of the eleventh transistor) is connected to the second region of the active pattern of the second transistor via a fourth via, to the second region of the active pattern of the third transistor via a sixth via, to the first region of the active pattern of the eleventh transistor via a nineteenth via, and to the gate electrode of the fifth transistor via a forty-seventh via.

[0408] In an exemplary embodiment, as shown in Figures 22 and 23, the first electrode 33 of the third transistor is provided separately. The first electrode 33 of the third transistor is strip-shaped and extends along the second direction D2. The first electrode 33 of the third transistor is connected to the first region of the active pattern of the third transistor through a fifth via hole, and is connected to the gate electrode of the eleventh transistor (also the gate electrode of the fifteenth transistor) through a fifty-second via hole.

[0409] In an exemplary embodiment, as shown in Figures 22 and 23, the first electrode 43 of the fourth transistor is provided separately. The first electrode 43 of the fourth transistor is strip-shaped and extends at least partially along the first direction D1. The first electrode 43 of the fourth transistor is connected to the first region of the active pattern of the fourth transistor through the seventh via hole and is connected to the first connection line through the sixty-second via hole.

[0410] In an exemplary embodiment, as shown in FIG22 and FIG23, the second electrode 44 of the fourth transistor and the second electrode 54 of the fifth transistor are provided as an integral structure. The shape of the integral structure of the second electrode 44 of the fourth transistor and the second electrode 54 of the fifth transistor is The second electrode 44 of the fourth transistor (also the second electrode 54 of the fifth transistor) is connected to the second region of the active pattern of the fourth transistor through the eighth via, connected to the second region of the active pattern of the fifth transistor through the tenth via, and connected to the second plate of the third capacitor through the sixty-seventh via.

[0411] In an exemplary embodiment, as shown in Figures 22 and 23, the first electrode 53 of the fifth transistor, the first electrode 83 of the eighth transistor, the first electrode 93 of the ninth transistor, and the first electrode 133 of the thirteenth transistor are integrated into an integral structure, and the integrated structure of the first electrode 53 of the fifth transistor, the first electrode 83 of the eighth transistor, the first electrode 93 of the ninth transistor, and the first electrode 133 of the thirteenth transistor forms an "E" shape. The first electrode 53 of the fifth transistor (which is also the first electrode 83 of the eighth transistor, the first electrode 83 of the ninth transistor, and the first electrode 133 of the thirteenth transistor) is connected to the first area of ​​the active pattern of the fifth transistor (which is also the first area of ​​the active pattern of the eighth transistor and the first area of ​​the active pattern of the thirteenth transistor) via a ninth via, is connected to the first area of ​​the active pattern of the ninth transistor via a sixteenth via, and is connected to the second plate of the second capacitor via a sixty-sixth via.

[0412] In the exemplary embodiment, as shown in Figures 22 and 23, the first electrode 63 of the sixth transistor is provided separately. The first electrode 63 of the sixth transistor is shaped like an "I". The first electrode 63 of the sixth transistor is connected to the first region of the active pattern of the sixth transistor through the eleventh via hole, and is connected to the gate electrode of the seventh transistor through the forty-ninth via hole.

[0413] In an exemplary embodiment, as shown in FIG22 and FIG23, the second electrode 64 of the sixth transistor and the first electrode 73 of the seventh transistor are an integral structure. The shape of the integral structure of the second electrode 64 of the sixth transistor and the first electrode 73 of the seventh transistor is The second electrode 64 of the sixth transistor (also the first electrode 73 of the seventh transistor) is connected to the second region of the active pattern of the sixth transistor through a twelfth via, connected to the first region of the active pattern of the seventh transistor through a thirteenth via, and connected to the second plate of the first capacitor through a sixty-fifth via.

[0414] In an exemplary embodiment, as shown in Figures 22 and 23, the second electrode 74 of the seventh transistor and the second electrode 84 of the eighth transistor are integrally formed. The integral structure of the second electrode 74 of the seventh transistor and the second electrode 84 of the eighth transistor is strip-shaped and extends along a first direction D1. The second electrode 74 of the seventh transistor (also the second electrode 84 of the eighth transistor) is connected to the second region of the active pattern of the seventh transistor via a fourteenth via, to the second region of the active pattern of the eighth transistor via a fifteenth via, and to the gate electrode of the ninth transistor (also the gate electrode of the eighteenth transistor and the first plate of the second capacitor) via a fiftieth via.

[0415] In an exemplary embodiment, as shown in Figures 22 and 23, the second electrode 94 of the ninth transistor and the first electrode 104 of the tenth transistor are integrally formed. The integral structure of the second electrode 94 of the ninth transistor and the first electrode 104 of the tenth transistor is shaped like a comb, with the teeth of the comb located on the side of the comb back away from the display area. The second electrode 94 of the ninth transistor (also the first electrode 104 of the tenth transistor) is connected to the second area of ​​the active pattern of the ninth transistor (also the second area of ​​the active pattern of the tenth transistor) via the seventeenth via, connected to the second plate of the fifth capacitor via the sixty-ninth via, connected to the fourth connection line via the seventieth via, and connected to the fifth connection line via the seventy-first via.

[0416] In an exemplary embodiment, as shown in Figures 22 and 23, the first electrode 103 of the tenth transistor can be provided separately. The first electrode 103 of the tenth transistor is shaped like a "[". The first electrode 103 of the tenth transistor is connected to the first region of the active pattern of the tenth transistor through an eighteenth via hole, and is connected to the gate electrode of the twelfth transistor (which is also the first plate of the fifth capacitor) through a fifty-third via hole.

[0417] In an exemplary embodiment, as shown in Figures 22 and 23, the second electrode 114 of the eleventh transistor can be provided separately. The second electrode 114 of the eleventh transistor is shaped like a broken line and extends at least partially along the second direction D2. The second electrode 114 of the eleventh transistor is connected to the second region of the active pattern of the eleventh transistor through the twentieth via hole, and is connected to the gate electrode of the sixth transistor (the first plate of the first capacitor) through the forty-eighth via hole.

[0418] In an exemplary embodiment, as shown in Figures 22 and 23, the first electrode 123 of the twelfth transistor can be provided separately. The first electrode 123 of the twelfth transistor is strip-shaped and extends along the first direction D1. The first electrode 123 of the twelfth transistor is connected to the first region of the active pattern of the twelfth transistor through a twenty-first via hole and is connected to the second connection line through a sixty-third via hole.

[0419] In an exemplary embodiment, as shown in Figures 22 and 23, the second electrode 124 of the twelfth transistor and the first electrode 164 of the sixteenth transistor are integrally formed. The integral structure of the second electrode 124 of the twelfth transistor and the first electrode 164 of the sixteenth transistor is strip-shaped and extends along a first direction D1. The second electrode 124 of the twelfth transistor (also the first electrode 164 of the sixteenth transistor) is connected to the second region of the active pattern of the twelfth transistor (also the second region of the active pattern of the sixteenth transistor) through a twenty-second via, and is connected to the gate electrode of the tenth transistor (also the gate electrode of the seventeenth transistor) through a fifty-first via.

[0420] In an exemplary embodiment, as shown in Figures 22 and 23, the second electrode 134 of the thirteenth transistor can be provided separately. The second electrode 134 of the thirteenth transistor is in the shape of a strip and extends along the second direction D2. The second electrode 134 of the thirteenth transistor is connected to the second region of the active pattern of the thirteenth transistor through a twenty-third via hole, connected to the gate electrode of the second transistor (also the gate electrode of the eighth transistor) through a forty-fourth via hole, and connected to the second connection line through a sixty-third via hole.

[0421] In an exemplary embodiment, as shown in Figures 22 and 23, the second electrode 144 of the fourteenth transistor and the first electrode 153 of the fifteenth transistor are integrally formed. The integral structure of the second electrode 144 of the fourteenth transistor and the first electrode 153 of the fifteenth transistor is strip-shaped and extends along the second direction D2. The second electrode 144 of the fourteenth transistor (also the first electrode 153 of the fifteenth transistor) is connected to the second region of the active pattern of the fourteenth transistor via a twenty-fifth via, and is connected to the first region of the active pattern of the fifteenth transistor via a twenty-sixth via.

[0422] In an exemplary embodiment, as shown in Figures 22 and 23, the second electrode 154 of the fifteenth transistor can be provided separately. The second electrode 154 of the fifteenth transistor is strip-shaped and extends along the second direction D2. The second electrode 154 of the fifteenth transistor is connected to the second region of the active pattern of the fifteenth transistor through a twenty-seventh via hole, and is connected to the gate electrode of the fourth transistor (which is also the gate electrode of the sixteenth transistor and the first plate of the third capacitor) through a forty-sixth via hole.

[0423] In an exemplary embodiment, as shown in Figures 22 and 23, the first electrode 163 of the sixteenth transistor can be provided separately. The first electrode 163 of the sixteenth transistor is strip-shaped and extends along the first direction D1. The first electrode 163 of the sixteenth transistor is connected to the first region of the active pattern of the sixteenth transistor through a twenty-eighth via hole, and is connected to the gate electrode of the fourth transistor (which is also the gate electrode of the sixteenth transistor and the first plate of the third capacitor) through a forty-sixth via hole.

[0424] In an exemplary embodiment, as shown in Figures 22 and 23, the first electrode 173 of the seventeenth transistor can be provided separately. The first electrode 173 of the seventeenth transistor is strip-shaped and extends along the first direction D1. The number of first electrodes 173 of the seventeenth transistor can be multiple, and the multiple first electrodes 173 of the seventeenth transistor are arranged along the second direction D2. The first electrode 173 of the seventeenth transistor is connected to the first region of the active pattern of the seventeenth transistor through a twenty-ninth via.

[0425] In an exemplary embodiment, as shown in Figures 22 and 23, the second electrode 174 of the seventeenth transistor, the second electrode 194 of the nineteenth transistor, and the second electrode 244 of the twenty-fourth transistor are integrally structured. The second electrode 174 of the seventeenth transistor includes a fourth connecting segment 174A and a plurality of fourth branch segments 174B. The plurality of fourth branch segments 174B are located on the side of the fourth connecting segment 174A away from the display area. The fourth connecting segment 174A is strip-shaped and extends along the second direction D2. The fourth branch segments 174B are strip-shaped and extend along the first direction D1. The plurality of fourth branch segments 174B are arranged along the second direction D2. The second electrode 174 of the seventeenth transistor has a comb-like structure, with the fourth connecting segment 174A acting as the back of a comb and the plurality of fourth branch segments 174B acting as the teeth of the comb. The plurality of fourth branch segments 174B are interspersed with the plurality of first electrodes 173 of the seventeenth transistor. The second electrode 194 of the nineteenth transistor includes a fifth connecting segment 194A and a plurality of fifth branch segments 194B. The plurality of fifth branch segments 194B are located on the side of the fifth connecting segment 194A away from the display area. The fifth connecting segment 194A is strip-shaped and extends along the second direction D2. The fifth branch segment 194B is strip-shaped and extends along the first direction D1. The plurality of fifth branch segments 194B are arranged along the second direction D2. The fourth connecting segment 174A is connected to one of the fifth branch segments 194B. The second electrode 194 of the nineteenth transistor has a comb-like structure, with the fifth connecting segment 194A acting as the back of a comb and the plurality of fifth branch segments 194B acting as the teeth of the comb. The second electrode 244 of the twenty-fourth transistor is located on the side of the fifth connecting segment 194A closer to the display area. The second electrode 244 of the twenty-fourth transistor has a zigzag shape and extends at least partially along the first direction D1. The second electrode 174 of the seventeenth transistor (which is also the second electrode 194 of the nineteenth transistor and the second electrode 244 of the twenty-fourth transistor) is connected to the second area of ​​the active pattern of the seventeenth transistor through the thirtieth via, is connected to the second area of ​​the active pattern of the nineteenth transistor through the thirty-fourth via, is connected to the second area of ​​the active pattern of the twenty-fourth transistor through the forty-second via, and is connected to the sixth connecting line through the seventy-second via.

[0426] In an exemplary embodiment, as shown in Figures 22 and 23, the first electrode 183 of the eighteenth transistor can be provided separately. The first electrode 183 of the eighteenth transistor is strip-shaped and extends along the first direction D1. The number of first electrodes 183 of the eighteenth transistor can be multiple, and the multiple first electrodes 183 of the eighteenth transistor are arranged along the second direction D2. The first electrode 183 of the eighteenth transistor is connected to the first region of the active pattern of the eighteenth transistor through a thirty-first via.

[0427] In an exemplary embodiment, as shown in Figures 22 and 23, the second electrode 184 of the eighteenth transistor and the first electrode 193 of the nineteenth transistor are integrally formed. The integral structure of the second electrode 184 of the eighteenth transistor and the first electrode 193 of the nineteenth transistor includes a sixth connecting segment 184A, a plurality of sixth branch segments 184B, and a plurality of seventh branch segments 184C. The plurality of sixth branch segments 184B are located on a side of the sixth connecting segment 184A away from the display area, and the plurality of seventh branch segments 184C are located on a side of the sixth connecting segment 184A closer to the display area. The plurality of sixth branch segments 184B and the plurality of seventh branch segments 184C are respectively connected to the sixth connecting segment 184A. The sixth connecting segment 184A is strip-shaped and extends along the second direction D2. The sixth branch segment 184B is strip-shaped and extends along the first direction D1. Multiple sixth branch segments 184B are arranged along the second direction D2. Multiple seventh branch segments 184C are strip-shaped and extend along the first direction D1. Multiple seventh branch segments 184C are arranged along the second direction D2. The multiple sixth branch segments 184B are interspersed with the multiple first electrodes 183 of the eighteenth transistor. The multiple seventh branch segments 184C are interspersed with the multiple fifth branch segments 194B. The second electrode 184 of the eighteenth transistor (also the first electrode 193 of the nineteenth transistor) is connected to the second electrode of the active pattern of the eighteenth transistor through a thirty-second via, and is connected to the second region of the active pattern of the nineteenth transistor through a thirty-third via.

[0428] In an exemplary embodiment, as shown in FIG22 and FIG23, the first electrode 203 of the twentieth transistor is provided separately. The shape of the first electrode 203 of the twentieth transistor may be The first electrode 203 of the 20th transistor is connected to the first region of the active pattern of the 20th transistor through the 35th via, connected to the gate electrode of the 19th transistor through the 55th via, connected to the first gate electrode of the 24th transistor through the 60th via, and connected to the second gate electrode of the 24th transistor through the 61st via.

[0429] In an exemplary embodiment, as shown in Figures 22 and 23, the first electrode 213 of the 21st transistor is separately provided. The first electrode 213 of the 21st transistor is strip-shaped and extends along the first direction D1. The first electrode 213 of the 21st transistor is connected to the first region of the active pattern of the 21st transistor through the 36th via.

[0430] In an exemplary embodiment, as shown in FIG22 and FIG23, the first electrode 223 of the twenty-second transistor is separately provided. The first electrode 223 of the twenty-second transistor is connected to the first region of the active pattern of the twenty-second transistor through the thirty-seventh via hole.

[0431] In an exemplary embodiment, as shown in FIG22 and FIG23, the second electrode 224 of the 22nd transistor and the second electrode 234 of the 23rd transistor are an integral structure. The shape of the integral structure of the second electrode 224 of the 22nd transistor and the second electrode 234 of the 23rd transistor is The second electrode 224 of the 22nd transistor (also the second electrode 234 of the 23rd transistor) is connected to the second region of the active pattern of the 22nd transistor through the 38th via, connected to the second region of the active pattern of the 23rd transistor through the 40th via, and connected to the third connection line through the 64th via.

[0432] In an exemplary embodiment, as shown in Figures 22 and 23, the first electrode 233 of the twenty-third transistor is separately provided. The first electrode 233 of the twenty-third transistor is strip-shaped and extends along the first direction D1. The first electrode 233 of the twenty-third transistor is connected to the first region of the active pattern of the twenty-third transistor through a thirty-ninth via.

[0433] In an exemplary embodiment, as shown in FIG22 and FIG23, the first electrode 243 of the twenty-fourth transistor is separately provided. The first electrode 243 of the twenty-fourth transistor is connected to the first region of the active pattern of the twenty-fourth transistor through the forty-first via hole.

[0434] In an exemplary embodiment, as shown in Figures 22 and 23, the seventh connection line L7 is provided separately. The seventh connection line L7 is strip-shaped and extends along the second direction D2. The seventh connection line L7 is electrically connected to the second gate electrode of the 22nd transistor through the 58th via hole and is electrically connected to the gate electrode of the 20th transistor through the 56th via hole.

[0435] In an exemplary embodiment, as shown in Figures 22 and 23, the eighth connection line L8 is provided separately. The eighth connection line L8 is strip-shaped and extends along the second direction D2. The eighth connection line L8 is electrically connected to the second gate electrode of the 22nd transistor through the 58th via hole, electrically connected to the first gate electrode of the 22nd transistor through the 57th via hole, and electrically connected to the gate electrode of the 23rd transistor through the 59th via hole.

[0436] In an exemplary embodiment, as shown in Figures 22 and 23, the ninth connection line L9 is provided separately. The ninth connection line L9 is strip-shaped and extends along the first direction D1. The ninth connection line L9 is electrically connected to the gate electrode of the twenty-third transistor through the fifty-ninth via hole and is electrically connected to the fifth connection line through the seventy-first via hole.

[0437] In an exemplary embodiment, as shown in Figures 22 and 23, the tenth connection line L10 is provided separately. The tenth connection line L10 has a block shape. The tenth connection line L10 is electrically connected to the gate electrode of the twenty-third transistor through the fifty-ninth via hole and is electrically connected to the fifth connection line through the seventy-first via hole.

[0438] 22 and 23 , the eleventh connection line L11 is provided separately. The eleventh connection line L11 is in a strip shape and extends along the first direction D1. The eleventh connection line L11 is electrically connected to the fourth connection line through the seventieth via hole.

[0439] In an exemplary embodiment, as shown in Figures 22 and 23, the initial signal line STV, the first clock signal line CLK1, the second clock signal line CLK2, and the third power line VEL are arranged in sequence in a direction approaching the display area. The initial signal line STV, the first clock signal line CLK1, and the second clock signal line CLK2 are located on a side of the first and second electrodes of all transistors in the shift register that is away from the display area. The orthographic projection of the third power line VEL on the substrate at least partially overlaps with a portion of any one of the fifth transistor, the eighth transistor, the twelfth transistor, the thirteenth transistor, and the sixteenth transistor.

[0440] In exemplary embodiments, as shown in FIG. 22 and FIG. 23 , the initial signal line STV may have a line shape in which a main portion extends along the second direction D2 , and the third power line VEL is connected to the gate electrode of the thirteenth transistor through the fifty-fourth via hole.

[0441] In an exemplary embodiment, as shown in Figures 22 and 23, the shape of any one of the first clock signal line CLK1 and the second clock signal line CLK2 can be a line shape with a main portion extending along the second direction D2, the first clock signal line CLK1 is connected to the gate electrode of the first transistor (also the gate electrode of the fourteenth transistor) through the forty-third via, and is connected to the gate electrode of the third transistor through the forty-fifth via, the second clock signal line CLK2 is connected to the gate electrode of the seventh transistor through the forty-ninth via, and is connected to the first connecting line through the sixty-second via, or the first clock signal line CLK1 is connected to the gate electrode of the seventh transistor through the forty-ninth via, and is connected to the first connecting line through the sixty-second via, the second clock signal line CLK2 is connected to the gate electrode of the first transistor (also the gate electrode of the fourteenth transistor) through the forty-third via, and is connected to the gate electrode of the third transistor through the forty-fifth via. Figure 23 is illustrated by an example in which the first clock signal line CLK1 is connected to the gate electrode of the first transistor (which is also the gate electrode of the fourteenth transistor) through the forty-third via, and is connected to the gate electrode of the third transistor through the forty-fifth via, and the second clock signal line CLK2 is connected to the gate electrode of the seventh transistor through the forty-ninth via, and is connected to the first connecting line through the sixty-second via.

[0442] In an exemplary embodiment, the second clock signal line is connected to the first electrode of the fourth transistor via a first connecting line. The first electrode of the twelfth transistor is connected to the second electrode of the thirteenth transistor via a second connecting line. The gate electrode of the twentieth transistor is connected to the gate electrode of the twenty-second transistor via a seventh connecting line. The first gate electrode and the second gate electrode of the twenty-second transistor are connected to the gate electrode of the twenty-third transistor via an eighth connecting line. The gate electrode of the twenty-third transistor is connected to the second electrode of the ninth transistor (which is also the second electrode of the tenth transistor) via a ninth connecting line and a fifth connecting line.

[0443] In an exemplary embodiment, the first to eleventh connecting lines serve as connecting electrodes, which can reduce the depth of the via holes in the display substrate and improve the reliability of the display substrate.

[0444] In an exemplary embodiment, the initial signal line STV, the first clock signal line CLK1, the second clock signal line CLK2 and the third power line VEL can be designed with equal width, or can be designed with unequal width, can be straight lines, or can be broken lines, which not only facilitates the layout of the shift register, but also reduces the parasitic capacitance between the signal lines. The present disclosure does not limit this.

[0445] (8) Forming a first planar layer pattern. In an exemplary embodiment, forming the first planar layer pattern may include: depositing a sixth insulating film and coating a first planar film on the substrate having the aforementioned pattern formed thereon, patterning the sixth insulating film and the first planar film through a patterning process to form a sixth insulating layer pattern and a first planar layer pattern covering the aforementioned structure, wherein the sixth insulating layer and the first planar layer are provided with a plurality of via patterns, as shown in FIG24 , which is a schematic diagram of FIG9 after the first planar layer pattern is formed.

[0446] In an exemplary embodiment, as shown in FIG. 24 , the sixth insulation layer pattern and the first planarization layer pattern may include at least seventy-third to eighty-third via holes V73 to V83 located at each stage of the shift register.

[0447] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the seventy-third via V73 on the substrate is located within the range of the orthographic projection of the second electrode of the fourth transistor (also the second electrode of the fifth transistor) on the substrate, and the seventy-third via V73 exposes the surface of the second electrode of the fourth transistor (also the second electrode of the fifth transistor). The seventy-third via V73 is configured to connect the subsequently formed thirteenth signal line to the second electrode of the fourth transistor (also the second electrode of the fifth transistor) through the via.

[0448] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the seventy-fourth via V74 on the substrate is located within the range of the orthographic projection of the first electrode of the third transistor on the substrate, the seventy-fourth via V74 exposes the surface of the first electrode of the third transistor, and the seventy-fourth via V74 is configured to connect a subsequently formed first second power line to the first electrode of the third transistor through the via.

[0449] In an exemplary embodiment, as shown in Figure 24, the orthographic projection of the seventy-fifth via V75 on the substrate is located within the range of the orthographic projection of the first electrode of the fifth transistor (also the first electrode of the eighth transistor, the first electrode of the ninth transistor, and the first electrode of the thirteenth transistor) on the substrate, and the seventy-fifth via V75 exposes the surface of the first electrode of the fifth transistor (also the first electrode of the eighth transistor, the first electrode of the ninth transistor, and the first electrode of the thirteenth transistor), and the seventy-fifth via V75 is configured to connect a subsequently formed first first power line to the first electrode of the fifth transistor (also the first electrode of the eighth transistor, the first electrode of the ninth transistor, and the first electrode of the thirteenth transistor) through the via.

[0450] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the seventy-sixth via V76 on the substrate is located within the range of the orthographic projection of the first electrode of the tenth transistor on the substrate, the seventy-sixth via V76 exposes the surface of the first electrode of the tenth transistor, and the seventy-sixth via V76 is configured to connect a subsequently formed second power line to the first electrode of the tenth transistor through the via.

[0451] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the seventy-seventh via V77 on the substrate is located within the range of the orthographic projection of the first electrode of the seventeenth transistor on the substrate, the seventy-seventh via V77 exposes the surface of the first electrode of the seventeenth transistor, and the seventy-seventh via V77 is configured to connect a subsequently formed third second power line to the first electrode of the seventeenth transistor through the via.

[0452] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the seventy-eighth via V78 on the substrate is located within the range of the orthographic projection of the first electrode of the eighteenth transistor on the substrate, the seventy-eighth via V78 exposes the surface of the first electrode of the eighteenth transistor, and the seventy-eighth via V78 is configured to connect a subsequently formed second first power line to the first electrode of the eighteenth transistor through the via.

[0453] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the seventy-ninth via V79 on the substrate is located within the range of the orthographic projection of the first electrode of the twenty-first transistor on the substrate, the seventy-ninth via V79 exposes the surface of the first electrode of the twenty-first transistor, and the seventy-ninth via V79 is configured to connect a subsequently formed masked signal line to the first electrode of the twenty-first transistor through the via.

[0454] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the 80th via V80 on the substrate is located within the range of the orthographic projection of the first electrode of the 22nd transistor on the substrate, the 80th via V80 exposes the surface of the first electrode of the 22nd transistor, and the 80th via V80 is configured to connect a subsequently formed fourth second power line to the first electrode of the 22nd transistor through the via.

[0455] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the eighty-first via V81 on the substrate is located within the range of the orthographic projection of the first electrode of the twenty-third transistor on the substrate, the eighty-first via V81 exposes the surface of the first electrode of the twenty-third transistor, and the eighty-first via V81 is configured to connect a subsequently formed second first power line to the first electrode of the twenty-third transistor through the via.

[0456] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the eighty-second via V82 on the substrate is located within the range of the orthographic projection of the first electrode of the twenty-fourth transistor on the substrate, the eighty-second via V82 exposes the surface of the first electrode of the twenty-fourth transistor, and the eighty-second via V82 is configured to connect a subsequently formed fourth second power line to the first electrode of the twenty-fourth transistor through the via.

[0457] In an exemplary embodiment, as shown in FIG24 , the orthographic projection of the eighty-third via V83 on the substrate is located within the range of the orthographic projection of the tenth connecting line on the substrate, the eighty-third via V83 exposes the surface of the tenth connecting line, and the eighty-third via V83 is configured to connect a subsequently formed second first power line to the tenth connecting line through the via.

[0458] (9) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer pattern may include: depositing a fifth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fifth conductive film using a patterning process to form a fifth conductive layer disposed on the fifth insulating layer, as shown in FIG25 and FIG26 , where FIG25 is a schematic diagram of the fifth conductive layer pattern in FIG9 , and FIG26 is a schematic diagram of FIG9 after the fifth conductive layer pattern is formed. In an exemplary embodiment, the fifth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0459] In an exemplary embodiment, as shown in Figures 25 and 26, the fifth conductive layer pattern may include at least two first power lines, four second power lines, a mask signal line MSL, and a thirteenth connection line L13. The two first power lines include a first first power line VGH-1 and a second first power line VGH-2. The four second power lines include a first second power line VGL-1, a second second power line VGL-2, a third second power line VGL-3, and a fourth second power line VGL-4.

[0460] In an exemplary embodiment, as shown in Figures 25 and 26, the first second power line VGL-1, the second second power line VGL-2, the first first power line VGH-1, the third second power line VGL-3, the second first power line VGH-2, the masking signal line MSL and the fourth second power line VGL-4 are arranged in sequence in a direction close to the display area.

[0461] In an exemplary embodiment, as shown in FIG. 25 and FIG. 26 , an orthographic projection of the second power line VGL- 2 on the substrate at least partially overlaps with an orthographic projection of the third power line on the substrate.

[0462] In an exemplary embodiment, as shown in FIG. 25 and FIG. 26 , the orthographic projection of the first second power line VGL- 1 on the substrate is located between the orthographic projection of the second clock signal line and the orthographic projection of the third power line on the substrate.

[0463] In an exemplary embodiment, as shown in Figures 25 and 26, the orthographic projection of the first first power line VGH-1, the third second power line VGL-3, the second first power line VGH-2, the masking signal line MSL and the fourth second power line VGL-4 on the substrate is located on a side of the orthographic projection of the third power line on the substrate close to the display area.

[0464] In an exemplary embodiment, the thirteenth connection line L13 is located between the first second power line VGL-1 and the second second power line VGL-2 and is connected to the second electrode of the fourth transistor (also the second electrode of the fifth transistor) through the seventy-third via hole.

[0465] 25 and 26 , the first second power line VGL- 1 may be in the shape of a line having a main portion extending along the second direction D2 . The first second power line VGL- 1 is connected to the first electrode of the third transistor through the seventy-fourth via hole.

[0466] 25 and 26 , the second second power line VGL- 2 may be in the shape of a line having a main portion extending along the second direction D2 . The second second power line VGL- 2 is connected to the first electrode of the tenth transistor through the seventy-sixth via hole.

[0467] In an exemplary embodiment, as shown in Figures 25 and 26, the first first power line VGH-1 may be in the shape of a line having a main portion extending along the second direction D2. The first first power line VGH-1 is connected to the first electrode of the fifth transistor (the first electrode of the eighth transistor, the first electrode of the ninth transistor, and the first electrode of the thirteenth transistor) through the seventy-fifth via hole.

[0468] 25 and 26, the third second power line VGL-3 may be in a line shape with a main portion extending along the second direction D2. The third second power line VGL-3 is connected to the first electrode of the seventeenth transistor through the seventy-seventh via hole.

[0469] In an exemplary embodiment, as shown in Figures 25 and 26, the second first power line VGH-2 may be in the shape of a line having a main portion extending along the second direction D2. The second first power line VGH-2 is connected to the first electrode of the eighteenth transistor through the seventy-eighth via hole, to the first electrode of the twenty-third transistor through the eighty-first via hole, and to the tenth connection line through the eighty-third via hole.

[0470] 25 and 26 , the masking signal line MSL may be in a line shape with a main portion extending along the second direction D2 . The masking signal line MSL is connected to the first electrode of the twenty-first transistor through the seventy-ninth via hole.

[0471] In an exemplary embodiment, as shown in Figures 25 and 26, the fourth second power line VGL-4 may be in the shape of a line having a main portion extending along the second direction D2. The fourth second power line VGL-4 is connected to the first electrode of the 22nd transistor through the 80th via hole and to the first electrode of the 24th transistor through the 82nd via hole.

[0472] In an exemplary embodiment, the fourth second power line VGL-4 can be electrically connected to the adjacent driving circuit of the shift register, so that the two driving circuits share one second power line, which can reduce the area occupied by the gate driving circuit and thus achieve a narrow frame of the display substrate.

[0473] In an exemplary embodiment, as shown in FIG. 25 and FIG. 26 , the line width of the first second power line VGL- 1 is smaller than the line width of any one signal line of the second second power line VGL- 2 and the third second power line VGL- 3 .

[0474] In an exemplary embodiment, as shown in FIG. 25 and FIG. 26 , the line width of the fourth second power line VGL- 4 is smaller than the line width of any one signal line of the second second power line VGL- 2 and the third second power line VGL- 3 .

[0475] In an exemplary embodiment, as shown in FIG. 25 and FIG. 26 , the line width of the first first power line VGH- 1 is smaller than the line width of the second first power line VGH- 2 .

[0476] In an exemplary embodiment, as shown in Figures 25 and 26, the line width of the masking signal line MSL is larger than the line width of any one of the first second power line VGL-1, the fourth second power line VGL-4 and the first first power line VGH-1, and smaller than the line width of the second second power line VGL-2, the third second power line VGL-3 and the second first power line VGH-2.

[0477] (10) Forming a second planar layer. In an exemplary embodiment, forming the planar layer pattern may include: depositing a seventh insulating film on the substrate having the aforementioned pattern, coating a second planar film, and patterning the seventh insulating film and the second planar film through a patterning process to form a seventh insulating layer pattern covering the aforementioned structure and a second planar layer pattern covering the seventh insulating layer pattern.

[0478] At this point, the drive circuit layer is prepared on the substrate. In a plane parallel to the display substrate, the drive circuit layer may include multiple shift registers, and the shift registers are electrically connected to the initial signal line, the first clock signal line, the second clock signal line, the first power line, the second power line, the third power line, and the scan mask signal line. In a plane perpendicular to the display substrate, the drive circuit layer can be arranged on the substrate. The drive circuit layer may include a first semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a second semiconductor layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a fourth conductive layer, a sixth insulating layer, a first planar layer, a fifth conductive layer, a seventh insulating layer, and a second planar layer, which are arranged in sequence on the substrate. The first semiconductor layer may include at least active patterns of the first to twenty-first transistors and the active pattern of the twenty-third transistor, the first conductive layer may include at least gate electrodes of the first to twenty-first transistors, the gate electrode of the twenty-third transistor, and the first plate of the first capacitor to the first plate of the fifth capacitor, the second conductive layer may include at least the second plate of the first capacitor to the second plate of the fifth capacitor, the first gate electrode of the twenty-second transistor and the first gate electrode of the twenty-fourth transistor, the second semiconductor layer may include at least: the active pattern of the twenty-second transistor and the active pattern of the twenty-fourth transistor, the third conductive layer may include at least: the second gate electrode of the twenty-second transistor and the second gate electrode of the twenty-fourth transistor, the fourth conductive layer may include at least: the initial signal line, the first clock signal line, the second clock signal line, the third power line, the first and second electrodes of multiple transistors, and the fifth conductive layer may include at least: the first power line, the second power line and the masking signal line.

[0479] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and metal foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0480] In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The first and second flexible material layers may be made of polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The first and second inorganic material layers may be made of silicon nitride (SiNx) or silicon oxide (SiOx) to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers. The semiconductor layer may be made of amorphous silicon (a-Si). In an exemplary embodiment, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, its preparation process may include: first coating a layer of polyimide on a glass carrier, and forming a first flexible (PI1) layer after curing; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing a layer of amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating the amorphous silicon layer with another layer of polyimide, and forming a second flexible (PI2) layer after curing; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thereby completing the preparation of the substrate.

[0481] In example embodiments, the first semiconductor layer may be an amorphous silicon layer or a polycrystalline silicon layer.

[0482] In an exemplary embodiment, the second semiconductor layer may be a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0483] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0484] In exemplary embodiments, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, the sixth insulating layer, and the seventh insulating layer may be formed of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The first insulating layer, the second insulating layer, and the third insulating layer may be referred to as a gate insulating (GI) layer, the fourth insulating layer may be referred to as an interlayer insulating (ILD) layer, and the fifth insulating layer may be referred to as a passivation (PVX) layer.

[0485] In an exemplary embodiment, the first planarization layer and the second planarization layer may be made of an organic material such as resin.

[0486] In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer is prepared on the driving circuit layer. The preparation process of the light emitting structure layer may include the following operations.

[0487] An anode conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the anode conductive film is patterned using a patterning process to form an anode conductive layer pattern arranged on the second flat layer. A pixel definition film is deposited on the substrate on which the aforementioned pattern is formed, and the pixel definition film is patterned using a patterning process to form a pixel definition layer pattern exposing the anode conductive layer pattern. An organic light-emitting material is coated on the substrate on which the pixel definition layer pattern is formed, and the organic light-emitting material is patterned using a patterning process to form an organic structure layer pattern. A cathode conductive film is deposited on the substrate on which the organic material layer pattern is formed, and the cathode conductive film is patterned using a patterning process to form a cathode conductive layer.

[0488] At this point, the light-emitting structure layer is prepared on the substrate.

[0489] In an exemplary embodiment, the anode conductive layer includes at least a plurality of anode patterns. The plurality of anode patterns may include an anode of a first light-emitting device, an anode of a second light-emitting device, an anode of a third light-emitting device, and an anode of a fourth light-emitting device, wherein the anode of the first light-emitting device is located in a red sub-pixel emitting red light, the anode of the second light-emitting device may be located in a blue sub-pixel emitting blue light, the anode of the third light-emitting device may be located in a first green sub-pixel emitting green light, and the anode of the fourth light-emitting device may be located in a second green sub-pixel emitting green light.

[0490] In an exemplary embodiment, the anode of the first light emitting device and the anode of the second light emitting device may be alternately arranged along the first direction D1, and the anode of the third light emitting device and the anode of the fourth light emitting device may be alternately arranged along the first direction D1. Alternatively, the anode of the first light emitting device and the anode of the second light emitting device may be alternately arranged along the second direction D2, and the anode of the third light emitting device and the anode of the fourth light emitting device may be alternately arranged along the second direction D2.

[0491] In an exemplary embodiment, the shapes and areas of the anode electrodes of the four sub-pixels in one pixel unit may be the same, or may be different.

[0492] In an exemplary embodiment, the anode conductive layer has a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or may have a multi-layer composite structure, such as ITO / Ag / ITO.

[0493] In an exemplary embodiment, the organic structure layer may include at least an organic light emitting layer of a light emitting device.

[0494] In an exemplary embodiment, the cathode conductive layer may include at least cathodes of a plurality of light emitting devices.

[0495] In an exemplary embodiment, the cathode layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material thereof, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may have a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. For example, the fourth conductive layer may be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0496] The display substrate adopted in the embodiment of the present disclosure can be applied to display products with any resolution.

[0497] In an exemplary embodiment, the subsequent preparation process may include: forming a packaging structure layer on the cathode conductive layer, the packaging structure layer may include a stacked first packaging layer, a second packaging layer and a third packaging layer, the first packaging layer and the third packaging layer may be made of inorganic materials, the second packaging layer may be made of organic materials, and the second packaging layer is arranged between the first packaging layer and the third packaging layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0498] An embodiment of the present disclosure further provides a display device, which may include: a display substrate.

[0499] The display substrate is the display substrate provided by any of the aforementioned embodiments, and the implementation principle and effect are similar, which will not be repeated here.

[0500] In an exemplary embodiment, the display device may be any product or component with a display function, such as a wearable device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator.

[0501] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to general designs.

[0502] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0503] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A display substrate having a display area and a non-display area, the display substrate comprising: A pixel driving circuit located in the display area and a gate driving circuit group located in the non-display area, the gate driving circuit group at least comprising a first driving circuit, the first driving circuit being connected to the pixel driving circuit, the first driving circuit comprising a plurality of cascaded shift registers; the shift register at least comprising: a first output transistor, a second output transistor, a third output transistor, a fourth output transistor, a fifth output transistor, a cascade signal output terminal, a driving signal output terminal, a first power supply terminal and a second power supply terminal, the driving signal output terminal being electrically connected to the pixel driving circuit; The first output transistor is electrically connected to the cascade signal output terminal and the first power supply terminal respectively, the second output transistor is electrically connected to the cascade signal output terminal and the second power supply terminal respectively, the third output transistor is electrically connected to the fifth output transistor and the first power supply terminal respectively, the fourth output transistor is electrically connected to the drive signal output terminal and the second power supply terminal respectively, and the fifth output transistor is electrically connected to the drive signal output terminal; The gate electrode of the first output transistor and the gate electrode of the third output transistor are an integrated structure, and the gate electrode of the second output transistor and the gate electrode of the fourth output transistor are an integrated structure.

2. The display substrate according to claim 1, wherein: The shift register further includes: a fifth capacitor; The fifth capacitor is connected to the cascade signal output terminal and the second power supply terminal respectively.

3. The display substrate according to claim 2, wherein: The capacitance value of the fifth capacitor is less than or equal to 60 farads.

4. The display substrate according to claim 2, wherein: Any one of the third output transistor and the fourth output transistor is located at a side of any one of the first output transistor and the second output transistor close to the display area, the fifth output transistor is located at a side of any one of the third output transistor and the fourth output transistor close to the display area, and the fifth capacitor is located at a side of the second output transistor away from the display area; The first output transistor and the third output transistor are arranged along a first direction, the second output transistor and the fourth output transistor are arranged along the first direction, the first output transistor and the second output transistor are arranged along a second direction, the third output transistor and the fourth output transistor are arranged along the second direction, and the first direction intersects with the second direction.

5. The display substrate according to claim 1, wherein: Transistors include: an active pattern, wherein a length of the active pattern of the first output transistor along the first direction is shorter than a length of the active pattern of the third output transistor along the first direction; The channel width of the active pattern of the first output transistor is smaller than the channel width of the active pattern of the third output transistor, and the channel length of the active pattern of the first output transistor is greater than the channel length of the active pattern of the third output transistor.

6. The display substrate according to claim 1, wherein: Transistors include: An active pattern, the length of the active pattern of the third output transistor along the first direction is greater than the length of the active pattern of the fourth output transistor along the first direction, and the length of the active pattern of the third output transistor along the second direction is less than the length of the active pattern of the fourth output transistor along the second direction.

7. The display substrate according to claim 5, wherein: A channel width of the active pattern of the first output transistor ranges from 80 micrometers to 100 micrometers, and a channel length of the active pattern of the first output transistor ranges from 3.2 micrometers to 3.7 micrometers.

8. The display substrate according to claim 5, wherein: The channel width of the active pattern of the third output transistor ranges from 250 micrometers to 300 micrometers, and the channel length of the active pattern of the third output transistor ranges from 2.9 micrometers to 3.2 micrometers.

9. The display substrate according to claim 1, wherein: Transistors include: Active pattern; The length of the active pattern of the second output transistor along the first direction is shorter than the length of the active pattern of the fourth output transistor along the first direction; The channel width of the active pattern of the second output transistor is smaller than the channel width of the active pattern of the fourth output transistor, and the channel length of the active pattern of the second output transistor is greater than the channel length of the active pattern of the fourth output transistor.

10. The display substrate according to claim 9, wherein: A channel width of the active pattern of the second output transistor ranges from 80 micrometers to 100 micrometers, and a channel length of the active pattern of the second output transistor ranges from 3.2 micrometers to 3.7 micrometers.

11. The display substrate according to claim 8, wherein: The channel width of the active pattern of the fourth output transistor ranges from 250 micrometers to 300 micrometers, and the channel length of the active pattern of the fourth output transistor ranges from 2.9 micrometers to 3.2 micrometers.

12. The display substrate according to claim 1, wherein: The length of the active pattern of the fifth output transistor along the second direction is greater than the length of the active pattern of any one of the third output transistor and the fourth output transistor along the second direction; The channel width of the active pattern of the fifth output transistor ranges from 250 micrometers to 300 micrometers, and the channel length of the active pattern of the fifth output transistor ranges from 2.9 micrometers to 3.2 micrometers.

13. The display substrate according to claim 1, wherein: Transistors include: A gate electrode, a length of the gate electrode of the third output transistor along the first direction is greater than a length of the gate electrode of the fourth output transistor along the first direction.

14. The display substrate according to claim 1, wherein: Transistors include: A gate electrode, a length of the gate electrode of the fifth output transistor along the second direction is greater than a length of the gate electrode of any one of the first output transistor and the second output transistor along the second direction.

15. The display substrate according to claim 1, wherein: The shift register further includes: a fourth capacitor; The fourth capacitor is connected to the fifth output transistor and the first power supply terminal respectively.

16. The display substrate according to claim 14, wherein: The fourth capacitor is located between the second output transistor and the fourth output transistor.

17. The display substrate according to claim 1, wherein: The shift register further includes: a twenty-fourth transistor; The twenty-fourth transistor is connected to the fifth output transistor and the second power supply terminal respectively, and a transistor type of the twenty-fourth transistor is opposite to a transistor type of any transistor among the first to fifth output transistors.

18. The display substrate according to claim 17, wherein: The twenty-fourth transistor is located at a side of the fifth output transistor close to the display area, and is arranged along a first direction with the first output transistor and the third output transistor.

19. The display substrate according to claim 1, wherein: The shift register further includes: a twentieth transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a reverse signal output terminal and a masking signal terminal; The 20th transistor is connected to the cascade signal output terminal, the fifth output transistor, and the 21st transistor respectively, and the 21st transistor is connected to the reverse signal output terminal and the masking signal terminal of the previous stage shift register respectively. The twenty-second transistor is respectively connected to the cascade signal output terminal, the reverse signal output terminal and the second power supply terminal, and the twenty-third transistor is respectively connected to the cascade signal output terminal, the reverse signal output terminal and the first power supply terminal; The transistor type of the twenty-second transistor is opposite to the transistor type of any one of the first to third output transistors, the twentieth transistor, the twenty-first transistor, and the twenty-third transistor.

20. The display substrate according to claim 19, wherein: The 20th to 23rd transistors are located on a side of the fifth output transistor close to the display area; The 21st transistor and the 20th transistor are arranged along the second direction, and the 20th transistor is located on the side of the 21st transistor close to the 22nd transistor, and the 23rd transistor is located between the 22nd transistor and the fifth output transistor, and on the side of the 22nd transistor away from the 21st transistor.

21. The display substrate according to claim 1, wherein: The shift register further includes: first to eighth transistors, eleventh to sixteenth transistors, first to third capacitors, a signal input terminal, a first clock signal terminal, a second clock signal terminal and a third power supply terminal; The first transistor is connected to the signal input terminal, the first clock signal terminal, the second transistor, the eighth transistor, the twelfth transistor and the thirteenth transistor respectively, the second transistor is connected to the first clock signal line, the third transistor, the fifth transistor, the eighth transistor, the eleventh transistor, the twelfth transistor and the thirteenth transistor respectively, the third transistor is connected to the first clock signal terminal, the second power supply terminal, the fifth transistor and the eleventh transistor respectively, the fourth transistor is connected to the second clock signal terminal, the third capacitor, the fifth transistor, the fifteenth transistor and the sixteenth transistor respectively, the fifth transistor is connected to the first power supply terminal, the third capacitor and the eleventh transistor respectively, the sixth transistor is connected to the second clock signal terminal, the first capacitor, the seventh transistor and the eleventh transistor respectively, the seventh transistor is connected to the second clock signal terminal, the first capacitor, the second capacitor, The first output transistor, the third output transistor and the eighth transistor are connected, the eighth transistor is connected to the first power supply terminal, the second capacitor, the first output transistor, the third output transistor, the twelfth transistor and the thirteenth transistor respectively, the eleventh transistor is connected to the second power supply terminal and the first capacitor respectively, the twelfth transistor is connected to the second power supply terminal, the second output transistor, the fourth output transistor, the thirteenth transistor and the sixteenth transistor respectively, the thirteenth transistor is connected to the first power supply terminal and the third power supply terminal respectively, the thirteenth transistor is connected to the first power supply terminal and the third power supply terminal respectively, the fourteenth transistor is connected to the signal input terminal, the first clock signal terminal and the fifteenth transistor respectively, the fifteenth transistor is connected to the second power supply terminal, the third capacitor and the sixteenth transistor respectively, and the sixteenth transistor is connected to the second output transistor, the fourth output transistor and the third capacitor respectively; The capacitance value of the third capacitor is greater than the capacitance value of the second capacitor, and the capacitance value of the second capacitor is greater than the voltage value of the first capacitor; The transistor type of any one of the first to eighth transistors and the eleventh to sixteenth transistors is the same as the transistor type of any one of the first to fifth output transistors; Any one of the first to eighth transistors, the eleventh to sixteenth transistors, and the first to third capacitors is located on a side of any one of the first output transistor and the second output transistor away from the display area.

22. The display substrate according to claim 1, wherein: The shift register includes: at least one P-type transistor, at least one N-type transistor and at least one capacitor, wherein the capacitor includes: a first plate and a second plate; the at least one P-type transistor includes: the first output transistor to the fifth output transistor, and the gate electrode of the N-type transistor includes: a first gate electrode and a second gate electrode; The display substrate comprises: a substrate and a driving circuit layer arranged on the substrate, the gate driving circuit group and the pixel driving circuit are arranged on the driving circuit layer, and the driving circuit layer comprises a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer stacked in sequence; The first semiconductor layer at least includes: an active pattern of a P-type transistor; The first conductive layer at least includes: a gate electrode of a P-type transistor and a first plate of at least one capacitor; The second conductive layer at least includes: a second plate of at least one capacitor and a first gate electrode of an N-type transistor The second semiconductor layer at least includes: an active pattern of an N-type transistor; The third conductive layer at least includes: a second gate electrode of the N-type transistor; The fourth conductive layer at least includes: a first electrode and a second electrode of any one of a P-type transistor and an N-type transistor.

23. The display substrate according to claim 1, further comprising: an initial signal line, a first clock signal line, a second clock signal line, a first second power line, a third power line, a second second power line and a first first power line, wherein the second second power line is connected to the second power terminal connected to the second output transistor, and the first first power line is connected to the first power terminal connected to the first output transistor; Any signal line among the initial signal line, the first clock signal line, the second clock signal line, the first second power line, the third power line, the second second power line and the first first power line at least partially extends along the second direction; The orthographic projections of the initial signal line, the first clock signal line, the second clock signal line, the first second power line, the third power line, the second second power line and the first first power line on the substrate are arranged in sequence along a direction close to the display area, and there is no overlapping area between the orthographic projections of any two of the initial signal line, the first clock signal line, the second clock signal line, the first second power line, the second second power line and the first first power line on the substrate; The orthographic projection of the second clock signal line on the substrate is located on a side of the orthographic projection of any transistor in the shift register on the substrate away from the display area.

24. The display substrate according to claim 23, wherein: The display substrate comprises: a substrate and a driving circuit layer arranged on the substrate, the gate driving circuit group and the pixel driving circuit are arranged on the driving circuit layer, and the driving circuit layer comprises a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer stacked in sequence; The initial signal line, the first clock signal line, the second clock signal line and the third power supply line are located in the fourth conductive layer; The first second power line, the second second power line and the first first power line are located in the fifth conductive layer.

25. The display substrate according to claim 23, wherein: The orthographic projection of the second second power line on the substrate at least partially overlaps with the orthographic projection of the third power line on the substrate; The line width of the second second power line is greater than the line width of the third power line.

26. The display substrate according to claim 23, further comprising: a third second power line, a fourth second power line, a second first power line and a masking signal line, wherein the third second power line is connected to the second power terminal connected to the fourth output transistor, and the second first power line is connected to the first power terminal connected to the third output transistor; Any signal line among the third second power line, the fourth second power line, the second first power line and the masking signal line at least partially extends along the second direction; The orthographic projections of the third second power line, the second first power line, the masking signal line and the fourth second power line on the substrate are arranged in sequence along a direction close to the display area, and there is no overlapping area between the orthographic projections of any two of the third second power line, the second first power line, the masking signal line and the fourth second power line on the substrate.

27. The display substrate according to claim 26, wherein: The display substrate comprises: a substrate and a driving circuit layer arranged on the substrate, the gate driving circuit group and the pixel driving circuit are arranged on the driving circuit layer, and the driving circuit layer comprises a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer stacked in sequence; The third second power line, the fourth second power line, the second first power line and the masking signal line are located in the fifth conductive layer.

28. The display substrate according to claim 26, wherein: The gate driving circuit group further includes: a second driving circuit, the second driving circuit is electrically connected to the pixel driving circuit, and the first driving circuit and the second driving circuit are arranged along the first direction; The second driving circuit is electrically connected to the fourth second power line.

29. A display device comprising: A display substrate as claimed in any one of claims 1 to 28.

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