Display substrate and its control method as well as display device

Abstract

A display substrate and a control method therefor, as well as a display device. The display substrate comprises several circuit units. A circuit unit comprises at least one pixel driver circuit and at least one control signal line (24, 25) configured to provide a control signal to the pixel driver circuit.In at least one circuit unit, the pixel driver circuit comprises at least one driver transistor (T3), a first control transistor (T5, T8) and a second control transistor (T6, T7), wherein the first control transistor (T5, T8) and the second control transistor (T6, T7) are each connected to the driver transistor (T3); and in at least one pixel driver circuit of at least one unit row, the first control transistor (T5, T8) is connected to a control signal line (24, 25) in a previous unit row, and the second control transistor (T6, T7) is connected to a control signal line (24, 25) in the current unit row.

Description

Display substrate, driving method thereof, and display device Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and specifically to a display substrate and a driving method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] On the one hand, the present disclosure provides a display substrate, comprising a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising at least a pixel driving circuit and at least one control signal line, wherein the control signal line is configured to provide a control signal to the pixel driving circuit; in at least one circuit unit, the pixel driving circuit comprises at least a driving transistor, a first control transistor, and a second control transistor, wherein the first control transistor and the second control transistor are respectively connected to the driving transistor; in at least one pixel driving circuit of at least one unit row, the first control transistor is connected to the control signal line in the previous unit row, and the second control transistor is connected to the control signal line in the current unit row.

[0006] In an exemplary embodiment, the control signal line includes a light-emitting signal line, the first control transistor includes a first light-emitting control transistor, the second control transistor includes a second light-emitting control transistor, the first electrode of the first light-emitting control transistor is connected to the first power line, the second electrode of the first light-emitting control transistor is connected to the first electrode of the driving transistor, and the first electrode of the second light-emitting control transistor is connected to the second electrode of the driving transistor; in at least one pixel driving circuit of at least one unit row, the gate electrode of the first control transistor is connected to the light-emitting signal line in the previous unit row, and the gate electrode of the second control transistor is connected to the light-emitting signal line in the current unit row.

[0007] In an exemplary embodiment, in at least one pixel driving circuit, the first light emission control transistor and the second light emission control transistor connected to the same driving transistor are respectively arranged on both sides of the driving transistor unit in a column direction.

[0008] In an exemplary embodiment, the first light-emitting control transistor includes at least a first light-emitting control active layer, and the second light-emitting control transistor includes at least a second light-emitting control active layer; in at least one pixel driving circuit of at least one unit row, the first light-emitting control active layer is arranged in a circuit unit of the previous unit row, and the second light-emitting control active layer is arranged in a circuit unit of the current unit row.

[0009] In an exemplary embodiment, in at least one pixel driving circuit of at least one unit row, the first light emission control active layer is arranged on one side of the second light emission control active layer of the pixel driving circuit in the previous unit row in the unit row direction.

[0010] In an exemplary embodiment, the pixel driving circuit further includes a storage capacitor and a power connection electrode, the storage capacitor includes a first plate and a second plate, the orthographic projection of the first plate on the plane of the display substrate at least partially overlaps with the orthographic projection of the second plate on the plane of the display substrate; in at least one pixel driving circuit of at least one unit row, the first end of the power connection electrode is connected to the first area of ​​the first light-emitting control active layer of the pixel driving circuit in the next unit row, and the second end of the power connection electrode is connected to the second plate of the pixel driving circuit in this unit row.

[0011] In an exemplary embodiment, the control signal line includes a scanning signal line, the first control transistor includes a third initialization transistor, the second control transistor includes a second initialization transistor, the first electrode of the second initialization transistor is connected to the second initial signal line, the second electrode of the second initialization transistor is connected to the second electrode of the driving transistor through the second light-emitting control transistor, the first electrode of the third initialization transistor is connected to the third initial signal line, and the second electrode of the third initialization transistor is connected to the first electrode of the driving transistor; in at least one pixel driving circuit of at least one unit row, the gate electrode of the third initialization transistor is connected to the scanning signal line in the previous unit row, and the gate electrode of the second initialization transistor is connected to the scanning signal line in the current unit row.

[0012] In an exemplary embodiment, in at least one pixel driving circuit, the second initialization transistor and the third initialization transistor connected to the same driving transistor are respectively disposed on both sides of the driving transistor unit in a column direction.

[0013] In an exemplary embodiment, the second initialization transistor includes at least a second initialization active layer, and the third initialization transistor includes at least a third initialization active layer; in at least one pixel driving circuit of at least one unit row, the third initialization active layer is arranged in a circuit unit of the previous unit row, and the second initialization active layer is arranged in a circuit unit of the current unit row.

[0014] In an exemplary embodiment, in at least one pixel driving circuit of at least one unit row, the third initialization active layer is disposed on one side of the second initialization active layer of the pixel driving circuit in the previous unit row in the unit row direction.

[0015] In an exemplary embodiment, in at least one pixel driving circuit of at least one unit row, the first area of ​​the second initialization active layer is connected to the second initialization signal line in the current unit row, and the first area of ​​the third initialization active layer is connected to the third initialization signal line in the previous unit row.

[0016] In an exemplary embodiment, the pixel driving circuit further includes a first initialization transistor, a compensation transistor and an isolation transistor, the first electrode of the first initialization transistor being connected to the first initial signal line, the second electrode of the first initialization transistor and the first electrode of the compensation transistor being connected to the first electrode of the isolation transistor, the second electrode of the isolation transistor being connected to the gate electrode of the driving transistor, and the second electrode of the compensation transistor being connected to the second electrode of the driving transistor.

[0017] In an exemplary embodiment, the pixel driving circuit further includes a data writing transistor, a first electrode of the data writing transistor being connected to a data signal line, and a second electrode of the data writing transistor being connected to the first electrode of the driving transistor; a channel region of the isolation transistor being located between a channel region of the compensation transistor and a channel region of the data writing transistor, and a channel width-to-length ratio of the isolation transistor being greater than a channel width-to-length ratio of the data writing transistor.

[0018] In an exemplary embodiment, the first control transistor includes a first light-emitting control transistor and a third initialization transistor, the first electrode of the first light-emitting control transistor is connected to the first power line, the first electrode of the third initialization transistor is connected to the third initialization signal line, and the second electrode of the first light-emitting control transistor and the second electrode of the third initialization transistor are connected to the first electrode of the driving transistor; the pixel driving circuit also includes a second node electrode, the second node electrode is respectively connected to the first electrode of the driving transistor, the second electrode of the first light-emitting control transistor and the second electrode of the third initialization transistor, and the orthographic projection of the second node electrode on the display substrate plane at least partially overlaps with the orthographic projection of the first initialization signal line on the display substrate plane.

[0019] In an exemplary embodiment, the pixel driving circuit further includes a first initialization transistor and a compensation transistor, the first electrode of the first initialization transistor is connected to the first initial signal line, the second electrode of the first initialization transistor and the first electrode of the compensation transistor are connected to the gate electrode of the driving transistor, and the second electrode of the compensation transistor is connected to the second electrode of the driving transistor.

[0020] On the other hand, the present disclosure further provides a display device comprising the aforementioned display substrate.

[0021] On the other hand, the present disclosure also provides a driving method for a display substrate, wherein the display substrate includes multiple circuit units constituting multiple unit rows and multiple unit columns, at least one circuit unit includes at least a pixel driving circuit and at least one control signal line, the pixel driving circuit includes at least a driving transistor, a first control transistor and a second control transistor, the first control transistor and the second control transistor are respectively connected to the driving transistor; the driving method includes at least a data writing stage and a light-emitting stage, in the light-emitting stage, in at least one pixel driving circuit of at least one unit row, the conduction and disconnection of the first control transistor are controlled by the control signal line in the previous unit row, and the conduction and disconnection of the second control transistor are controlled by the control signal line in the current unit row.

[0022] In an exemplary embodiment, the pixel driving circuit further includes a first initialization transistor, a compensation transistor and an isolation transistor, the first electrode of the first initialization transistor being connected to the first initial signal line, the second electrode of the first initialization transistor and the first electrode of the compensation transistor being connected to the first electrode of the isolation transistor, the second electrode of the isolation transistor being connected to the gate electrode of the driving transistor, and the second electrode of the compensation transistor being connected to the second electrode of the driving transistor; the driving method further includes: before the data writing stage, the isolation transistor being turned on at least twice.

[0023] In an exemplary embodiment, the driving method further includes a node reset phase between the data writing phase and the light emitting phase, in which the first electrode and the second electrode of the driving transistor are reset.

[0024] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0026] FIG1 is a schematic structural diagram of a display device;

[0027] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0028] FIG3 is a schematic diagram of a cross-sectional structure of a display substrate;

[0029] FIG4 is a schematic diagram of an equivalent circuit of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0030] FIG5A is a driving timing diagram of the pixel driving circuit shown in FIG4 ;

[0031] FIG5B is another driving timing diagram of the pixel driving circuit shown in FIG4 ;

[0032] FIG6 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0033] FIG7 is a schematic diagram of a display substrate after a shielding layer pattern is formed according to the present disclosure;

[0034] 8A and 8B are schematic diagrams of a display substrate after forming a first semiconductor layer pattern according to the present disclosure;

[0035] 9A and 9B are schematic diagrams of a display substrate after forming a first conductive layer pattern according to the present disclosure;

[0036] 10A and 10B are schematic diagrams of a display substrate after forming a second conductive layer pattern according to the present disclosure;

[0037] 11A and 11B are schematic diagrams of a display substrate after forming a second semiconductor layer pattern according to the present disclosure;

[0038] 12A and 12B are schematic diagrams of a display substrate after a third conductive layer pattern is formed thereon according to the present disclosure;

[0039] FIG13 is a schematic diagram of a display substrate after a sixth insulating layer pattern is formed according to the present disclosure;

[0040] 14A and 14B are schematic diagrams of a display substrate after a fourth conductive layer pattern is formed thereon according to the present disclosure;

[0041] FIG15 is a schematic diagram of a display substrate after forming a first flat layer pattern according to the present disclosure;

[0042] 16A and 16B are schematic diagrams of a display substrate after a fifth conductive layer pattern is formed thereon according to the present disclosure;

[0043] FIG17 is a schematic diagram of an equivalent circuit of another pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0044] FIG18 is a driving timing diagram of the pixel driving circuit shown in FIG17 ;

[0045] FIG19 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0046] FIG20 is a schematic diagram of another display substrate after forming a first semiconductor layer pattern according to the present disclosure;

[0047] FIG21 is a schematic diagram of another display substrate after forming a first conductive layer pattern according to the present disclosure;

[0048] FIG22 is a schematic diagram of another display substrate after forming a second conductive layer pattern according to the present disclosure;

[0049] FIG23 is a schematic diagram of another display substrate according to the present disclosure after forming a second semiconductor layer pattern;

[0050] FIG24 is a schematic diagram of another display substrate after forming a third conductive layer pattern according to the present disclosure;

[0051] FIG25 is a schematic diagram of another display substrate after forming a sixth insulating layer pattern according to the present disclosure;

[0052] FIG26 is a schematic diagram of another display substrate after forming a fourth conductive layer pattern according to the present disclosure;

[0053] FIG27 is a schematic diagram of another display substrate after forming a first flat layer pattern according to the present disclosure;

[0054] FIG28 is a schematic diagram of another display substrate after forming a fifth conductive layer pattern according to the present disclosure;

[0055] FIG29 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0056] FIG30 is a schematic diagram of an equivalent circuit of yet another pixel driving circuit according to an exemplary embodiment of the present disclosure.

[0057] Description of the accompanying drawings:

[0058] 11—first active layer; 12—second active layer; 13—third active layer;

[0059] 14—fourth active layer; 15—fifth active layer; 16—sixth active layer;

[0060] 17—seventh active layer; 18—eighth active layer; 19—ninth active layer;

[0061] 21—first scanning signal line; 22—second scanning signal line; 23—third scanning signal line;

[0062] 24—fourth scanning signal line; 25—light-emitting signal line; 31—first electrode plate;

[0063] 32—second electrode plate; 33—first shielding line; 34—second shielding line;

[0064] 41—first initial signal line; 42—second initial signal line; 43—third initial signal line;

[0065] 51—first connecting electrode; 52—second connecting electrode; 53—third connecting electrode;

[0066] 54—fourth connecting electrode; 55—fifth connecting electrode; 56—sixth connecting electrode;

[0067] 57—seventh connecting electrode; 58—eighth connecting electrode; 59—ninth connecting electrode;

[0068] 60—tenth connecting electrode; 61—first power line; 62—data signal line;

[0069] 63—anode connection electrode; 101—substrate; 102—driving circuit layer;

[0070] 103—light-emitting structure layer; 104—encapsulation structure layer. DETAILED DESCRIPTION

[0071] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0072] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0073] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0074] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0075] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0076] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0077] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0078] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0079] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0080] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0081] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0082] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0083] FIG1 is a schematic diagram of the structure of a display device. As shown in FIG1 , the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is respectively connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a per-pixel basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can sequentially transmit scan start signals provided in the form of on-level pulses to the next-stage circuit under the control of a clock signal, where m can be a natural number. The light driver can generate emission signals to be supplied to light signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide emission signals having off-level pulses to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured as a shift register and may generate emission signals by sequentially transmitting emission stop signals provided in the form of off-level pulses to the next stage circuit under the control of a clock signal. o may be a natural number. In an exemplary embodiment, the pixel array may be provided on a display substrate.

[0084] FIG2 is a schematic diagram of a planar structure of a display substrate. As shown in FIG2 , the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit may include a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0085] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 and the fourth subpixel P4 may be green subpixels (G) that emit green light, and the third subpixel P3 may be a blue subpixel (B) that emits blue light. In an exemplary embodiment, the subpixels may be rectangular, diamond, pentagonal, or hexagonal in shape, and the four subpixels may be arranged horizontally, vertically, or in a square, etc., which is not limited in this disclosure.

[0086] In an exemplary embodiment, a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a triangular arrangement, which is not limited in the present disclosure.

[0087] Figure 3 is a schematic cross-sectional view of a display substrate, illustrating the structure of four sub-pixels in the display area. As shown in Figure 3, in a plane perpendicular to the display substrate, the display substrate may include a drive circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the drive circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in this disclosure.

[0088] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 may include a plurality of circuit units, each of which may include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 may include a plurality of light-emitting units, each of which may include a light-emitting device, which may include at least an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the drive of the anode and the cathode. The encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0089] The exemplary embodiments of the present disclosure provide a display substrate. In an exemplary embodiment, on a plane perpendicular to the display substrate, the display substrate may include a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate. On a plane parallel to the display substrate, the driving structure layer may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one of the circuit units may include a pixel driving circuit, and the pixel driving circuit is configured to output a corresponding current to the connected light-emitting device. The light-emitting structure layer may include a plurality of light-emitting units, at least one of the light-emitting units may include a light-emitting device, the light-emitting device being connected to the pixel driving circuit of the corresponding circuit unit, and the light-emitting device being configured to emit light of corresponding brightness in response to the current output by the connected pixel driving circuit.

[0090] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device. In exemplary embodiments, the position and shape of the orthographic projection of the light-emitting unit on the substrate may correspond to the position and shape of the orthographic projection of the circuit unit on the substrate, or the position and shape of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position and shape of the orthographic projection of the circuit unit on the substrate.

[0091] In an exemplary embodiment, the display substrate of the present disclosure may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, wherein at least one circuit unit includes at least a pixel driving circuit and at least one control signal line, wherein the control signal line is configured to provide a control signal to the pixel driving circuit to control the conduction and disconnection of a transistor in the pixel driving circuit. In at least one circuit unit, the pixel driving circuit includes at least a driving transistor, a first control transistor, and a second control transistor, wherein the first control transistor and the second control transistor are respectively connected to the driving transistor; and in at least one pixel driving circuit of at least one unit row, the first control transistor is connected to the control signal line in the previous unit row, and the second control transistor is connected to the control signal line in the current unit row.

[0092] In an exemplary embodiment, the control signal line includes a light-emitting signal line, the first control transistor includes a first light-emitting control transistor, the second control transistor includes a second light-emitting control transistor, the first electrode of the first light-emitting control transistor is connected to the first power line, the second electrode of the first light-emitting control transistor is connected to the first electrode of the driving transistor, and the first electrode of the second light-emitting control transistor is connected to the second electrode of the driving transistor; in at least one pixel driving circuit of at least one unit row, the gate electrode of the first control transistor is connected to the light-emitting signal line in the previous unit row, and the gate electrode of the second control transistor is connected to the light-emitting signal line in the current unit row.

[0093] In an exemplary embodiment, the control signal line includes a scanning signal line, the first control transistor includes a third initialization transistor, the second control transistor includes a second initialization transistor, the first electrode of the second initialization transistor is connected to the second initial signal line, the second electrode of the second initialization transistor is connected to the second electrode of the driving transistor through the second light-emitting control transistor, the first electrode of the third initialization transistor is connected to the third initial signal line, and the second electrode of the third initialization transistor is connected to the first electrode of the driving transistor; in at least one pixel driving circuit of at least one unit row, the gate electrode of the third initialization transistor is connected to the scanning signal line in the previous unit row, and the gate electrode of the second initialization transistor is connected to the scanning signal line in the current unit row.

[0094] In an exemplary embodiment, the pixel driving circuit further includes a first initialization transistor, a compensation transistor and an isolation transistor, the first electrode of the first initialization transistor is connected to the first initial signal line, the second electrode of the first initialization transistor and the first electrode of the compensation transistor are connected to the first electrode of the isolation transistor, the second electrode of the isolation transistor is connected to the gate electrode of the driving transistor, and the second electrode of the compensation transistor is connected to the second electrode of the driving transistor.

[0095] In another exemplary embodiment, the pixel driving circuit further includes a first initialization transistor and a compensation transistor, the first electrode of the first initialization transistor is connected to the first initial signal line, the second electrode of the first initialization transistor and the first electrode of the compensation transistor are connected to the gate electrode of the driving transistor, and the second electrode of the compensation transistor is connected to the second electrode of the driving transistor.

[0096] The display substrate of the exemplary embodiments of the present disclosure will be described below with reference to some examples.

[0097] Figure 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit according to an exemplary embodiment of the present disclosure. As shown in Figure 4, the pixel driving circuit has a 9T1C structure and may include nine transistors (first transistor T1 to ninth transistor T9) and one storage capacitor C. Each pixel driving circuit is connected to 12 signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, fifth scan signal line S5, first light-emitting signal line EM1, second light-emitting signal line EM2, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, data signal line DATA, and first power line VDD).

[0098] In an exemplary embodiment, each pixel driving circuit may include a first node N1, a second node N2, a third node N3, a fourth node N4, and a fifth node. The first node N1 is connected to the gate electrode of the third transistor T3, the second electrode of the ninth transistor T9, and the first end of the storage capacitor C, respectively. The second node N2 is connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8, respectively. The third node N3 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively. The fourth node N4 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, respectively. The fifth node N5 is connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the first electrode of the ninth transistor T9, respectively. The fourth node N4 is also connected to the first electrode of the light emitting device EL.

[0099] In an exemplary embodiment, a first terminal of the storage capacitor C in the pixel driving circuit is connected to the first node N1 , and a second terminal of the storage capacitor C is connected to the first power line VDD.

[0100] In an exemplary embodiment, the first transistor T1 may be referred to as a first initialization transistor, a gate electrode of the first transistor T1 is connected to the third scan signal line S3 , a first electrode of the first transistor T1 is connected to the first initial signal line INIT1 , and a second electrode of the first transistor T1 is connected to the fifth node N5 .

[0101] In an exemplary embodiment, the second transistor T2 may be referred to as a compensation transistor, a gate electrode of the second transistor T2 is connected to the first scan signal line S1 , a first electrode of the second transistor T2 is connected to the fifth node N5 , and a second electrode of the second transistor T2 is connected to the third node N3 .

[0102] In an exemplary embodiment, the third transistor T3 may be referred to as a driving transistor, a gate electrode of the third transistor T3 is connected to the first node N1 , a first electrode of the third transistor T3 is connected to the second node N2 , and a second electrode of the third transistor T3 is connected to the third node N3 .

[0103] In an exemplary embodiment, the fourth transistor T4 may be referred to as a data writing transistor, a gate electrode of the fourth transistor T4 is connected to the second scan signal line S2 , a first electrode of the fourth transistor T4 is connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is connected to the second node N2 .

[0104] In an exemplary embodiment, the fifth transistor T5 may be referred to as a first light emission control transistor, a gate electrode of the fifth transistor T5 is connected to the first light emission signal line EM1, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2.

[0105] In an exemplary embodiment, the sixth transistor T6 may be referred to as a second light emission control transistor, a gate electrode of the sixth transistor T6 is connected to the second light emission signal line EM2 , a first electrode of the sixth transistor T6 is connected to the third node N3 , and a second electrode of the sixth transistor T6 is connected to the fourth node N4 .

[0106] In an exemplary embodiment, the seventh transistor T7 may be referred to as a second initialization transistor, a gate electrode of the seventh transistor T7 is connected to the fourth scan signal line S4, a first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and a second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0107] In an exemplary embodiment, the eighth transistor T8 may be referred to as a third initialization transistor, a gate electrode of the eighth transistor T8 is connected to the fifth scan signal line S5, a first electrode of the eighth transistor T8 is connected to the third initialization signal line INIT3, and a second electrode of the eighth transistor T8 is connected to the second node N2.

[0108] In an exemplary embodiment, a gate electrode of the ninth transistor T9 is connected to the second scan signal line S2 , a first electrode of the ninth transistor T9 is connected to the fifth node N5 , and a second electrode of the ninth transistor T9 is connected to the first node N1 .

[0109] In an exemplary embodiment, a first electrode of the light-emitting device EL is connected to the fourth node N4, and a second electrode of the light-emitting device EL is connected to the second power supply line VSS. The light-emitting device EL may be an OLED including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED including a stacked first electrode, a quantum dot light-emitting layer, and a second electrode.

[0110] In an exemplary embodiment, the signal of the first power line VDD is a continuously provided high level signal, and the signal of the second power line VSS is a continuously provided low level signal.

[0111] In some possible exemplary embodiments, the first transistor T1 to the ninth transistor T9 in the pixel driving circuit may be a P-type transistor, or may be an N-type transistor. In other possible exemplary embodiments, the first transistor T1 to the ninth transistor T9 in the pixel driving circuit may include a P-type transistor and an N-type transistor.

[0112] In an exemplary embodiment, the first transistor T1 to the ninth transistor T9 in the pixel driving circuit may be low-temperature polysilicon transistors, or oxide transistors, or both. The active layer of the low-temperature polysilicon transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Integrating low-temperature polysilicon transistors and oxide transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can leverage the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0113] As shown in FIG4 , in this exemplary embodiment, the first transistor T1 and the second transistor T2 in the pixel driving circuit may be oxide transistors (N-type transistors), and the third transistor T3 to the ninth transistor T9 may be low-temperature polysilicon transistors (P-type transistors).

[0114] FIG5A is a driving timing diagram of the pixel driving circuit shown in FIG4. As shown in FIG5A, in an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0115] The first phase A1 can be referred to as a phase in which the second node N2 and the fourth node N4 are reset. The signals on the first scan signal line S1, the third scan signal line S3, the fourth scan signal line S4, and the fifth scan signal line S5 are low-level signals, while the signals on the second scan signal line S2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals. This turns on the seventh transistor T7 and the eighth transistor T8, while turning off the other transistors.

[0116] The seventh transistor T7 is turned on so that the signal of the second initialization signal line INIT2 is provided to the fourth node N4, thereby initializing (resetting) the first electrode of the light-emitting device EL, clearing the original charge in the first electrode of the light-emitting device EL, and setting the potential of the fourth node N4 to Vinit2. The eighth transistor T8 is turned on so that the signal of the third initialization signal line INIT3 is provided to the second node N2, thereby initializing (resetting) the second node N2, and setting the potential of the second node N2 to Vinit3.

[0117] The second phase A2 can be called the first node N1 reset phase. The signal on the first scan signal line S1 is a low-level signal. The signal on the second scan signal line S2 is a low-level signal twice and a high-level signal the rest of the time. The signals on the third scan signal line S3, the fourth scan signal line S4, the fifth scan signal line S5, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals, turning on the first transistor T1, turning on the fourth transistor T4 and the ninth transistor T9 twice, and turning off the other transistors.

[0118] When the first transistor T1 is turned on, the signal from the first initial signal line INIT1 is provided to the fifth node N5. When the fourth transistor T4 and the ninth transistor T9 are turned on, the signal from the first initial signal line INIT1 is provided to the first node N1, initializing (resetting) the first node N1 and clearing the existing charge in the first node N1. The potential of the first node N1 is Vinit1. Because the ninth transistor T9 is a low-temperature polysilicon transistor, before the ninth transistor T9 is turned on for the first time, it is affected by the potential of the first node N1 and the gate bias. The potential of the first node N1 is related to the data voltage in the previous stage, and thus the characteristics of the ninth transistor T9 are affected by the previous stage. After the ninth transistor T9 is turned on for the first time, the potential of the first node N1 is reset to Vinit1. The gate voltage of the ninth transistor T9 is relatively fixed, whether high or low. Therefore, after the first turn-on and turn-off, the influence of the previous stage data on the characteristics of the ninth transistor T9 is cleared. When the ninth transistor T9 is turned on for the second time, the potential of the first node N1 is reset to Vinit1 again. By resetting the first node N1 twice in succession, the present disclosure can effectively eliminate the influence of the data voltage in the previous stage on the characteristics of the ninth transistor T9, thereby improving afterimages and low grayscale image quality. In addition, because the fourth transistor T4 is turned on twice in this stage, the data signal line DATA writes the data voltages of the previous several cell rows to the second node N2, changing the potential of the second node N2. As a result, the gate-source voltage of the third transistor T3 changes, resetting the characteristics of the third transistor T3, and thus improving afterimages.

[0119] The third stage A3 can be called the third node N3 reset stage. The signals on the first scan signal line S1, the second scan signal line S2, the third scan signal line S3, the fourth scan signal line S4, the fifth scan signal line S5, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals, turning on the first transistor T1 and the second transistor T2, and turning off the other transistors.

[0120] The second transistor T2 is turned on, so that the third node N3 and the fifth node N5 are turned on, and the first transistor T1 is turned on so that the signal of the first initial signal line INIT1 is provided to the third node N3, the third node N3 is initialized (reset), the original charge in the third node N3 is cleared, and the potential of the third node N3 is Vinit1.

[0121] The fourth phase A4 can be called a data writing phase. The signal on the third scan signal line S3 is a low-level signal, the signal on the second scan signal line S2 is a low-level signal for a short period of time, and the signals on the first scan signal line S1, the fourth scan signal line S4, the fifth scan signal line S5, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals, turning on the second transistor T2, the fourth transistor T4, and the ninth transistor T9, while turning off the other transistors.

[0122] The second transistor T2 is turned on, thereby conducting the third node N3 and the fifth node N5. The ninth transistor T9 is turned on, thereby conducting the first node N1 and the fifth node N5. Since the third transistor T3 is continuously turned on during this stage, the fourth transistor T4 is turned on, causing the data signal output from the data signal line DATA to be provided to the first node N1 through the second node N2, the turned-on third transistor T3, the third node N3, the turned-on second transistor T2, the fifth node N5, and the turned-on ninth transistor T9. The difference between the data voltage output from the data signal line DATA and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage at the first node N1 is Vd1-|Vth|, where Vd is the data voltage output from the data signal line DATA and Vth is the threshold voltage of the third transistor T3. When the ninth transistor T9 is turned off, the storage capacitor C holds the data voltage.

[0123] The fifth stage A5 can be referred to as a reset stage for the second node N2, the third node N3, and the fourth node N4. The signals on the first scan signal line S1 and the third scan signal line S3 are low-level signals. The signals on the fourth scan signal line S4 and the fifth scan signal line S5 are low-level signals in succession for a short period of time. The signals on the second scan signal line S2, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals. This turns on the seventh transistor T7 and the eighth transistor T8, while turning off the other transistors.

[0124] The seventh transistor T7 is turned on, causing the signal of the second initial signal line INIT2 to be supplied to the fourth node N4. Since the third transistor T3 is continuously turned on during this stage, the eighth transistor T8 is turned on, causing the signal of the third initial signal line INIT3 to be supplied to the second node N2 and the third node N3, respectively resetting the second node N2, the third node N3, and the fourth node N4. The potentials of the second node N2 and the third node N3 are Vinit3, and the potential of the fourth node N4 is Vinit2. Resetting the second node N2, the third node N3, and the fourth node N4 in this stage can eliminate and reduce hysteresis deviation caused by grayscale differences between adjacent pixels. It can also periodically reset the OLED anode to improve low-frequency flicker.

[0125] The sixth stage A6 can be referred to as a stage where the second node N2 and the third node N3 are reset. The signals on the first scan signal line S1, the third scan signal line S3, and the first light-emitting signal line EM1 are low-level signals, while the signals on the second scan signal line S2, the fourth scan signal line S4, the fifth scan signal line S5, and the second light-emitting signal line EM2 are high-level signals, turning on the fifth transistor T5 and turning off the other transistors.

[0126] The fifth transistor T5 is turned on so that the power supply voltage Vdd outputted from the first power supply line VDD is provided to the second node N2 and the third node N3, thereby resetting the second node N2 and the third node N3, that is, resetting the first electrode and the second electrode of the third transistor T3.

[0127] The seventh stage A7 can be called the light-emitting stage. The signals on the first scan signal line S1, the third scan signal line S3, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are low-level signals, and the signals on the second scan signal line S2, the fourth scan signal line S4, and the fifth scan signal line S5 are high-level signals, turning on the fifth transistor T5 and the sixth transistor T6, and turning off the other transistors.

[0128] The fifth transistor T5 and the sixth transistor T6 are turned on so that the power voltage output from the first power line VDD provides a driving voltage to the first electrode of the light emitting device EL through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the light emitting device EL to emit light.

[0129] During the pixel driving circuit driving process, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the first node N1 is Vd-|Vth|, the driving current of the third transistor T3 is: I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd] 2

[0130] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device EL, K is a constant related to process and design, and Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3.

[0131] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 of each pixel driving circuit is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0132] FIG5B is another driving timing diagram of the pixel driving circuit shown in FIG4 . As shown in FIG5B , in an exemplary embodiment, the operation of the pixel driving circuit is substantially the same as that of FIG5A , except that: in the first phase A1, the signals on the fourth scan signal line S4 and the fifth scan signal line S5 are high-level signals, the seventh transistor T7 and the eighth transistor T8 are off, and the second node N2 and the fourth node N4 are not reset during this phase. In the fifth phase A5, before the seventh transistor T7 and the eighth transistor T8 are turned on, the second scan signal line S2 is low-level for a short period of time, and the fourth transistor T4 and the ninth transistor T9 are turned on again. The fourth transistor T4 is turned on, causing the data voltage of the next cell row to reset the second node N2 and the third node N3. The ninth transistor T9 is turned on, causing the first node N1 and the fifth node N5 to be conductive. After the charges on the two nodes are neutralized, there is no longer a potential difference between the two nodes.

[0133] Figure 6 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure. In this exemplary embodiment, the display substrate may include a plurality of circuit units, which may form a plurality of unit rows and a plurality of unit columns. The plurality of circuit units in each unit row are sequentially arranged along a first direction X, and the plurality of unit rows are sequentially arranged along a second direction Y, forming an array of circuit units arranged in an array, with the first direction X intersecting the second direction Y.

[0134] As shown in FIG6 , at least one circuit unit may include a pixel driving circuit, and first scan signal lines 21, second scan signal lines 22, third scan signal lines 23, fourth scan signal lines 24, light emitting signal lines 25, first initial signal lines 41, second initial signal lines 42, third initial signal lines 43, first power supply lines 61, and data signal lines 62 connected to the pixel driving circuit. In an exemplary embodiment, the first scan signal lines 21, second scan signal lines 22, third scan signal lines 23, fourth scan signal lines 24, light emitting signal lines 25, first initial signal lines 41, second initial signal lines 42, and third initial signal lines 43 may be in the shape of a straight line with a main portion extending along the first direction X or a zigzag line, and the first power supply lines 61 and data signal lines 62 may be in the shape of a straight line with a main portion extending along the second direction Y or a zigzag line.

[0135] In this disclosure, "A extends along direction B" means that A can include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In the following description, "A extends along direction B" means "the main portion of A extends along direction B."

[0136] In an exemplary embodiment, at least one pixel driving circuit may include at least a storage capacitor and a plurality of transistors, the storage capacitor may include a stacked first electrode plate and a second electrode plate, and the plurality of transistors may include a first transistor T1 as a first initialization transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a drive transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first emission control transistor, a sixth transistor T6 as a second emission control transistor, a seventh transistor T7 as a second initialization transistor, an eighth transistor T8 as a third initialization transistor, and a ninth transistor T9 as an isolation transistor. The first transistor T1 and the second transistor T2 are oxide transistors, and the third transistor T3 to the ninth transistor T9 are low-temperature polysilicon transistors.

[0137] In the exemplary embodiment, a first electrode of the first transistor T1 is connected to the first initial signal line 41, a first electrode of the fourth transistor T4 is connected to the data signal line 62, a first electrode of the fifth transistor T5 is connected to the first power supply line 61, a first electrode of the seventh transistor T7 is connected to the second initial signal line 42, and a first electrode of the eighth transistor T8 is connected to the third initial signal line 43. The second electrode of the first transistor T1 and the first electrode of the second transistor T2 are connected to the first electrode of the ninth transistor T9, the second electrode of the ninth transistor T9 is connected to the gate electrode (the first plate of the storage capacitor) of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8 are connected to the first electrode of the third transistor T3, the second electrode of the second transistor T2 and the first electrode of the sixth transistor T6 are connected to the second electrode of the third transistor T3, and the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7.

[0138] In an exemplary embodiment, in at least one pixel driving circuit in at least one unit row, the gate electrode of the fifth transistor T5 is connected to the light emission signal line 25 in the previous unit row, and the gate electrode of the sixth transistor T6 is connected to the light emission signal line 25 in the current unit row. For example, the gate electrode of the fifth transistor T5 in the pixel driving circuit in the nth unit row is connected to the light emission signal line 25 in the (n-1)th unit row, and the gate electrode of the sixth transistor T6 in the pixel driving circuit in the nth unit row is connected to the light emission signal line 25 in the nth unit row. For another example, the gate electrode of the fifth transistor T5 in the pixel driving circuit in the (n+1)th unit row is connected to the light emission signal line 25 in the nth unit row, and the gate electrode of the sixth transistor T6 in the pixel driving circuit in the (n+1)th unit row is connected to the light emission signal line 25 in the (n+1)th unit row. In an exemplary embodiment, the light emission signal line 25 can serve as a control signal line of the present disclosure, the fifth transistor T5 can serve as a first control transistor of the present disclosure, and the sixth transistor T6 can serve as a second control transistor of the present disclosure, where n is a positive integer greater than 1.

[0139] In an exemplary embodiment, in at least one pixel driving circuit, the fifth transistor T5 and the sixth transistor T6 connected to the same third transistor T3 may be respectively disposed on both sides of the third transistor T3 in the second direction Y (unit column direction). For example, in a pixel driving circuit in the nth unit row, the fifth transistor T5 may be disposed on a side opposite to the second direction Y of the third transistor T3, and the sixth transistor T6 may be disposed on a side of the third transistor T3 in the second direction Y.

[0140] In an exemplary embodiment, the fifth transistor T5 may include at least a fifth active layer, and the sixth transistor T6 may include at least a sixth active layer. The fifth active layer may serve as the first light emission control active layer of the present disclosure, and the sixth active layer may serve as the second light emission control active layer of the present disclosure. In at least one pixel driving circuit of at least one unit row, the fifth active layer may be disposed in the circuit unit of the previous unit row, and the sixth active layer may be disposed in the circuit unit of the current unit row. For example, in a pixel driving circuit of the nth unit row, the fifth active layer may be disposed in the circuit unit of the (n-1)th unit row, and the sixth active layer may be disposed in the circuit unit of the nth unit row.

[0141] In an exemplary embodiment, in at least one pixel driving circuit of at least one unit row, the fifth active layer may be disposed on one side of the first direction X (unit row direction) of the sixth active layer of the pixel driving circuit in the previous unit row. For example, in a pixel driving circuit in the nth unit row, the fifth active layer may be disposed on one side of the first direction X of the sixth active layer of the pixel driving circuit in the (n-1)th unit row.

[0142] In an exemplary embodiment, the pixel driving circuit may further include a storage capacitor and a power connection electrode 54. The storage capacitor may include a first plate 31 and a second plate 32. The orthographic projection of the first plate 31 on the display substrate plane at least partially overlaps with the orthographic projection of the second plate 32 on the display substrate plane. In at least one pixel driving circuit in at least one unit row, the first end of the power connection electrode 54 is connected to the first region of the fifth active layer of the pixel driving circuit in the next unit row, and the second end of the power connection electrode 54 is connected to the second plate 32 of the pixel driving circuit in the unit row. For example, in a pixel driving circuit in the nth unit row, the first end of the power connection electrode 54 is connected to the first region of the fifth active layer of the pixel driving circuit in the (n+1)th unit row, and the second end of the power connection electrode 54 is connected to the second plate 32 of the pixel driving circuit in the nth unit row.

[0143] In an exemplary embodiment, in at least one pixel driving circuit in at least one unit row, the gate electrode of the eighth transistor T8 is connected to the fourth scan signal line 24 in the previous unit row, and the gate electrode of the seventh transistor T7 is connected to the fourth scan signal line 24 in the current unit row. For example, the gate electrode of the eighth transistor T8 in the pixel driving circuit in the nth unit row is connected to the fourth scan signal line 24 in the (n-1)th unit row, and the gate electrode of the seventh transistor T7 in the pixel driving circuit in the nth unit row is connected to the fourth scan signal line 24 in the nth unit row. For another example, the gate electrode of the eighth transistor T8 in the pixel driving circuit in the (n+1)th unit row is connected to the fourth scan signal line 24 in the nth unit row, and the gate electrode of the seventh transistor T7 in the pixel driving circuit in the (n+1)th unit row is connected to the fourth scan signal line 24 in the (n+1)th unit row. In an exemplary embodiment, the fourth scan signal line 24 can serve as another control signal line of the present disclosure, the eighth transistor T8 can serve as another first control transistor of the present disclosure, and the seventh transistor T7 can serve as another second control transistor of the present disclosure.

[0144] In an exemplary embodiment, in at least one pixel driving circuit, the seventh transistor T7 and the eighth transistor T8 connected to the same third transistor T3 may be respectively disposed on both sides of the third transistor T3 in the second direction Y. For example, in a pixel driving circuit in the nth unit row, the eighth transistor T8 may be disposed on a side opposite to the second direction Y of the third transistor T3, and the seventh transistor T7 may be disposed on one side of the third transistor T3 in the second direction Y.

[0145] In an exemplary embodiment, the seventh transistor T7 may include at least a seventh active layer, and the eighth transistor T8 may include at least an eighth active layer. The seventh transistor T7 may serve as the second initialization active layer of the present disclosure, and the eighth active layer may serve as the third initialization active layer of the present disclosure. In at least one pixel driving circuit of at least one unit row, the eighth active layer may be provided in the circuit unit of the previous unit row, and the seventh active layer may be provided in the circuit unit of the current unit row. For example, in a pixel driving circuit of the nth unit row, the eighth active layer may be provided in the circuit unit of the (n-1)th unit row, and the seventh active layer may be provided in the circuit unit of the nth unit row.

[0146] In an exemplary embodiment, in at least one pixel driving circuit of at least one unit row, the eighth active layer may be disposed on one side in the first direction X (unit row direction) of the seventh active layer of the pixel driving circuit in the previous unit row. For example, in a pixel driving circuit in the nth unit row, the eighth active layer may be disposed on one side in the first direction X of the seventh active layer of the pixel driving circuit in the (n-1)th unit row.

[0147] In an exemplary embodiment, in at least one pixel driving circuit of at least one unit row, the first area of ​​the seventh active layer is connected to the second initial signal line 42 in the current unit row, and the first area of ​​the eighth active layer is connected to the third initial signal line 43 in the previous unit row. For example, in a pixel driving circuit in the nth unit row, the first area of ​​the seventh active layer is connected to the second initial signal line 42 in the nth unit row, and the first area of ​​the eighth active layer is connected to the third initial signal line 43 in the (n-1)th unit row.

[0148] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include a first semiconductor layer arranged on a substrate, a first conductive layer arranged on a side of the first semiconductor layer away from the substrate, a second conductive layer arranged on a side of the first conductive layer away from the substrate, a second semiconductor layer arranged on a side of the second conductive layer away from the substrate, a third conductive layer arranged on a side of the second semiconductor layer away from the substrate, a fourth conductive layer arranged on a side of the third conductive layer away from the substrate, and a fifth conductive layer arranged on a side of the fourth conductive layer away from the substrate. The first semiconductor layer may include at least the active layers of the third transistor T3 to the ninth transistor T9, the first conductive layer may include at least the second scan signal line 22, the fourth scan signal line 24, the light-emitting signal line 25, the first initial signal line 41 and the first plate 31 of the storage capacitor, the second conductive layer may include at least the second plate 32 of the storage capacitor, the second semiconductor layer may include at least the active layers of the first transistor T1 and the second transistor T2, the third conductive layer may include at least the first scan signal line 21, the third scan signal line 23, the second initial signal line 42 and the third initial signal line 43, the fourth conductive layer may include at least a plurality of connecting electrodes, and the fifth conductive layer may include at least the first power line 61 and the data signal line 62.

[0149] In an exemplary embodiment, an orthographic projection of the second preliminary signal line 42 on the substrate at least partially overlaps with an orthographic projection of the fourth scan signal line 24 on the substrate.

[0150] In an exemplary embodiment, an orthographic projection of the third initial signal line 43 on the substrate at least partially overlaps with an orthographic projection of the light emitting signal line 25 on the substrate.

[0151] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes the deposition of film layers, coating of photoresist on the film layers, mask exposure, development, etching, stripping of photoresist and other processes for metal materials, inorganic materials or transparent conductive materials, and includes the coating of organic materials, mask exposure and development and other processes for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0152] In an exemplary embodiment, taking a circuit unit as an example, the preparation process of the display substrate in this embodiment may include the following operations.

[0153] (1) Forming a blocking layer pattern. In an exemplary embodiment, forming the blocking layer pattern may include: depositing a blocking film on a substrate, patterning the blocking film through a patterning process, and forming a blocking layer pattern on the substrate, as shown in FIG7 . In an exemplary embodiment, the blocking layer may be referred to as a bottom blocking metal (BSM) layer.

[0154] In an exemplary embodiment, the shielding layer pattern in each circuit unit may include at least a first shielding connection line 91 , a second shielding connection line 92 , and a shielding electrode 93 .

[0155] In an exemplary embodiment, the shielding electrode 93 may be rectangular in shape, and the corners of the rectangle may be chamfered. The first shielding connection line 91 may be in the shape of a straight line or a zigzag line extending along the first direction X. The first shielding connection line 91 may be disposed on both sides of the shielding electrode 93 in the first direction X and connected to the shielding electrode 93. The second shielding connection line 92 may be in the shape of a straight line or a zigzag line extending along the second direction Y. The second shielding connection line 92 may be disposed on both sides of the shielding electrode 93 in the second direction Y and connected to the shielding electrode 93.

[0156] In an exemplary embodiment, within a cell row, the first shielding connection lines 91 in two adjacent circuit cells in the first direction X can be connected to form an interconnected, integrated structure. And / or, within a cell column, the second shielding connection lines 92 in two adjacent circuit cells in the second direction Y can be connected to form an interconnected, integrated structure. The integrated connection of the shielding layers in the cell rows and columns ensures that the shielding layers in the display substrate have the same potential, which helps improve panel uniformity, prevent display defects on the display substrate, and ensure the display quality of the display substrate.

[0157] In an exemplary embodiment, the first shielding connection lines 91 on both sides of the shielding electrode 93 can be located on a straight line extending along the first direction X, and the second shielding connection lines 92 on both sides of the shielding electrode 93 can be staggered in the first direction X, which is not limited in this disclosure.

[0158] (2) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming the first semiconductor layer pattern may include: sequentially depositing a first insulating film and a first semiconductor film on the substrate on which the aforementioned pattern is formed, patterning the first semiconductor film through a patterning process to form a first insulating layer covering the shielding layer, and a first semiconductor layer pattern disposed on the first insulating layer, as shown in FIG8A and FIG8B , where FIG8B is a plan view schematic diagram of the first semiconductor layer in FIG8A .

[0159] In an exemplary embodiment, the first semiconductor layer pattern in each circuit unit may include at least the third active layer 13 of the third transistor T3 to the ninth active layer 19 of the ninth transistor T9, and the third active layer 13, the fourth active layer 14, the sixth active layer 16 and the seventh active layer 17 are an integrated structure connected to each other, and the fifth active layer 15, the eighth active layer 18 and the ninth active layer 19 are separately provided.

[0160] In an exemplary embodiment, the orthographic projection of the third active layer 13 on the substrate at least partially overlaps with the orthographic projection of the shielding electrode 93 on the substrate. The shielding electrode 93 serves as a shielding layer for the third transistor T3, shielding the channel region of the third transistor T3 to ensure the electrical performance of the third transistor T3.

[0161] In an exemplary embodiment, in the pixel driving circuit of the present circuit unit, in the first direction X, the fourth active layer 14, the fifth active layer 15, and the eighth active layer 18 may be located on one side of the third active layer 13 in the present circuit unit in the first direction X, and the sixth active layer 16 may be located on a side of the third active layer 13 in the present circuit unit in the opposite direction to the first direction X. In the second direction Y, the sixth active layer 16 and the seventh active layer 17 may be located on one side of the third active layer 13 in the present circuit unit in the second direction Y, and the fourth active layer 14, the fifth active layer 15, the eighth active layer 18, and the ninth active layer 19 may be located on a side of the third active layer 13 in the present circuit unit in the opposite direction to the second direction Y.

[0162] In example embodiments, the ninth active layer 19 may be located on a side of the fourth active layer 14 in an opposite direction to the first direction X.

[0163] In an exemplary embodiment, the third active layer 13 may have an inverted "Ω" shape, the fourth active layer 14, the fifth active layer 15, the sixth active layer 16, and the ninth active layer 19 may have a strip shape with a main portion extending along the second direction Y, and the seventh active layer 17 and the eighth active layer 18 may have an "L" shape.

[0164] In an exemplary embodiment, each of the third to ninth active layers 13 to 19 may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the first region 13-1 of the third active layer is connected to the second region 14-2 of the fourth active layer, and the first region 13-1 of the third active layer may serve as the second region 14-2 of the fourth active layer. The second region 13-2 of the third active layer is connected to the first region 16-1 of the sixth active layer, and the second region 13-2 of the third active layer may serve as the first region 16-1 of the sixth active layer. The second region 16-2 of the sixth active layer is connected to the second region 17-2 of the seventh active layer, and the second region 16-2 of the sixth active layer may serve as the second region 17-2 of the seventh active layer. The first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, the second region 15-2 of the fifth active layer, the first region 17-1 of the seventh active layer, the first region 18-1 of the eighth active layer, the second region 18-2 of the eighth active layer, the first region 19-1 of the ninth active layer, and the second region 19-2 of the ninth active layer can be set separately.

[0165] In an exemplary embodiment, in a unit column, the fifth active layer 15 and the eighth active layer 18 of the pixel driving circuit in the present circuit unit can be set in the circuit unit of the previous unit row, and the third active layer 13, the fourth active layer 14, the sixth active layer 16, the seventh active layer 17 and the ninth active layer 19 can be set in the present circuit unit.

[0166] In an exemplary embodiment, the fifth active layer 15 of the pixel driving circuit in the circuit unit of the current unit row can be located on one side of the sixth active layer 16 of the pixel driving circuit in the circuit unit of the previous unit row in the first direction X, so that the fifth active layer 15 and the sixth active layer 16 of the pixel driving circuit in the circuit unit of the previous unit row can share a light-emitting signal line, and the light-emitting signal line can simultaneously control the conduction and disconnection of the sixth transistor T6 of the current unit row and the fifth transistor T5 of the next unit row. For example, the fifth active layer 15 of the pixel driving circuit in the nth unit row is disposed in the circuit unit of the n-1th unit row, so that the fifth active layer 15 of the pixel driving circuit in the nth unit row and the sixth active layer 16n-1 of the pixel driving circuit in the n-1th unit row can share a light-emitting signal line, and the light-emitting signal line can simultaneously control the conduction and disconnection of the fifth transistor T5 of the nth unit row and the sixth transistor T6 of the n-1th unit row. For another example, the fifth active layer 15n+1 of the pixel driving circuit in the n+1th unit row is arranged in the circuit unit of the nth unit row, so that the fifth active layer 15n+1 of the pixel driving circuit in the n+1th unit row and the sixth active layer 16 of the pixel driving circuit in the nth unit row can share a light-emitting signal line, and the one light-emitting signal line can simultaneously control the conduction and disconnection of the fifth transistor T5 of the n+1th unit row and the sixth transistor T6 of the nth unit row.

[0167] In an exemplary embodiment, the eighth active layer 18 of the pixel driving circuit in the circuit unit of the current unit row can be located on one side of the seventh active layer 17 of the pixel driving circuit in the circuit unit of the previous unit row in the first direction X, so that the seventh active layer 17 and the eighth active layer 18 of the two unit rows can share a scan signal line, and the scan signal line can simultaneously control the conduction and disconnection of the seventh transistor T7 of the current unit row and the eighth transistor T8 of the next unit row. For example, the eighth active layer 18 of the pixel driving circuit in the n-th unit row is disposed in the circuit unit of the n-1-th unit row, so that the eighth active layer 18 of the pixel driving circuit in the n-th unit row and the seventh active layer 17n-1 of the pixel driving circuit in the n-1-th unit row can share a scan signal line, and the scan signal line can simultaneously control the conduction and disconnection of the seventh transistor T7 of the n-1-th unit row and the eighth transistor T8 of the n-th unit row. For another example, the eighth active layer 18n+1 of the pixel driving circuit in the n+1th unit row is arranged in the circuit unit of the nth unit row, so that the eighth active layer 18n+1 of the pixel driving circuit in the n+1th unit row and the seventh transistor T7 of the pixel driving circuit in the nth unit row can share a scanning signal line, and the one scanning signal line can simultaneously control the conduction and disconnection of the seventh transistor T7 of the nth unit row and the eighth transistor T8 of the n+1th unit row.

[0168] In an exemplary embodiment, the first semiconductor layer may be made of polycrystalline silicon (p-Si), meaning that the third transistor T3 to the ninth transistor T9 are LTPS transistors. In an exemplary embodiment, patterning the first semiconductor film through a patterning process may include: first forming an amorphous silicon (a-Si) film on the first insulating film, performing a dehydrogenation treatment on the amorphous silicon film, and then crystallizing the dehydrogenated amorphous silicon film to form a polycrystalline silicon film. Subsequently, patterning the polycrystalline silicon film to form a first semiconductor layer pattern.

[0169] (3) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a second insulating layer covering the first semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG9A and FIG9B , FIG9B being a planar schematic diagram of the first conductive layer in FIG9A . In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0170] In an exemplary embodiment, the first conductive layer pattern of each circuit unit may include at least a second scan signal line 22 , a fourth scan signal line 24 , a light emitting signal line 25 , a first initial signal line 41 , and a first plate 31 of a storage capacitor.

[0171] In an exemplary embodiment, the first electrode plate 31 may be rectangular, and the corners of the rectangle may be chamfered. The orthographic projection of the first electrode plate 31 on the substrate at least partially overlaps the orthographic projection of the third active layer of the third transistor T3 on the substrate. In an exemplary embodiment, the first electrode plate 31 may serve as both a plate of the storage capacitor and a gate electrode of the third transistor T3.

[0172] In an exemplary embodiment, an orthographic projection of the first electrode plate 31 on the substrate at least partially overlaps with an orthographic projection of the shielding electrode 93 on the substrate.

[0173] In an exemplary embodiment, the shape of the second scanning signal line 22 can be a straight line or a broken line with the main portion extending along the first direction X. The second scanning signal line 22 can be located on the side of the first electrode 31 in the opposite direction of the second direction Y. The area where the second scanning signal line 22 overlaps with the fourth active layer can serve as the gate electrode of the fourth transistor T4, and the area where the second scanning signal line 22 overlaps with the ninth active layer can serve as the gate electrode of the ninth transistor T9.

[0174] In an exemplary embodiment, the fourth scan signal line 24 may be in the shape of a straight line or a zigzag line, with the main portion extending along the first direction X. The fourth scan signal line 24 may be located on one side of the first electrode plate 31 in the second direction Y. The area where the fourth scan signal line 24 of the current unit row overlaps with the seventh active layer of the pixel driving circuit in the current unit row may serve as the gate electrode of the seventh transistor T7 of the current unit row, and the area where the fourth scan signal line 24 of the current unit row overlaps with the eighth active layer of the pixel driving circuit in the next unit row may serve as the gate electrode of the eighth transistor T8 of the next unit row. For example, for the fourth scan signal line 24 of the (n-1)th unit row, the area where the fourth scan signal line 24 overlaps with the seventh active layer of the pixel driving circuit in the (n-1)th unit row may serve as the gate electrode of the seventh transistor T7 in the (n-1)th unit row, and the area where the fourth scan signal line 24 overlaps with the eighth active layer of the pixel driving circuit in the (n)th unit row may serve as the gate electrode of the eighth transistor T8 in the (n)th unit row. For another example, for the fourth scanning signal line 24 of the nth unit row, the area overlapping with the seventh active layer of the pixel driving circuit in the nth unit row can be used as the gate electrode of the seventh transistor T7 in the nth unit row, and the area overlapping with the eighth active layer of the pixel driving circuit in the n+1th unit row can be used as the gate electrode of the eighth transistor T8 in the n+1th unit row.

[0175] In an exemplary embodiment, the shape of the light-emitting signal line 25 can be a straight line or a zigzag line with a main portion extending along the first direction X. The light-emitting signal line 25 can be located between the first electrode 31 and the fourth scanning signal line 24. The area where the light-emitting signal line 25 of the current unit row overlaps with the sixth active layer of the pixel driving circuit in the current unit row can serve as the gate electrode of the sixth transistor T6 of the current unit row, and the area where the light-emitting signal line 25 of the current unit row overlaps with the fifth active layer of the pixel driving circuit in the next unit row can serve as the gate electrode of the fifth transistor T5 of the next unit row. For example, for the light-emitting signal line 25 of the n-1th unit row, the area where it overlaps with the sixth active layer of the pixel driving circuit in the n-1th unit row can serve as the gate electrode of the sixth transistor T6 in the n-1th unit row, and the area where it overlaps with the fifth active layer of the pixel driving circuit in the nth unit row can serve as the gate electrode of the fifth transistor T5 in the nth unit row. For another example, for the light-emitting signal line 25 of the nth unit row, the area overlapping with the sixth active layer of the pixel driving circuit in the nth unit row can be used as the gate electrode of the sixth transistor T6 in the nth unit row, and the area overlapping with the fifth active layer of the pixel driving circuit in the n+1th unit row can be used as the gate electrode of the fifth transistor T5 in the n+1th unit row.

[0176] In an exemplary embodiment, the shape of the first initial signal line 41 can be a straight line or a broken line with the main portion extending along the first direction X. The first initial signal line 41 can be located on the side of the second scanning signal line 22 away from the first electrode 31. The first initial signal line 41 is configured to be connected to the first region of the first active layer through a seventh connecting electrode formed subsequently.

[0177] In an exemplary embodiment, the second scanning signal line 22, the fourth scanning signal line 24, the light-emitting signal line 25 and the first initial signal line 41 can be designed with non-equal widths, and the width is the dimension in the second direction Y, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the signal lines. The present disclosure does not limit this.

[0178] In an exemplary embodiment, the second scan signal line 22, the fourth scan signal line 24 and the light emitting signal line 25 may include an overlapping area with the first semiconductor layer and an area not overlapping with the first semiconductor layer, and the width of the signal line in the area overlapping with the first semiconductor layer may be greater than the width of the signal line in the area not overlapping with the first semiconductor layer.

[0179] In an exemplary embodiment, the dimension of the second direction Y of the overlapping area between the second scanning signal line 22 and the fourth active layer may be greater than the dimension of the second direction Y of the overlapping area between the second scanning signal line 22 and the ninth active layer, so that the channel length of the fourth transistor T4 is greater than the channel length of the ninth transistor T9. When the channel widths of the fourth transistor T4 and the ninth transistor T9 are similar, the channel width-to-length ratio of the ninth transistor T9 is greater than the channel width-to-length ratio of the fourth transistor T4.

[0180] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the first semiconductor layer. The first semiconductor layer in the area shielded by the first conductive layer forms the channel region of the third transistor T3 to the ninth transistor T9, and the first semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first electrode 31 and the first and second areas of the third active layer 13 to the ninth active layer 19 are all conductorized.

[0181] (4) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate having the aforementioned pattern formed thereon, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, as shown in FIG10A and FIG10B , where FIG10B is a plan view schematic diagram of the second conductive layer in FIG10A . In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0182] In an exemplary embodiment, the second conductive layer pattern of each circuit unit includes at least a second plate 32 of the storage capacitor, a first shielding line 33 , and a second shielding line 34 .

[0183] In an exemplary embodiment, the outline of the second electrode plate 32 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode plate 32 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 31 on the substrate. The second electrode plate 32 can serve as another electrode plate of the storage capacitor, and the first electrode plate 31 and the second electrode plate 32 constitute the storage capacitor of the pixel driving circuit.

[0184] In an exemplary embodiment, the second electrode plate 32 is provided with an opening 32-1. The opening 32-1 can be rectangular and located in the central region of the second electrode plate 32, forming an annular structure. The opening 32-1 exposes the third insulating layer covering the first electrode plate 31, and the orthographic projection of the first electrode plate 31 on the substrate includes the orthographic projection of the opening 32-1 on the substrate. In an exemplary embodiment, the opening 32-1 is configured to accommodate a fifteenth via hole to be formed later. The fifteenth via hole is located within the opening 32-1 and exposes the first electrode plate 31, allowing a first connecting electrode to be formed later to be connected to the first electrode plate 31 through the via hole.

[0185] In an exemplary embodiment, a plate 32-2 may be provided on the second electrode plate 32. The plate 32-2 may be in the shape of a strip extending along the first direction X. A first end of the plate 32-2 is connected to a side edge of the second electrode plate 32 in the first direction X, and a second end of the plate 32-2 extends away from the second electrode plate 32.

[0186] In an exemplary embodiment, the shape of the first shielding line 33 can be a straight line or a broken line with the main part extending along the first direction X. The first shielding line 33 can be located between the first electrode 31 and the second scanning signal line 22. The first shielding line 33 is configured as a shielding layer of the second transistor T2, shielding the channel region of the second transistor T2, ensuring the electrical performance of the oxide second transistor T2, and at the same time being configured as the bottom gate electrode of the second transistor T2.

[0187] In an exemplary embodiment, the shape of the second shielding line 34 can be a straight line or a broken line with the main part extending along the first direction X. The second shielding line 34 can be located between the second scanning signal line 22 and the first initial signal line 41. The second shielding line 34 is configured as a shielding layer of the first transistor T1, shielding the channel region of the first transistor T1, ensuring the electrical performance of the oxide first transistor T1, and at the same time being configured as the bottom gate electrode of the first transistor T1.

[0188] In an exemplary embodiment, the first shielding line 33 and the second shielding line 34 may be designed with unequal widths, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines.

[0189] (5) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming the second semiconductor layer pattern may include: sequentially depositing a fourth insulating film and a second semiconductor film on the substrate having the aforementioned pattern formed thereon, patterning the second semiconductor film through a patterning process to form a fourth insulating layer covering the substrate, and a second semiconductor layer pattern disposed on the fourth insulating layer, as shown in FIG11A and FIG11B , where FIG11B is a plan view schematic diagram of the second semiconductor layer in FIG11A .

[0190] In an exemplary embodiment, the second semiconductor layer pattern of each circuit unit includes at least a first active layer 11 of the first transistor T1 and a second active layer 12 of the second transistor T2 .

[0191] In an exemplary embodiment, the shape of the first active layer 11 and the second active layer 12 can be a strip shape with the main portion extending along the second direction Y, the orthographic projection of the first active layer 11 on the substrate at least partially overlaps with the orthographic projection of the second shading line 34 on the substrate, and the orthographic projection of the second active layer 12 on the substrate at least partially overlaps with the orthographic projection of the first shading line 33 on the substrate.

[0192] In an exemplary embodiment, the first region 11-1 of the first active layer can be located on the side of the second shielding line 34 away from the second electrode plate 32, the second region 12-2 of the second active layer can be located on the side of the first shielding line 33 close to the second electrode plate 32, the second region 11-2 of the first active layer is connected to the first region 12-1 of the second active layer, and the second region 11-2 of the first active layer can serve as the first region 12-1 of the second active layer.

[0193] In exemplary embodiments, the first active layer 11 and the second active layer 12 may be an integral structure connected to each other.

[0194] In an exemplary embodiment, the second active layer 12 may be located on a side of the ninth active layer 19 in a direction opposite to the first direction X. Since the fourth active layer 14 is located on a side of the ninth active layer 19 in the first direction X, the ninth active layer 19 may be located between the second active layer 12 and the fourth active layer 14 in the first direction X, that is, the channel region of the ninth transistor T9 is located between the channel region of the second transistor T2 and the channel region of the fourth transistor T4.

[0195] In an exemplary embodiment, the second semiconductor layer may be made of oxide, that is, the eighth transistor T8 is an oxide transistor. In an exemplary embodiment, the second semiconductor thin film may be made of indium gallium zinc oxide (IGZO), which has higher electron mobility than amorphous silicon.

[0196] (6) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: sequentially depositing a fifth insulating film and a third conductive film on the substrate having the aforementioned pattern formed thereon, patterning the third conductive film using a patterning process to form a fifth insulating layer covering the second semiconductor layer, and a third conductive layer pattern disposed on the fifth insulating layer, as shown in FIG12A and FIG12B , where FIG12B is a plan view schematic diagram of the third conductive layer in FIG12A . In an exemplary embodiment, the second conductive layer may be referred to as a third gate metal (GATE3) layer.

[0197] In an exemplary embodiment, the third conductive layer pattern of each circuit unit includes at least a first scan signal line 21 , a third scan signal line 23 , a second preliminary signal line 42 , and a third preliminary signal line 43 .

[0198] In an exemplary embodiment, the shape of the first scanning signal line 21 can be a straight line or a broken line with the main portion extending along the first direction X. The first scanning signal line 21 can be located between the first electrode 31 and the second scanning signal line 22. The area where the first scanning signal line 21 overlaps with the second active layer can serve as the gate electrode of the second transistor T2.

[0199] In an exemplary embodiment, the orthographic projection of the first scanning signal line 21 on the substrate at least partially overlaps with the orthographic projection of the first shielding line 33 on the substrate. The first scanning signal line 21 and the first shielding line 33 can be connected to the same signal source, so that the first shielding line 33 can serve as the bottom gate electrode of the second transistor T2, and the first scanning signal line 21 can serve as the top gate electrode of the second transistor T2, forming a second transistor T2 with a top-gate and bottom-gate structure.

[0200] In an exemplary embodiment, the shape of the third scan signal line 23 can be a straight line or a broken line with the main portion extending along the first direction X. The third scan signal line 23 can be located between the second scan signal line 22 and the first initial signal line 41. The area where the third scan signal line 23 overlaps with the first active layer can serve as the gate electrode of the first transistor T1.

[0201] In an exemplary embodiment, the orthographic projection of the third scan signal line 23 on the substrate at least partially overlaps with the orthographic projection of the second shading line 34 on the substrate, and the third scan signal line 23 and the second shading line 34 can be connected to the same signal source, so that the second shading line 34 can serve as the bottom gate electrode of the first transistor T1, and the third scan signal line 23 can serve as the top gate electrode of the first transistor T1, forming the first transistor T1 with a top-gate and bottom-gate structure.

[0202] In an exemplary embodiment, the shape of the second initial signal line 42 can be a straight line or a broken line with the main part extending along the first direction X. The second initial signal line 42 can be located on the side of the second light-emitting signal line 32 away from the second electrode 32. The second initial signal line 42 of this unit row is configured to be connected to the first area of ​​the seventh active layer of the pixel driving circuit in the circuit unit of this unit row through the eighth connecting electrode formed subsequently.

[0203] In an exemplary embodiment, the positive projection of the second initial signal line 42 on the substrate at least partially overlaps with the positive projection of the fourth scanning signal line 24 on the substrate, so that the second initial signal line 42 with a constant potential can effectively shield the influence of the voltage jump of the fourth scanning signal line 24 on the pixel driving circuit.

[0204] In an exemplary embodiment, the third initial signal line 43 may be in the shape of a straight line or a zigzag line, with the main portion extending along the first direction X. The third initial signal line 43 may be located between the second electrode plate 32 and the second initial signal line 42. The third initial signal line 43 of the current unit row is configured to be connected to the first region of the eighth active layer of the pixel driving circuit in the circuit unit of the next unit row via a subsequently formed ninth connecting electrode. For example, the third initial signal line 43 of the (n-1)th unit row is configured to be connected to the first region of the eighth active layer of the pixel driving circuit in the circuit unit of the (n)th unit row via a subsequently formed ninth connecting electrode. For another example, the third initial signal line 43 of the (n)th unit row is configured to be connected to the first region of the eighth active layer of the pixel driving circuit in the circuit unit of the (n+1)th unit row via a subsequently formed ninth connecting electrode.

[0205] In an exemplary embodiment, the positive projection of the third initial signal line 43 on the substrate at least partially overlaps with the positive projection of the luminous signal line 25 on the substrate, so that the third initial signal line 43 with a constant potential can effectively shield the influence of the voltage jump of the luminous signal line 25 on the pixel driving circuit.

[0206] (7) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming the sixth insulating layer pattern may include: depositing a sixth insulating film on the substrate having the aforementioned pattern formed thereon, patterning the fifth insulating film using a patterning process to form a sixth insulating layer covering the third conductive layer, wherein the sixth insulating layer is provided with a plurality of vias, as shown in FIG. 13 .

[0207] In an exemplary embodiment, the multiple vias of each circuit unit include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17, an eighteenth via V18 and a nineteenth via V19.

[0208] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the sixth insulating layer and the fifth insulating layer within the first via hole V1 are etched away to expose the surface of the first region of the first active layer, and the first via hole V1 is configured to connect a subsequently formed seventh connecting electrode to the first region of the first active layer through the via hole.

[0209] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second region of the first active layer (also the first region of the second active layer) on the substrate, the sixth insulating layer and the fifth insulating layer in the second via hole V2 are etched away to expose the surface of the second region of the first active layer (also the first region of the second active layer), and the second via hole V2 is configured to connect the subsequently formed tenth connecting electrode to the second region of the first active layer (also the first region of the second active layer) through the via hole.

[0210] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the second region of the second active layer on the substrate, the sixth insulating layer and the fifth insulating layer in the third via hole V3 are etched away to expose the surface of the second region of the second active layer, and the third via hole V3 is configured to connect a subsequently formed second connecting electrode to the second region of the second active layer through the via hole.

[0211] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the first area of ​​the third active layer (also the second area of ​​the fourth active layer) on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the fourth via hole V4 are etched away to expose the surface of the first area of ​​the third active layer (also the second area of ​​the fourth active layer), and the fourth via hole V4 is configured to connect the subsequently formed fifth connecting electrode to the first area of ​​the third active layer (also the second area of ​​the fourth active layer) through the via hole.

[0212] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the second area of ​​the third active layer (also the first area of ​​the sixth active layer) on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the fifth via hole V5 are etched away to expose the surface of the second area of ​​the third active layer (also the first area of ​​the sixth active layer), and the fifth via hole V5 is configured to connect the subsequently formed second connecting electrode to the second area of ​​the third active layer (also the first area of ​​the sixth active layer) through the via hole.

[0213] In an exemplary embodiment, the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the first area of ​​the fourth active layer on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the sixth via hole V6 are etched away to expose the surface of the first area of ​​the fourth active layer. The sixth via hole V6 is configured to connect a subsequently formed third connecting electrode to the first area of ​​the fourth active layer through the via hole.

[0214] In an exemplary embodiment, the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the first area of ​​the fifth active layer on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the seventh via hole V7 are etched away to expose the surface of the first area of ​​the fifth active layer, and the seventh via hole V7 is configured to connect a subsequently formed fourth connecting electrode to the first area of ​​the fifth active layer through the via hole.

[0215] In an exemplary embodiment, the pixel driving circuits of two adjacent circuit units in the first direction X can be substantially mirror-symmetrical with respect to the column reference line, the two adjacent circuit units can share a seventh via V7, and the column reference line can be a straight line located between the two adjacent circuit units and extending along the second direction Y.

[0216] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the second region of the fifth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the eighth via V8 are etched away to expose the surface of the second region of the fifth active layer, and the eighth via V8 is configured to connect a subsequently formed fifth connecting electrode to the second region of the fifth active layer through the via hole.

[0217] In an exemplary embodiment, the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the ninth via hole V9 are etched away to expose the surface of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer), and the ninth via hole V9 is configured to connect the subsequently formed sixth connecting electrode to the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) through the via hole.

[0218] In an exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the first region of the seventh active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the tenth via hole V10 are etched away to expose the surface of the first region of the seventh active layer, and the tenth via hole V10 is configured to connect the subsequently formed eighth connecting electrode to the first region of the seventh active layer through the via hole.

[0219] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the first region of the eighth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the eleventh via hole V11 are etched away to expose the surface of the first region of the eighth active layer, and the eleventh via hole V11 is configured to connect a subsequently formed ninth connecting electrode to the first region of the eighth active layer through the via hole.

[0220] In an exemplary embodiment, the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the second region of the eighth active layer on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the twelfth via hole V12 are etched away to expose the surface of the second region of the eighth active layer. The twelfth via hole V12 is configured to connect the subsequently formed fifth connecting electrode to the second region of the eighth active layer through the via hole.

[0221] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the first region of the ninth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the thirteenth via hole V13 are etched away to expose the surface of the first region of the ninth active layer, and the thirteenth via hole V13 is configured to connect the subsequently formed tenth connecting electrode to the first region of the ninth active layer through the via hole.

[0222] In an exemplary embodiment, the orthographic projection of the fourteenth via hole V14 on the substrate is located within the range of the orthographic projection of the second region of the ninth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the fourteenth via hole V14 are etched away to expose the surface of the second region of the ninth active layer, and the fourteenth via hole V14 is configured to connect a subsequently formed first connecting electrode to the second region of the ninth active layer through the via hole.

[0223] In an exemplary embodiment, the orthographic projection of the fifteenth via hole V15 on the substrate is located within the range of the orthographic projection of the opening 32-1 on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer and the third insulating layer in the fifteenth via hole V15 are etched away to expose the surface of the first electrode 31. The fifteenth via hole V15 is configured to connect the subsequently formed first connecting electrode to the first electrode 31 through the via hole.

[0224] In an exemplary embodiment, the orthographic projection of the sixteenth via hole V16 on the substrate is located within the range of the orthographic projection of the second electrode plate 32 on the substrate, the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the sixteenth via hole V16 are etched away to expose the surface of the second electrode plate 32, and the sixteenth via hole V16 is configured to connect the subsequently formed fourth connecting electrode to the second electrode plate 32 through the via hole.

[0225] In an exemplary embodiment, the orthographic projection of the seventeenth via hole V17 on the substrate is located within the range of the orthographic projection of the first initial signal line 41 on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer and the third insulating layer in the seventeenth via hole V17 are etched away to expose the surface of the first initial signal line 41, and the seventeenth via hole V17 is configured to connect the subsequently formed seventh connecting electrode to the first initial signal line 41 through the via hole.

[0226] In an exemplary embodiment, the orthographic projection of the eighteenth via hole V18 on the substrate is located within the range of the orthographic projection of the second initial signal line 42 on the substrate, the sixth insulating layer in the eighteenth via hole V18 is etched away to expose the surface of the second initial signal line 42, and the eighteenth via hole V18 is configured to connect the subsequently formed eighth connecting electrode to the second initial signal line 42 through the via hole.

[0227] In an exemplary embodiment, the orthographic projection of the nineteenth via V19 on the substrate is located within the range of the orthographic projection of the third initial signal line 43 on the substrate, the sixth insulating layer in the nineteenth via V19 is etched away to expose the surface of the third initial signal line 43, and the nineteenth via V19 is configured to connect the subsequently formed ninth connecting electrode to the third initial signal line 43 through the via.

[0228] (8) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the sixth insulating layer, as shown in FIG. 14A and FIG. 14B , where FIG. 14B is a plan view schematic diagram of the fourth conductive layer in FIG. 14A . In an exemplary embodiment, the fourth conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0229] In an exemplary embodiment, the fourth conductive layer of each circuit unit includes at least: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, a seventh connection electrode 57, an eighth connection electrode 58, a ninth connection electrode 59 and a tenth connection electrode 60.

[0230] In an exemplary embodiment, the first connection electrode 51 may be in the shape of a strip with a main portion extending along the second direction Y. The first end of the first connection electrode 51 is connected to the second region of the ninth active layer through a fourteenth via hole V14. The second end of the first connection electrode 51 extends along the second direction Y and is connected to the first electrode plate 31 through a fifteenth via hole V15. In an exemplary embodiment, because the first electrode plate 31 also serves as the gate electrode of the third transistor T3, the first connection electrode 51 causes the gate electrode of the third transistor T3, the second electrode of the ninth transistor T9, and the first electrode plate 31 to have the same potential, thereby forming a first node N1 of the pixel driving circuit.

[0231] In an exemplary embodiment, the second connection electrode 52 may be in the shape of a strip with a main portion extending along the second direction Y. A first end of the second connection electrode 52 is connected to the second region of the second active layer via a third via hole V3. A second end of the second connection electrode 52 extends along the second direction Y and is connected to the second region of the third active layer (also the first region of the sixth active layer) via a fifth via hole V5. In an exemplary embodiment, the second connection electrode 52 causes the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6 to have the same potential, forming a third node N3 of the pixel driving circuit.

[0232] In an exemplary embodiment, the third connection electrode 53 may be in a block shape (eg, rectangular), connected to the first region of the fourth active layer through the sixth via hole V6, and configured to be connected to a subsequently formed data signal line.

[0233] In an exemplary embodiment, the shape of the fourth connection electrode 54 can be an "L" shape, the first end of the fourth connection electrode 54 is connected to the first region of the fifth active layer through the seventh via V7, and the second end of the fourth connection electrode 54 is connected to the second electrode plate 32 through the sixteenth via V16, thereby achieving the same potential for the first electrode of the fifth transistor T5 and the second electrode plate 32 of the storage capacitor in the circuit unit.

[0234] In an exemplary embodiment, the pixel driving circuits of two adjacent circuit units in the first direction X can be substantially mirror-symmetrical with respect to the column reference line, and the fourth connection electrodes 54 of the two adjacent circuit units can be an integrated structure connected to each other and connected to the first area of ​​the fifth active layer of the two circuit units through a common seventh via V7.

[0235] In an exemplary embodiment, a power connection block 54 - 1 is provided on the fourth connection electrode 54 . The power connection block 54 - 1 is provided on a side of the second end of the fourth connection electrode 54 away from the first end. The power connection block 54 - 1 is configured to be connected to a first power line formed subsequently.

[0236] In an exemplary embodiment, since the fifth active layer of the pixel driving circuit in the current unit row is disposed in the circuit unit of the previous unit row, the first end of the fourth connecting electrode 54 in the current unit row is connected to the first region of the fifth active layer of the pixel driving circuit in the next unit row, and the second end of the fourth connecting electrode 54 is connected to the second electrode plate 32 of the pixel driving circuit in the current unit row. For example, the fourth connecting electrode 54 of the pixel driving circuit in the nth unit row has a first end connected to the first region of the fifth active layer of the pixel driving circuit in the (n+1)th unit row, and a second end connected to the second electrode plate 32 of the pixel driving circuit in the nth unit row. For another example, the fourth connecting electrode 54 in the (n-1)th unit row has a first end connected to the first region of the fifth active layer of the pixel driving circuit in the nth unit row, and a second end connected to the second electrode plate 32 of the pixel driving circuit in the (n-1)th unit row.

[0237] In an exemplary embodiment, the fifth connection electrode 55 may be in the shape of a strip with a main portion extending along the second direction Y. The first end of the fifth connection electrode 55 is connected to the second region of the fifth active layer via an eighth via hole V8. The second end of the fifth connection electrode 55, after extending along the second direction Y, is connected to the first region of the third active layer (also the second region of the fourth active layer) via a fourth via hole V4. The area between the first and second ends of the fifth connection electrode 55 is connected to the second region of the eighth active layer via a twelfth via hole V12. In an exemplary embodiment, the fifth connection electrode 55 causes the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8 to have the same potential, forming the second node N2 of the pixel driving circuit. In an exemplary embodiment, the fifth connection electrode 55 may serve as the second node electrode of the present disclosure.

[0238] In an exemplary embodiment, since the fifth active layer of the pixel driving circuit in the current unit row is disposed in the circuit unit of the previous unit row, the fifth connecting electrode 55 in the current unit row is arranged across two circuit units. The via hole connecting the fifth connecting electrode 55 to the second region of the fifth active layer and the second region of the eighth active layer is located in the circuit unit of the previous unit row, and the via hole connecting the fifth connecting electrode 55 to the first region of the third active layer (also the second region of the fourth active layer) is located in the circuit unit of the current unit row. For example, the via hole connecting the fifth connecting electrode 55 of the pixel driving circuit in the nth unit row to the second region of the fifth active layer and the second region of the eighth active layer of the pixel driving circuit in the nth unit row is located in the circuit unit of the n-1th unit row, and the via hole connecting the fifth connecting electrode 55 to the first region of the third active layer (also the second region of the fourth active layer) of the pixel driving circuit in the nth unit row is located in the circuit unit of the nth unit row. For another example, the fifth connecting electrode 55 in the n+1th unit row has a via position connecting it to the second area of ​​the fifth active layer and the second area of ​​the eighth active layer of the pixel driving circuit in the n+1th unit row, which is located in the circuit unit of the nth unit row; and a via position connecting it to the first area of ​​the third active layer (also the second area of ​​the fourth active layer) of the pixel driving circuit in the n+1th unit row, which is located in the circuit unit of the n+1th unit row.

[0239] In an exemplary embodiment, the positive projection of the fifth connecting electrode 55 (the second node N2 of the pixel driving circuit) on the substrate at least partially overlaps with the positive projection of the first initial signal line 41 and the second initial signal line 42 on the substrate, so that the first initial signal line 41 and the second initial signal line 42 with a constant potential can effectively stabilize the potential of the second node N2.

[0240] In an exemplary embodiment, the orthographic projection of the fifth connection electrode 55 on the substrate at least partially overlaps with the orthographic projections of the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, and the fourth scan signal line 24. Because the power supply voltage output by the first power line is provided to the second node N2 during the sixth phase of the driving sequence of the pixel driving circuit, the influence of the scan lines on the second node N2 can be reset, thereby improving the light emission stability during the light emission phase.

[0241] In an exemplary embodiment, the sixth connection electrode 56 may be in a block shape (e.g., a rectangle), and is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through a ninth via hole V9. In an exemplary embodiment, the sixth connection electrode 56 is configured to be connected to a subsequently formed anode connection electrode to form a fourth node N4 of the pixel driving circuit.

[0242] In an exemplary embodiment, the seventh connection electrode 57 may be in the shape of a strip with a main portion extending along the first direction X. A first end of the seventh connection electrode 57 is connected to the first region of the first active layer via a first via hole V1, and a second end of the seventh connection electrode 57 is connected to the first initial signal line 41 via a seventeenth via hole V17. In an exemplary embodiment, the seventh connection electrode 57 connects the first initial signal line 41 to the first electrode of the first transistor T1. The first initial signal line 41 can write the transmitted first initial signal into the first electrode of the first transistor T1.

[0243] In an exemplary embodiment, the eighth connection electrode 58 may be in the shape of a strip with a main portion extending along the second direction Y. A first end of the eighth connection electrode 58 is connected to the first region of the seventh active layer via a tenth via hole V10, and a second end of the eighth connection electrode 58 is connected to the second initial signal line 42 via an eighteenth via hole V18. In an exemplary embodiment, the eighth connection electrode 58 connects the second initial signal line 42 to the first electrode of the seventh transistor T7. The second initial signal line 42 can write the transmitted second initial signal into the first electrode of the seventh transistor T7.

[0244] In an exemplary embodiment, the ninth connection electrode 59 may be in the shape of a strip with a main portion extending along the second direction Y. A first end of the ninth connection electrode 59 is connected to the first region of the eighth active layer via an eleventh via hole V11, and a second end of the ninth connection electrode 59 is connected to the third initial signal line 43 via a nineteenth via hole V19. In an exemplary embodiment, the ninth connection electrode 59 connects the third initial signal line 43 to the first electrode of the eighth transistor T8, and the third initial signal line 43 can write the transmitted third initial signal into the first electrode of the eighth transistor T8.

[0245] In an exemplary embodiment, since the eighth active layer of the pixel driving circuit in the current unit row is disposed in the circuit unit of the previous unit row, the first end of the ninth connecting electrode 59 in the current unit row is connected to the first region of the eighth active layer of the pixel driving circuit in the next unit row, and the second end of the ninth connecting electrode 59 is connected to the third initial signal line 43 in the current unit row. For example, for the ninth connecting electrode 59 in the (n-1)th unit row, its first end is connected to the first region of the eighth active layer of the pixel driving circuit in the (n)th unit row, and its second end is connected to the third initial signal line 43 in the (n-1)th unit row. For another example, for the ninth connecting electrode 59 in the pixel driving circuit in the (n)th unit row, its first end is connected to the first region of the eighth active layer of the pixel driving circuit in the (n+1)th unit row, and its second end is connected to the third initial signal line 43 in the (n)th unit row.

[0246] In an exemplary embodiment, the tenth connection electrode 60 may be in the shape of a strip with a main portion extending along the first direction X. A first end of the tenth connection electrode 60 is connected to the second region of the first active layer (also the first region of the second active layer) via a second via hole V2, and a second end of the tenth connection electrode 60 is connected to the first region of the ninth active layer via a thirteenth via hole V13. In an exemplary embodiment, the tenth connection electrode 60 connects the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the first electrode of the ninth transistor T9, forming a fifth node N5 of the pixel driving circuit.

[0247] (9) Forming a first planar layer pattern. In an exemplary embodiment, forming the first planar layer pattern may include: coating a first planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process to form a first planar layer covering the fourth conductive layer pattern, wherein a plurality of vias are provided on the first planar layer, as shown in FIG. 15 .

[0248] In an exemplary embodiment, the plurality of vias in each circuit unit includes at least a twenty-first via V21 , a twenty-second via V22 , and a twenty-third via V23 .

[0249] In an exemplary embodiment, the orthographic projection of the twenty-first via V21 on the substrate is located within the range of the orthographic projection of the power connection block 54-1 of the fourth connection electrode 54 on the substrate, the first flat layer within the twenty-first via V21 is etched away, exposing the surface of the power connection block 54-1, and the twenty-first via V21 is configured to connect the subsequently formed first power line to the power connection block 54-1 through the via.

[0250] In an exemplary embodiment, the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the third connecting electrode 53 on the substrate, the first flat layer in the twenty-second via hole V22 is etched away to expose the surface of the third connecting electrode 53, and the twenty-second via hole V22 is configured to connect a subsequently formed data signal line to the third connecting electrode 53 through the via hole.

[0251] In an exemplary embodiment, the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the sixth connecting electrode 56 on the substrate, the first flat layer within the twenty-third via hole V23 is etched away to expose the surface of the sixth connecting electrode 56, and the twenty-third via hole V23 is configured to connect the subsequently formed anode connecting electrode to the sixth connecting electrode 56 through the via hole.

[0252] (10) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fifth conductive film using a patterning process to form a fifth conductive layer disposed on the first flat layer, as shown in FIG16A and FIG16B , where FIG16B is a planar schematic diagram of the fifth conductive layer in FIG16A . In an exemplary embodiment, the fifth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0253] In an exemplary embodiment, the fifth conductive layer of each circuit unit includes at least a first power line 61 , a data signal line 62 , and an anode connection electrode 63 .

[0254] In an exemplary embodiment, the first power line 61 may be in the shape of a straight line or a zigzag line, with its main portion extending along the second direction Y. The first power line 61 is connected to the power connection block 54-1 through the twenty-first via V21. Since the power connection block 54-1 is connected to the fourth connection electrode 54, and the fourth connection electrode 54 is respectively connected to the first electrode of the fifth transistor T5 and the second plate 32 of the storage capacitor, the first power line 61 can write the first power signal to the fifth transistor T5 and the second plate 32 of the storage capacitor.

[0255] In an exemplary embodiment, the first power line 61 may be a zigzag line with unequal width, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the first power line and the data signal line.

[0256] In an exemplary embodiment, the orthographic projection of the first power line 61 on the substrate at least partially overlaps with the orthographic projection of the first active layer on the substrate, and the orthographic projection of the first power line 61 on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate, so that the first power line 61 can block the first active layer and the second active layer, and can block the light emitted by the light-emitting device and the light reflected by the film layer from irradiating the first transistor T1 and the second transistor T2 of the oxide, and can prevent the characteristics of the oxide transistor from drifting due to light, thereby improving the electrical characteristics of the oxide transistor.

[0257] In an exemplary embodiment, the orthographic projection of the first power line 61 on the substrate at least partially overlaps with the orthographic projection of the first connection electrode 51 on the substrate. The first power line 61 having a constant potential can effectively shield the influence of data voltage jumps and other signals on the first node N1 in the pixel driving circuit, thereby preventing the data voltage jumps and other signals from affecting the potential of the first node N1, thereby improving the driving performance of the pixel driving circuit.

[0258] In an exemplary embodiment, the orthographic projection of the first power line 61 on the substrate at least partially overlaps with the orthographic projections of the second connection electrode 52 and the tenth connection electrode 60 on the substrate. The first power line 61 with a constant potential can effectively shield the influence of data voltage jumps and other signals on various nodes in the pixel driving circuit, thereby avoiding the influence of data voltage jumps and other signals on the node potentials and improving the driving performance of the pixel driving circuit.

[0259] In an exemplary embodiment, the data signal line 62 may be in the shape of a straight line or a zigzag line, with the main portion extending along the second direction Y. The data signal line 62 is connected to the third connection electrode 53 through the twenty-second via hole V22. Since the third connection electrode 53 is connected to the first region of the fourth active layer through the via hole, the data signal line 62 is connected to the first electrode of the fourth transistor T4. The data signal line 62 can write a data signal to the first electrode of the fourth transistor T4.

[0260] In an exemplary embodiment, the anode connection electrode 63 may be in a block shape (e.g., a rectangular shape). The anode connection electrode 63 is connected to the sixth connection electrode 56 via a twenty-third via hole V23. The anode connection electrode 63 is configured to be connected to a subsequently formed anode. Since the sixth connection electrode 56 is connected to the second region of the sixth active layer and the second region of the seventh active layer via the via hole, the subsequently formed anode can be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the pixel driving circuit can drive the light-emitting device to emit light.

[0261] The subsequent process may include forming a second flat layer covering the fifth conductive layer pattern, wherein the second flat layer is provided with an anode via hole, the anode via hole exposing the anode connection electrode, and the anode via hole is configured to connect the subsequently formed anode to the anode connection electrode through the via hole.

[0262] At this point, the driving circuit layer is prepared on the substrate. In a plane parallel to the display substrate, the driving circuit layer may include a plurality of circuit units, each circuit unit may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, a third scanning signal line, a fourth scanning signal line, a light-emitting signal line, a first initial signal line, a second initial signal line, a third initial signal line, a first power line, and a data signal line connected to the pixel driving circuit. In a plane perpendicular to the display substrate, the driving circuit layer may include a shielding layer, a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a second semiconductor layer, a fifth insulating layer, a third conductive layer, a sixth insulating layer, a fourth conductive layer, a first planar layer, a fifth conductive layer, and a second planar layer sequentially arranged on the substrate. The blocking layer may include at least a blocking electrode, the first semiconductor layer may include at least the active layer of the third transistor to the ninth transistor, the first conductive layer may include at least the second scanning signal line, the fourth scanning signal line, the light-emitting signal line, the first initial signal line and the first plate of the storage capacitor, the second conductive layer may include at least the first blocking line, the second blocking line and the second plate of the storage capacitor, the second semiconductor layer may include at least the active layer of the first transistor and the second transistor, the third conductive layer may include at least the first scanning signal line, the third scanning signal line, the second initial signal line and the third initial signal line, the fourth conductive layer may include at least a plurality of connecting electrodes, and the fifth conductive layer may include at least the first power line, the data signal line and the anode connecting electrode.

[0263] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-Si).

[0264] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single layer structure or a multilayer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multilayer, or a composite layer. The first planarizing layer and the second planarizing layer can be made of an organic material, such as a resin.

[0265] In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer may be prepared on the driving circuit layer first, and then an encapsulation structure layer may be prepared on the light emitting structure layer, which will not be described in detail here.

[0266] A pixel drive circuit for a display substrate uses an 8T1C structure. The first and second transistors T1 and T2 are oxide transistors, and the third to eighth transistors T3 and T8 are low-temperature polysilicon transistors. The first node N1 of the pixel drive circuit is connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor C, respectively. During product reliability testing, the display substrate exhibited horizontal streaks. Research has found that the horizontal streaks are caused by characteristic shifts in the oxide second transistor T2. Long-term circuit bias and high temperatures during product reliability testing can cause characteristic shifts in the oxide second transistor T2, particularly shifts in the threshold voltage Vth. The pixel drive circuit is very sensitive to characteristic changes in the second transistor T2, especially changes in the threshold voltage Vth. A shift in the threshold voltage Vth of the second transistor T2 can cause fluctuations in the potential of the gate electrode (first node N1) of the drive transistor. Small fluctuations can cause large changes in the light-emitting current, leading to horizontal streaks. The horizontal streaks are more severe at low brightness and low grayscale.

[0267] The display substrate provided by the embodiment of the present disclosure effectively avoids potential fluctuations of the gate electrode of the driving transistor caused by characteristic changes of the second transistor T2 by disposing a ninth transistor T9 made of low-temperature polysilicon between the oxide transistor and the gate electrode of the driving transistor, thereby improving or eliminating horizontal streaks. The pixel driving circuit of the display substrate of the present disclosure adopts a 9T1C structure, adding a ninth polysilicon transistor T9 to the 8T1C structure. The ninth transistor T9 is disposed between the gate electrode of the driving transistor and the second electrode of the first transistor T1 and the first electrode of the second transistor T2, isolating the gate electrode of the driving transistor from the oxide first transistor T1 and the oxide second transistor T2. Because the characteristics of the ninth polysilicon transistor T9 are relatively stable and the ninth transistor T9 is disconnected before the second transistor T2 in the fourth stage, the influence of the characteristic changes of the second transistor T2 on the potential of the gate electrode of the driving transistor is effectively eliminated, thus avoiding changes in the light-emitting current, thereby effectively improving or eliminating horizontal streaks.

[0268] FIG17 is a schematic diagram of an equivalent circuit of another pixel driving circuit according to an exemplary embodiment of the present disclosure. As shown in FIG17 , the pixel driving circuit has an 8T1C structure and may include eight transistors (first transistor T1 to eighth transistor T8) and one storage capacitor C. Each pixel driving circuit is connected to 12 signal lines (a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a fourth scan signal line S4, a fifth scan signal line S5, a first light-emitting signal line EM1, a second light-emitting signal line EM2, a first initial signal line INIT1, a second initial signal line INIT2, a third initial signal line INIT3, a data signal line DATA, and a first power line VDD).

[0269] In an exemplary embodiment, the connection structure of the first transistor T1 to the eighth transistor T8 and the storage capacitor C in the pixel driving circuit of this embodiment is substantially the same as that shown in FIG4 , except that the pixel driving circuit does not include the ninth transistor, and thus the first node N1 is respectively connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor C, that is, the second electrode of the first transistor T1 is connected to the first node N1, and the first electrode of the second transistor T2 is connected to the first node N1.

[0270] As shown in FIG. 17 , in this exemplary embodiment, the first transistor T1 and the second transistor T2 in the pixel driving circuit may be oxide transistors (N-type transistors), and the third transistor T3 to the eighth transistor T8 may be low-temperature polysilicon transistors (P-type transistors).

[0271] FIG18 is a driving timing diagram of the pixel driving circuit shown in FIG17 . As shown in FIG18 , in the exemplary embodiment, the operation of the pixel driving circuit is substantially the same as that of FIG5A , except that: in the second phase A2, the second scan signal line S2 is a high-level signal, and the first transistor T1 is turned on, so that the signal of the first initialization signal line INIT1 is provided to the first node N1 to initialize (reset) the first node N1. In the fifth phase A5, before the seventh transistor T7 and the eighth transistor T8 are turned on, the second scan signal line S2 is a low-level signal for a short period of time, and the fourth transistor T4 is turned on again. Turning on the fourth transistor T4 causes the data voltage of the next cell row to reset the second node N2 and the third node N3.

[0272] Figure 19 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the structure of the display substrate of this embodiment is substantially the same as that shown in Figure 6 , except that the pixel driving circuit has an 8T1C structure.

[0273] In an exemplary embodiment, the pixel driving circuit includes a storage capacitor and a plurality of transistors. The storage capacitor may include a stacked first electrode plate and a second electrode plate. The plurality of transistors may include a first transistor T1 as a first initialization transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a drive transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first emission control transistor, a sixth transistor T6 as a second emission control transistor, a seventh transistor T7 as a second initialization transistor, and an eighth transistor T8 as a third initialization transistor. The first transistor T1 and the second transistor T2 are oxide transistors, and the third transistor T3 to the ninth transistor T9 are low-temperature polysilicon transistors.

[0274] In the exemplary embodiment, the connection structure of the first to eighth transistors T1 to T8 is substantially the same as that of the aforementioned embodiment, except that the second electrode of the first transistor T1 and the first electrode of the second transistor T2 are connected to the first plate 31 of the storage capacitor via the first connection electrode 51.

[0275] In an exemplary embodiment, taking a circuit unit as an example, the preparation process of the display substrate in this embodiment may include the following operations.

[0276] (11) Forming a shielding layer pattern In the exemplary embodiment, the process of forming the shielding layer and the structure of the shielding layer are substantially the same as those in the previous embodiment.

[0277] (12) Forming a first semiconductor layer pattern. In the exemplary embodiment, the process of forming the first semiconductor layer and the structure of the first semiconductor layer are substantially the same as those of the aforementioned embodiment, except that the first semiconductor layer may include at least the third active layer 13 of the third transistor T3 to the eighth active layer 18 of the eighth transistor T8, and the first semiconductor layer does not have a ninth active layer, as shown in FIG. 20 .

[0278] (13) Forming a First Conductive Layer Pattern In the exemplary embodiment, the process of forming the first conductive layer and the structure of the first conductive layer are substantially the same as those in the previous embodiment, as shown in FIG. 21 .

[0279] (14) Forming a Second Conductive Layer Pattern In the exemplary embodiment, the process of forming the second conductive layer and the structure of the second conductive layer are substantially the same as those in the previous embodiment, as shown in FIG.

[0280] (15) Forming a Second Semiconductor Layer Pattern In the exemplary embodiment, the process of forming the second semiconductor layer and the structure of the second semiconductor layer are substantially the same as those in the previous embodiment, as shown in FIG. 23 .

[0281] (16) Forming a Third Conductive Layer Pattern In the exemplary embodiment, the process of forming the third conductive layer and the structure of the third conductive layer are substantially the same as those in the previous embodiment, as shown in FIG. 24 .

[0282] (17) Forming a sixth insulating layer pattern. In the exemplary embodiment, the process of forming the sixth insulating layer and the structure of the plurality of vias are substantially the same as those in the aforementioned embodiment, except that the plurality of vias of each circuit unit does not include the thirteenth via V13 and the fourteenth via V14, and the second via V2 is configured to connect the subsequently formed first connection electrode to the second region of the first active layer (also the first region of the second active layer) through the via, as shown in FIG. 25 .

[0283] (18) Forming a fourth conductive layer pattern. In the exemplary embodiment, the process of forming the fourth conductive layer and the structure of the fourth conductive layer are substantially the same as those of the aforementioned embodiment, except that the fourth conductive layer does not have a tenth connection electrode, the first connection electrode 51 is in an "L" shape, the first end of the first connection electrode 51 is connected to the second region of the first active layer (also the first region of the second active layer) through the second via hole V2, and the second end of the first connection electrode 51 is connected to the first electrode plate 31 through the fifteenth via hole V15, as shown in FIG. 26 .

[0284] In an exemplary embodiment, the first connection electrode 51 enables the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, the second electrode of the ninth transistor T9 and the first electrode plate 31 to have the same potential, forming a first node N1 of the pixel driving circuit.

[0285] (19) Forming a First Planarization Layer Pattern In an exemplary embodiment, the process of forming the first planarization layer and the structure of the plurality of via holes are substantially the same as those in the previous embodiment, as shown in FIG. 27 .

[0286] (20) Forming a Fifth Conductive Layer Pattern In the exemplary embodiment, the process of forming the fifth conductive layer and the structure of the fifth conductive layer are substantially the same as those in the previous embodiment, as shown in FIG. 28 .

[0287] The subsequent process may include forming a second flat layer covering the fifth conductive layer pattern, wherein the second flat layer is provided with an anode via hole, the anode via hole exposing the anode connection electrode, and the anode via hole is configured to connect the subsequently formed anode to the anode connection electrode through the via hole.

[0288] At this point, the driving circuit layer is prepared on the substrate. In a plane parallel to the display substrate, the driving circuit layer may include a plurality of circuit units, each circuit unit may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, a third scanning signal line, a fourth scanning signal line, a light-emitting signal line, a first initial signal line, a second initial signal line, a third initial signal line, a first power line, and a data signal line connected to the pixel driving circuit. In a plane perpendicular to the display substrate, the driving circuit layer may include a shielding layer, a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a second semiconductor layer, a fifth insulating layer, a third conductive layer, a sixth insulating layer, a fourth conductive layer, a first planar layer, a fifth conductive layer, and a second planar layer sequentially arranged on the substrate. The blocking layer may include at least a blocking electrode, the first semiconductor layer may include at least the active layer of the third transistor to the eighth transistor, the first conductive layer may include at least the second scanning signal line, the fourth scanning signal line, the light-emitting signal line, the first initial signal line and the first plate of the storage capacitor, the second conductive layer may include at least the first blocking line, the second blocking line and the second plate of the storage capacitor, the second semiconductor layer may include at least the active layer of the first transistor and the second transistor, the third conductive layer may include at least the first scanning signal line, the third scanning signal line, the second initial signal line and the third initial signal line, the fourth conductive layer may include at least a plurality of connecting electrodes, and the fifth conductive layer may include at least the first power line, the data signal line and the anode connecting electrode.

[0289] In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer may be prepared on the driving circuit layer first, and then an encapsulation structure layer may be prepared on the light emitting structure layer, which will not be described in detail here.

[0290] In a display substrate, each circuit unit's pixel driver circuit is connected to five scan signal lines (first to fifth scan signal lines) and two light-emitting signal lines (first to second light-emitting signal lines). This increased number of signal lines not only increases the occupied area but also increases the complexity of the pixel driver circuit structure. This makes it difficult to reduce the size of the circuit units and improve the display device's pixel per inch (PPI) resolution. Furthermore, the increased number of scan signal lines and light-emitting signal lines increases the number of corresponding gate driver circuits in the border area, increasing the gate driver circuitry and occupied area, hindering the realization of a narrow border.

[0291] The display substrate provided by the embodiment of the present disclosure sets signal borrowing between two adjacent unit rows. The fifth transistor T5 of the current unit row is controlled by the light-emitting signal line of the previous unit row, and the eighth transistor T8 of the current unit row is controlled by the fourth scanning signal line of the previous unit row. This can effectively reduce the size of the circuit unit and effectively improve the resolution of the display device.

[0292] The display substrate disclosed herein arranges the sixth transistor T6 of the pixel driving circuit in a unit row within the circuit unit of the unit row, with the sixth transistor T6 connected to the light-emitting signal line of the unit row, and arranges the fifth transistor T5 of the pixel driving circuit in the unit row within the circuit unit of the previous unit row, with the fifth transistor T5 connected to the light-emitting signal line of the previous unit row. This allows the fifth transistor T5 of the current unit row to borrow the control signal of the sixth transistor T6 of the previous unit row. Compared to the existing structure in which a first light-emitting signal line for controlling the fifth transistor T5 and a second light-emitting signal line for controlling the sixth transistor T6 are provided in each unit row, the present disclosure adopts the staggered arrangement of transistors in adjacent unit rows and signal borrowing, thereby providing only one light-emitting signal line in each unit row. This not only reduces the number of signal lines and the occupied area, but also reduces the complexity of the pixel driving circuit structure, effectively reducing the size of the circuit unit and effectively improving the resolution of the display device.

[0293] The present disclosure separately controls the fifth transistor and the sixth transistor, connects the fifth transistor T5 of the current unit row to the light-emitting signal line of the previous unit row, and connects the sixth transistor T6 to the light-emitting signal line of the current unit row. The light-emitting signal lines of the two unit rows jointly adjust the duty cycle of the pulse width modulation (PWM), thereby achieving ultra-high frequency and higher precision pulse width modulation, light-emitting signal duty cycle compensation, low grayscale compensation, and improved afterimage.

[0294] The display substrate disclosed herein arranges the seventh transistor T7 of the pixel driving circuit in a unit row within the circuit unit of the unit row, where the seventh transistor T7 is connected to the fourth scan signal line of the unit row, and arranges the eighth transistor T8 of the pixel driving circuit in the unit row within the circuit unit of the previous unit row, where the eighth transistor T8 is connected to the fourth scan signal line of the previous unit row. This allows the eighth transistor T8 in the unit row to borrow the control signal of the seventh transistor T7 in the previous unit row. Compared to the existing structure in which each unit row is provided with a fourth scan signal line for controlling the seventh transistor T7 and a fifth scan signal line for controlling the eighth transistor T8, the present disclosure adopts a staggered arrangement of transistors in adjacent unit rows and uses signals for borrowing, thereby providing only one fourth scan signal line in the unit row. This not only reduces the number of signal lines and the occupied area, but also reduces the complexity of the pixel driving circuit structure, effectively reducing the size of the circuit unit and improving the resolution of the display device.

[0295] The present disclosure optimizes space utilization by reducing the number of light-emitting signal lines and scanning signal lines in a unit row, making the layout more reasonable, ensuring the distance between nodes within the pixel driving circuit and the distance between each node and the signal line, effectively avoiding crosstalk, effectively improving the display quality of the display device, effectively improving the product yield, and reducing production costs.

[0296] The present disclosure reduces the number of light-emitting signal lines and scanning signal lines in the unit row, so that the number of corresponding gate drive circuits in the border area can be reduced exponentially, effectively reducing the occupied area of ​​the gate drive circuit, which is conducive to achieving a narrow border and improving product advantages.

[0297] The present disclosure arranges that the orthographic projection of the second initial signal line on the substrate at least partially overlaps with the orthographic projection of the fourth scanning signal line on the substrate, and the orthographic projection of the third initial signal line on the substrate at least partially overlaps with the orthographic projection of the luminous signal line on the substrate, so that the initial signal line with a constant potential can effectively shield the influence of the voltage jump of the scanning signal line or the luminous signal line on the pixel driving circuit, thereby improving the driving performance of the pixel driving circuit.

[0298] The present disclosure sets a first power line to cover the first connection electrode, which can effectively shield the influence of data voltage jumps and other signals on the first node in the pixel driving circuit, avoid the influence of data voltage jumps and other signals on the potential of the first node, and effectively avoid the deterioration of crosstalk. The present disclosure sets a first power line to cover the first active layer and the second active layer, which can effectively block the light emission of the light-emitting device and the light reflected by the film layer from irradiating the oxide transistor, prevent the oxide transistor from drifting due to light, and improve the electrical characteristics of the oxide transistor. The preparation process of the present disclosure is well compatible with existing preparation processes, and the process is simple to implement, easy to implement, high in production efficiency, low in production cost, and high in yield.

[0299] Figure 29 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure. In the exemplary embodiment, the structure of the display substrate of this embodiment is substantially the same as that shown in Figure 6 , except that the first connection electrode 51 is further provided with a first auxiliary electrode 51 - 1 and a second auxiliary electrode 51 - 2 .

[0300] In an exemplary embodiment, the first connection electrode 51 may be in the shape of a strip with a main portion extending along the second direction Y. The first end of the first connection electrode 51 is connected to the second region of the ninth active layer through a fourteenth via hole V14. The second end of the first connection electrode 51 extends along the second direction Y and is connected to the first electrode plate 31 through a fifteenth via hole V15. In an exemplary embodiment, because the first electrode plate 31 also serves as the gate electrode of the third transistor T3, the first connection electrode 51 causes the gate electrode of the third transistor T3, the second electrode of the ninth transistor T9, and the first electrode plate 31 to have the same potential, thereby forming a first node N1 of the pixel driving circuit.

[0301] In an exemplary embodiment, the first auxiliary electrode 51-1 may be in the shape of a strip extending along the second direction Y. A first end of the first auxiliary electrode 51-1 is connected to a first end of the first connection electrode 51. A second end of the first auxiliary electrode 51-1 extends away from the first connection electrode 51 and is then connected to the second auxiliary electrode 51-2. The orthographic projection of the first auxiliary electrode 51-1 on the substrate at least partially overlaps with the orthographic projection of the first scan signal line 21 on the substrate. The second auxiliary electrode 51-2 may be in the shape of a strip extending along the first direction X. The orthographic projection of the second auxiliary electrode 51-2 on the substrate at least partially overlaps with the orthographic projection of the second scan signal line 22 on the substrate.

[0302] In the exemplary embodiment, the second scan signal line 22 controls the on / off switching of the fourth transistor T4, and the first connection electrode 51 serves as the first node N1 of the pixel driving circuit. By arranging the first node N1 to overlap with the first scan signal line 21 and the second scan signal line 22, the present disclosure not only facilitates the display of low grayscale images but also balances the parasitic capacitance between the first node N1 and the second scan signal line 22. Since the second transistor T2 is an N-type transistor and the fourth transistor T4 is a P-type transistor, the turn-on signals of the first scan signal line 21 controlling the second transistor T2 and the second scan signal line 22 controlling the fourth transistor T4 are opposite. Therefore, the structure of the first auxiliary electrode 51-1 and the second auxiliary electrode 51-2 in this embodiment can balance the parasitic capacitance between the first node N1 and the second scan signal line 22.

[0303] In an exemplary embodiment, the orthographic projection of the first scan signal line 21 on the substrate overlaps with the orthographic projection of the ninth active layer on the substrate. The width of the overlapping region in the ninth active layer can be greater than the width at other locations to adjust the capacitance between the first semiconductor layer and the first scan signal line 21. Because the widening is performed in the underlying first semiconductor layer, it is not affected by the flatness of the upper first scan signal line 21, thereby reducing the risk of line breakage.

[0304] Figure 30 is an equivalent circuit diagram of another pixel driving circuit of an exemplary embodiment of the present disclosure, illustrating the pixel driving circuits of the n-1th unit row and the nth unit row. The structures of the pixel driving circuits of the n-1th unit row and the nth unit row are basically the same as those shown in Figure 4.

[0305] As shown in FIG30 , the second light-emitting signal line EM2 of the n-1th unit row is interconnected with the first light-emitting signal line EM1 of the nth unit row, that is, the second light-emitting signal line EM2 of the n-1th unit row and the first light-emitting signal line EM1 of the nth unit row are the same light-emitting signal line, and the sixth transistor T6 of the n-1th unit row and the fifth transistor T5 of the nth unit row share the same light-emitting signal line. The fourth scan signal line S4 of the n-1th unit row and the fifth scan signal line S5 of the nth unit row are interconnected, that is, the fourth scan signal line S4 of the n-1th unit row and the fifth scan signal line S5 of the nth unit row are the same scan signal line, and the seventh transistor T7 of the n-1th unit row and the eighth transistor T8 of the nth unit row share the same scan signal line.

[0306] In some possible implementations, the fourth scan signal line S4 and the fifth scan signal line S5 of each unit row may not use a cascade signal, but may use the same control signal. The fourth scan signal line S4 and the fifth scan signal line S5 of each unit row are the same control signal, which is not limited in the present disclosure.

[0307] In some possible implementations, the first scan signal line S1 and the third scan signal line S3 of each unit row may be provided by different gate driving circuits, or may adopt cascade signals, which is not limited in the present disclosure.

[0308] The structure and preparation process shown above in the present disclosure are merely exemplary. In exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0309] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0310] The present disclosure also provides a method for driving a display substrate to drive the display substrate provided by the above embodiment. In an exemplary embodiment, the display substrate may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit at least including a pixel driving circuit and at least one control signal line, the pixel driving circuit at least including a driving transistor, a first control transistor and a second control transistor, the first control transistor and the second control transistor being connected to the driving transistor, respectively. In an exemplary embodiment, the method for driving a display substrate may include at least a data writing phase and a light emitting phase, in which, in at least one pixel driving circuit of at least one unit row, the conduction and disconnection of the first control transistor are controlled by the control signal line in the previous unit row, and the conduction and disconnection of the second control transistor are controlled by the control signal line in the current unit row.

[0311] In an exemplary embodiment, the pixel driving circuit further includes a first initialization transistor, a compensation transistor and an isolation transistor, the first electrode of the first initialization transistor being connected to the first initial signal line, the second electrode of the first initialization transistor and the first electrode of the compensation transistor being connected to the first electrode of the isolation transistor, the second electrode of the isolation transistor being connected to the gate electrode of the driving transistor, and the second electrode of the compensation transistor being connected to the second electrode of the driving transistor; the driving method further includes: before the data writing stage, the isolation transistor being turned on at least twice.

[0312] In an exemplary embodiment, the driving method further includes a node reset phase between the data writing phase and the light emitting phase, in which the first electrode and the second electrode of the driving transistor are reset.

[0313] The present disclosure also provides a method for preparing a display substrate to produce the display substrate provided in the above embodiment. In an exemplary embodiment, the display substrate includes a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns; the preparation method may include:

[0314] A pixel driving circuit and at least one control signal line are formed in at least one circuit unit, wherein the pixel driving circuit includes at least a driving transistor, a first control transistor, and a second control transistor, and the first control transistor and the second control transistor are respectively connected to the driving transistor; in at least one pixel driving circuit of at least one unit row, the first control transistor is connected to the control signal line in the previous unit row, and the second control transistor is connected to the control signal line in the current unit row.

[0315] The present disclosure further provides a display device including the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, but the embodiments of the present invention are not limited thereto.

[0316] While the embodiments disclosed herein are as described above, it should be noted that the above embodiments are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate, comprising a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, wherein at least one circuit unit comprises at least a pixel driving circuit and at least one control signal line, wherein the control signal line is configured to provide a control signal to the pixel driving circuit; in at least one circuit unit, the pixel driving circuit comprises at least a driving transistor, a first control transistor and a second control transistor, wherein the first control transistor and the second control transistor are respectively connected to the driving transistor; in at least one pixel driving circuit of at least one unit row, the first control transistor is connected to the control signal line in the previous unit row, and the second control transistor is connected to the control signal line in the current unit row.

2. The display substrate according to claim 1, wherein: The control signal line includes a light-emitting signal line, the first control transistor includes a first light-emitting control transistor, the second control transistor includes a second light-emitting control transistor, the first electrode of the first light-emitting control transistor is connected to the first power line, the second electrode of the first light-emitting control transistor is connected to the first electrode of the driving transistor, and the first electrode of the second light-emitting control transistor is connected to the second electrode of the driving transistor; in at least one pixel driving circuit of at least one unit row, the gate electrode of the first control transistor is connected to the light-emitting signal line in the previous unit row, and the gate electrode of the second control transistor is connected to the light-emitting signal line in the current unit row.

3. The display substrate according to claim 2, wherein: In at least one pixel driving circuit, the first light emission control transistor and the second light emission control transistor connected to the same driving transistor are respectively arranged on both sides of the driving transistor unit in a column direction.

4. The display substrate according to claim 2, wherein: The first light-emitting control transistor includes at least a first light-emitting control active layer, and the second light-emitting control transistor includes at least a second light-emitting control active layer; in at least one pixel driving circuit of at least one unit row, the first light-emitting control active layer is arranged in the circuit unit of the previous unit row, and the second light-emitting control active layer is arranged in the circuit unit of the current unit row.

5. The display substrate according to claim 4, wherein: In at least one pixel driving circuit of at least one unit row, the first light-emitting control active layer is arranged on one side of the second light-emitting control active layer unit row direction of the pixel driving circuit in the previous unit row.

6. The display substrate according to claim 4, wherein: The pixel driving circuit also includes a storage capacitor and a power connection electrode, the storage capacitor includes a first electrode plate and a second electrode plate, the orthographic projection of the first electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the second electrode plate on the display substrate plane; in at least one pixel driving circuit of at least one unit row, the first end of the power connection electrode is connected to the first area of ​​the first light-emitting control active layer of the pixel driving circuit in the next unit row, and the second end of the power connection electrode is connected to the second electrode plate of the pixel driving circuit in the current unit row.

7. The display substrate according to claim 1, wherein: The control signal line includes a scanning signal line, the first control transistor includes a third initialization transistor, the second control transistor includes a second initialization transistor, the first electrode of the second initialization transistor is connected to the second initial signal line, the second electrode of the second initialization transistor is connected to the second electrode of the driving transistor through the second light-emitting control transistor, the first electrode of the third initialization transistor is connected to the third initial signal line, and the second electrode of the third initialization transistor is connected to the first electrode of the driving transistor; in at least one pixel driving circuit of at least one unit row, the gate electrode of the third initialization transistor is connected to the scanning signal line in the previous unit row, and the gate electrode of the second initialization transistor is connected to the scanning signal line in the current unit row.

8. The display substrate according to claim 7, wherein: In at least one pixel driving circuit, the second initialization transistor and the third initialization transistor connected to the same driving transistor are respectively arranged on both sides of the driving transistor unit in a column direction.

9. The display substrate according to claim 7, wherein: The second initialization transistor includes at least a second initialization active layer, and the third initialization transistor includes at least a third initialization active layer; in at least one pixel driving circuit of at least one unit row, the third initialization active layer is arranged in the circuit unit of the previous unit row, and the second initialization active layer is arranged in the circuit unit of the current unit row.

10. The display substrate according to claim 9, wherein: In at least one pixel driving circuit of at least one unit row, the third initialization active layer is arranged on one side of the second initialization active layer unit row direction of the pixel driving circuit in the previous unit row.

11. The display substrate according to claim 9, wherein: In at least one pixel driving circuit of at least one unit row, the first area of ​​the second initialization active layer is connected to the second initialization signal line in the current unit row, and the first area of ​​the third initialization active layer is connected to the third initialization signal line in the previous unit row.

12. The display substrate according to any one of claims 1 to 11, wherein: The pixel driving circuit also includes a first initialization transistor, a compensation transistor and an isolation transistor, the first electrode of the first initialization transistor is connected to the first initial signal line, the second electrode of the first initialization transistor and the first electrode of the compensation transistor are connected to the first electrode of the isolation transistor, the second electrode of the isolation transistor is connected to the gate electrode of the driving transistor, and the second electrode of the compensation transistor is connected to the second electrode of the driving transistor.

13. The display substrate according to claim 12, wherein: The pixel driving circuit also includes a data writing transistor, a first electrode of the data writing transistor is connected to the data signal line, and a second electrode of the data writing transistor is connected to the first electrode of the driving transistor; a channel region of the isolation transistor is located between a channel region of the compensation transistor and a channel region of the data writing transistor, and a channel width-to-length ratio of the isolation transistor is greater than a channel width-to-length ratio of the data writing transistor.

14. The display substrate according to claim 12, wherein: The first control transistor includes a first light-emitting control transistor and a third initialization transistor, the first electrode of the first light-emitting control transistor is connected to the first power line, the first electrode of the third initialization transistor is connected to the third initialization signal line, the second electrode of the first light-emitting control transistor and the second electrode of the third initialization transistor are connected to the first electrode of the driving transistor; the pixel driving circuit also includes a second node electrode, the second node electrode is respectively connected to the first electrode of the driving transistor, the second electrode of the first light-emitting control transistor and the second electrode of the third initialization transistor, and the orthographic projection of the second node electrode on the display substrate plane at least partially overlaps with the orthographic projection of the first initialization signal line on the display substrate plane.

15. The display substrate according to any one of claims 1 to 11, wherein: The pixel driving circuit also includes a first initialization transistor and a compensation transistor, the first electrode of the first initialization transistor is connected to the first initial signal line, the second electrode of the first initialization transistor and the first electrode of the compensation transistor are connected to the gate electrode of the driving transistor, and the second electrode of the compensation transistor is connected to the second electrode of the driving transistor.

16. A display device comprising the display substrate according to any one of claims 1 to 15.

17. A driving method for a display substrate, the display substrate comprising a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising at least a pixel driving circuit and at least one control signal line, the pixel driving circuit comprising at least a driving transistor, a first control transistor and a second control transistor, the first control transistor and the second control transistor being respectively connected to the driving transistor; the driving method comprising at least a data writing phase and a light emitting phase, in the light emitting phase, in at least one pixel driving circuit of at least one unit row, the conduction and disconnection of the first control transistor are controlled by the control signal line in the previous unit row, and the conduction and disconnection of the second control transistor are controlled by the control signal line in the current unit row.

18. The driving method according to claim 17, wherein: The pixel driving circuit further includes a first initialization transistor, a compensation transistor and an isolation transistor, wherein a first electrode of the first initialization transistor is connected to a first initial signal line, a second electrode of the first initialization transistor and a first electrode of the compensation transistor are connected to a first electrode of the isolation transistor, a second electrode of the isolation transistor is connected to a gate electrode of the driving transistor, and a second electrode of the compensation transistor is connected to a second electrode of the driving transistor; The driving method further includes: before the data writing phase, the isolation transistor is turned on at least twice.

19. The driving method according to claim 17, wherein: The driving method further includes a node resetting phase between the data writing phase and the light emitting phase. In the node resetting phase, the first electrode and the second electrode of the driving transistor are reset.

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