Display substrate and display device

Abstract

Display substrate and display device. The display substrate comprises a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, one circuit unit of which comprises a pixel driver circuit and a control line, the pixel driver circuit comprising a driver transistor (T3), a first light emission control transistor (T5) and a second light emission control transistor (T6), wherein a second electrode of the first light emission control transistor (T5) is connected to a first electrode of the driver transistor (T3), a first electrode of the second light emission control transistor (T6) is connected to a second electrode of the driver transistor (T3), and the first light emission control transistor (T5) and the second light emission control transistor (T6) are connected to different control lines;the first light emission control transistor (T5) and the second light emission control transistor (T6) are each arranged on two sides of the driver transistor (T3) in a unit column direction.

Description

Technical field The present disclosure relates to, but is not limited to, the field of display technologies, in particular to a display substrate and a display device. background Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active light-emitting display devices and offer advantages such as self-luminescence, a wide viewing angle, high contrast ratio, low power consumption, very fast response time, lightness and thinness, flexibility, and low cost. With the continuous development of display technologies, a display device (flexible display) that uses an OLED or QLED as the light-emitting device and uses a thin-film transistor (TFT) for signal control has now become a mainstream product in the field of display devices. Summary of the invention The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of protection of the claims. In one aspect, the present disclosure provides a display substrate with a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, wherein at least one circuit unit comprises a pixel driver circuit and at least one control line configured to supply a light emission control signal to the pixel driver circuit;In at least one circuit unit, the pixel driver circuit comprises at least one driver transistor, a first light emission control transistor, and a second light emission control transistor, wherein a first electrode of the first light emission control transistor is connected to a first power supply line, a second electrode of the first light emission control transistor is connected to a first electrode of the driver transistor, and a first electrode of the second light emission control transistor is connected to a second electrode of the driver transistor; the first light emission control transistor and the second light emission control transistor are connected to different control lines, and the first light emission control transistor and the second light emission control transistor are each arranged on opposite sides of the driver transistor in a unit column direction. In an exemplary embodiment, the at least one control line comprises a first signal line and a second signal line, and the first light emission control transistor is connected to the first signal line and the second light emission control transistor is connected to the second signal line, and the first signal line and the second signal line are each arranged on two sides of the driver transistor in the unit column direction. In an exemplary embodiment, the display substrate comprises a plurality of conductive layers in a direction perpendicular to the display substrate, and the first signal line and the second signal line are arranged in different conductive layers. In an exemplary embodiment, the second light emission control transistor comprises at least one second gate, wherein the second gate and the first signal line are arranged in the same conductive layer and the second gate and the second signal line are arranged in different conductive layers. In an exemplary embodiment, the pixel driver circuit further comprises a compensation transistor, wherein a gate electrode of the compensation transistor is connected to a first sampling signal line, a first electrode of the compensation transistor is connected to a gate electrode of the driver transistor via a first connecting electrode, and a second electrode of the compensation transistor is connected to the second electrode of the driver transistor.is connected to the first electrode of the second light emission control transistor; an orthographic projection of the first connecting electrode onto a plane of the display substrate is at least partially overlapped with an orthographic projection of the first signal line onto the plane of the display substrate, and the orthographic projection of the first connecting electrode onto the plane of the display substrate is at least partially overlapped with an orthographic projection of the first sampling signal line onto the plane of the display substrate. In an exemplary embodiment, the compensation transistor comprises at least one compensation active layer, the second light emission control transistor comprises at least one second light emission control active layer, and a second region of the compensation active layer is connected to a first region of the second light emission control active layer via a fifth connecting electrode; in a direction perpendicular to the display substrate, the display substrate comprises at least one semiconductor layer and at least one conductive layer, wherein the compensation active layer and the second light emission control active layer are arranged in the semiconductor layer and the fifth connecting electrode is arranged in the conductive layer. In an exemplary embodiment, the pixel driver circuit further comprises a data write transistor, wherein a first electrode of the data write transistor is connected to a data signal line, a second electrode of the data write transistor is connected to the first electrode of the driver transistor, and the data write transistor and the compensation transistor are each arranged on two sides of the driver transistor in the unit column direction. In an exemplary embodiment, the at least one control line comprises a light emission signal line, wherein the light emission signal line is connected to the second light emission control transistor in an existing unit column and the light emission signal line is connected to a first light emission control transistor in a next unit column. In an exemplary embodiment, the first light emission control transistor comprises at least one first gate, the second light emission control transistor comprises at least one second gate of the second light emission control transistor, the light emission signal line is connected to the second gate electrode in the current unit row, and the light emission signal line is connected to the first light emission control transistor in the next unit row via a light emission signal link line. In an exemplary embodiment, the display substrate comprises a plurality of conductive layers in a direction perpendicular to the display substrate, wherein the first gate of the first light emission control transistor and the second gate of the second light emission control transistor are arranged in the same conductive layer, the first gate and the light emission signal line are arranged in different conductive layers, the first gate and the light emission signal link line are arranged in different conductive layers, and the light emission signal link line and the light emission signal line are arranged in different conductive layers. In an exemplary embodiment, the plurality of conductive layers comprises at least a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer arranged sequentially on a base substrate along a direction remote from the base substrate, wherein the first gate and the second gate are arranged in the first conductive layer, the light emission signal line is arranged in the third conductive layer, the light emission signal line is connected to the second gate via a through-hole, and the light emission signal link line is arranged in the fourth conductive layer.a first end of the light emission signal link is connected via a through-hole to the light emission signal link in the current unit row, and a second end of the light emission signal link is connected via a through-hole to the first gate in the next unit row. In an exemplary embodiment, the plurality of conductive layers further comprises a fifth conductive layer arranged on a side of the fourth conductive layer furthest from the base substrate, wherein the first power supply line is arranged in the fifth conductive layer and an orthographic projection of the first power supply line onto the plane of the display substrate overlaps at least partially with an orthographic projection of the light emission signal link line onto the plane of the display substrate. In an exemplary embodiment, at least one circuit unit further comprises a first initial signal line extending along a pixel row direction and a first interconnect line extending along a pixel column direction, wherein the first initial signal line is configured to supply a first initial signal to the pixel driver circuit, wherein the first initial signal line and the first interconnect line are connected to form a net-like interconnect structure for transmitting the first initial signal. In an exemplary embodiment, an orthographic projection of the first connecting line onto the plane of the display substrate does not overlap an orthographic projection of a gate electrode of the driver transistor onto the plane of the display substrate. In an exemplary embodiment, the pixel driver circuit further comprises a compensation transistor, wherein an active layer of the compensation transistor and an active layer of the driver transistor are connected to each other by an active interconnecting line, wherein an orthographic projection of the first interconnecting line onto the plane of the display substrate and an orthographic projection of the active interconnecting line onto the plane of the display substrate do not overlap at least partially. In an exemplary embodiment, at least one circuit unit further comprises a second initial signal line extending along a pixel row direction and a second connecting line extending along a pixel column direction, wherein the second initial signal line is configured to supply a second initial signal to the pixel driver circuit, wherein the second initial signal line and the second connecting line are interconnected in a net-like manner to form a net-like interconnect structure for transmitting the second initial signal. In an exemplary embodiment, an orthographic projection of the second connecting line onto the plane of the display substrate does not overlap with an orthographic projection of a gate electrode of the driver transistor onto the plane of the display substrate. In an exemplary embodiment, the pixel driver circuit further comprises a compensation transistor, wherein an active layer of the compensation transistor and an active layer of the driver transistor are connected to each other by an active interconnecting line, wherein an orthographic projection of the second interconnecting line onto the plane of the display substrate and an orthographic projection of the active interconnecting line onto the plane of the display substrate do not overlap at least partially. In an exemplary embodiment, at least one circuit unit further comprises a third connecting line extending along a pixel row direction and a second power supply line extending along a pixel column direction, wherein the second power supply line and the third connecting line are interconnected to form a net-like interconnect structure for transmitting a second power supply signal. In an exemplary embodiment, an orthographic projection of the second power supply line onto the plane of the display substrate does not overlap with an orthographic projection of a gate electrode of the driver transistor onto the plane of the display substrate. In an exemplary embodiment, the pixel driver circuit further comprises a compensation transistor, wherein an active layer of the compensation transistor and an active layer of the driver transistor are connected to each other by an active interconnect line, and an orthographic projection of the second power supply line onto the plane of the display substrate and an orthographic projection of the active interconnect line onto the plane of the display substrate do not overlap at least partially. In an exemplary embodiment, the pixel driver circuit further comprises a storage capacitor and a first capacitor; the storage capacitor comprises a first plate and a second plate, an orthographic projection of the first plate onto the plane of the display substrate is at least partially overlapped with an orthographic projection of the second plate onto the plane of the display substrate, the first plate serves as the gate electrode of the driver transistor, and the second plate is connected to the first power supply line;the first capacitor comprises a third plate and a fourth plate, an orthographic projection of the third plate onto the plane of the display substrate overlaps at least partially with an orthographic projection of the fourth plate onto the plane of the display substrate, the third plate is connected to the first electrode of the driver transistor and the second electrode of the first light emission control transistor, and the fourth plate is connected to the first power supply line. In an exemplary embodiment, the display substrate comprises, in a direction perpendicular to the display substrate, at least one semiconductor layer, a first conductive layer and a second conductive layer, arranged successively on the base substrate along a direction away from the base substrate, wherein the third plate is arranged in the semiconductor layer, the first plate is arranged in the first conductive layer and the second plate and the fourth plate are arranged in the second conductive layer. In another aspect, the present disclosure further provides a display device comprising the display substrate described above. Further aspects of this revelation can be understood after reading and understanding the drawings and the detailed descriptions. Brief description of the drawings The accompanying drawings serve to illustrate the technical solution of this disclosure and form part of the description. The accompanying drawings and embodiments of this disclosure serve to explain the technical solution of this disclosure and do not represent any limitations of the technical solution of this disclosure. Fig. 1 is a schematic diagram of a structure of a display device. Fig. 2 is a schematic diagram of a planar structure of a display substrate. Fig. 3 is a schematic diagram of a sectional structure of a display substrate. Fig. 4 is an equivalent circuit diagram of a pixel driver circuit according to an exemplary embodiment of this disclosure. Fig. 5 is a schematic diagram of a structure of a display substrate according to an exemplary embodiment of this disclosure.Figure 6 is a schematic representation of a display substrate after the formation of a semiconductor layer pattern according to the present disclosure. Figures 7A and 7B are schematic representations of a display substrate after the formation of a first conductive layer pattern according to the present disclosure. Figures 8A and 8B are schematic representations of a display substrate after the formation of a second conductive layer pattern according to the present disclosure. Figure 9 is a schematic representation of a display substrate after the formation of a fourth insulating layer pattern according to the present disclosure. Figures 10A and 10B are schematic representations of a display substrate after the formation of a third conductive layer pattern according to the present disclosure.Figure 11 is a schematic representation of a display substrate after the formation of a pattern of a first planarization layer according to the present disclosure. Figures 12A and 12B are schematic representations of a display substrate after the formation of a pattern of a fourth conducting layer according to the present disclosure. Figures 12C to 12E are schematic representations of network-like interconnect structures for a first initial signal and a second initial signal according to the present disclosure. Figure 13 is a schematic representation of a display substrate after the formation of a pattern of a second planarization layer according to the present disclosure. Figures 14A and 14B are schematic representations of a display substrate after the formation of a pattern of an anode-conducting layer according to the present disclosure.Figure 15 is a schematic representation of a display substrate after the formation of a pattern of a pixel definition layer according to the present disclosure. Figure 16 is an equivalent circuit diagram of another pixel driver circuit according to an exemplary embodiment of the present disclosure. Figure 17 is a schematic diagram of a structure of another display substrate according to an exemplary embodiment of the present disclosure. Figure 18 is a schematic diagram of another display substrate after the formation of a pattern of a semiconductor layer according to the present disclosure. Figures 19A and 19B are schematic representations of another display substrate after the formation of a pattern of a first conductive layer according to the present disclosure. Figures 20A and 20B are schematic representations of another display substrate after the formation of a pattern of a second conductive layer according to the present disclosure.Figure 21 is a schematic representation of a further indicator substrate after the formation of a pattern of a fourth insulating layer according to the present disclosure. Figures 22A and 22B are schematic representations of a further indicator substrate after the application of a pattern of a third conductive layer according to the present disclosure. Figure 23 is a schematic diagram of a further indicator substrate after the formation of a pattern of a first planarization layer according to the present disclosure. Figures 24A and 24B are schematic representations of a further indicator substrate after the formation of a pattern of a fourth conductive layer according to the present disclosure. Figure 25 is a schematic representation of a further indicator substrate after the formation of a pattern of a second planarization layer according to the present disclosure. Figures 26A and 26B are schematic representations of a further indicator substrate after the formation of a pattern of a second planarization layer according to the present disclosure.Figures 26B and 26C are schematic representations of a further display substrate after the formation of a pattern of a fifth conductive layer according to the present disclosure. Figure 26C is a schematic diagram of a network-like interconnection structure for an initial signal and a second power supply according to the present disclosure. Figure 27 is a schematic diagram of a structure of a further display substrate according to an exemplary embodiment of the present disclosure. Figures 28A and 28B are schematic representations of a further display substrate after the formation of a pattern of a third conductive layer according to the present disclosure. Figure 29 is a schematic representation of a further display substrate after the formation of a pattern of a first planarization layer according to the present disclosure. Figures 30A and 30B are schematic representations of a further display substrate after the formation of a pattern of a first planarization layer according to the present disclosure.Figures 30B and 30D are schematic representations of a further display substrate after the formation of a pattern of a fourth conductive layer according to the present disclosure. Figures 30C and 30D are schematic representations of a further network-like interconnection structure for a first signal and a second power supply according to the present disclosure. Figures 31A and 31B are schematic representations of a further display substrate after the formation of a pattern of an anode-conducting layer according to the present disclosure. Figure 32 is a schematic diagram of a further display substrate after the formation of a pattern of a pixel definition layer according to the present disclosure. Figures 33A and 33B are schematic representations of a further display substrate after the formation of a pattern of an anode-conducting layer according to the present disclosure. The reference symbols are described as follows: 11 first active layer; 12 second active layer; 13 third active layer; 14 fourth active layer; 15 fifth active layer; 16 sixth active layer; 17 seventh active layer; 18 active connecting line; 21 first scanning signal line; 22 second scanning signal line; 23 third scanning signal line; 31 first initial signal line; 32 second initial signal line; 41 first connecting electrode; 42 second connecting electrode; 43 third connecting electrode; 44 fourth connecting electrode; 45 fifth connecting electrode; 46 sixth connecting electrode; 47 seventh connecting electrode; 48 eighth connecting electrode; 49 ninth connecting electrode; 51 eleventh connecting electrode; 52 twelfth connecting electrode; 53 thirteenth connecting electrode; 54 fourteenth connecting electrode; 55 fifteenth connecting electrode; 56 light emission signal connecting line; 61 first power supply line. 62 Data signal line; 63 Anode connection electrode;64 Second power supply line; 71 First plate; 72 Second plate; 73 Third plate; 74 Fourth plate; 75 Opening; 76 Plate connecting strip; 81 First connecting line; 82 Second connecting line; 83 Third connecting line; 90 Anode; 91 First signal line; 92 Second signal line; 93 Light emission signal line; 101 Base substrate; 102 Driver circuit layer; 103 Light emission structural layer; 104 Encapsulation structural layer. Detailed To clarify the objectives, technical solutions, and advantages of this disclosure, the embodiments of this disclosure are described in detail below with reference to the accompanying drawings. It should be noted that implementations can take several different forms. Those skilled in the art will readily understand that implementations and content can be transformed into various forms without deviating from the purpose and scope of this disclosure. Therefore, this disclosure should not be considered limited to the content of the following embodiments. The embodiments and features in the embodiments of this disclosure can be combined arbitrarily, provided there are no conflicts. The scales of the drawings in this disclosure may be used as a reference in actual processes, but are not limited to this. For example, the width-to-length ratio of a channel, the thickness and spacing of each film, and the width and spacing of each signal line may be adjusted according to actual requirements. The number of pixels in a display substrate and the number of subpixels in each pixel are not limited to the numbers specified in the drawings. The drawings described in this disclosure are only schematic structural diagrams, and an embodiment of this disclosure is not limited to the shapes, numerical values, or the like shown in the drawings. Ordinal numbers such as "first", "second", "third", etc. in the description do not serve to limit numbers, but only to avoid confusion between components. For the sake of clarity, the specification uses terms such as "central," "top," "bottom," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," "outside," etc., which indicate directional or positional relationships, to illustrate the positional relationships between the components. These terms are not intended to indicate or imply that the devices or elements involved must have specific orientations and be assembled and operated in those orientations, but rather to simplify the present description. Therefore, they are not to be understood as limitations of the present disclosure. The positional relationships between the components may be modified as necessary, depending on the direction in which the individual components are described. Therefore, situation-appropriate substitutions are permissible and are not limited to the terms used in the description. Unless otherwise specified and defined in the description, the terms "fastening," "connection," and "connection" are to be understood in a broad sense. For example, a connection may be a permanent connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be a direct connection or an indirect connection via middleware or internal communication within two elements. Persons skilled in the art may understand the specific meanings of the above terms in the present disclosure according to the specific situations. In this description, a transistor refers to a device that has at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. It is important to note that the term "channel region" in this description refers to the area through which current primarily flows. In the description, the first electrode can be a drain electrode and the second electrode a source electrode. Alternatively, the first electrode can be a source electrode and the second electrode a drain electrode. In cases where transistors with opposite polarities are used, or where the current direction changes during circuit operation, or similar situations, the functions of the "source electrode" and the "drain electrode" are sometimes interchangeable. Therefore, the terms "source electrode" and "drain electrode," as well as "source terminal" and "drain terminal," are interchangeable in the description. In this description, "electrical connection" encompasses the connection of components via an element with a specific electrical effect. An "element with a specific electrical effect" is not particularly restricted, as long as electrical signals can be sent and received between the connected components. Examples of an "element with a specific electrical effect" include not only an electrode and wiring, but also a switching element such as a transistor, a resistor, an inductor, a capacitor, or any other element with various functions, etc. In this description, "parallel" refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less, and thus also includes a state in which the angle is -5° or more and 5° or less. Furthermore, "perpendicular" refers to a state in which the angle between two straight lines is 80° or more and 100° or less, and thus also includes a state in which the angle is 85° or more and 95° or less. In the description, "film" and "layer" are interchangeable. For example, a "conductive layer" can sometimes be replaced by a "conductive thin film." Likewise, an "insulating film" can sometimes be replaced by an "insulating layer." Triangle, rectangle, trapezoid, pentagon, hexagon, etc., are not strictly defined in this description and may be approximate triangles, rectangles, trapezoids, pentagons, hexagons, etc. Minor deformations may occur due to tolerances, and chamfers, curved edges, distortions, etc., may be present. In the present disclosure, “approximately” refers to the fact that a limit is not so strictly defined and numerical values ​​within a range of process and measurement errors are permissible. Fig. 1 is a schematic diagram of the structure of a display device. As shown in Fig. 1, the display device can comprise a timing controller, a data driver, a sampling driver, a light emission driver, and a pixel array. The timing controller is connected to the data driver, the sampling driver, and the light emission driver, respectively. The data driver is connected to a plurality of data signal lines (D1 to Dn). The sampling driver is connected to a plurality of sampling signal lines (S1 to Sm). The light emission driver is connected to a plurality of light emission signal lines (E1 to Eo). The pixel array can comprise a plurality of subpixels Pxij, where i and j can be natural numbers. At least one subpixel Pxij can comprise a circuit unit and a light-emitting unit.The circuit unit can comprise at least one pixel driver circuit connected to a sampling signal line, a light emission signal line, and a data signal line. The light emission unit can comprise a light-emitting device connected to the pixel driver circuit of the circuit unit. In an exemplary embodiment, the timing controller can provide the data driver with a grayscale value and a control signal suitable for the data driver specification, the sampling driver with a clock signal and a sampling start signal, and the like, suitable for the sampling driver specification, and the light emission driver with a clock signal and an emission stop signal, and the like, suitable for the light emission driver specification. The data driver can generate data voltages that are applied to the data signal lines DATA1, D2, D3, ...The data driver can supply data signals to S1, S2, S3, ..., and Sm using the grayscale value and the control signal received from the timer. For example, the data driver can sample the grayscale value using the clock signal and apply a data voltage corresponding to the grayscale value to the data signal lines DATA1 to Dn, taking a pixel row as the unit, where n can be a natural number. The sampler driver can generate sample signals that are fed to the sample signal lines S1, S2, S3, ..., and Sm by receiving the clock signal and the sample start signal from the timer. For example, the sampler driver can sequentially feed a sample signal with a turn-on pulse to the sample signal lines S1 to Sm.For example, the sampling driver can be implemented as a shift register and generate a sampling signal such that a sampling start signal, provided as a switch-on pulse, is successively passed to the next stage under the control of the clock signal, where m can be a natural number. The light emitter driver can receive a clock signal, an emission stop signal, etc., from the timing unit to generate an emission signal to be delivered to the light emission signal lines EM1, E2, E3, ..., and Eo. For example, the light emitter driver can sequentially deliver an emission signal with a switch-off pulse to the light emission signal lines EM1 to Eo.For example, the light emission driver can be implemented as a shift register and generate an emission signal by sequentially passing an emission stop signal, provided as an off pulse, to the next stage under the control of the clock signal, where o can be a natural number. In an exemplary embodiment, the pixel array can be arranged on the display substrate. Fig. 2 is a schematic diagram of a planar structure of a display substrate. As shown in Fig. 2, the display substrate can comprise a plurality of pixel units P arranged in a matrix, and at least one of the pixel units P can comprise a first subpixel P1, a second subpixel P2, a third subpixel P3, and a fourth subpixel P4. Each subpixel can comprise a circuit unit and a light emission unit. The circuit unit can comprise at least one pixel driver circuit, wherein the pixel driver circuit is connected to a sampling signal line, a data signal line, and a light emission signal line, and is configured to receive a data voltage transmitted from the data signal line and, under the control of the sampling signal line and the light emission signal line, output a corresponding current to the light emission unit.The light emission unit may include a light emission device connected to a pixel driver circuit of a subpixel in which the light emission device is located, and the light emission device is configured to emit light of an appropriate brightness in response to the current supplied by the pixel driver circuit of the subpixel in which the light emission device is located. In one exemplary embodiment, the first subpixels P1 can be red subpixels (R) that emit red light, the second subpixels P2 and the fourth subpixels P4 can be green subpixels (G) that emit green light, and the third subpixels P3 can be blue subpixels (B) that emit blue light. In another exemplary embodiment, a subpixel can have the shape of a rectangle, a rhombus, a pentagon, or a hexagon. The four subpixels can be arranged to form a rhombus to create an RGBG pixel array. In other exemplary embodiments, the four subpixels can be arranged horizontally adjacent to each other, vertically adjacent to each other, or to form a square, which is not limited in the present disclosure. In an exemplary embodiment, a pixel unit may comprise three subpixels, and the three subpixels may be arranged horizontally next to each other, vertically next to each other, or in a delta-shaped arrangement, which is not limited in the present disclosure. Fig. 3 is a schematic diagram of a cross-sectional view of a display substrate structure, illustrating a structure of four subpixels in a display area. As shown in Fig. 3, the display substrate can, on a plane perpendicular to the display substrate, include a driver circuit layer 102 arranged on a base substrate 101, a light emission structure layer 103 arranged on one side of the driver circuit layer 102 away from the base substrate 101, and an encapsulation structure layer 104 arranged on one side of the light emission structure layer 103 away from the base substrate 101. In some possible embodiments, the display substrate can include a further film layer, such as a touch structure layer, which is not limited in the present disclosure. In an exemplary embodiment, the base substrate 101 can be a flexible or a rigid substrate. The driver circuit layer 102 can comprise a plurality of circuit units, each of which can include at least one pixel driver circuit consisting of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 can comprise a plurality of light-emitting units, each of which can include a light-emitting device, and the light-emitting device can include at least one anode, an organic emission layer, and a cathode. The anode is connected to a pixel driver circuit. The organic emission layer is connected to the anode. The cathode is connected to the organic emission layer. The organic emission layer emits light of a corresponding color when the anode and the cathode are driven.The encapsulation layer 104 can comprise a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer arranged one above the other. The first and third encapsulation layers can be made of an inorganic material, the second encapsulation layer can be made of an organic material, and the second encapsulation layer is arranged between the first and third encapsulation layers to form a laminated inorganic / organic / inorganic material structure and to ensure that no external moisture can penetrate the light-emitting structure 103. An exemplary embodiment of the present disclosure provides a display substrate. In one exemplary embodiment, the display substrate may, on a plane perpendicular to the display substrate, comprise a driver structure layer arranged on a base substrate and a light-emitting structure layer arranged on one side of the driver structure layer away from the base substrate. On a plane parallel to the display substrate, the driver structure layer may comprise a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, and at least one of the circuit units may comprise a pixel driver circuit configured to output a corresponding current to a light-emitting device connected to the pixel driver circuit. The light-emitting structure layer may comprise a plurality of light-emitting units.At least one of the light-emitting units may include a light-emitting device connected to a pixel driver circuit of the corresponding circuit unit. The light-emitting device is configured to emit light of a corresponding brightness in response to a current output by the pixel driver circuit connected to the light-emitting device. In an exemplary embodiment, the circuit units mentioned in the present disclosure relate to areas subdivided according to pixel driver circuits, and the light-emitting diodes mentioned in the present disclosure relate to areas subdivided according to light-emitting diodes. In an exemplary embodiment, the position and shape of an orthographic projection of a light-emitting unit on the base substrate may correspond to the position and shape of an orthographic projection of a circuit unit on the base substrate, or the position and shape of the orthographic projection of the light-emitting unit on the base substrate may not correspond to the position and shape of the orthographic projection of the circuit unit on the base substrate. The display substrate according to the exemplary embodiment of the present disclosure can comprise a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns. At least one circuit unit comprises a pixel driver circuit and at least one control line configured to supply a light emission control signal to the pixel driver circuit. In at least one circuit unit, the pixel driver circuit comprises at least one driver transistor, a first light emission control transistor, and a second light emission control transistor. A first electrode of the first light emission control transistor is connected to a first power supply line, and a second electrode of the first light emission control transistor is connected to a first electrode of the driver transistor.A first electrode of the second light emission control transistor is connected to a second electrode of the driver transistor. The first and second light emission control transistors are connected to different control lines, and each is arranged on opposite sides of the driver transistor in a unit column direction. In an exemplary embodiment, the at least one control line comprises a first signal line and a second signal line, and the first light emission control transistor is connected to the first signal line and the second light emission control transistor is connected to the second signal line, and the first signal line and the second signal line are each arranged on two sides of the driver transistor in the unit column direction. In an exemplary embodiment, the at least one control line comprises a light emission signal line, wherein the light emission signal line is connected to the second light emission control transistor in the present unit series and the light emission signal line is connected to the first light emission control transistor in the next unit series. An indicator substrate according to an exemplary embodiment of the present disclosure is illustrated below by means of some examples. Fig. 4 is a schematic diagram of an equivalent circuit of a pixel driver circuit according to an exemplary embodiment of the present disclosure. As shown in Fig. 4, the pixel driver circuit can comprise seven transistors (a first transistor T1 to a seventh transistor T7) and a storage capacitor C, and the pixel driver circuit is connected to nine signal lines (a first sampling signal line S1, a second sampling signal line S2, a third sampling signal line S3, a first signal line EM1, a second signal line EM2, a first initial signal line INIT1, a second initial signal line INIT2, a first power supply line VDD, and a data signal line DATA). In an exemplary embodiment, the pixel driver circuit can comprise a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to a second electrode of the first transistor T1, a first electrode of the second transistor T2, a gate electrode of the third transistor T3, and a second end of the storage capacitor C. The second node N2 is connected to a first electrode of the third transistor T3, a second electrode of the fourth transistor T4, and a second electrode of the fifth transistor T5. The third node N3 is connected to a second electrode of the second transistor T2, a second electrode of the third transistor T3, and a first electrode of the sixth transistor T6.The fourth node N4 is connected to a second electrode of the sixth transistor T6 and a second electrode of the seventh transistor T7, and the fourth node N4 is also connected to a first electrode of a light-emitting device EL. In an exemplary embodiment, a first end of the storage capacitor C is connected to the first power supply line VDD, and a second end of the storage capacitor C is connected to the first node N1. In one exemplary embodiment, a gate electrode of the first transistor T1 is connected to the second sampling signal line S2, a first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor is connected to the first node N1. A gate electrode of the second transistor T2 is connected to the first sampling signal line S1, a first electrode of the second transistor T2 is connected to the first node N1, and a second electrode of the second transistor T2 is connected to the third node N3. A gate electrode of the third transistor T3 is connected to the first node N1, a first electrode of the third transistor T3 is connected to the second node N2, and a second electrode of the third transistor T3 is connected to the third node N3.One gate electrode of the fourth transistor T4 is connected to the third sampling signal line S3, one electrode of the fourth transistor T4 is connected to the data signal line DATA, and one electrode of the fourth transistor T4 is connected to the second node N2. One gate electrode of the fifth transistor T5 is connected to the first signal line EM1, one electrode of the fifth transistor T5 is connected to the first power supply line VDD, and one electrode of the fifth transistor T5 is connected to the second node N2. One gate electrode of the sixth transistor T6 is connected to the second signal line EM2, one electrode of the sixth transistor T6 is connected to the third node N3, and one electrode of the sixth transistor T6 is connected to the fourth node N4.A gate electrode of the seventh transistor T7 is connected to the third sampling signal line S3, a first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and a second electrode of the seventh transistor T7 is connected to the fourth node N4. In the present disclosure, separate control of the fifth transistor T5 and the sixth transistor T6 is realized by connecting the fifth transistor T5 to the first signal line EM1 and the sixth transistor T6 to the second signal line EM2, i.e., the fifth transistor T5 and the sixth transistor T6 are each controlled by the two light emission signal lines. In an exemplary embodiment, the light-emitting device EL can be an OLED comprising a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) arranged one above the other, or a QLED comprising a first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode) arranged one above the other. The first electrode of the light-emitting device EL is connected to the fourth node N4, and a second electrode of the light-emitting device EL is connected to the second power supply line VSS. In an exemplary embodiment, a signal from the first power supply line VDD can be a continuously provided high-level signal, and a signal from the second power supply line VSS can be a continuously provided low-level signal. In one exemplary embodiment, the first transistor T1 through the seventh transistor T7 can be either P-type or N-type transistors. Using transistors of the same type in a pixel driver circuit can simplify the process flow, reduce the complexity of a display panel, and improve product yield. In some possible embodiments, the first transistor T1 through the seventh transistor T7 can comprise either a P-type or an N-type transistor. In one exemplary embodiment, low-temperature polysilicon thin-film transistors can be used for the first transistor T1 through the seventh transistor T7, or oxide thin-film transistors can be used, or both a low-temperature polysilicon thin-film transistor and an oxide thin-film transistor can be used. The active layer of a low-temperature polysilicon thin-film transistor consists of low-temperature polysilicon (LTPS), and the active layer of an oxide thin-film transistor consists of an oxide semiconductor (oxide). A low-temperature polysilicon thin-film transistor has advantages such as a high migration rate and fast charging, and an oxide thin-film transistor has advantages such as low leakage current.The low-temperature polysilicon thin-film transistor and the oxide thin-film transistor are integrated on a display substrate to form a low-temperature polycrystal oxide display substrate (LTPO), thus utilizing the advantages of both the low-temperature polysilicon thin-film transistor and the oxide thin-film transistor, enabling low-frequency drive, reduced power consumption, and improved display quality. Fig. 5 is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure and illustrates a planar structure of eight circuit units (2 unit rows and 4 unit columns). As shown in Fig. 5, the display substrate can comprise a plurality of circuit units in a plane parallel to the display substrate. A plurality of circuit units arranged sequentially along a first direction X is called a unit row, and a plurality of circuit units arranged sequentially along a second direction Y is called a unit column. The plurality of unit rows and the plurality of unit columns form an arrangement of circuit units arranged in a matrix, with the first direction X intersecting the second direction Y. In an exemplary embodiment, at least one circuit unit can comprise a pixel driver circuit connected to a first power supply line 61, a first signal line 91, and a second signal line 92. The first power supply line 61 is configured to supply a first power supply signal to the pixel driver circuit, the first signal line 91 is configured to supply a first light emission control signal to the pixel driver circuit, the second signal line 92 is configured to supply a second light emission control signal to the pixel driver circuit, and the first light emission control signal and the second light emission control signal are distinct signals. In an exemplary embodiment, the first signal line 91 and the second signal line 92 can have the form of a straight line or a curved line, the main body section of which extends along the first direction X, and the first power supply line 61 can have the form of a straight line or a curved line, the main body section of which extends along the second direction Y. In the present disclosure, “A extends along a B direction” means that A may comprise a main body section and a sub-section connected to the main body section, wherein the main body section is a line, a line segment, or a strip-shaped body, the main body section extends along the B direction, and a length of the main body section extending along the B direction is greater than a length of the sub-section extending along any other direction. In the following description, “A extends along a B direction” means “a main body section of A extends along a B direction.” In an exemplary embodiment, the at least one pixel driver circuit can comprise at least a plurality of transistors, and the plurality of transistors can include at least a third transistor T3 as a driver transistor, a fifth transistor T5 as a first light emission control transistor, and a sixth transistor T6 as a second light emission control transistor. A gate electrode of the fifth transistor T5 is connected to the first signal line 91, a first electrode of the fifth transistor T5 is connected to the first power supply line 61, and a second electrode of the fifth transistor T5 is connected to a first electrode of the third transistor T3. A gate electrode of the sixth transistor T6 is connected to the second signal line 92, and a first electrode of the sixth transistor T6 is connected to a second electrode of the third transistor T3. In one exemplary embodiment, the fifth transistor T5 and the sixth transistor T6 can be arranged on opposite sides of the third transistor T3 in the first direction X (a unit series direction). For example, the fifth transistor T5 can be arranged on one side of the third transistor T3 in a direction opposite to the first direction X, and the sixth transistor T6 can be arranged on one side of the third transistor T3 in the first direction X. In one exemplary embodiment, the fifth transistor T5 and the sixth transistor T6 can be arranged on opposite sides of the third transistor T3 in the second direction Y (the unit column direction). For example, the fifth transistor T5 can be arranged on one side of the third transistor T3 in a direction opposite to the second direction Y, and the sixth transistor T6 can be arranged on one side of the third transistor T3 in the second direction Y. In an exemplary embodiment, the first signal line 91 and the second signal line 92 can be arranged on opposite sides of the third transistor T3 in the second direction Y (the unit column direction). For example, the first signal line 91 can be arranged on one side of the third transistor T3 in a direction opposite to the second direction Y, and the second signal line 92 can be arranged on one side of the third transistor T3 in the second direction Y. In an exemplary embodiment, the display substrate can comprise a plurality of conductive layers in a direction perpendicular to the display substrate, and the first signal line 91 and the second signal line 92 can be arranged in different conductive layers. In an exemplary embodiment, the sixth transistor T6 can comprise at least one sixth gate electrode, wherein the sixth gate electrode can serve as the second gate of the present disclosure, wherein the sixth gate electrode and the second signal line 92 can be arranged in different conductive layers, and wherein the second signal line 92 can be connected to the sixth gate electrode via a through-hole. In an exemplary embodiment, the sixth gate electrode and the first signal line 91 can be arranged in the same conductive layer. In an exemplary embodiment, the pixel driver circuit can further include a second transistor T2 as a compensation transistor. A gate electrode of the second transistor T2 is connected to the first sampling signal line 21, a first electrode of the second transistor T2 is connected via the first connecting electrode 41 to a gate electrode of the third transistor T3, and a second electrode of the second transistor T2 is connected to a second electrode of the third transistor T3 or a first electrode of the sixth transistor T6. In an exemplary embodiment, an orthographic projection of the first connecting electrode 41 onto the plane of the display substrate overlaps at least partially an orthographic projection of the first signal line 91 onto the plane of the display substrate, and the orthographic projection of the first connecting electrode 41 onto the plane of the display substrate overlaps at least partially with an orthographic projection of the first scanning signal line 21 onto the plane of the display substrate, i.e., the first connecting electrode 41 overlaps simultaneously with the first signal line 91 and the first scanning signal line 21. In an exemplary embodiment, the pixel driver circuit can further include a first transistor T1 as a first initialization transistor. A gate electrode of the first transistor T1 is connected to a second sampling signal line 22 in a gate connection, a first electrode of the first transistor T1 is connected to a first initial signal line 31, and a second electrode of the first transistor T1 is connected via the first connection electrode 41 to a gate electrode of the third transistor T3. The first initial signal line 31 is configured to supply a first initial signal to the pixel driver circuit, and the first initial signal line 31 can have the form of a straight line or a curved line extending along the first direction X. In an exemplary embodiment, at least one circuit unit may further comprise a first connecting line 81 extending along the second direction Y, and the first connecting line 81 is connected to the first initial signal line 31 to form a net-like connecting structure for transmitting the first initial signal on the display substrate. In an exemplary embodiment, the pixel driver circuit can further include a seventh transistor T7 as a second initialization transistor. A gate electrode of the seventh transistor T7 is connected to a third sampling signal line 23, a first electrode of the seventh transistor T7 is connected to a second initialization signal line 32, and a second electrode of the seventh transistor T7 is connected to a second electrode of the sixth transistor T6. The second initialization signal line 32 is configured to supply a second initialization signal to the pixel driver circuit, and the second initialization signal line 32 can be in the form of a straight line or a curved line extending along the first direction X. In an exemplary embodiment, at least one circuit unit may further comprise a second connecting line 82 extending along the second direction Y, and the second connecting line 82 is connected to the second initial signal line 32 to form a net-like connecting structure for transmitting the second initial signal on the display substrate. In an exemplary embodiment, the first output signal line 31 and the second output signal line 32 can be arranged in each unit row, and the first connecting lines 81 and the second connecting lines 82 can be arranged alternately in a plurality of unit columns. In an exemplary embodiment, the pixel driver circuit can further include a fourth transistor T4 as a data write transistor. A gate electrode of the fourth transistor T4 is connected to the third sampling signal line 23, a first electrode of the fourth transistor T4 is connected to a data signal line 62, and a second electrode of the fourth transistor T4 is connected to the first electrode of the third transistor T3. The second transistor T2 and the fourth transistor T4 can be arranged on opposite sides of the third transistor T3 in the second direction Y (the unit column direction). For example, the second transistor T2 can be arranged on one side of the third transistor T3 in a direction opposite to the second direction Y, and the fourth transistor T4 can be arranged on one side of the third transistor T3 in the second direction Y. In an exemplary embodiment, the display substrate comprises, in a plane perpendicular to the display substrate, a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer, arranged sequentially on the base substrate. The semiconductor layer can comprise active layers of a plurality of transistors; the first conductive layer can comprise at least one first signal line 91, a plurality of sampling signal lines, and gate electrodes of the plurality of transistors; the second conductive layer can comprise at least one second initial signal line 32; the third conductive layer can comprise at least one first initial signal line 31, a second signal line 92, and a plurality of interconnect electrodes; and the fourth conductive layer can comprise at least one first power supply line 61, a first interconnect line 81, and a second interconnect line 82. In an exemplary embodiment, the display substrate can further comprise a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a first planarization layer. The first insulating layer can be arranged between the base substrate and the semiconductor layer, the second insulating layer can be arranged between the semiconductor layer and the first conductive layer, the third insulating layer can be arranged between the first conductive layer and the second conductive layer, the fourth insulating layer can be arranged between the second conductive layer and the third conductive layer, and the first planarization layer can be arranged between the third conductive layer and the fourth conductive layer. An exemplary description is given below using the manufacturing process of an indicator substrate as an example. A “structuring process” mentioned in the present disclosure includes a treatment such as the application of a layer, the application of a photoresist layer to a layer, the exposure of a mask, development, etching and removal of the photoresist for a metallic material, an inorganic material or a transparent conductive material, and includes a treatment such as the application of an organic layer, the exposure of a mask and development for an organic material.The deposition may include one or more of the following processes: sputtering, evaporation, and chemical vapor deposition; the coating may include one or more of the following processes: spray coating, spin coating, and inkjet printing; and the etching may include one or more of the following processes: dry etching and wet etching, without limitation to the present disclosure. A "thin film" refers to a layer of a particular material produced on a base substrate using deposition, coating, or other processes. If the "thin film" does not require any structuring process during the entire manufacturing process, the "thin film" may also be referred to as a "layer."If the "thin film" must be processed by the structuring process throughout the entire manufacturing process, the "thin film" is referred to as a "thin film" before the structuring process is carried out, and as a "layer" after the structuring process is carried out. The "layer" that has been processed by the structuring process comprises at least one "pattern." "A and B are arranged in the same layer" means, in the present disclosure, that A and B are formed simultaneously by the same structuring process, and a "thickness" of a film layer is a dimension of the film layer in a direction perpendicular to a display substrate.In an exemplary embodiment of the present disclosure, “an orthographic projection of B within a range of an orthographic projection of A” or “an orthographic projection of A that includes an orthographic projection of B” means that a boundary of the orthographic projection of B lies within a range of a boundary of the orthographic projection of A or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. In an exemplary embodiment, taking eight circuit units (two unit rows and four unit columns) as an example, a manufacturing process for the display substrate of the present embodiment may include the following operations. (11) A pattern of semiconductor layer is formed. In an exemplary embodiment, the formation of the semiconductor layer pattern may comprise: depositing a first insulating thin film and a semiconductor thin film successively onto a base substrate, and the semiconductor thin film being structured by a structuring process to form a first insulating layer covering the base substrate and the semiconductor layer arranged on the first insulating layer, as shown in Fig. 6. In an exemplary embodiment, the semiconductor layer can comprise a first active layer 11 of the first transistor T1 up to a seventh active layer 17 of the seventh transistor T7, and the first active layer 11 and the second active layer 12 are formed in an interconnected integral structure, and the third active layer 13 up to the seventh active layer 17 are formed in an interconnected integral structure. In an exemplary embodiment, in the first direction X, the fourth active layer 14 and the fifth active layer 15 can be arranged in an N-th unit column on one side of the third active layer 13 of the present circuit unit away from an (N+1)-th unit column, and the sixth active layer 16 can be arranged on one side of the third active layer 13 of the present circuit unit near the (N+1)-th unit column, i.e., the fifth active layer 15 and the sixth active layer 16 are each arranged on two sides of the third active layer 13 in the first direction X. In an exemplary embodiment, in the second direction Y, the first active layer 11, the second active layer 12 and the fifth active layer 15 can be arranged in an M-th unit row on one side of the third active layer 13 of the present circuit unit away from an (M+1)-th unit row, and the fourth active layer 14, the sixth active layer 16 and the seventh active layer 17 can be arranged on one side of the third active layer 13 of the present circuit unit close to the (M+1)-th unit row, i.e. the fifth active layer 15 and the sixth active layer 16 are each arranged on two sides of the second direction Y of the third active layer 13. The present disclosure facilitates the realization of separate control of the fifth transistor T5 and the sixth transistor T6 by providing the fifth transistor T5 and the sixth transistor T6 on two sides of the third transistor T3 in the first direction X and in the second direction Y. In an exemplary embodiment, the first active layer 11 can have an “n” shape, the second active layer 12 and the seventh active layer 17 can have an “L” shape, the third active layer 13 can have an “Ω” shape, and the fourth active layer 14, the fifth active layer 15 and the sixth active layer 16 can have an “I” shape. In an exemplary embodiment, an active layer of each transistor can comprise a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, a second region 11-2 of the first active layer can serve as the first region 12-1 of the second active layer, i.e., the second region 11-2 of the first active layer and the first region 12-1 of the second active layer are connected. A first region 13-1 of the third active layer can simultaneously serve as the second region 14-2 of the fourth active layer and as the second region 15-2 of the fifth active layer, i.e., the first region 13-1 of the third active layer, the second region 14-2 of the fourth active layer, and the second region 15-2 of the fifth active layer are connected. A second region 13-2 of the third active layer can serve as the first region 16-1 of the sixth active layer.The second region 13-2 of the third active layer and the first region 16-1 of the sixth active layer are connected. A second region 16-2 of the sixth active layer can serve as the second region 17-2 of the seventh active layer, i.e., the second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer are connected. A first region 11-1 of the first active layer 11, a second region 12-2 of the second active layer, a first region 14-1 of the fourth active layer, a first region 15-1 of the fifth active layer, and a first region 17-1 of the seventh active layer can be provided separately. In an exemplary embodiment, the first semiconductor layer can consist of polysilicon (p-Si), i.e., the first through seventh transistors are LTPS transistors. In an exemplary embodiment, the structuring of the first semiconductor thin film by the structuring process can include: forming an amorphous silicon (a-Si) thin film on the first insulating thin film, dehydrating the amorphous silicon thin film, and crystallizing the dehydrated amorphous silicon thin film to form a polysilicon thin film. Subsequently, the polysilicon thin film is structured to form the pattern of the first semiconductor layer. (12) A pattern of a first conductive layer is formed. In an exemplary embodiment, the formation of the pattern of the first conductive layer may comprise: sequentially depositing a second insulating thin film and a first conductive thin film onto the base substrate on which the aforementioned patterns are formed, and structuring the first conductive thin film by a structuring process to form a second insulating layer covering a pattern of the semiconductor layer and to form the pattern of the first conductive layer provided on the second insulating layer, as shown in Fig. 7A and Fig. 7B, where Fig. 7B is a planar schematic representation of the first conductive layer in Fig. 7A. In an exemplary embodiment, the first conductive layer may be designated as the first gate metal layer (GATE1). In an exemplary embodiment, the pattern of the first conductive layer of each circuit unit comprises at least a first sampling signal line 21, a second sampling signal line 22, a third sampling signal line 23, a sixth gate electrode 26, a first plate 71 of a storage capacitor and a first signal line 91. In an exemplary embodiment, the first plate 71 can have the shape of a rectangle, and a chamfer or groove can be provided at one corner of the rectangle. An orthographic projection of the first plate 71 onto the base substrate overlaps at least partially an orthographic projection of the third active layer of the third transistor T3 onto the base substrate. In an exemplary embodiment, the first plate 71 can simultaneously serve as a plate of the storage capacitor and as the gate electrode of the third transistor T3. In an exemplary embodiment, the first sampling signal line 21 can have the form of a straight line or a curved line, the main body section of which extends along the first direction X. The first sampling signal line 21 can be arranged on one side of the first plate 71 in a direction opposite to the second direction Y, a gate block 21-1 is connected to one side of the first sampling signal line 21 that is away from the first plate 71, and an area where the first sampling signal line 21 and the gate block 21-1 overlap with the second active layer can serve as the gate electrode of the second transistor T2 with a double-gate structure. In an exemplary embodiment, the second scanning signal line 22 can have the form of a straight line or a curved line, the main body part of which extends along the first direction X. The second scanning signal line 22 can be arranged on one side of the first scanning signal line 21, away from the first plate 71, and an area where the second scanning signal line 22 overlaps with the first active layer can serve as the gate electrode of the first transistor T1 with a double-gate structure. In an exemplary embodiment, the third scanning signal line 23 can have the form of a straight line or a curved line, the main body section of which extends along the first direction X. The third scanning signal line 23 can be arranged on one side of the first plate 71 in a direction opposite to the second direction Y. A region where the third scanning signal line 23 overlaps the fourth active layer can serve as the gate electrode of the fourth transistor T4, and a region where the third scanning signal line 23 overlaps the seventh active layer can serve as the gate electrode of the seventh transistor T7. That is, the fourth transistor T4 and the seventh transistor T7 of the present disclosure are switched on and off by the same scanning signal line. In an exemplary embodiment, the first signal line 91 can have the form of a straight line or a curved line, the main body section of which extends along the first direction X. The first signal line 91 can be arranged between the first sampling signal line 21 and the first plate 71, and a region where the first signal line 91 overlaps with the fifth active layer can serve as the gate electrode of the fifth transistor T5. In an exemplary embodiment, the sixth gate electrode 26 can be in the form of a strip extending along the first direction X. The sixth gate electrode 26 can be arranged between the third sampling signal line 23 and the first plate 71, and an area where the sixth gate electrode 26 overlaps the sixth active layer can serve as the gate electrode of the sixth transistor T6. In an exemplary embodiment, the sixth gate electrode 26 is configured to be connected to the second signal line to be formed subsequently. In an exemplary embodiment, the first sampling signal line 21, the second sampling signal line 22, the third sampling signal line 23, and the first signal line 91 each comprise a region that overlaps with the first semiconductor layer and a region that does not overlap with the first semiconductor layer. The width of at least one signal line in the region that overlaps with the first semiconductor layer can be greater than the width of at least one signal line in the region that does not overlap with the first semiconductor layer, and the width can be a quantity in the second direction Y. In an exemplary embodiment, after the formation of the pattern of the first conductive layer, conductive processing can be carried out on the semiconductor layer using the first conductive layer as a shield. The semiconductor layer in an area shielded by the first conductive layer forms channel regions of the first transistor T1 to the seventh transistor T7, and the semiconductor layer in an area not shielded by the first conductive layer is made conductive; that is, the first and second regions of the first active layer up to the seventh active layer are all made conductive. (13) A pattern of a second conductive layer is formed. In an exemplary embodiment, the formation of the pattern of the second conductive layer may comprise: sequentially depositing a third insulating thin film and a second conductive thin film onto the base substrate on which the above-mentioned patterns are formed, and structuring the second conductive thin film by a structuring process to form a third insulating layer covering the first conductive layer and the structural pattern of the second conductive layer provided on the third insulating layer, as shown in Figs. 8A and 8B. Fig. 8B is a planar schematic representation of the second conductive layer in Fig. 8A. In an exemplary embodiment, the second conductive layer may be referred to as the second gate metal layer (GATE2). In an exemplary embodiment, the pattern of the second conductive layer of each circuit unit can comprise at least a second initial signal line 32 and a second plate 72 of the storage capacitor. In an exemplary embodiment, the profile of the second plate 72 can have the form of a rectangle, a chamfer can be provided at one corner of the rectangle, an orthographic projection of the second plate 72 onto the base substrate overlaps at least one orthographic projection of the first plate 71 onto the base substrate, the second plate 72 can serve as another plate of the storage capacitor, and the first plate 71 and the second plate 72 form the storage capacitor of the pixel driver circuit. In an exemplary embodiment, the second plate 72 is provided with an opening 75. The opening 75 can be rectangular and located in the center of the second plate 72, such that the second plate 72 is formed in an annular structure. The opening 75 exposes the third insulating layer covering the first plate 71, and an orthographic projection of the first plate 71 onto the base substrate includes an orthographic projection of the opening 75 onto the base substrate. In an exemplary embodiment, the opening 75 is configured to accommodate a subsequently formed ninth via, and the ninth via is located within the opening 75 and exposes the first plate 71, so that a subsequently formed first interconnect is connected to the first plate 71. In an exemplary embodiment, the second conductive layer of each circuit unit can further comprise a plate-connecting strip 76. The plate-connecting strip 76 can be in the form of a strip extending along the first direction X, and the plate-connecting strip 76 can be provided on one side of the second plate 72 in the first direction X or on one side of the second plate 72 in a direction opposite to the first direction X. A first end of the plate-connecting strip 76 is connected to the second plate 72 in the present circuit unit, and a second end of the plate-connecting strip 76 is connected to the second plate 72 in a circuit unit adjacent in the first output direction X, such that the second plates 72 in adjacent circuit units are connected to each other in a unit series to form an integral structure.Since the second plate 72 in each circuit unit is connected to a first power supply line that is subsequently formed, by forming an integral structure in which the second plates 72 of adjacent circuit units are connected to each other, the second plates of the integral structure can also be used as a power supply signal line, so that it can be ensured that several second plates in a unit row have the same potential, which is advantageous to improve the uniformity of the display substrate, avoid a poor display of the display substrate and ensure a display effect of the display substrate. In an exemplary embodiment, the second initial signal line 32 can have the form of a straight line or a curved line, the main body section of which extends along the first direction X, and the second initial signal line 32 can be arranged on one side of the third scanning signal line 23, away from the second plate 72. In an exemplary embodiment, the second initial signal line 32 is configured to be connected to a first region of the seventh active layer by a sixth connecting electrode, which is subsequently formed. (14) A pattern of a fourth insulating layer is formed. In an exemplary embodiment, the formation of the pattern of the fourth insulating layer may comprise: depositing a fourth insulating thin film onto the base substrate on which the aforementioned patterns are formed, and structuring the fourth insulating thin film by a structuring process to form a fourth insulating layer covering the second conductive layer, with a plurality of vias provided on the fourth insulating layer, as shown in Fig. 9. In an exemplary embodiment, multiple vias in each circuit unit may comprise at least the following: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11 and a twelfth via V12. In an exemplary embodiment, an orthographic projection of the first via V1 on the base substrate lies within an area of ​​an orthographic projection of the first region of the first active layer on the base substrate, the fourth insulating layer of the third insulating layer and the second insulating layer within the first via V1 are etched away to expose a surface of the first region of the first active layer, and the first via V1 is configured such that a subsequently formed first initial interconnect block is connected to the first region of the first active layer via the first via V1. In an exemplary embodiment, an orthographic projection of the second via V2 on the base substrate lies within an area of ​​an orthographic projection of the second area of ​​the first active layer (also the first area of ​​the second active layer) on the base substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the second via V2 are etched away to expose a surface of the second area of ​​the first active layer, and the second via V2 is configured such that the first interconnect electrode to be formed subsequently is connected to the second area of ​​the first active layer (also the first area of ​​the second active layer) via the second via V2. In an exemplary embodiment, an orthographic projection of the third via V3 on the base substrate lies within an area of ​​an orthographic projection of the second area of ​​the second active layer on the base substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the third via V3 are etched away to expose a surface of the second area of ​​the second active layer, and the third via V3 is configured such that a fifth interconnect electrode to be formed subsequently is connected to the second area of ​​the second active layer via the third via V3. In an exemplary embodiment, an orthographic projection of the fourth via V4 on the base substrate lies within an area of ​​an orthographic projection of the second area of ​​the third active layer (also the first area of ​​the sixth active layer) on the base substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the fourth via V4 are etched away to expose a surface of the second area of ​​the third active layer, and the fourth via V4 is configured such that the fifth interconnect electrode to be formed subsequently is connected to the second area of ​​the third active layer (also the first area of ​​the sixth active layer) via the fourth via V4. In an exemplary embodiment, an orthographic projection of the fifth via V5 on the base substrate lies within an area of ​​an orthographic projection of the first region of the fourth active layer on the base substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the fifth via V5 is etched away to expose a surface of the first region of the fourth active layer, and the fifth via V5 is configured such that a subsequently formed third interconnect electrode is connected to the first region of the fourth active layer via the fifth via V5. In an exemplary embodiment, an orthographic projection of the sixth via V6 on the base substrate lies within an area of ​​an orthographic projection of the first region of the fifth active layer on the base substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the sixth via V6 are etched away to expose a surface of the first region of the fifth active layer, and the sixth via V6 is configured such that a second interconnect electrode to be formed subsequently is connected to the first region of the fifth active layer via the sixth via V6. In an exemplary embodiment, an orthographic projection of the seventh via V7 on the base substrate lies within an area of ​​an orthographic projection of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) on the base substrate, the fourth insulating layer of the third insulating layer and the second insulating layer within the seventh via V7 is etched away to expose a surface of the second area of ​​the sixth active layer, and the seventh via V7 is configured such that a subsequently formed fourth interconnect electrode is connected via the seventh via V7 to the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer). In an exemplary embodiment, an orthographic projection of the eighth via V8 on the base substrate lies within an area of ​​an orthographic projection of the first area of ​​the seventh active layer on the base substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the eighth via V8 are etched away to expose a surface of the first area of ​​the seventh active layer, and the eighth via V8 is configured such that the sixth interconnect electrode to be formed subsequently is connected to the first area of ​​the seventh active layer via the eighth via V8. In an exemplary embodiment, an orthographic projection of the ninth via V9 on the base substrate lies within an area of ​​an orthographic projection of the opening 75 on the base substrate, the fourth insulating layer and the third insulating layer within the ninth via V9 are etched away to expose a surface of the first plate 71, and the ninth via V9 is configured such that the first interconnect electrode to be formed subsequently is connected to the first plate 71 via the ninth via V9. In an exemplary embodiment, an orthographic projection of the tenth via V10 on the base substrate lies within an area of ​​an orthographic projection of the second plate 72 on the base substrate, the fourth insulating layer within the tenth via V10 is etched away to expose a surface of the second plate 72, and the tenth via V10 is configured such that the second interconnect electrode, which is subsequently formed, is connected to the second plate 72 via the tenth via V10. In an exemplary embodiment, an orthographic projection of the eleventh via V11 on the base substrate lies within an area of ​​an orthographic projection of the second initial signal line 32 on the base substrate, the fourth insulating layer within the eleventh via V11 is etched away to expose a surface of the second output signal line 32, and the eleventh via V11 is configured such that the sixth interconnect electrode to be formed subsequently is connected to the second output signal line 32 via the eleventh via V11. In an exemplary embodiment, an orthographic projection of the twelfth via V12 on the base substrate lies within an area of ​​an orthographic projection of the sixth gate electrode 26 on the base substrate, the fourth insulating layer and the third insulating layer within the twelfth via V12 are etched away to expose a surface of the sixth gate electrode 26, and the twelfth via V12 is configured such that the second signal line to be formed subsequently is connected to the sixth gate electrode 26 via the twelfth via V12. (15) A pattern of a third conductive layer is formed. In an exemplary embodiment, the formation of the third conductive layer may comprise: depositing a third conductive thin layer onto the base substrate on which the aforementioned patterns are formed, and structuring the third conductive thin layer by a structuring process to form the third conductive layer provided on the fourth insulating layer, as shown in Fig. 10A and Fig. 10B, where Fig. 10B is a planar schematic representation of the third conductive layer in Fig. 10A. In an exemplary embodiment, the third conductive layer may be designated as the first source-drain metal layer (SD1). In an exemplary embodiment, the third conductive layer of each circuit unit can comprise at least a first initial signal line 31, a first connecting electrode 41, a second connecting electrode 42, a third connecting electrode 43, a fourth connecting electrode 44, a fifth connecting electrode 45, a sixth connecting electrode 46, a seventh connecting electrode 47, an eighth connecting electrode 48 and a second signal line 92. In an exemplary embodiment, the first initial signal line 31 can have the form of a straight line or a curved line extending along the first direction X. The first initial signal line 31 can be arranged on one side of the first scanning signal line 21, away from the second plate 72, wherein an orthographic projection of the first initial signal line 31 onto the base substrate overlaps at least partially with an orthographic projection of the second scanning signal line 22 onto the base substrate, and the first initial signal line 31, with a constant voltage, can perform a shielding function to reduce the influence of the second scanning signal line 22 on the pixel driver circuit. In an exemplary embodiment, the second signal line 92 can have the form of a straight line or a curved line extending along the first direction X. The second signal line 92 can be arranged between the third sampling signal line 23 and the second plate 72, and the second signal line 92 can be connected via the twelfth via V12 of each circuit unit to the sixth gate electrode 26 of each circuit unit, so that the second signal line 92 can control the switching on and off of the sixth transistor T6. In an exemplary embodiment, the first connecting electrode 41 can have the form of a strip extending along the second direction Y, wherein a first end of the first connecting electrode 41 is connected via the second via V2 to the second region of the first active layer (also the first region of the second active layer), and a second end of the first connecting electrode 41 is connected via the ninth via V9 to the first plate 71. In an exemplary embodiment, since the first plate 71 simultaneously serves as the gate electrode of the third transistor T3, the first connecting electrode 41 enables the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first plate 71 to have the same potential and form the first node N1 of the pixel driver circuit. In an exemplary embodiment, an orthographic projection of the first connecting electrode 41 onto the base substrate is at least partially overlapped with an orthographic projection of the first scanning signal line 21 onto the base substrate, and the orthographic projection of the first connecting electrode 41 onto the base substrate is at least partially overlapped with an orthographic projection of the first signal line 91 onto the base substrate, i.e., the first connecting electrode 41 is simultaneously overlapped with both the first scanning signal line 21 and the first signal line 91.In contrast to an existing structure in which the first node N1 overlaps with a signal line, in the present disclosure, by providing the first node N1 of the pixel driver circuit, which overlaps with both the first sampling signal line 21 and the first signal line 91, the coupling influence to which the first node N1 is subject can be complemented by jumping the two signal lines. In an exemplary embodiment, the second connecting electrode 42 can have the form of a strip extending along the second direction Y, with a first end of the second connecting electrode 42 connected to the first region of the fifth active layer via the sixth via V6 and a second end of the second connecting electrode 42 connected to the second plate 72 via the tenth via V10. In an exemplary embodiment, the second connecting electrode 42 causes the first electrode of the fifth transistor T5 and the second plate 72 of the storage capacitor to have the same potential in each circuit unit. In an exemplary embodiment, a first power supply connection block 42-1 can be provided between the first end and the second end of the second connection electrode 42, wherein the first power supply connection block 42-1 can have a block shape (e.g. a rectangle), an orthographic projection of the first power supply connection block 42-1 onto the base substrate can lie within an area of ​​an orthographic projection of the second plate 72 onto the base substrate, and the first power supply connection block 42-1 is configured to be connected to the first power supply line to be formed subsequently. In an exemplary embodiment, the third interconnect electrode 43 can have the form of a block (e.g., a rectangle) and is connected to the first region of the fourth active layer via the fifth via V5. In another exemplary embodiment, the third interconnect electrode 43 can serve as the first electrode of the fourth transistor T4 and is configured to be connected to a data signal line to be formed subsequently. In an exemplary embodiment, the fourth interconnect electrode 44 can have the form of a block (e.g., a rectangle), and the fourth interconnect electrode 44 is connected via the seventh via V7 to the second region of the sixth active layer (also the second region of the seventh active layer). In an exemplary embodiment, the fourth interconnect electrode 44 can simultaneously serve as the second electrode of the sixth transistor T6 and as the second electrode of the seventh transistor T7, and the fourth interconnect electrode 44 is configured to be connected to an anode interconnect electrode to be formed subsequently. In an exemplary embodiment, the fifth interconnect electrode 45 can have the form of a strip extending along the second direction Y, with a first end of the fifth interconnect electrode 45 connected to the second region of the second active layer via the third via V3, and a second end of the fifth interconnect electrode 45 connected to the first region of the sixth active layer via the fourth via V4. In an exemplary embodiment, since the first region of the sixth active layer can serve as the second region of the third active layer, the fifth interconnect electrode 45 causes a second electrode of the second transistor T2, a second electrode of the third transistor T3, and a first electrode of the sixth transistor T6 to have the same potential to form the third node N3 of the pixel driver circuit.The second active layer can serve as the compensation active layer of the present disclosure, the sixth active layer can serve as the second light emission control active layer of the present disclosure, the second active layer and the sixth active layer are arranged in the semiconductor layer, and the fifth connecting electrode is arranged in the third conductive layer, and thus the sixth active layer and the fifth connecting electrode are arranged in different layer films. In an exemplary embodiment, the sixth connecting electrode 46 can have the form of a strip extending along the first direction X, a first end of the sixth connecting electrode 46 being connected to the first region of the seventh active layer via the eighth via V8, and a second end of the sixth connecting electrode 46 being connected to the second initial signal line 32 via the eleventh via V11, so that the second initial signal line 32 can write the second initial signal to a first electrode of the seventh transistor T7. In an exemplary embodiment, the sixth connecting electrode 46 in some circuit units can be connected to an initial connecting block 46-1, which may have the form of a block (e.g., a rectangle), and the initial connecting block 46-1 is configured to be connected to the second connecting line to be formed subsequently. For example, the initial connecting blocks 46-1 in the circuit units can be provided in an N-th unit column and an (N+2)-th unit column. In an exemplary embodiment, the seventh connecting electrode 47 can have the form of a block (e.g., a rectangle), the seventh connecting electrode 47 can be arranged on one side of the first initial signal line 31 near the first sampling signal line 21, a first end of the seventh connecting electrode 47 is connected to the first initial signal line 31, and a second end of the seventh connecting electrode 47 is connected via the first via V1 to the first region of the first active layer, so that the first initial signal line 31 can write the first initial signal to the first electrode of the first transistor T1. In an exemplary embodiment, the first initial signal line 31 and the seventh connecting electrode 47 can have an interconnected integral structure. In an exemplary embodiment, the eighth connecting electrode 48 can have the shape of a block (such as a rectangle), the eighth connecting electrode 48 can be arranged on one side of the first initial signal line 31 near the first sampling signal line 21, a first end of the eighth connecting electrode 48 is connected to the first initial signal line 31, a second end of the eighth connecting electrode 48 extends in one direction of the first sampling signal line 21.The eighth junction electrode 48 can serve as a node shielding electrode, wherein an orthographic projection of the eighth junction electrode 48 onto the base substrate overlaps at least partially with an orthographic projection of the second active layer between two gate electrodes of the second transistor T2 on the base substrate, and the eighth junction electrode 48 with a constant voltage can assume a shielding function to reduce the influence of signals in the pixel driver circuit on the node between the two gate electrodes of the second transistor T2 and to ensure the electrical performance of the second transistor T2. In an exemplary embodiment, the first initial signal line 31 and the eighth connecting electrode 48 can be an interconnected integral structure. In an exemplary embodiment, the eighth connecting electrode 48 in the circuit units of an (N+1)th unit column and an (N+3)th unit column is further configured such that it is connected to the first connecting line to be formed subsequently, while the eighth connecting electrode 48 in the circuit units of the Nth unit column and an (N+2)th unit column serves as a dummy pad and is not connected to the fourth conductive layer to be formed subsequently. (16) A pattern of a first planarization layer is formed. In an exemplary embodiment, forming the pattern of the first planarization layer may include depositing a first planarization thin film onto the base substrate on which the above-mentioned patterns are formed, and structuring the first planarization thin film by a structuring process to form a first planarization layer covering the third conductive layer, wherein the first planarization layer is provided with a plurality of vias, as shown in Fig. 11. In an exemplary embodiment, the plurality of vias in each circuit unit comprises at least a twenty-first via V21, a twenty-second via V22 and a twenty-third via V23. In an exemplary embodiment, an orthographic projection of the twenty-first via V21 on the base substrate lies within an area of ​​an orthographic projection of the first power supply connection block 42-1 on the base substrate, wherein the first planarization layer within the twenty-first via V21 is removed to expose a surface of the first power supply connection block 42-1, and the twenty-first via V21 is configured such that the first power supply line to be formed subsequently is connected to the first power supply connection block 42-1 via the twenty-first via V21. In an exemplary embodiment, the twenty-first via V21 can be designated as the power supply via, and an orthographic projection of the twenty-first via V21 onto the base substrate can lie within a region of an orthographic projection of the second plate 72 onto the base substrate. In an exemplary embodiment, an orthographic projection of the twenty-second via 22 on the base substrate lies within an area of ​​an orthographic projection of the third interconnect electrode 43 on the base substrate, the first planarization layer within the twenty-second via V22 is removed to expose a surface of the third interconnect electrode 43, and the twenty-second via V22 is configured such that a data signal line to be formed subsequently is connected to the third interconnect electrode 43 via the twenty-second via V22. In an exemplary embodiment, an orthographic projection of the twenty-third via V23 on the base substrate lies within an area of ​​an orthographic projection of the fourth interconnect electrode 44 on the base substrate, the first planarization layer within the twenty-third via V23 is removed to expose a surface of the fourth interconnect electrode 44, and the twenty-third via V23 is configured such that a subsequently formed anode interconnect electrode is connected to the fourth interconnect electrode 44 in an orthographic projection via the twenty-third via V23. In an exemplary embodiment, a twenty-fourth via V24 and a twenty-fifth via V25 can be provided on the first planarization layer. In an exemplary embodiment, an orthographic projection of the twenty-fourth via V24 on the base substrate lies within a region of an orthographic projection of the eighth interconnect electrode 48 on the base substrate, wherein the first planarization layer within the twenty-fourth via V24 is removed to expose a surface of the eighth interconnect electrode 48, and the twenty-fourth via V24 is configured such that the first interconnect to be formed subsequently is connected to the eighth interconnect electrode 48 via the twenty-fourth via V24. In an exemplary embodiment, the twenty-fourth via V24 can be arranged in the circuit units of the (N+1)th unit column and the (N+3)th unit column. In an exemplary embodiment, an orthographic projection of the twenty-fifth via V25 on the base substrate lies within an area of ​​an orthographic projection of the initial interconnect block 46-1 on the base substrate. The first planarization layer within the twenty-fifth via V25 is removed to expose a surface of the initial interconnect block 46-1, and the twenty-fifth via V25 is configured such that the second interconnect to be formed subsequently is connected to the initial interconnect block 46-1 via the twenty-fifth via V25. In an exemplary embodiment, the twenty-fifth via V25 can be located in the circuit units of the Nth unit column and the (N+2)th unit column. (17) A pattern of a fourth conductive layer is formed. In an exemplary embodiment, the formation of the pattern of the fourth conductive layer may comprise: depositing a fourth conductive thin layer onto the base substrate on which the aforementioned patterns are formed, and structuring the fourth conductive thin layer by a structuring process to form the fourth conductive layer provided on the first planarization layer, as shown in Fig. 12A and Fig. 12B. Fig. 12B is a planar schematic representation of the fourth conductive layer in Fig. 12A. In an exemplary embodiment, the fourth conductive layer may be designated as the second source-drain metal layer (SD2). In an exemplary embodiment, the fourth conductive layer in each circuit unit comprises at least a first power supply line 61, a data signal line 62 and an anode connection electrode 63. In an exemplary embodiment, the first power supply line 61 can have the form of a straight line or a curved line extending along the second direction Y, and the first power supply line 61 is connected to the first power supply connection block 42-1 via the twenty-first via V21. Since the first power supply connection block 42-1 is connected to the second connection electrode 42, and the second connection electrode 42 is connected to the first electrode of the fifth transistor T5 and the second plate 72 of the storage capacitor, the first power supply line 61 can write the first power supply signal to the fifth transistor T5 and the second plate 72 of the storage capacitor. In the exemplary embodiment, the data signal line 62 can have the form of a straight line or a curved line extending along the second direction Y, and the data signal line 62 is connected to the third interconnect electrode 43 via the twenty-second via V22. Since the third interconnect electrode 43 is connected to the first region of the fourth active layer, the data signal line 62 is connected to a first electrode of the fourth transistor T4, and the data signal line 62 can write a data signal to the first electrode of the fourth transistor T4. In an exemplary embodiment, the anode connection electrode 63 can have the form of a strip extending along the second direction Y, wherein the anode connection electrode 63 is connected to the fourth connection electrode 44 via the twenty-third via V23 and the anode connection electrode 63 is configured to be connected to the anode to be formed subsequently. Since the fourth connection electrode 44 is connected to the second region of the sixth active layer and a second region of the seventh active layer, a connection can be established between the anode to be formed subsequently and the second electrode of the sixth transistor T6 as well as the second electrode of the seventh transistor T7, and the pixel driver circuit can control the light-emitting device to emit light. In an exemplary embodiment, the fourth conductive layer can further comprise a first connecting line 81 and a second connecting line 82. In an exemplary embodiment, the first connecting line 81 can have the form of a straight line or a curved line extending along the second direction Y, and the first connecting line 81 is connected to the eighth connecting electrode 48 via the twenty-fourth via V24. Since the eighth connecting electrode 48 is connected to the first initial signal line 31, the connection between the first initial signal line 31, whose main body section extends along the first direction X, and the first connecting line 81, whose main body section extends along the second direction Y, is realized, and a network-like interconnect structure is formed on the display substrate.By providing the first initial signal line 31 and the first connecting line 81 to form the network-like connection structure, the present disclosure not only allows the resistances of the signal lines to be effectively reduced and the voltage drop of the first initial signal to be reduced, but also effectively improves the uniformity of the first initial signal in the display substrate, thereby effectively improving the display uniformity and improving the display effect and display quality. In an exemplary embodiment, the second connecting line 82 can have the form of a straight line or a curved line extending along the second direction Y, and the second connecting line 82 is connected to the first connecting block 46-1 via the twenty-fifth via V25. Since the first connecting block 46-1 is connected to the sixth connecting electrode 46, and the sixth connecting electrode 46 is connected to the second first signal line 32, the connection between the second first signal line 32, whose main body section extends along the first direction X, and the second connecting line 82, whose main body section extends along the second direction Y, is realized, and a network-like connection structure is formed on the display substrate.In the present disclosure, by providing the second initial signal line 32 and the second connecting line 82 to form the network-like connection structure, not only can the resistances of the signal lines be effectively reduced and a voltage drop of the second initial signal be reduced, but also the uniformity of the second initial signal in the display substrate can be effectively improved, the display uniformity can be effectively improved, and the display effect and display quality can be improved. Fig. 12C is a schematic diagram of a network-like connection structure of a first initial signal according to an exemplary embodiment of the present disclosure, Fig. 12D is a schematic diagram of a network-like connection structure of a second initial signal according to an exemplary embodiment of the present disclosure, and Fig. 12E is a schematic diagram of a network-like connection structure of a first initial signal and a network-like connection structure of a second initial signal according to an exemplary embodiment of the present disclosure. As shown in Figs. 12C and 12E, the first initial signal line 31 can be connected to the eighth connection electrode 48, and a first connection block 81-1 can be provided on the first connection line 81. The first connection block 81-1 can be in the form of a strip extending along the first direction X, with a first end of the first connection block 81-1 being connected to the first connection line 81 and a second end of the first connection block 81-1 being connected to the eighth connection electrode 48 via a through-hole, thereby realizing the connection between the first initial signal line 31, whose main body part extends along the first direction X, and the first connection line 81, whose main body part extends along the second direction Y, and forming a network-like connection structure for a first initial signal on the display substrate. In an exemplary embodiment, the first connecting line 81 and the first connecting block 81-1 can have an interconnected integral structure. As shown in Figs. 12D and 12E, a second connection block 82-1 can be provided on the second connection line 82. The second connection block 82-1 can be in the form of a block, wherein a first end of the second connection block 82-1 is connected to the second connection line 82, a second end of the second connection block 82-1 is connected to the first connection block 46-1 via a through-hole, and the first connection block 46-1 is connected to the second initial signal line 32 via a through-hole, thereby realizing the connection between the second initial signal line 32, whose main body section extends along the first direction X, and the second connection line 82, whose main body section extends along the second direction Y, and forming a network-like connection structure for a second initial signal on the display substrate. In an exemplary embodiment, the connecting line 82 and the second connecting block 82-1 can have an interconnected integral structure. As shown in Fig. 12E, the first output signal line 31, the first connecting block 46-1 and the eighth connecting electrode 48 can be arranged in the third conductive layer, the second output signal line 32 can be arranged in the second conductive layer and the first connecting line 81 and the second connecting line 82 can be arranged in the fourth conductive layer. In an exemplary embodiment, the first connecting line 81 and the second connecting line 82 can be arranged in different circuit units. For example, the first connecting line 81 can be arranged in the circuit units of the (N+1)th unit column and the (N+3)th unit column, and the second connecting line 82 can be arranged in the circuit units of the Nth unit column and the (N+2)th unit column. As another example, the first connecting line 81 can be arranged in the circuit units of the Nth unit column and the (N+2)th unit column, and the second connecting line 82 can be arranged in the circuit units of the (N+1)th unit column and the (N+3)th unit column. In an exemplary embodiment, the first initial signal line 31 and the second initial signal line 32 can be arranged in each unit row, and the first connecting line 81 and the second connecting line 82 can be arranged alternately in a plurality of unit columns, thereby making full use of the layout space, avoiding impairment of the light transmission for providing the first connecting line 81 and the second connecting line 82, and improving the display effect. (18) A pattern of a second planarization layer is formed. In an exemplary embodiment, forming the pattern of the second planarization layer may include applying a second planarization film to the base substrate on which the above-mentioned patterns are formed, and structuring the second planarization film using a structuring process to form the second planarization layer covering the fourth conductive layer, wherein the second planarization layer is provided with a plurality of vias, as shown in Fig. 13. In an exemplary embodiment, the multiple vias in each circuit unit include at least one anode via V30. In an exemplary embodiment, an orthographic projection of the anode via V30 lies on the base substrate within an area of ​​an orthographic projection of the anode connection electrode 63 on the base substrate, the second planarization layer within the anode via V30 is removed to expose a surface of the anode connection electrode 63, and the anode via V30 is configured such that the anode to be formed subsequently is connected to the anode connection electrode 63 via the anode via V30. Previously, a driver circuit layer was fabricated on the base substrate. In a plane parallel to the display substrate, the driver circuit layer can comprise multiple circuit units, each of which can include a pixel driver circuit and a first sampling signal line, a second sampling signal line, a third sampling signal line, a first signal line, a second signal line, a data signal line, a first power supply line, a second power supply line, a first initial signal line, and a second initial signal line, all connected to the pixel driver circuit.In a plane perpendicular to the display substrate, the driver circuit layer can comprise a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a first planarization layer, a fourth conductive layer, and the second planarization layer, stacked sequentially on the base substrate. In an exemplary embodiment, after completion of the driver circuit layer, a light emission structure layer is produced on the driver circuit layer, wherein a manufacturing process of the light emission structure layer can comprise the following steps. (19) A pattern of an anode-conducting layer is formed. In an exemplary embodiment, the formation of the pattern of the anode-conducting layer may comprise: depositing an anode-conducting thin film onto the base substrate on which the above-mentioned patterns are formed, structuring the anode-conducting thin film by a structuring process to form an anode-conducting layer on the second planarization layer, as shown in Figs. 14A and 14B, where Fig. 14B is a schematic top view of the anode-conducting layer in Fig. 14A. In an exemplary embodiment, the anode-conducting layer can comprise a plurality of anodes 90, and each anode 90 can be connected via the anode through-hole V30 to an anode connection electrode 63 of a corresponding circuit unit. Since the anode connection electrode 63 is connected to the fourth connection electrode 44, and the fourth connection electrode 44 is connected to the second region of the sixth active layer and the second region of the seventh active layer, a corresponding connection is established between the light-emitting device and the pixel driver circuit, and the pixel driver circuit can control the light-emitting device to emit light. In an exemplary embodiment, the multiple anodes 90 can comprise a first anode of a red light-emitting device, a second anode of a first green light-emitting device, a third anode of a blue light-emitting device, and a fourth anode of a second green light-emitting device. The first anode, the second anode, the third anode, and the fourth anode can be arranged sequentially along the first direction X, and the first anodes, the second anodes, the third anodes, and the fourth anodes of adjacent rows are staggered to form an RGBG pixel array. (20) A pattern of a pixel definition layer is formed. In an exemplary embodiment, a process forming the pattern of the pixel definition layer may comprise: depositing a pixel definition thin film onto the base substrate on which the above-mentioned patterns are formed; the pixel definition thin film is structured by a structuring process to form a pattern of a pixel definition layer, as shown in Fig. 15. In an exemplary embodiment, the pixel definition layer can comprise a plurality of pixel apertures K, each of which can expose a surface of an anode 90. In an exemplary embodiment, a subsequent preparation process may include: forming an organic emission layer using an evaporation or inkjet printing process, wherein the organic emission layer is connected to an anode via a pixel aperture, and forming a cathode on the organic emission layer, wherein the cathode is connected to the organic emission layer.An encapsulation structure layer is formed, and the encapsulation structure layer can comprise a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer arranged on top of each other, wherein the first encapsulation layer and the third encapsulation layer can be made of an inorganic material, the second encapsulation layer can be made of an organic material, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, ensuring that no moisture from the outside can penetrate into a light-emitting structure layer. In an exemplary embodiment, the base substrate can be a flexible or a rigid substrate. The rigid substrate can consist of one or more of the following materials, but is not limited to them: glass and quartz. The flexible substrate can consist of one or more of the following materials, but is not limited to them: polyethylene terephthalate, ethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyaryl esters, polyimide, polyvinyl chloride, polyethylene, and textile fibers.In an exemplary embodiment, the flexible substrate can comprise a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer arranged one above the other, wherein the materials of the first flexible material layer and the second flexible material layer can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, or the like; materials of the first inorganic material layer and the second inorganic material layer can be silicon nitride (SiNx) or silicon oxide (SiOx), or the like, to improve the water and oxygen resistance of the base substrate; and a material of the semiconductor layer can be amorphous silicon (a-si). In an exemplary embodiment, the first, second, third, and fourth conductive layers can be made of a metallic material, such as one or more of the following: silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy of the aforementioned metals, such as an aluminum-neodymium alloy (AlNd) or a molybdenum-niobium alloy (MoNb), and can have a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. The anodic conductive layer can consist of a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a multi-layer composite structure, such as ITO / Ag / ITO, etc.The first, second, third, and fourth insulating layers can be made of one or more of the following materials: silicon dioxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite. The first and second planarization layers can be made of an organic material, such as resin. The pixel definition layer can be made of polyimide, acrylic, or polyethylene terephthalate. The cathode can be made of one or more of the following materials: magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy of one or more of the aforementioned metals. An exemplary embodiment of the present disclosure provides a display substrate in which, by separately controlling a fifth and a sixth transistor, pulse-width modulation with higher accuracy at an ultra-high frequency, compensation of the light emission signal duty cycle, compensation for low gray levels, and an improved afterimage can be achieved. The fifth transistor, T5, is connected to a first signal line, the sixth transistor, T6, is connected to a second signal line, and the first and second signal lines together establish the duty cycle of a pulse-width modulation (PWM). The display substrate of the present disclosure facilitates the separate control of the fifth transistor T5 and the sixth transistor T6 by providing the first signal line and the second signal line in different conductive layers, providing the first signal line and the second signal line on two sides of the third transistor T3 in the second direction, and providing the fifth transistor T5 and the sixth transistor T6 on two sides of the third transistor T3 in the first and second directions. In the display substrate of the present disclosure, by providing the first node of the pixel driver circuit such that it overlaps with the first sampling signal line and the first signal line, the coupling influence to which the first node is exposed can be complemented by the jumping of the two signal lines. The display substrate of the present disclosure is provided with a first initial signal line, the main body section of which extends along the first direction, and a first connecting line, the main body section of which extends along the second direction, as well as a second initial signal line, the main body section of which extends along the first direction, and a second connecting line, the main body section of which extends along the second direction, such that the first output signal line and the second output signal line each form a network-like connecting structure which not only effectively reduces the resistances of the output signal lines and reduces a voltage drop of the output voltages, but also effectively improves the uniformity of the output voltage in the display substrate, effectively improves the display uniformity, and improves the display effect and the display quality. In the display substrate of the present disclosure, the influence of signals in the pixel driver circuit on the node between the two gate electrodes of the second transistor T2 is reduced by providing a node shielding electrode, and the electrical performance of the second transistor T2 is ensured. The manufacturing process of the present disclosure can be well compatible with an existing manufacturing process, is simple in process implementation, easy to implement and exhibits high production efficiency, low production costs and high yield. Fig. 16 is an equivalent circuit diagram of another pixel driver circuit according to an exemplary embodiment of the present disclosure. As shown in Fig. 16, a main structure of the pixel driver circuit according to an embodiment of the present disclosure is essentially the same as that shown in Fig. 4, except that the pixel driver circuit of the present embodiment further comprises a first capacitor C1, wherein a first end of the first capacitor C1 is connected to the first power supply line VDD and a second end of the first capacitor C1 is connected to the second node N2. In an exemplary embodiment, a gate electrode of the fifth transistor T5 in the pixel driver circuit of the present embodiment is connected to a light emission signal line EM_n-1 in the previous unit series, and a gate electrode of the sixth transistor T6 is connected to a light emission signal line EM_n in the present unit series, thereby realizing separate control of the fifth transistor T5 and the sixth transistor T6. Fig. 17 is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure and illustrates a planar structure of eight circuit units (2 unit rows and 4 unit columns). In an exemplary embodiment, the main structure of the display substrate of the present embodiment is essentially the same as that shown in Fig. 5, except that the display unit of the present embodiment has only one light emission signal line, and the light emission signal line is connected on one side to a gate electrode of the sixth transistor T6 in the present unit row and on the other side to a gate electrode of a fifth transistor T5 in the next unit row. In an exemplary embodiment, at least one circuit unit can comprise a pixel driver circuit connected to a first power supply line 61 or a light emission signal line 93, and the light emission signal line 93 is configured to provide a light emission control signal to the sixth transistor T6 in the present unit row and the fifth transistor T5 in the next unit row. In an exemplary embodiment, at least one pixel driver circuit may comprise a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7, and the positions and interconnection relationships of the above-mentioned transistors are substantially the same as in the preceding embodiments. In an exemplary embodiment, the light emission signal line 93 can have the form of a straight line or a curved line, the main body section of which extends along the first direction X, and the light emission signal line 93 can be arranged on one side of the third transistor T3 in the second direction Y. In an exemplary embodiment, the fifth transistor T5 can comprise at least one fifth gate electrode, the sixth transistor T6 can comprise at least one sixth gate electrode, the fifth gate electrode can serve as the first gate of the present disclosure, and the sixth gate electrode can serve as the second gate of the present disclosure. In at least one circuit unit, the light emission signal line 93 is connected to a sixth gate electrode in the present unit series, and the light emission signal line 93 is connected via the light emission signal link line 56 to a fifth gate electrode in the next unit series. In an exemplary embodiment, the display substrate can comprise a plurality of conductive layers in a direction perpendicular to the display substrate. The fifth gate electrode and the sixth gate electrode can be arranged in the same conductive layer, the fifth gate electrode (the sixth gate electrode) and the light emission signal line 93 can be arranged in different conductive layers, the fifth gate electrode (the sixth gate electrode) and the light emission signal link line 56 can be arranged in different conductive layers, and the light emission signal link line 56 and the light emission signal line 93 can be arranged in different conductive layers. In an exemplary embodiment, the plurality of conductive layers can comprise at least a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer, arranged sequentially on the base substrate along a direction away from the base substrate. The fifth gate electrode and the sixth gate electrode can be arranged in the first conductive layer, the light emission signal line 93 can be arranged in the third conductive layer, and the light emission signal link line 56 can be arranged in the fourth conductive layer. In an exemplary embodiment, the light emission signal line 93 can be connected to the sixth gate electrode via a via, wherein the light emission signal link line 56 can have the form of a strip extending along the second direction Y. A first end of the light emission signal link line 56 is connected via the via to the light emission signal line 93 in the current unit row, and a second end of the light emission signal link line 56, after extending from the current unit row to the next unit row, is connected via a via to the fifth gate electrode in the next unit row. In an exemplary embodiment, the plurality of conductive layers may further comprise a fifth conductive layer which is arranged on a side of the fourth conductive layer furthest from the base substrate, the first power supply line 61 may be arranged in the fifth conductive layer, and an orthographic projection of the first power supply line 61 onto the plane of the display substrate is at least partially overlapped with an orthographic projection of the light emission signal link line 56 onto the plane of the display substrate. In an exemplary embodiment, at least one circuit unit can comprise a first initial signal line 31 extending along the first direction X and a first connecting line 81 extending along the second direction Y, and the first connecting line 81 is connected to the first initial signal line 31 to form a net-like interconnect structure for transmitting a first initial signal on the display substrate. In an exemplary embodiment, at least one circuit unit can comprise a second initial signal line 32 extending along the first direction X and a second connecting line 82 extending along the second direction Y, wherein the second connecting line 82 is connected to the second initial signal line 32 to form a net-like interconnect structure for transmitting a second initial signal on the display substrate. In an exemplary embodiment, at least one circuit unit can comprise a third connecting line 83 extending along the first direction X and a second power supply line 64 extending along the second direction Y, wherein the third connecting line 83 is connected to the second power supply line 64 to form a net-like interconnect structure that transmits a second power supply signal to the display substrate. In an exemplary embodiment, taking eight circuit units (two unit rows and four unit columns) as an example, the manufacturing process for the display substrate of the present embodiment may comprise the following steps. (21) A pattern of semiconductor layer is formed, wherein the process for forming the pattern of the semiconductor layer and the structure of the semiconductor layer are essentially the same as shown in Fig. 6, and the semiconductor layer may comprise a first active layer 11 to a seventh active layer 17, except that the first active layer 11 to the seventh active layer 17 have an interconnected integral structure, and the semiconductor layer further comprises a third plate 73 of the first capacitor, as shown in Fig. 18. In an exemplary embodiment, a second region 13-2 of the third active layer can simultaneously serve as the second region 12-2 of the second active layer and as the first region 16-1 of the sixth active layer; that is, the second region 12-2 of the second active layer, the second region 13-2 of the third active layer, and the first region 16-1 of the sixth active layer are interconnected. In contrast to the missing connection between the second and third active layers shown in Fig. 6, the second region 12-2 of the second active layer and the second region 13-2 of the third active layer are connected in the present embodiment by an active connecting line 18., one end of the active connecting line 18 is connected to the second area 12-2 of the second active layer 12, and the other end of the active connecting line 18 is connected to the second area 13-2 of the third active layer 13, and the second active layer 12, the third active layer 13 and the active connecting line 18 have an interconnected integral structure. In an exemplary embodiment, the third plate 73 can have the form of a block (e.g., a rectangle) and can be arranged on one side of the third active layer 13 of the present circuit unit, away from the (N+1)th unit column, and the third plate 73 is connected to the first region 13-1 of the third active layer, the second region 14-2 of the fourth active layer, and the second region 15-2 of the fifth active layer. In an exemplary embodiment, the third plate 73 can serve as the plate of the first capacitor. (22) A pattern of a first conductive layer is formed, the process for forming the pattern of the first conductive layer and the structure of the first conductive layer being essentially the same as in Fig. 7A and Fig. 7B, except that the first conductive layer is provided with a fifth gate electrode 25 without a light emission signal line, as shown in Fig. 19A and Fig. 19B, and Fig. 19B is a schematic top view of the first conductive layer in Fig. 19A. In an exemplary embodiment, the pattern of the first conductive layer in each circuit unit can comprise a first sampling signal line 21, a second sampling signal line 22, a third sampling signal line 23, a fifth gate electrode 25, a sixth gate electrode 26 and a first plate 71 of the storage capacitor, and the structures of the first sampling signal line 21 to the third sampling signal line 23, the sixth gate electrode 26 and the first plate 71 are essentially the same as those of the preceding embodiments. In one exemplary embodiment, the fifth gate electrode 25 can be in the form of a strip extending along the first direction X. The fifth gate electrode 25 can be arranged between the first scanning signal line 21 and the first plate 71, and an area where the fifth gate electrode 25 overlaps with the fifth active layer can serve as the gate electrode of the fifth transistor T5. In another exemplary embodiment, the fifth gate electrode 25 is configured to be connected to a subsequently formed light emission signal link, and the sixth gate electrode 26 is configured to be connected to the subsequently formed light emission signal link. In an exemplary embodiment, an orthographic projection of the first plate 71 on the base substrate and an orthographic projection of the third plate 73 on the base substrate do not overlap. (23) A pattern of a second conductive layer is formed, wherein the process for forming the pattern of the second conductive layer and the structure of the second conductive layer are essentially the same as in Fig. 8A and Fig. 8B, except that the second conductive layer is additionally provided with a fourth plate 74 of the first capacitor, as shown in Fig. 20A and Fig. 20B, and Fig. 20B is a schematic top view of the second conductive layer in Fig. 20A. In an exemplary embodiment, the pattern of the second conductive layer of each circuit unit can comprise at least a second initial signal line 32, a second plate 72 of the storage capacitor and a fourth plate 74 of the first capacitor, and the structures of the second initial signal line 32 and the second plate 72 are essentially the same as in the preceding embodiments. In an exemplary embodiment, the fourth plate 74 can have a rectangular shape, a chamfer can be provided at one corner of the rectangle, the fourth plate 74 can be arranged on one side of the second plate 72 of the present circuit unit away from the (N+1)th unit column, an orthographic projection of the fourth plate 74 onto the base substrate is at least partially overlapped with an orthographic projection of the third plate 73 onto the base substrate, the fourth plate 74 can serve as another plate of the first capacitor, and the third plate 73 and the fourth plate 74 form the first capacitor of the pixel driver circuit. In an exemplary embodiment, the second plate 72 and the fourth plate 74 of each circuit unit can have an interconnected integral structure. (24) A pattern of a fourth insulating layer is formed, wherein the process for forming the pattern of the fourth insulating layer and the structure of the multiple vias are essentially the same as shown in Fig. 9, except that the multiple vias additionally include a thirteenth via V13, but do not include a third via and a fourth via as shown in Fig. 21. In an exemplary embodiment, the multiple vias in each circuit unit can comprise at least a first via V1, a second via V2, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12 and the thirteenth via V13. The positions and connection structures of the first via V1 to the second via V2 and of the fifth via V5 to the twelfth via V12 are essentially the same as in the aforementioned embodiments. In an exemplary embodiment, an orthographic projection of the thirteenth via V13 on the base substrate lies within an area of ​​an orthographic projection of the fifth gate electrode 25 on the base substrate, wherein the fourth insulating layer and the third insulating layer within the thirteenth via V13 are etched away to expose a surface of the fifth gate electrode 25, and the thirteenth via V13 is configured such that a ninth interconnect electrode to be formed subsequently is connected to the fifth gate electrode 25 via the thirteenth via V13. (25) A pattern of a third conductive layer is formed, the process for forming the third conductive layer and the structure of the third conductive layer being essentially the same as those shown in Fig. 10A and Fig. 10B, except that the third conductive layer is additionally provided with a ninth connecting electrode 49 without a fifth connecting electrode, as shown in Fig. 22A and Fig. 22B, and Fig. 22B is a schematic top view of the third conductive layer in Fig. 22A. In an exemplary embodiment, the third conductive layer in each circuit unit can comprise at least a first initial signal line 31, a light emission signal line 93, a first connecting electrode 41, a second connecting electrode 42, a third connecting electrode 43, a fourth connecting electrode 44, a sixth connecting electrode 46, a seventh connecting electrode 47, an eighth connecting electrode 48 and a ninth connecting electrode 49, and the structures of the first initial signal line 31, the first connecting electrode 41 to the fourth connecting electrode 44 and the sixth connecting electrode 46 to the eighth connecting electrode 48 are essentially the same as in the preceding embodiments. In an exemplary embodiment, the light emission signal line 93 can have the form of a straight line or a curved line extending along the first direction X, the light emission signal line 93 can be arranged between the third scanning signal line 23 and the second plate 72, and the light emission signal line 93 can be connected to the sixth gate electrode 26 of each circuit unit via the twelfth via V12 of each circuit unit, so that the light emission signal line 93 can control the switching on and off of the sixth transistor T6. In an exemplary embodiment, a light-emitting connecting block 93-1 can further be provided on one side of the light-emitting signal line 93, away from the second plate 72, wherein the light-emitting connecting block 93-1 can have a block shape (such as a rectangular shape). A first end of the light-emitting connecting block 93-1 is connected to the light-emitting signal line 93, a second end of the light-emitting connecting block 93-1 extends in one direction away from the second plate 72, and the light-emitting connecting block 93-1 is configured such that it can be connected to the light-emitting signal connecting line to be formed subsequently. In an exemplary embodiment, an orthographic projection of the first connecting electrode 41 on the base substrate overlaps at least partially an orthographic projection of the first scanning signal line 21 on the base substrate. In an exemplary embodiment, a first power supply connection block 42-1 can be provided at a second end of the second connection electrode 42, the first power supply connection block 42-1 can have the form of a block (e.g. a rectangle), an orthographic projection of the first power supply connection block 42-1 on the base substrate can lie within an area of ​​an orthographic projection of the second plate 72 on the base substrate, and the first power supply connection block 42-1 is configured to be connected to a first power supply line to be formed subsequently. In an exemplary embodiment, an initial connection block 46-1 can be provided in the circuit units of the Nth unit column, and the initial connection block 46-1 is configured so that it can be connected to a second connection line to be formed subsequently. In an exemplary embodiment, the ninth connecting electrode 49 can have the form of a block (e.g., a rectangle), the ninth connecting electrode 49 can be arranged between the first initial signal line 31 and the second plate 72, the ninth connecting electrode 49 is connected to the fifth gate electrode 25 via the thirteenth via V13, and the ninth connecting electrode 49 is configured so that it can be connected to the light emission signal connecting line to be formed subsequently. (26) A pattern of a first planarization layer is formed. In an exemplary embodiment, forming the pattern of the first planarization layer may include depositing a first planarization thin film onto the base substrate on which the above-mentioned patterns are formed, and structuring the first planarization thin film by a structuring process to form a first planarization layer covering the third conductive layer, wherein the first planarization layer is provided with a plurality of vias, as shown in Fig. 23. In an exemplary embodiment, the plurality of vias on the first planarization layer comprises at least a twenty-first via V21, a twenty-second via V22, a twenty-third via V23, a twenty-fourth via V24, a twenty-fifth via V25, a twenty-sixth via V26 and a twenty-seventh via V27. In an exemplary embodiment, an orthographic projection of the twenty-first via V21 on the base substrate lies within a region of an orthographic projection of the first power supply interconnect block 42-1 on the base substrate, wherein the first planarization layer within the twenty-first via V21 is removed to expose a surface of the first power supply interconnect block 42-1, and the twenty-first via V21 is configured such that an eleventh interconnect electrode, subsequently formed, is connected to the first power supply interconnect block 42-1 via the twenty-first via V21. In an exemplary embodiment, the twenty-first via V21 can be provided in each circuit unit. In an exemplary embodiment, the orthographic projection of the twenty-first via V21 on the base substrate can lie within an area of ​​an orthographic projection of the second plate 72 on the base substrate. In an exemplary embodiment, an orthographic projection of the twenty-second via V22 on the base substrate lies within an area of ​​an orthographic projection of the third interconnect electrode 43 on the base substrate. The first planarization layer within the twenty-second via V22 is removed to expose a surface of the third interconnect electrode 43, and the twenty-second via V22 is configured such that a twelfth interconnect electrode, subsequently formed, is connected to the third interconnect electrode 43 via the twenty-second via V22. In an exemplary embodiment, the twenty-second via V22 can be provided in each circuit unit. In an exemplary embodiment, an orthographic projection of the twenty-third via V23 on the base lies within an area of ​​an orthographic projection of the fourth interconnect electrode 44 on the base substrate. The first planarization layer within the twenty-third via V23 is removed to expose a surface of the fourth interconnect electrode 44, and the twenty-third via V23 is configured such that a subsequently formed thirteenth interconnect electrode is connected to the fourth interconnect electrode 44 via the twenty-third via V23. In an exemplary embodiment, the twenty-third via V23 can be provided in each circuit unit. In an exemplary embodiment, an orthographic projection of the twenty-fourth via V24 on the base substrate lies within an area of ​​an orthographic projection of the eighth interconnect electrode 48 on the base substrate. The first planarization layer within the twenty-fourth via V24 is removed to expose a surface of the eighth interconnect electrode 48, and the twenty-fourth via V24 is configured such that a fourteenth interconnect electrode, subsequently formed, is connected to the eighth interconnect electrode 48 via the twenty-fourth via V24. In an exemplary embodiment, the twenty-fourth via V24 can be provided in each circuit unit. In an exemplary embodiment, an orthographic projection of the twenty-fifth via V25 on the base substrate lies within an area of ​​an orthographic projection of the initial interconnect block 46-1 on the base substrate, wherein the first planarization layer within the twenty-fifth via V25 is removed to expose a surface of the initial interconnect block 46-1, and the twenty-fifth via V25 is configured such that a fifteenth interconnect electrode, subsequently formed, is connected to the initial interconnect block 46-1 via the via. In an exemplary embodiment, the twenty-fifth via V25 can be provided in the circuit units of the Nth unit column. In an exemplary embodiment, an orthographic projection of the twenty-sixth via V26 on the base substrate lies within an area of ​​an orthographic projection of the light emission interconnect block 93-1 of the light emission signal line 93 on the base substrate. The first planarization layer within the twenty-sixth via V26 is removed to expose a surface of the light emission interconnect block 93-1, and the twenty-sixth via V26 is configured such that the light emission signal interconnect line to be formed subsequently is connected to the light emission interconnect block 93-1 via the twenty-sixth via V26. In an exemplary embodiment, the twenty-sixth via V26 can be provided in each circuit unit. In an exemplary embodiment, an orthographic projection of the twenty-seventh via V27 onto the base substrate lies within an area of ​​an orthographic projection of the ninth interconnect electrode 49 onto the base substrate. The first planarization layer within the twenty-seventh via V27 is removed to expose a surface of the ninth interconnect electrode 49, and the twenty-seventh via V27 is configured such that the subsequently formed light-emitting signal link is connected to the ninth interconnect electrode 49 via the twenty-seventh via V27. In an exemplary embodiment, the twenty-seventh via V27 can be provided in each circuit unit. (27) A pattern of a fourth conductive layer is formed. In an exemplary embodiment, the formation of the pattern of the fourth conductive layer may comprise: depositing a fourth conductive thin film onto the base substrate on which the aforementioned patterns are formed, and structuring the fourth conductive thin film by a structuring process to form the fourth conductive layer arranged on the first planarized layer, as shown in Fig. 24A and Fig. 24B. Fig. 24B is a schematic planar representation of the fourth conductive layer in Fig. 24A. In an exemplary embodiment, the fourth conductive layer comprises at least an eleventh connecting electrode 51, a twelfth connecting electrode 52, a thirteenth connecting electrode 53, a fourteenth connecting electrode 54, a fifteenth connecting electrode 55, a light emission signal connecting line 56 and a third connecting line 83. In an exemplary embodiment, the eleventh connecting electrode 51 can have the form of a block (e.g., a rectangle), wherein the eleventh connecting electrode 51 is connected to the first power supply connection block 42-1 via the twenty-first via V21, and the eleventh connecting electrode 51 is configured to be connected to the first power supply line to be formed subsequently. In an exemplary embodiment, the eleventh connecting electrode 51 can be provided in each circuit unit. In an exemplary embodiment, an orthographic projection of the eleventh connecting electrode 51 onto the base substrate is at least partially overlapped with an orthographic projection of the second plate 72 onto the base substrate. In an exemplary embodiment, the twelfth interconnect electrode 52 can have the form of a strip extending along the second direction Y, wherein the twelfth interconnect electrode 52 is connected to the third interconnect electrode 43 via the twenty-second via V22, and the twelfth interconnect electrode 52 is configured to be connected to a data signal line to be formed subsequently. In an exemplary embodiment, the twelfth interconnect electrode 52 can be provided in each circuit unit. In an exemplary embodiment, the thirteenth connecting electrode 53 can have the form of a strip extending along the second direction Y, wherein the thirteenth connecting electrode 53 is connected to the fourth connecting electrode 44 via the twenty-third via V23, and the thirteenth connecting electrode 53 is configured to be connected to the anode connecting electrode to be formed subsequently. In an exemplary embodiment, the thirteenth connecting electrode 53 can be provided in each circuit unit. In an exemplary embodiment, the fourteenth interconnect electrode 54 can have the form of a block (such as a rectangle) or a strip, and the fourteenth interconnect electrode 54 is connected to the eighth interconnect electrode 48 via the twenty-fourth via V24. In an exemplary embodiment, the fourteenth interconnect electrode 54 can be provided in each circuit unit, wherein the fourteenth interconnect electrode 54 in a circuit unit of the Nth unit column, the (N+1)th unit column, and the (N+3)th unit column has the form of a block (e.g., a rectangle), and the fourteenth interconnect electrode 54 in the form of a block is a dummy pad and is not connected to the fifth conductive layer to be formed subsequently, and the dummy pad is configured to ensure etch uniformity and uniformity between the subpixels.The fourteenth connecting electrode 54 in the circuit unit of the (N+2)th unit column has the form of a strip, and the fourteenth connecting electrode 54 of the (N+2)th unit column is configured to be connected to a first connecting line that is subsequently formed. In an exemplary embodiment, the fifteenth connecting electrode 55 can have the form of a block (such as a rectangle), wherein the fifteenth connecting electrode 55 is connected to the first connecting block 46-1 via the twenty-fifth via V25 and the fifteenth connecting electrode 55 is configured to be connected to the second connecting line to be formed subsequently. In an exemplary embodiment, the fifteenth connecting electrode 55 can be provided in the circuit units of the Nth unit column. In an exemplary embodiment, the light emission signal connection line 56 can have the form of a strip extending along the second direction Y, wherein a first end of the light emission signal connection line 56 is connected via the twenty-sixth via V26 to the light emission connection block 93-1 of the circuit unit in the present unit series, and a second end of the light emission signal connection line 56 extends along the second direction Y to the circuit unit in the next unit series and is connected via the twenty-seventh via V27 to a ninth connection electrode 49 of the circuit unit in the next unit series. In an exemplary embodiment, the light emission signal connection line 56 can be provided in each circuit unit. In an exemplary embodiment, the light emission connection block 93-1 of the circuit unit in the present unit series is connected to the light emission signal line 93 in the present unit series, and the ninth connection electrode 49 of the circuit unit in the next unit series is connected to the fifth gate electrode 25 of this circuit unit, so that the light emission signal line 56 establishes a connection between the light emission signal line 93 in the present unit series and the fifth gate electrode 25 in the next unit series, the light emission signal line 93 in the present unit series can control not only the switching on and off of the sixth transistor T6 in the present unit series, but also the switching on and off of the fifth transistor T5 in the next unit series, i.e.In the circuit unit of the present unit series, the fifth transistor T5 is controlled by the light emission signal line 93 of the previous unit series, and the sixth transistor T6 is controlled by the light emission signal line 93 of the present unit series. For example, the light emission signal line 93 in the (M-1)th unit series can control the switching on and off of the sixth transistor T6 in the (M-1)th unit series while simultaneously controlling the switching on and off of the fifth transistor T5 in the Mth unit series. As another example, the light signal line 93 in the Mth unit series can control the switching on and off of the sixth transistor T6 in the Mth unit series while simultaneously controlling the switching on and off of the fifth transistor T5 in the (M+1)th unit series.In the circuit unit of the M-th unit series, the fifth transistor T5 is controlled by the light emission signal line 93 in the (M-1)-th unit series, and the sixth transistor T6 is controlled by the light emission signal line 93 in the M-th unit series. In another example, the light signal line 93 in the (M+1)-th unit series can control the switching on and off of the sixth transistor T6 in the (M+1)-th unit series, while it controls the switching on and off of the fifth transistor T5 in an (M+2)-th unit series. In an exemplary embodiment, the third connecting line 83 can have the form of a straight line or a curved line extending along the first direction X, wherein the third connecting line 83 can be arranged between the first scanning signal line 21 and the second plate 72, and the third connecting line 83 is configured to be connected to a second power supply line, which is subsequently formed. In an exemplary embodiment, one side of the third connecting line 83, which is close to the first sampling signal line 21, is connected to a second power supply connection block 83-1, wherein the second power supply connection block 83-1 can have the shape of a block (such as a rectangle) and is configured to be connected to the second power supply line to be formed subsequently. In an exemplary embodiment, the second power supply connection block 83-1 can be provided in the circuit units of the (N+1)th unit column and the (N+3)th unit column. In an exemplary embodiment, an orthographic projection of the third connecting conductor 83 on the base substrate does not overlap an orthographic projection of the second plate 72 on the base substrate, and the orthographic projection of the third connecting conductor 83 on the base substrate overlaps at least partially orthographic projections of the first connecting electrode 41 and the second connecting electrode 42 on the base substrate. (28) A pattern of a second planarization layer is formed. In an exemplary embodiment, forming the pattern of the second planarization layer may include depositing a second planarization thin film onto the base substrate on which the above-mentioned patterns are formed, and structuring the second planarization thin film using a structuring process to form the second planarization layer covering the fourth conductive layer, wherein the second planarization layer is provided with a plurality of vias, as shown in Fig. 25. In an exemplary embodiment, the plurality of vias on the second planarization layer comprises at least a thirty-first via V31, a thirty-second via V32, a thirty-third via V33, a thirty-fourth via V34, a thirty-fifth via V35 and a thirty-sixth via V36. In an exemplary embodiment, an orthographic projection of the thirty-first via V31 on the base substrate lies within a region of an orthographic projection of the eleventh interconnect electrode 51 on the base substrate, wherein the second planarization layer within the thirty-first via V31 is removed to expose a surface of the thirty-first via V31, and the thirty-first via V31 is configured such that the first power supply line subsequently formed is connected to the eleventh interconnect electrode 51 of the first power supply line via the thirty-first via V31. In an exemplary embodiment, the thirty-first via V31 can be provided in each circuit unit. In an exemplary embodiment, an orthographic projection of the thirty-second via V32 on the base substrate lies within an area of ​​an orthographic projection of the twelfth interconnect electrode 52 on the base substrate. The second planarization layer within the thirty-second via V32 is removed to expose a surface of the twelfth interconnect electrode 52, and the thirty-second via V32 is configured such that the data signal line to be subsequently formed is connected to the twelfth interconnect electrode 52 via the thirty-second via V32. In an exemplary embodiment, the thirty-second via V32 can be provided in each circuit unit. In an exemplary embodiment, an orthographic projection of the thirty-third via V33 on the base substrate lies within an area of ​​an orthographic projection of the thirteenth interconnect electrode 53 on the base substrate. The second planarization layer within the thirty-third via V33 is removed to expose a surface of the thirteenth interconnect electrode 53, and the thirty-third via V33 is configured such that the anode interconnect electrode to be formed subsequently is connected to the thirteenth interconnect electrode 53 via the thirty-third via V33. In an exemplary embodiment, the thirty-third via V33 can be provided in each circuit unit. In an exemplary embodiment, an orthographic projection of the thirty-fourth via V34 on the base substrate lies within a region of an orthographic projection of the fourteenth interconnect electrode 54 on the base substrate. The second planarization layer within the thirty-fourth via V34 is removed to expose a surface of the fourteenth interconnect electrode 54, and the thirty-third via V34 is configured such that the first interconnect to be formed subsequently is connected to the fourteenth interconnect electrode 54 via the thirty-third via V34. In an exemplary embodiment, the thirty-third via V34 can be provided in the circuit units of the (N+2)th unit column. In an exemplary embodiment, an orthographic projection of the thirty-fifth via V35 on the base substrate lies within an area of ​​an orthographic projection of the fifteenth interconnect electrode 55 on the base substrate. The second planarization layer within the thirty-fifth via V35 is removed to expose a surface of the fifteenth interconnect electrode 55, and the thirty-fifth via V35 is configured such that the second interconnect to be formed subsequently is orthographically connected to the fifteenth interconnect electrode 55 through the thirty-fifth via V35. In an exemplary embodiment, the thirty-fifth via V35 can be provided in the circuit units of the Nth unit column. In an exemplary embodiment, an orthographic projection of the thirty-sixth via V36 on the base substrate lies within a region of an orthographic projection of the second power supply connection block 83-1 of the third connection line 83 on the base substrate, wherein the second planarization layer within the thirty-sixth via V36 is removed to expose a surface of the second power supply connection block 83-1, and the thirty-sixth via V36 is configured such that the second power supply line to be formed subsequently is connected to the second power supply connection block 83-1 via the thirty-sixth via V36. In an exemplary embodiment, the thirty-sixth via V36 can be provided in the circuit units of the (N+1)th unit column and the (N+3)th unit column. (29) A pattern of a fifth conductive layer is formed. In an exemplary embodiment, the formation of the fifth conductive layer pattern may comprise: depositing a fifth conductive thin layer onto the base substrate on which the above-mentioned patterns are formed, and structuring the fifth conductive thin layer using a structuring method to form the fifth conductive layer arranged on the second planarization layer, as shown in Fig. 26A and Fig. 26B, where Fig. 26B is a schematic top view of the fifth conductive layer in Fig. 26A. In an exemplary embodiment, the fifth conductive layer may be designated as the third source-drain metal layer (SD3). In an exemplary embodiment, the fifth conductive layer can comprise at least a first power supply line 61, a data signal line 62, an anode connection electrode 63, a second power supply line 64, a first connection line 81 and a second connection line 82. In an exemplary embodiment, the first power supply line 61 can have the form of a straight line or a curved line extending along the second direction Y, and the first power supply line 61 is connected to the eleventh connection electrode 51 via the thirty-first via V31. Since the eleventh connection electrode 51 is connected to the first power supply connection block 42-1, the first power supply connection block 42-1 is connected to the second connection electrode 42, and the second connection electrode 42 is connected to the first anode electrode of the fifth transistor T5, the second plate 72 of the storage capacitor, and the fourth plate 74 of the first capacitor, so that the first power supply line 61 can write the first power supply signal to the first electrode of the fifth transistor T5, the second plate 72 of the storage capacitor, and the fourth plate 74 of the first capacitor.In an exemplary embodiment, the first power supply line 61 can be provided in each circuit unit. In an exemplary embodiment, an orthographic projection of the first power supply line 61 onto the base substrate is at least partially overlapped with an orthographic projection of the light emission signal connection line 56 onto the base substrate, and the first power supply line 61 with a constant voltage can assume a shielding function, reduce the influence of the light emission signal on the pixel driver circuit and stabilize a potential of the light emission signal. In an exemplary embodiment, the data signal line 62 can have the form of a straight line or a curved line extending along the second direction Y, and the data signal line 62 is connected to the twelfth connection electrode 52 via the thirty-second via V32. Since the twelfth connection electrode 52 is connected to the third connection electrode 43, and the third connection electrode 43 is connected to the first region of the fourth active layer, a connection is established between the data signal line 62 and the first electrode of the fourth transistor T4, and the data signal line 62 can write a data signal to the first electrode of the fourth transistor T4. In an exemplary embodiment, the data signal line 62 can be provided in each circuit unit. In an exemplary embodiment, the anode connection electrode 63 can have the form of a strip extending along the first direction X or along the second direction Y, wherein the anode connection electrode 63 is connected to the thirteenth connection electrode 53 via the thirty-third via V33 and the anode connection electrode 63 is configured to be connected to an anode to be formed subsequently.Since the thirteenth connection electrode 53 is connected to the fourth connection electrode 44, and the fourth connection electrode 44 is connected to the second region of the sixth active layer and the second region of the seventh active layer, the connection of the anode to be formed subsequently can be realized with the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the pixel driver circuit can control the light-emitting device to emit light. In an exemplary embodiment, the anode connection electrode 63 can be provided in each circuit unit. In an exemplary embodiment, the second power supply line 64 can have the form of a straight line or a curved line extending along the second direction Y, and the second power supply line 64 is connected to the second power supply connection block 83-1 via the thirty-sixth via V36. Since the second power supply connection block 83-1 is connected to the third connection line 83, a connection is established between the third connection line 83, whose main body extends along the first direction X, and the second power supply line 64, whose main body extends along the second direction Y, and a network-like connection structure is formed on the display substrate.In the present disclosure, the second power supply line 64 and the third connecting line 83 form a network-like interconnection structure that can not only effectively reduce the resistance of the second power supply line and the voltage drop of the second power supply signal, but also effectively improve the uniformity of the second power supply signal in the display substrate, thereby improving the display uniformity and the display effect and quality. In an exemplary embodiment, the second power supply line 64 can be provided in the circuit units of the (N+1)th unit column and the (N+3)th unit column. In an exemplary embodiment, the first connecting line 81 can have the form of a straight line or a curved line extending along the second direction Y, and the first connecting line 81 is connected to the fourteenth connecting electrode 54 via the thirty-fourth via V34. Since the fourteenth connecting electrode 54 is connected to the eighth connecting electrode 48, and the eighth connecting electrode 48 is connected to the first initial signal line 31, a connection is established between the first initial signal line 31, whose main body section extends along the first direction X, and the first connecting line 81, whose main body section extends along the second direction Y, and a network-like interconnect structure is formed on the display substrate.In the present disclosure, the first initial signal line 31 and the first connecting line 81 form a network-like interconnection structure that not only effectively reduces the resistances of the initial signal lines and decreases the voltage drop of the first initial signal, but also effectively improves the uniformity of the first initial signal in the display substrate, thereby effectively improving display uniformity, display effectiveness, and display quality. In an exemplary embodiment, the first connecting line 81 can be provided in the circuit units of the (N+2)th unit column. In an exemplary embodiment, the second connecting line 82 can have the form of a straight line or a curved line extending along the second direction Y, and the second connecting line 82 is connected to the fifteenth connecting electrode 55 via the thirty-fifth via V35. Since the fifteenth connecting electrode 55 is connected to the first connecting block 46-1, the first connecting block 46-1 is connected to the sixth connecting electrode 46, and the sixth connecting electrode 46 is connected to the second first signal line 32, thereby establishing a connection between the second first signal line 32, whose main body extends along the first direction X, and the second connecting line 82, whose main body extends along the second direction Y, thus forming a network-like interconnect structure on the display substrate.In the present disclosure, the second initial signal line 32 and the second connecting line 82 form a network-like interconnection structure which can not only effectively reduce the resistance of the second signal line and the voltage drop of the second initial signal, but also effectively improve the uniformity of the second initial signal in the display substrate, thereby effectively improving the display uniformity, display effectiveness, and display quality. In an exemplary embodiment, the second connecting line 82 can be provided in the circuit units of the Nth unit column. Fig. 26C is a schematic diagram of a network-like connection structure for an initial signal and a network-like connection structure for a second power supply according to an exemplary embodiment of the present disclosure. As shown in Fig. 26C, a second power supply connection block 83-1 can be provided on the third connection line 83, and the second power supply line 64 is connected to the second power supply connection block 83-1 via a through-hole, thereby establishing a connection between the third connection line 83, whose main body section extends along the first direction X, and the second power supply line 64, whose main body section extends along the second direction Y, thus forming a network-like connection structure for a second power supply on the display substrate.The first connecting line 81 is connected via a through-hole to the fourteenth connecting electrode 54, the fourteenth connecting electrode 54 is connected via a through-hole to the eighth connecting electrode 48, and the eighteenth connecting electrode 48 is connected to the first initial signal line 31, thereby realizing a connection between the first initial signal line 31, whose main body part extends along the first direction X, and the first connecting line 81, whose main body part extends along the second direction Y, thereby forming a network-like connection structure for a first initial signal on the display substrate.The second connecting line 82 is connected via a through-hole to the fifteenth connecting electrode 55, the fifteenth connecting electrode 55 is connected via a through-hole to the first connecting block 46-1, and the first connecting block 46-1 is connected to the second initial signal line 32, whereby a connection is realized between the second initial signal line 32, the main body part of which extends along the first direction X, and the second connecting line 82, the main body part of which extends along the second direction Y, thereby forming a net-like connection structure for a second initial signal on the display substrate. In an exemplary embodiment, the second initial signal line 32 can be arranged in the second conductive layer, wherein the first initial signal line 31, the first connecting block 46-1 and the eighth connecting electrode 48 can be arranged in the third conductive layer, the fourteenth connecting electrode 54, the fifteenth connecting electrode 55 and the third connecting line 83 can be arranged in the fourth conductive layer, and the second power supply line 64, the first connecting line 81 and the second connecting line 82 can be arranged in the fifth conductive layer. In an exemplary embodiment, the first initial signal line 31, the second initial signal line 32, and the third connecting line 83 can be arranged in each unit row; the first connecting line 81, the second power supply line 64, the second connecting line 82, and the second power supply line 64 can be arranged alternately in the unit columns; a first connecting line 81, a second connecting line 82, and two second power supply lines 64 can each be arranged in four unit columns; and the first connecting line 81, the second connecting line 82, and the second power supply line 64 can be arranged in different unit columns, thereby fully utilizing the layout space, avoiding any impairment of light transmission, and improving the display effect. In an exemplary embodiment, the Nth unit column can be provided with a second connecting line 82, the (N+1)th unit column can be provided with a second power supply line 64, the (N+2)th unit column can be provided with a first connecting line 81, and the (N+3)th unit column can be provided with a second power supply line 64. (30) A pattern of a third planarization layer is formed. In an exemplary embodiment, the formation of the pattern of the third planarization layer may comprise: depositing a third planarization thin film on the base substrate on which the above-mentioned patterns are formed, structuring the third planarization thin film by a structuring process to form a third planarization layer covering the fifth conductive layer, and the third planarization layer being provided with a plurality of anode vias, and an anode via being configured such that an anode to be formed subsequently is connected to the anode junction electrode via the via. So far, a driver circuit layer has been fabricated on the base substrate. In a plane parallel to the display substrate, the driver circuit layer can comprise a variety of circuit units, each of which includes a pixel driver circuit and a first sampling signal line, a second sampling signal line, a third sampling signal line, a light emission signal line, a data signal line, a first power supply line, a first initial signal line, and a second initial signal line connected to the pixel driver circuit, and the light emission signal lines are each connected to the sixth transistor T6 in the current unit row and the fifth gate electrode 25 in the next unit row.In a plane perpendicular to the display substrate, the driver circuit layer can comprise a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a first planarization layer, a fourth conductive layer, a second planarization layer, a fifth conductive layer, and a third planarization layer stacked sequentially on the base substrate. In an exemplary embodiment, after the driver circuit layer has been fabricated, a light emission structure layer is first fabricated on the driver circuit layer, and then an encapsulation structure layer is formed. The light emission structure layer can comprise an anode-conducting layer, a pixel definition layer, an organic light-emitting layer, and a cathode, wherein the anode-conducting layer can comprise multiple anodes, the pixel definition layer can comprise multiple pixel openings, and the encapsulation structure can comprise a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer arranged one above the other. The display substrate provided in the present embodiment also implements separate control of the fifth and sixth transistors and can realize pulse-width modulation with higher control accuracy at an ultra-high frequency, light emission signal duty cycle compensation, low grayscale compensation, and improved image retention. In at least one circuit unit of the present embodiment, the sixth transistor T6 is controlled by the light emission signal line of the present unit series, and the fifth transistor T5 is controlled by a light emission signal line of the previous unit series.The fifth transistor T5 assumes the (cascaded) mode in which it is driven by a light emission signal line of the sixth transistor T6 of a previous stage, which not only reduces the capacitance of the first node N1 and prevents the first node N1 from being affected by the light emission signal line, but also reduces the number of light emission signal lines, which is advantageous for achieving high resolution. In the display substrate of the present embodiment, a fifth gate electrode and a sixth gate electrode are provided in the first conductive layer, a light emission signal line is provided in the third conductive layer, the light emission signal line is connected to the sixth gate electrode via a through-hole, and a light emission signal link line is provided in the fourth conductive layer, a first end of the light emission signal link line is connected to the light emission signal line in the present unit row, a second end of the light emission signal link line is connected to the fifth gate electrode in the next unit row, and a cascaded light emission control signal is transmitted using the light emission signal link line arranged in the SD2 layer.and the first power supply line of the SD3 layer shields the light emission signal link line, thereby effectively stabilizing the potential of the light emission signal. The display substrate of the present disclosure forms a network-like interconnection structure by providing a third connecting line, the main body of which extends along the first direction, and a second power supply line, the main body of which extends along the second direction, which not only effectively reduces the resistance of the second power supply line and reduces the voltage drop of the second supply voltage, but also effectively improves the uniformity of the second supply voltage in the display substrate, effectively improves the display uniformity and improves the display effect and display quality. The display substrate of the present disclosure uses a 3SD mode and adds a first capacitor and forms a net-like connection structure for a second power supply signal, a net-like connection structure for a first initial signal and a net-like connection structure for a second initial signal on the display substrate, thereby further improving the display effect. Fig. 27 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure and illustrates a planar structure of eight circuit units (2 unit rows and 4 unit columns). In an exemplary embodiment, a main structure of the display substrate of the present embodiment is essentially the same as that shown in Fig. 17, except that the display substrate of the present embodiment has a 2SD structure. In an exemplary embodiment, the plurality of conductive layers can comprise at least a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer, arranged sequentially on the base substrate along a direction away from the base substrate, wherein the fifth gate electrode and the sixth gate electrode can be arranged in the first conductive layer, the third interconnect line 83 and the light emission signal line 93 can be arranged in the third conductive layer, and the light emission signal interconnect line 56, the first power supply line 61, the data signal line 62, the second power supply line 64, the first interconnect line 81, and the second interconnect line 82 can be arranged in the fourth conductive layer. In an exemplary embodiment, taking eight circuit units (two unit rows and four unit columns) as an example, the manufacturing process for the display substrate of the present embodiment may comprise the following steps. (31) A pattern of semiconductor layer is formed, and the process for forming the pattern of the semiconductor layer and the structure of the semiconductor layer are essentially the same as shown in Fig. 18. (32) A pattern of a first conducting layer is formed, and the process for forming the pattern of the first conducting layer and the structure of the first conducting layer are essentially the same as shown in Fig. 19A and Fig. 19B. (33) A pattern of a second conductive layer is formed, and the process for forming the pattern of the second conductive layer and the structure of the second conductive layer are essentially the same as shown in Fig. 20A and Fig. 20B. (34) A pattern of a fourth insulating layer is formed, and the process for forming the pattern of the fourth insulating layer and the structure of the multiple vias are essentially the same as shown in Fig. 21. (35) A pattern of a third conductive layer is formed, wherein the process for forming the third conductive layer and the structure of the third conductive layer are essentially the same as shown in Fig. 22A and Fig. 22B, except that the third conductive layer is additionally provided with a third connecting line 83, as shown in Fig. 28A and Fig. 28B, and Fig. 28B is a schematic top view of the third conductive layer in Fig. 28A. In an exemplary embodiment, the third conductive layer in each circuit unit can comprise at least a first initial signal line 31, a first connecting electrode 41, a second connecting electrode 42, a third connecting electrode 43, a fourth connecting electrode 44, a sixth connecting electrode 46, a seventh connecting electrode 47, an eighth connecting electrode 48, a ninth connecting electrode 49, a third connecting line 83 and a light emission signal line 93, and the structures of the first initial signal line 31, the light emission signal line 93, the first connecting electrode 41 to the fourth connecting electrode 44 and the sixth connecting electrode 46 to the ninth connecting electrode 49 are essentially the same as those of the preceding embodiments. In an exemplary embodiment, the third connecting line 83 can have the form of a straight line or a bending line extending along the first direction X, the third connecting line 83 can be arranged between the first scanning signal line 21 and the light emission signal line 93, and the third connecting line 83 is configured to be connected to a second power supply line subsequently formed. In an exemplary embodiment, one side of the third connecting line 83, which is located near the first sampling signal line 21, is connected to a second power supply connection block 83-1, wherein the second power supply connection block 83-1 can be in the form of a block (e.g., a rectangle) and is configured to be connected to the second power supply line to be formed subsequently. In an exemplary embodiment, the second power supply connection block 83-1 can be provided in the circuit units of the (N+1)th unit column and the (N+3)th unit column. In an exemplary embodiment, an orthographic projection of the third connecting line 83 onto the base substrate is at least partially overlapped with an orthographic projection of the second plate 72 onto the base substrate, and the orthographic projection of the third connecting line 83 onto the base substrate is not overlapped with orthographic projections of the first connecting electrode 41 and the second connecting electrode 42 onto the base substrate. (36) A pattern of a first planarization layer is formed. In an exemplary embodiment, forming the pattern of the first planarization layer may include depositing a first planarization thin film onto the base substrate on which the above-mentioned patterns are formed, and structuring the first planarization thin film by a structuring process to form a first planarization layer covering the third conductive layer, wherein the first planarization layer is provided with a plurality of vias, as shown in Fig. 29. In an exemplary embodiment, the multiple vias on the first planarization layer comprise at least a twenty-first via V21, a twenty-second via V22, a twenty-third via V23, a twenty-fourth via V24, a twenty-fifth via V25, a twenty-sixth via V26, a twenty-seventh via V27 and a twenty-eighth via V28. In an exemplary embodiment, an orthographic projection of the twenty-first via V21 on the base substrate lies within a region of an orthographic projection of the first power supply interconnect block 42-1 on the base substrate, wherein the first planarization layer within the twenty-first via V21 is removed to expose a surface of the first power supply interconnect block 42-1, and the twenty-first via V21 is configured such that the subsequent first power supply line is connected to a first power supply interconnect block 42-1 via the twenty-first via V21. In an exemplary embodiment, the twenty-first via V21 can be provided in each circuit unit. In an exemplary embodiment, an orthographic projection of the twenty-first via V21 on the base substrate can lie within an area of ​​an orthographic projection of the second plate 72 on the base substrate. In an exemplary embodiment, an orthographic projection of the twenty-second via 22 on the base substrate lies within an area of ​​an orthographic projection of the third interconnect electrode 43 on the base substrate. The first planarization layer within the twenty-second via V22 is removed to expose a surface of the third interconnect electrode 43, and the twenty-second via V22 is configured such that a data signal line to be subsequently formed is connected to the third interconnect electrode 43 via the twenty-second via V22. In an exemplary embodiment, the twenty-second via V22 can be provided in each circuit unit. In an exemplary embodiment, an orthographic projection of the twenty-third via V23 on the base substrate lies within an area of ​​an orthographic projection of the fourth interconnect electrode 44 on the base substrate. The first planarization layer within the twenty-third via V23 is removed to expose a surface of the fourth interconnect electrode 44, and the twenty-third via V23 is configured such that a subsequently formed anode interconnect electrode is connected to the fourth interconnect electrode 44 via the twenty-third via V23. In an exemplary embodiment, the twenty-third via V23 can be provided in each circuit unit. In an exemplary embodiment, an orthographic projection of the twenty-fourth via V24 on the base substrate lies within a region of an orthographic projection of the eighth interconnect electrode 48 on the base substrate. The first planarization layer within the twenty-fourth via V24 is removed to expose a surface of the eighth interconnect electrode 48, and the twenty-fourth via V24 is configured such that a subsequent first interconnect is connected to the eighth interconnect electrode 48 via the twenty-fourth via V24. In an exemplary embodiment, the twenty-fourth via V24 can be provided in the circuit units of the (N+2)th unit column. In an exemplary embodiment, an orthographic projection of the twenty-fifth via V25 on the base substrate lies within an area of ​​an orthographic projection of the initial interconnect block 46-1 on the base substrate. The first planarization layer within the twenty-fifth via V25 is removed to expose a surface of the initial interconnect block 46-1, and the twenty-fifth via V25 is configured such that the second interconnect to be formed subsequently is connected to the initial interconnect block 46-1 via the twenty-fifth via V25. In an exemplary embodiment, the twenty-fifth via V25 can be provided in the circuit units of the Nth unit column. In an exemplary embodiment, an orthographic projection of the twenty-sixth via V26 on the base substrate lies within an area of ​​an orthographic projection of the light emission interconnect block 93-1 of the light emission signal line 93 on the base substrate. The first planarization layer within the twenty-sixth via V26 is removed to expose a surface of the light emission interconnect block 93-1, and the twenty-sixth via V26 is configured such that a subsequently formed light emission signal interconnect line is connected to the light emission interconnect block 93-1 through the twenty-sixth via V26. In an exemplary embodiment, the twenty-sixth via V26 can be provided in each circuit unit. In an exemplary embodiment, an orthographic projection of the twenty-seventh via V27 on the base substrate lies within an area of ​​an orthographic projection of the ninth interconnect electrode 49 on the base substrate. The first planarization layer within the twenty-seventh via V27 is removed to expose a surface of the ninth interconnect electrode 49, and the twenty-seventh via V27 is configured such that the subsequently formed light emission signal link is connected to the ninth interconnect electrode 49 via the twenty-seventh via V27. In an exemplary embodiment, the twenty-seventh via V27 can be provided in each circuit unit. In an exemplary embodiment, an orthographic projection of the twenty-eighth via V28 on the base substrate lies within an area of ​​an orthographic projection of the second power supply connection block 83-1 of the third connection line 83 on the base substrate. The first planarization layer within the twenty-eighth via V28 is removed to expose a surface of the second power supply connection block 83-1, and the twenty-eighth via V28 is configured such that the second power supply line to be formed subsequently is connected to the second power supply connection block 83-1 via the twenty-eighth via V28. In an exemplary embodiment, the twenty-eighth via V28 can be provided in the circuit units of the (N+1)th unit column and the (N+3)th unit column. (37) A pattern of a fourth conductive layer is formed. In an exemplary embodiment, the formation of the pattern of the fourth conductive layer may comprise: depositing a fourth conductive thin film onto the base substrate on which the aforementioned patterns are formed, and structuring the fourth conductive thin film by a structuring process to form the fourth conductive layer arranged on the first planarized layer, as shown in Fig. 30A and Fig. 30B. Fig. 30B is a planar schematic representation of the fourth conductive layer in Fig. 30A. In an exemplary embodiment, the fourth conductive layer comprises at least one light emission signal link 56, a first power supply link 61, a data signal link 62, an anode link electrode 63, a second power supply link 64, a first link 81 and a second link 82. In an exemplary embodiment, the light emission signal link 56 can have the form of a strip extending along the second direction Y, wherein a first end of the light emission signal link 56 is connected via the twenty-sixth via V26 to the light emission connection block 93-1 of the circuit unit in the present unit series, and a second end of the light emission signal link 56 extends along the second direction Y to the circuit unit in the next unit series and is connected to a ninth connection electrode 49 of the circuit unit in the next unit series via the twenty-seventh via V27. In an exemplary embodiment, the light emission signal link 56 can be provided in each circuit unit. In an exemplary embodiment, the light emission connection block 93-1 of the circuit unit in the present unit series is connected to the light emission signal line 93 in the present unit series, and a ninth connection electrode 49 of the circuit unit in the next unit series is connected to the fifth gate electrode 25 of this circuit unit. The light emission signal connection line 56 thus realizes a connection between the light emission signal line 93 in the current unit series and the fifth gate electrode 25 in the next unit series, so that the light emission signal line 93 in the current unit series can control not only the switching on and off of the sixth transistor T6 in the current unit series, but also the switching on and off of a fifth transistor T5 in the next unit series., in the circuit unit of the current unit series, the fifth transistor T5 is controlled by a light emission signal line 93 of the previous unit series, and the sixth transistor T6 is controlled by the light emission signal line 93 of the current unit series. In an exemplary embodiment, the first power supply line 61 can have the form of a straight line or a curved line extending along the second direction Y, and the first power supply line 61 is connected to the first power supply connection block 42-1 via the twenty-first via V21. Since the first power supply connection block 42-1 is connected to the second connection electrode 42, and the second connection electrode 42 is connected to the first electrode of the fifth transistor T5, the second plate 72 of the storage capacitor, and the fourth electrode 74 of the first capacitor, the first power supply line 61 can transmit the first power supply signal to the first electrode of the fifth transistor T5, the second plate 72 of the storage capacitor, and the fourth plate 74 of the first capacitor.In an exemplary embodiment, the first power supply line 61 can be provided in each circuit unit. In an exemplary embodiment, the data signal line 62 can have the form of a straight line or a curved line extending along the second direction Y, and the data signal line 62 is connected to the third connection electrode 43 via the twenty-second via V22. Since the third connection electrode 43 is connected to the first region of the fourth active layer, the connection of the data signal line 62 to the first electrode of the fourth transistor T4 is realized, so that the data signal line 62 can write a data signal to the first electrode of the fourth transistor T4. In an exemplary embodiment, the data signal line 62 can be provided in each circuit unit. In an exemplary embodiment, the anode connection electrode 63 can have the form of a strip extending along the first direction X or the second direction Y, wherein the anode connection electrode 63 is connected to the fourth connection electrode 44 via the twenty-third via V23 and the anode connection electrode 63 is configured to be connected to the anode to be formed subsequently. Since the fourth connection electrode 44 is connected to the second region of the sixth active layer and a second region of the seventh active layer, a connection can be established between the anode to be formed subsequently and the second electrode of the sixth transistor T6 as well as the second electrode of the seventh transistor T7, and the pixel driver circuit can control the light-emitting device to emit light.In an exemplary embodiment, the anode connection electrode 63 can be provided in each circuit unit. In an exemplary embodiment, the second power supply line 64 can have the form of a straight line or a curved line extending along the second direction Y, and the second power supply line 64 is connected to the second power supply connection block 83-1 via the twenty-eighth via V28. Since the second power supply connection block 83-1 is connected to the third connection line 83, a connection is established between the third connection line 83, whose main body extends along the first direction X, and the second power supply line 64, whose main body extends along the second direction Y, forming a network-like connection structure on the display substrate. In an exemplary embodiment, the second power supply line 64 can be provided in the circuit units of the (N+1)th unit column and the (N+3)th unit column. In an exemplary embodiment, an orthographic projection of the second power supply line 64 on the base substrate does not overlap with an orthographic projection of the gate electrode of the third transistor (i.e., the first plate) on the base substrate. In an exemplary embodiment, an orthographic projection of the second power supply line 64 on the base substrate and an orthographic projection of the active interconnect line 18 in the semiconductor layer, which connects the second active layer and the third active layer on the base substrate, do not overlap, at least partially. In an exemplary embodiment, the first connecting line 81 can have the form of a straight line or a curved line extending along the second direction Y, and the first connecting line 81 is connected to the eighth connecting electrode 48 via the twenty-fourth via V24. Since the eighth connecting electrode 48 is connected to the first initial signal line 31, a connection is established between the first initial signal line 31, whose main body part extends along the first direction X, and the first connecting line 81, whose main body part extends along the second direction Y, and a network-like interconnect structure is formed on the display substrate. In an exemplary embodiment, the first connecting line 81 can be provided in the circuit units of the (N+2)th unit column. In an exemplary embodiment, an orthographic projection of the first connecting line 81 on the base substrate does not overlap an orthographic projection of the gate electrode of the third transistor (i.e., the first plate) on the base substrate. In an exemplary embodiment, an orthographic projection of the first connecting line 81 on the base substrate and an orthographic projection of the active connecting line 18 in the semiconductor layer, which connects the second active layer and the third active layer on the base substrate, do not overlap, at least partially. In an exemplary embodiment, the second connecting line 82 can have the form of a straight line or a curved line extending along the second direction Y, and the second connecting line 82 is connected to the first connecting block 46-1 via the twenty-fifth via V25. Since the first connecting block 46-1 is connected to the sixth connecting electrode 46, the first connecting block 46-1 is connected to the sixth connecting electrode 46 via the twenty-fifth via, and the sixth connecting electrode 46 is connected to the second initial signal line 32, thereby establishing the connection between the second initial signal line 32, whose main body part extends along the first direction X, and the second connecting line 82, whose main body part extends along the second direction Y, and forming a network-like interconnect structure on the display substrate.In an exemplary embodiment, the second connecting line 82 can be provided in the circuit units of the Nth unit column. In an exemplary embodiment, an orthographic projection of the second connecting line 82 on the base substrate does not overlap with an orthographic projection of the gate electrode of the third transistor (i.e., the first plate) on the base substrate. In an exemplary embodiment, the orthographic projection of the second connecting line 82 on the base substrate and an orthographic projection of the active connecting line 18 in the semiconductor layer, which connects the second active layer and the third active layer on the base substrate, do not overlap, at least partially. Figures 30C and 30D are schematic representations of a further network-like connection structure for an initial signal and a network-like connection structure for a second power supply according to an exemplary embodiment of the present disclosure. As shown in Figure 30C, the first initial signal line 31, the second initial signal line 32, and the third connection line 83 can be provided in each unit row, and the first connection line 81, the second power supply line 64, the second connection line 82, and the second power supply line 64 can be provided alternately in four successive unit columns.For example, the Nth unit column can be provided with a second connecting line 82, the (N+1)th unit column can be provided with a second power supply line 64, the (N+2)th unit column can be provided with a first connecting line 81, and the (N+3)th unit column can be provided with a second power supply line 64. As shown in Fig. 30D, the first initial signal line 31, the second initial signal line 32, and the third connecting line 83 can be provided in each unit row, and the first connecting line 81, the second power supply line 64, the second connecting line 82, and the second power supply line 64 can be provided alternately in eight consecutive unit columns.For example, the Nth unit column may be provided with a second connecting line 82, the (N+2)th unit column may be provided with a second power supply line 64, the (N+4)th unit column may be provided with a first connecting line 81, the (N+5)th unit t may be provided with a second power supply line 64, and the (N+1)th unit, the (N+3)th unit, the (N+5)th unit, the (N+7)th unit t may be provided with a first connecting line, a second connecting line, and a second power supply line, which is not limited in the present disclosure. (38) A pattern of a second planarization layer is formed. In an exemplary embodiment, the formation of the pattern of the second planarization layer may comprise: depositing a second planarization thin film onto the base substrate on which the above-mentioned patterns are formed, structuring the second planarization thin film by a structuring process, forming a second planarization layer covering the fourth conductive layer, wherein the second planarization layer is provided with a plurality of anode vias and an anode via is configured such that the anode to be formed subsequently is connected to the anode junction electrode via the vias. In an exemplary embodiment, after the production of the driver circuit layer, a light emission structure layer is first produced on the driver circuit layer and then an encapsulation structure layer is formed, which is not repeated here. The display substrate provided in the present embodiment also enables separate control of the fifth and sixth transistors and can implement pulse-width modulation with higher accuracy at an ultra-high frequency, compensation of the optical emission signal duty cycle, compensation of low grayscale values, and improved image retention. In at least one circuit unit of the present embodiment, the sixth transistor T6 is controlled by the optical emission signal line of the present unit series, and the fifth transistor T5 is controlled by an optical emission signal line of the previous unit series.The fifth transistor T5 assumes the (cascaded) mode in which it is driven by the light emission signal line of the sixth transistor T6 of a previous stage, which not only reduces the capacitance of the first node N1 and prevents the first node N1 from being influenced by the light emission signal line, but also reduces the number of light emission signal lines, which is advantageous for achieving high resolution. The display substrate of the present embodiment uses a 2SD mode and adds a first capacitor and forms a net-like interconnect structure for a second power supply signal, a net-like interconnect structure for a first initial signal and a net-like interconnect structure for a second initial signal on the display substrate, thereby further improving the display effect. Figures 31A and 31B are schematic representations of a further display substrate after the formation of a pattern of an anode-conducting layer according to the present disclosure, and Figure 31B is a schematic top view of the anode-conducting layer in Figure 31A. In the display substrate of the foregoing embodiments, since the dummy pad is provided in the third or fourth conductive layer, the consistency of the layer layers in each subpixel can be ensured by providing auxiliary electrodes in the anode-conducting layer. In an exemplary embodiment, taking as an example the display substrate shown in Fig. 17, the anode-conducting layer can comprise a plurality of anodes 90, each anode 90 being connected via an anode through-hole to an anode connection electrode of a corresponding circuit unit, and at least one anode 90 being provided with an auxiliary electrode 90A. A first end of the auxiliary electrode 90A is connected to the at least one anode 90, a second end of the auxiliary electrode 90A extends away from the at least one anode 90, and an orthographic projection of the auxiliary electrode 90A onto the base substrate at least partially overlaps an orthographic projection of the fourteenth connection electrode as a dummy pad on the base substrate, as shown in Figs. 31A and 31B. In Figs. 31A and 31B, theThis is illustrated in Figure 31B by an example in which an anode 90 is provided with an auxiliary electrode 90A. In fact, auxiliary electrodes 90A can each be provided on several anodes 90, and several auxiliary electrodes 90A can each overlap at least partially with several dummy pads, or several auxiliary electrodes 90A can be provided on one anode 90, which is not limited in the present disclosure. In the present disclosure, providing an auxiliary electrode on at least one anode can ensure the consistency of the layers in each subpixel and reduce visualization errors. In an exemplary embodiment, the anode 90 and the auxiliary electrode 90A can have an interconnected integral structure. Fig. 32 is a schematic diagram of another display substrate after the formation of a pattern of a pixel definition layer according to the present disclosure. As shown in Fig. 32, the pixel definition layer can comprise several pixel openings K, each of which can expose a surface of the anode, and at least one pixel opening K can be connected to a sub-opening K1, which can expose a surface of the auxiliary electrode. In an exemplary embodiment, a pixel aperture K and a sub-aperture K1 can be connected to each other. Figures 33A and 33B are schematic representations of a further display substrate after the formation of a pattern of an anode-conducting layer according to the present disclosure, and Figure 33B is a schematic top view of the anode-conducting layer in Figure 33A. The structure of the anode-conducting layer of the present embodiment is essentially the same as that shown in Figures 31A and 31B, except that the auxiliary electrode 90A is provided separately, i.e., the anode 90 is not connected to the auxiliary electrode 90A. In an exemplary embodiment, taking the display substrate shown in Fig. 17 as an example, the anode-conducting layer can comprise a plurality of anodes 90 and at least one auxiliary electrode 90A. Each anode 90 can be connected via an anode through-hole to an anode connection electrode of a corresponding circuit unit. An orthographic projection of the auxiliary electrode 90A onto the base substrate is at least partially overlapped with an orthographic projection of the fourteenth connection electrode as a dummy pad on the base substrate, as shown in Figs. 33A and 33B. In Figs. 33A and 33B, this is illustrated only by way of an example in which the anode-conducting layer is provided with an auxiliary electrode 90A.In fact, the anode-conducting layer can be provided with multiple auxiliary electrodes 90A, wherein the multiple auxiliary electrodes 90A are at least partially overlapped with multiple dummy pads and the auxiliary electrodes 90A can be provided in a floating state. During the subsequent formation of the pixel definition layer, no undercut is provided at the position where the auxiliary electrode 90A is located, which is not limited in the present disclosure. In the present disclosure, by providing at least one auxiliary electrode in the anode-conducting layer, the consistency of the layers in each subpixel can be ensured and visualization errors reduced. In an exemplary embodiment, the provision of an auxiliary electrode in the anode-conducting layer in the structure of the display substrate shown in Fig. 5 and Fig. 27 can be applied, which is not limited in the present disclosure. The structure and manufacturing process shown above in this disclosure are merely exemplary descriptions. In an exemplary embodiment, corresponding structures can be modified and structuring processes added or reduced according to the actual requirements, which is not limited in this disclosure. In an exemplary embodiment, the display substrate according to the present disclosure can be applied to a display device with a pixel driver circuit, such as an OLED, a quantum dot display (QLED), a light-emitting diode display (micro-LED or mini-LED) or a quantum dot light-emitting diode display (QDLED), which are not limited in the present disclosure. The present disclosure further provides a display device comprising the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, or a navigation device, which are not limited in the embodiments of the present disclosure. Although the embodiments disclosed in this disclosure are as described above, it should be noted that the embodiments mentioned above are only exemplary and not limiting. Therefore, this disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions may be made in the form and details of the embodiments without altering the scope of this disclosure.

Claims

Display substrate comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, wherein at least one circuit unit comprises a pixel driver circuit and at least one control line configured to supply a light emission control signal to the pixel driver circuit; in at least one circuit unit, the pixel driver circuit comprises at least one driver transistor, a first light emission control transistor, and a second light emission control transistor, wherein a first electrode of the first light emission control transistor is connected to a first power supply line, a second electrode of the first light emission control transistor is connected to a first electrode of the driver transistor, and a first electrode of the second light emission control transistor is connected to a second electrode of the driver transistor;the first light emission control transistor and the second light emission control transistor are connected to different control lines, and the first light emission control transistor and the second light emission control transistor are each arranged on opposite sides of the driver transistor in a unit column direction. Display substrate according to claim 1, wherein the at least one control line comprises a first signal line and a second signal line, and the first light emission control transistor is connected to the first signal line, and the second light emission control transistor is connected to the second signal line, and the first signal line and the second signal line are each arranged on two sides of the driver transistor in the unit column direction. Display substrate according to claim 2, wherein the display substrate comprises a plurality of conductive layers in a direction perpendicular to the display substrate, and the first signal line and the second signal line are arranged in different conductive layers. Display substrate according to claim 3, wherein the second light emission control transistor comprises at least one second gate, the second gate and the first signal line are arranged in the same conductive layer, and the second gate and the second signal line are arranged in different conductive layers. Display substrate according to claim 2, wherein the pixel driver circuit further comprises a compensation transistor, wherein a gate electrode of the compensation transistor is connected to a first sampling signal line, a first electrode of the compensation transistor is connected to a gate electrode of the driver transistor via a first connecting electrode, and a second electrode of the compensation transistor is connected to the second electrode of the driver transistor.is connected to the first electrode of the second light emission control transistor; an orthographic projection of the first connecting electrode on a plane of the display substrate overlaps at least partially with an orthographic projection of the first signal line on the plane of the display substrate, and the orthographic projection of the first connecting electrode on the plane of the display substrate overlaps at least partially with an orthographic projection of the first sampling signal line on the plane of the display substrate. Display substrate according to claim 5, wherein the compensation transistor comprises at least one compensation active layer, the second light emission control transistor comprises at least one second light emission control active layer, and a second region of the compensation active layer is connected to a first region of the second light emission control active layer via a fifth connecting electrode; in a direction perpendicular to the display substrate, the display substrate comprises at least one semiconductor layer and at least one conductive layer, wherein the compensation active layer and the second light emission control active layer are arranged in the semiconductor layer, and the fifth connecting electrode is arranged in the conductive layer. Display substrate according to claim 5, wherein the pixel driver circuit further comprises a data write transistor, wherein a first electrode of the data write transistor is connected to a data signal line, a second electrode of the data write transistor is connected to the first electrode of the driver transistor, and the data write transistor and the compensation transistor are each arranged on two sides of the driver transistor in the unit column direction. Display substrate according to claim 1, wherein the at least one control line comprises a light emission signal line, the light emission signal line is connected to a second light emission control transistor in a current unit row, and the light emission signal line is connected to a first light emission control transistor in a next unit row. Display substrate according to claim 8, wherein the first light emission control transistor comprises at least one first gate, the second light emission control transistor comprises at least one second gate, the light emission signal line is connected to the second gate of the first light emission control transistor in the current unit row, and the light emission signal line is connected to the first light emission control transistor in the next unit row via a light emission signal link line. Display substrate according to claim 9, wherein in a direction perpendicular to the display substrate the display substrate comprises a plurality of conductive layers, the first gate of the first light emission control transistor and the second gate of the second light emission control transistor are arranged in the same conductive layer, the first gate and the light emission signal line are arranged in different conductive layers, the first gate and the light emission signal link line are arranged in different conductive layers, and the light emission signal link line and the light emission signal line are arranged in different conductive layers. Display substrate according to claim 10, wherein the plurality of conductive layers comprises at least a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer, which are arranged successively on a base substrate along a direction remote from the base substrate, wherein the first gate and the second gate are arranged in the first conductive layer, the light emission signal line is arranged in the third conductive layer, the light emission signal line is connected to the second gate via a via, the light emission signal link line is arranged in the fourth conductive layer, a first end of the light emission signal link line is connected to the light emission signal line in the current unit row via a via,and a second end of the light emission signal link is connected via a through-hole to the first gate in the next unit row. Display substrate according to claim 11, wherein the plurality of conductive layers further comprises a fifth conductive layer arranged on a side of the fourth conductive layer furthest from the base substrate, the first power supply line arranged in the fifth conductive layer, and an orthographic projection of the first power supply line on a plane of the display substrate overlaps at least partially with an orthographic projection of the light emission signal link line on the plane of the display substrate. Display substrate according to one of claims 1 to 12, wherein the at least one circuit unit further comprises a first initial signal line extending along a pixel row direction and a first connecting line extending along a pixel column direction, wherein the first initial signal line is configured to supply a first initial signal to the pixel driver circuit, wherein the first initial signal line and the first connecting line are connected to each other to form a net-like interconnect structure for transmitting the first initial signal. Display substrate according to claim 13, wherein an orthographic projection of the first connecting line on a plane of the display substrate does not overlap with an orthographic projection of a gate electrode of the driver transistor on the plane of the display substrate. Display substrate according to claim 13, wherein the pixel driver circuit further comprises a compensation transistor, wherein an active layer of the compensation transistor and an active layer of the driver transistor are connected to each other by an active connecting line, wherein an orthographic projection of the first connecting line on the plane of the display substrate does not overlap at least partially with an orthographic projection of the active connecting line on the plane of the display substrate. Display substrate according to one of claims 1 to 12, wherein the at least one circuit unit further comprises a second initial signal line extending along a pixel row direction and a second connecting line extending along a pixel column direction, wherein the second initial signal line is configured to supply a second initial signal to the pixel driver circuit, wherein the second initial signal line and the second connecting line are connected to each other to form a net-like interconnect structure for transmitting the second initial signal. Display substrate according to claim 16, wherein an orthographic projection of the second connecting line on a plane of the display substrate does not overlap with an orthographic projection of a gate electrode of the driver transistor on the plane of the display substrate. Display substrate according to claim 16, wherein the pixel driver circuit further comprises a compensation transistor, wherein an active layer of the compensation transistor and an active layer of the driver transistor are connected to each other by an active connecting line, wherein an orthographic projection of the second connecting line on a plane of the display substrate does not at least partially overlap with an orthographic projection of the active connecting line on the plane of the display substrate. Display substrate according to one of claims 1 to 12, wherein the at least one circuit unit further comprises a third connecting line extending along a pixel row direction and a second power supply line extending along a pixel column direction, and the second power supply line and the third connecting line are connected to each other to form a net-like interconnect structure for transmitting a second power supply signal. Display substrate according to claim 19, wherein an orthographic projection of the second power supply line on a plane of the display substrate does not overlap with an orthographic projection of a gate electrode of the driver transistor on the plane of the display substrate. Display substrate according to claim 19, wherein the pixel driver circuit further comprises a compensation transistor, wherein an active layer of the compensation transistor and an active layer of the driver transistor are connected to each other by an active connecting line, and an orthographic projection of the second power supply line on a plane of the display substrate does not at least partially overlap with an orthographic projection of the active connecting line on the plane of the display substrate. Display substrate according to any one of claims 1 to 12, wherein the pixel driver circuit further comprises a storage capacitor and a first capacitor; the storage capacitor comprises a first plate and a second plate, an orthographic projection of the first plate on a plane of the display substrate overlaps at least partially with an orthographic projection of the second plate on the plane of the display substrate, the first plate serves as the gate electrode of the driver transistor, and the second plate is connected to the first power supply line;the first capacitor comprises a third plate and a fourth plate, wherein an orthographic projection of the third plate on the plane of the display substrate overlaps at least partially with an orthographic projection of the fourth plate on the plane of the display substrate, the third plate being connected to the first electrode of the driver transistor and the second electrode of the first light emission control transistor respectively, and the fourth plate being connected to the first power supply line. Display substrate according to claim 22, wherein in a direction perpendicular to the display substrate the display substrate comprises at least one semiconductor layer, a first conductive layer and a second conductive layer, which are arranged successively on the base substrate along a direction away from the base substrate, wherein the third plate is arranged in the semiconductor layer, the first plate is arranged in the first conductive layer, and the second plate and the fourth plate are arranged in the second conductive layer. Display device comprising a display substrate according to any one of claims 1 to 23.

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