Display substrate and display device

Abstract

The present disclosure relates to a display substrate and a display device. The display substrate comprises a base substrate and at least three functional layers, at least two first matching layers, and a target connection element arranged on the base substrate. At least two of the at least three functional layers are laminated one above the other in a direction away from the base substrate, wherein the at least three functional layers include a target functional layer, and the target functional layer is a functional layer of the at least three functional layers that is furthest from the base substrate.The at least two first adaptation layers comprise an upper adaptation layer and at least one lower adaptation layer, wherein the upper adaptation layer is arranged on one side of the objective function layer away from the base substrate and is coupled to the target connection element and the objective function layer, and at least a part of the lower adaptation layer is arranged between the objective function layer and the base substrate and is coupled to the objective function layer and at least one non-objective function layer of the at least three functional layers.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] In recent years, with the increasing pixel density of display products such as augmented reality (AR) and virtual reality (VR), the area of ​​individual pixels has become increasingly smaller, placing increasingly stringent demands on layout design and process capabilities. In particular, for complex processes such as low-temperature polycrystalline oxide (LTPO) and stacked thin-film transistor (TFT) fabrication, the reduced pixel area compresses the space for metal traces during layout design, creating short circuits and impacting product resolution. Furthermore, multiple vias are required for electrical connections between metal, metal, active layers, or both. This increase in the number of vias increases the width of the metal traces connecting these vias, further impacting display resolution. Therefore, the display panel industry is increasingly focused on optimizing layout design and process capabilities to reduce metal trace density or the number of vias, thereby further improving display resolution.

[0003] Summary of the Invention

[0004] An object of the present disclosure is to provide a display substrate and a display device.

[0005] In order to achieve the above objectives, the present disclosure provides the following technical solutions:

[0006] A first aspect of the present disclosure provides a display substrate, comprising: a base substrate, and at least three functional layers, at least two first transfer layers, and a target connection portion, all disposed on the base substrate;

[0007] At least two of the at least three functional layers are stacked in sequence in a direction away from the base substrate, the at least three functional layers include a target functional layer, and the target functional layer is the functional layer farthest from the base substrate among the at least three functional layers;

[0008] The at least two first switching layers include: a top switching layer and at least one bottom switching layer;

[0009] The top transfer layer is located on a side of the target functional layer facing away from the base substrate, and the top transfer layer is coupled to the target connection portion and the target functional layer respectively;

[0010] At least a portion of the bottom transfer layer is located between the target functional layer and the base substrate, and the bottom transfer layer is respectively coupled to the target functional layer and at least one non-target functional layer of the at least three functional layers.

[0011] Optionally, the at least three functional layers also include a first functional layer and a second functional layer; at least a portion of the first functional layer is located between the base substrate and the second functional layer; the at least two first transfer layers include one bottom transfer layer; the bottom transfer layer is coupled to the first functional layer and the second functional layer, respectively.

[0012] Optionally, the first functional layer includes a protruding portion, and an orthographic projection of the protruding portion on the base substrate does not overlap with an orthographic projection of the second functional layer on the base substrate;

[0013] The display substrate includes a first set of holes, and the bottom transfer layer is coupled to the first functional layer and the second functional layer respectively through the first set of holes; the target functional layer is directly overlapped with the portion of the bottom transfer layer located outside the first set of holes.

[0014] Optionally, the first set of holes includes a first sub-via and a second sub-via that are interconnected, the first sub-via is located between the second sub-via and the base substrate, the aperture of the second sub-via is larger than the aperture of the first sub-via, the bottom transfer layer is coupled to the second functional layer through the second sub-via, and the bottom transfer layer is coupled to the first functional layer through the second sub-via and the first sub-via.

[0015] Optionally, the target functional layer includes a first sub-target functional layer and a second sub-target functional layer that are stacked, the first sub-target functional layer is located between the second sub-target functional layer and the substrate, and the carrier mobility of the first sub-target functional layer is greater than the carrier mobility of the second sub-target functional layer;

[0016] The first sub-target functional layer is directly overlapped with a portion of the bottom switching layer located outside the first hole.

[0017] Optionally, the top switching layer is also directly coupled to the bottom switching layer.

[0018] Optionally, the display substrate also includes a second set of holes, the second set of holes also includes a third sub-via and a fourth sub-via that are interconnected, the third sub-via is located between the fourth sub-via and the base substrate, the aperture of the fourth sub-via is larger than the aperture of the third sub-via, the top transfer layer is coupled to the target functional layer through the fourth sub-via, and the top transfer layer is coupled to the bottom transfer layer through the fourth sub-via and the third sub-via.

[0019] Optionally, the display substrate includes a first source-drain metal layer, and the top transfer layer is provided in the same layer and with the same material as the first source-drain metal layer.

[0020] Optionally, the display substrate includes a plurality of sub-pixels disposed on the base substrate, the sub-pixels including a sub-pixel driving circuit and a light-emitting element, the sub-pixel driving circuit including a driving transistor, a sensing transistor, and a storage capacitor; a first plate of the storage capacitor is coupled to a gate of the driving transistor, and a second plate of the storage capacitor is coupled to a second electrode of the driving transistor, a second electrode of the sensing transistor, and an anode of the light-emitting element, respectively;

[0021] The first functional layer includes the active layer in the driving transistor, the second functional layer includes the second plate of the storage capacitor, the target functional layer includes the sensing active layer in the sensing transistor, and the target connection portion includes the anode of the light-emitting element.

[0022] Optionally, when the target functional layer includes a first sub-target functional layer and a second sub-target functional layer that are stacked, both the first sub-target functional layer and the second sub-target functional layer are made of transparent metal oxide material.

[0023] Optionally, the display substrate further includes a data line; the sub-pixel driving circuit further includes a data writing transistor, a first electrode of the data writing transistor is coupled to the corresponding data line, and a second electrode of the data writing transistor is coupled to the gate of the driving transistor;

[0024] The data writing transistor includes a data writing active layer, and the data line is located on a side of the data writing active layer facing the base substrate.

[0025] Optionally, the display substrate further includes a light shielding layer, and the light shielding layer is located on a side of the data line facing the base substrate.

[0026] Optionally, the display substrate further includes a sensing signal line, a second transfer layer, and a compensation signal line; the first electrode of the sensing transistor is coupled to the corresponding sensing signal line; the sensing signal line is coupled to the corresponding compensation signal line through the corresponding second transfer layer;

[0027] The compensation signal line and the light shielding layer are provided in the same layer and made of the same material, and at least a portion of the second transfer layer is located between the sensing signal line and the compensation signal line.

[0028] Optionally, the display substrate further includes a light shielding layer, and the data line is located on a side of the light shielding layer facing the base substrate.

[0029] Optionally, the display substrate further includes a light shielding layer, and the data line and the light shielding layer are provided in the same layer and with the same material.

[0030] Optionally, the display substrate also includes a second gate metal layer; the sub-pixel driving circuit also includes a third transfer layer, and the third transfer layer is coupled to the part of the data writing active layer serving as the first electrode of the data writing transistor, and the data line respectively; the third transfer layer is set in the same layer and material as the second gate metal layer.

[0031] Optionally, the display substrate further includes a fourth transfer layer, which is respectively coupled to a portion of the data writing active layer serving as the second electrode of the data writing transistor and the gate of the driving transistor; the fourth transfer layer is arranged in the same layer and material as the bottom transfer layer.

[0032] Optionally, the display substrate further includes a third gate insulating layer;

[0033] The sensing active layer includes a sensing channel portion and a sensing conductor portion, the sensing conductor portion is used to serve as the first electrode and the second electrode of the sensing transistor, and at least a portion of the third gate insulating layer is located between the gate of the sensing transistor and the sensing channel portion; the orthographic projection of the third gate insulating layer on the base substrate does not overlap with the orthographic projection of the sensing conductor portion on the base substrate.

[0034] Optionally, the display substrate further includes a third gate insulating layer;

[0035] The sensing active layer includes a sensing channel portion and a sensing conductor portion, the sensing conductor portion is used to serve as the first electrode and the second electrode of the sensing transistor, and at least a portion of the third gate insulating layer is located between the gate of the sensing transistor and the sensing channel portion; the orthographic projection of the third gate insulating layer on the base substrate covers the orthographic projection of the sensing conductor portion on the base substrate.

[0036] Based on the technical solution of the above-mentioned display substrate, a second aspect of the present disclosure provides a display device including the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0038] FIG1 is a schematic diagram of a circuit structure of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0039] FIG2 is a driving timing diagram of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0040] FIG3 is a first cross-sectional schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0041] FIG4 is a second cross-sectional schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0042] FIG5 is a schematic diagram showing the connection between the oxide active layer and the first source / drain metal layer according to an embodiment of the present disclosure;

[0043] FIG6 is an enlarged schematic diagram of the top transfer layer and the bottom transfer layer in FIG4 ;

[0044] FIG7 is a third cross-sectional schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0045] FIG8 is a fourth cross-sectional schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0046] FIG9 is an enlarged schematic diagram of the top transfer layer and the bottom transfer layer in FIG8 ;

[0047] FIG10 is a fifth cross-sectional schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0048] 11 to 15 are schematic diagrams of a manufacturing process of a display substrate provided by an embodiment of the present disclosure;

[0049] FIG16 is a sixth cross-sectional schematic diagram of the display substrate provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] In order to further illustrate the display substrate and the display device provided by the embodiments of the present disclosure, a detailed description is given below with reference to the accompanying drawings.

[0051] Based on analysis of background technology, the display panel industry is increasingly focused on optimizing layout design and process to reduce metal trace density or the number of vias, thereby lowering layout complexity while further improving the resolution of display products. To address this, the present disclosure provides the following technical solutions.

[0052] Referring to FIG. 4 , an embodiment of the present disclosure provides a display substrate, comprising: a base substrate 10 , and at least three functional layers, at least two first transfer layers, and a target connection portion 20 , all disposed on the base substrate 10 ;

[0053] At least two of the at least three functional layers are stacked in sequence in a direction away from the base substrate 10 , and the at least three functional layers include a target functional layer 33 , which is the functional layer farthest from the base substrate 10 among the at least three functional layers;

[0054] The at least two first transfer layers include: a top transfer layer 42 and at least one bottom transfer layer 41;

[0055] The top transfer layer 42 is located on a side of the target functional layer 33 facing away from the base substrate 10 , and the top transfer layer 42 is coupled to the target connection portion 20 and the target functional layer 33 respectively;

[0056] At least a portion of the bottom transfer layer 41 is located between the target functional layer 33 and the base substrate 10, and the bottom transfer layer 41 is coupled to the target functional layer 33 and at least one non-target functional layer (such as the first functional layer 31 and the second functional layer 32) of the at least three functional layers.

[0057] Exemplarily, the display substrate includes a display area and a peripheral area located around the display area. The display area includes a plurality of sub-pixels distributed in an array and a plurality of different types of signal lines. The peripheral area may include a gate driver circuit and a plurality of different types of signal lines. The peripheral area may also include other circuit structures. The peripheral area may also not include a gate driver circuit.

[0058] Exemplarily, the display area includes the at least three functional layers, the at least two first transfer layers and the target connection portion 20; and / or the peripheral area includes the at least three functional layers, the at least two first transfer layers and the target connection portion 20.

[0059] For example, the at least three functional layers are stacked in sequence in a direction away from the base substrate 10, and an insulating layer may be provided between adjacent functional layers. For example, the orthographic projections of any two functional layers on the base substrate 10 may overlap or not overlap.

[0060] Exemplarily, the target connection portion 20 is located on a side of the top transfer layer 42 facing away from the base substrate 10 , but is not limited thereto.

[0061] Exemplarily, the non-target functional layer includes the remaining film layers of the at least three functional layers except the target functional layer 33 .

[0062] Exemplarily, the bottom transfer layer 41 is coupled to the target functional layer 33 and all non-target functional layers in the at least three functional layers respectively.

[0063] According to the specific structure of the display substrate described above, in the display substrate provided by the embodiment of the present disclosure, the target functional layer 33 and the non-target functional layer are first connected together through the bottom transfer layer 41, and then the target functional layer 33 and the target connection portion 20 are connected together through the top transfer layer 42. In this way, all functional layers can be coupled to the target connection portion 20 through the top transfer layer 42. Since the top transfer layer 42 only needs to be coupled with the target functional layer 33 among the functional layers, the top transfer layer 42 only needs to cover the vias between the top transfer layer 42 and the target functional layer 33, thereby reducing the number of vias between the top transfer layer 42 and the functional layer, shrinking the area of ​​the top transfer layer 42, and further improving the resolution of the display product while reducing the layout difficulty of the display substrate.

[0064] More specifically, as shown in Figure 3, another connection method is provided for comparison. In Figure 3, only one top-layer transfer layer 42 is provided, through which coupling with each functional layer is achieved. This method requires that the top-layer transfer layer 42 have a larger area so as to simultaneously cover the vias between the top-layer transfer layer 42 and each functional layer. Compared to this method, the area of ​​the top-layer transfer layer 42 in the display substrate provided by the embodiment of the present disclosure is greatly reduced, which not only reduces the layout difficulty of the film layer where the top-layer transfer layer 42 is located, but also helps to improve the resolution of the display substrate.

[0065] As shown in Figure 4, in some embodiments, the at least three functional layers also include a first functional layer 31 and a second functional layer 32; at least a portion of the first functional layer 31 is located between the base substrate 10 and the second functional layer 32; the at least two first transfer layers include a bottom transfer layer 41; the bottom transfer layer 41 is coupled to the first functional layer 31 and the second functional layer 32, respectively.

[0066] Illustratively, the orthographic projection of the first functional layer 31 on the base substrate 10 at least partially overlaps with the orthographic projection of the second functional layer 32 on the base substrate 10 .

[0067] In the display substrate provided by the above embodiment, the target functional layer 33, the first functional layer 31, and the second functional layer 32 are first connected together via the bottom transfer layer 41, and then the target functional layer 33 and the target connection portion 20 are connected together via the top transfer layer 42. In this way, all functional layers can be coupled to the target connection portion 20 via the top transfer layer 42. Since the top transfer layer 42 only needs to be coupled with the target functional layer 33 among the functional layers, the top transfer layer 42 only needs to cover the vias between the top transfer layer 42 and the target functional layer 33. This reduces the number of vias between the top transfer layer 42 and the functional layers, shrinks the area of ​​the top transfer layer 42, and further improves the resolution of the display product while reducing the layout difficulty of the display substrate.

[0068] As shown in FIG4 , in some embodiments, the first functional layer 31 includes a protruding portion, and the orthographic projection of the protruding portion on the base substrate 10 does not overlap with the orthographic projection of the second functional layer 32 on the base substrate 10 ;

[0069] The display substrate includes a first set of holes, and the bottom transfer layer 41 is coupled to the first functional layer 31 and the second functional layer 32 respectively through the first set of holes; the target functional layer 33 is directly overlapped with the portion of the bottom transfer layer 41 located outside the first set of holes.

[0070] Illustratively, in a direction parallel to the base substrate 10 , the protruding portion protrudes from the second functional layer 32 and is not covered by the second functional layer 32 .

[0071] Exemplarily, the first set of holes includes a first sub-via and a second sub-via that are interconnected, the first sub-via is located between the second sub-via and the base substrate 10, the aperture of the second sub-via is larger than the aperture of the first sub-via, the bottom transfer layer 41 is coupled to the second functional layer 32 through the second sub-via, and the bottom transfer layer 41 is coupled to the first functional layer 31 through the second sub-via and the first sub-via.

[0072] Exemplarily, the first sub-via penetrates the insulating layer between the first functional layer 31 and the second functional layer 32, and the insulating layer adjacent to and covering the second functional layer 32. The second sub-via penetrates the insulating layer between the target functional layer 33 and the second functional layer 32.

[0073] In the display substrate provided by the above embodiment, the bottom transfer layer 41 is provided to be coupled to the first functional layer 31 and the second functional layer 32 respectively through the first hole; the target functional layer 33 is directly overlapped with the portion of the bottom transfer layer 41 located outside the first hole; the specific connection method between the bottom transfer layer 41 and the first functional layer 31, the second functional layer 32, and the target functional layer 33 is optimized, the connection complexity is reduced, and it is conducive to the development of display products in the direction of high resolution. At the same time, because the top transfer layer 42 only needs to be coupled with the target functional layer 33 among the functional layers, the top transfer layer 42 only needs to cover the vias between the top transfer layer 42 and the target functional layer 33, thereby reducing the number of vias between the top transfer layer 42 and the functional layer, reducing the area of ​​the top transfer layer 42, and further improving the resolution of the display product while reducing the layout difficulty of the display substrate.

[0074] As shown in Figure 7, in some embodiments, the target functional layer 33 includes a first sub-target functional layer 331 and a second sub-target functional layer 332 arranged in a stacked manner, the first sub-target functional layer 331 is located between the second sub-target functional layer 332 and the base substrate 10, and the carrier mobility of the first sub-target functional layer 331 is greater than the carrier mobility of the second sub-target functional layer 332; the first sub-target functional layer 331 is directly overlapped with the portion of the underlying transfer layer 41 located outside the first set of holes.

[0075] Exemplarily, both the first sub-target functional layer 331 and the second sub-target functional layer 332 are made of transparent metal oxides. For example, the first sub-target functional layer 331 is made of indium gallium zinc oxide (IGZO), and the second sub-target functional layer 332 is made of indium gallium tin oxide (IGTO), indium gallium zinc tin oxide (IGZYO), etc., but the present invention is not limited thereto.

[0076] For example, the target functional layer 33 includes a metal oxide active layer ACT (e.g., made of indium gallium zinc oxide (IGZO)). When coupling the metal oxide active layer ACT to the metal layer, the metal oxide active layer ACT is located between the base substrate 10 and the metal layer, i.e., the metal oxide active layer ACT is located below the metal layer, and the surface of the metal oxide active layer ACT facing away from the base substrate 10 contacts the metal layer. The portion of the metal oxide active layer ACT in contact with the metal layer requires conductorization to achieve a good electrical connection. Conductivity of the metal oxide active layer ACT can be achieved by doping ions, dry etching plasma, or H ion diffusion.

[0077] As shown in FIG5 , the metal oxide active layer ACT is located below the metal layer. As long as the upper surface of the metal oxide active layer ACT (as shown in point A in the figure) is conductive, the metal oxide active layer ACT and the metal layer can form good electrical contact even if the doping ions used for conductive connection do not enter the middle layer of the metal oxide active layer ACT (as shown in point C in the figure).

[0078] As shown in FIG6 , the connection between the top transfer layer 42 and the bottom transfer layer 41 requires electrical connection to be formed through the lower surface of the metal oxide active layer ACT and the bottom transfer layer 41, and then electrical connection to the top transfer layer 42 through the upper surface of the metal oxide active layer ACT. Because the lower surface of the metal oxide active layer ACT is not as conductive as the upper surface of the metal oxide active layer ACT during the conductorization process, that is, the contact resistance between the lower surface of the metal oxide active layer ACT and the bottom transfer layer 41 is relatively large, which ultimately affects the connection performance between the top transfer layer 42 and the bottom transfer layer 41, and further affects the electrical connection between the top transfer layer 42 and the first functional layer 31 and the second functional layer 32.

[0079] In the display substrate provided by the above embodiment, by setting the carrier mobility of the first sub-target functional layer 331 to be greater than the carrier mobility of the second sub-target functional layer 332; the first sub-target functional layer 331 is directly overlapped with the portion of the bottom transfer layer 41 located outside the first hole; not only the contact resistance between the target functional layer 33 and the bottom transfer layer 41 is reduced, but also the problem of large contact resistance between the target functional layer 33 and the bottom transfer layer 41 when overlapping is effectively improved; moreover, the use of the second sub-target functional layer 332 on the top layer can ensure the stability of the transistor structure formed thereby.

[0080] As shown in FIG. 8 , in some embodiments, the top transfer layer 42 is also directly coupled to the bottom transfer layer 41 .

[0081] Exemplarily, the display substrate also includes a second set of holes, the second set of holes also includes a third sub-via and a fourth sub-via that are interconnected, the third sub-via is located between the fourth sub-via and the base substrate 10, the aperture of the fourth sub-via is larger than the aperture of the third sub-via, the top transfer layer 42 is coupled to the target functional layer 33 through the fourth sub-via, and the top transfer layer 42 is coupled to the bottom transfer layer 41 through the fourth sub-via and the third sub-via.

[0082] Exemplarily, the third sub-via penetrates the insulating layer covering the target functional layer 33 and adjacent to the target functional layer 33. The fourth sub-via penetrates the insulating layer between the top transfer layer 42 and the target functional layer 33.

[0083] Illustratively, the top transfer layer 42 is directly overlapped with the bottom transfer layer 41 at a portion outside the first hole.

[0084] In the display substrate provided by the above embodiment, by providing the top transfer layer 42 and also directly coupling with the bottom transfer layer 41, a good electrical connection is further formed between the top transfer layer 42 and the bottom transfer layer 41. In more detail, the electrical connection between the top transfer layer 42 and the target functional layer 33 is formed through the top transfer layer 42 and the upper surface of the target functional layer 33, while the top transfer layer 42 and the bottom transfer layer 41 are directly in contact with each other to form an electrical connection. Therefore, a good electrical connection can be formed between the top transfer layer 42 and the first functional layer 31 and the second functional layer 32. This arrangement avoids the problem of high contact resistance when the lower surface of the target functional layer 33 is connected to the bottom transfer layer 41.

[0085] As shown in FIG. 8 , in some embodiments, the display substrate includes a first source / drain metal layer SD1 , and the top transfer layer 42 is provided in the same layer and with the same material as the first source / drain metal layer SD1 .

[0086] When the top transfer layer 42 and the first source / drain metal layer SD1 are provided in the same layer and with the same material, the area of ​​the top transfer layer 42 is greatly reduced, thereby effectively reducing the layout difficulty of the first source / drain metal layer SD1.

[0087] As shown in FIG1 and FIG4 to FIG10, in some embodiments, the display substrate includes a plurality of sub-pixels provided on the base substrate 10, the sub-pixels including a sub-pixel driving circuit and a light-emitting element, the sub-pixel driving circuit including a driving transistor DTFT, a sensing transistor M2, and a storage capacitor C1; a first electrode C11 of the storage capacitor C1 is coupled to a gate g3 of the driving transistor DTFT, and a second electrode C12 of the storage capacitor C1 is respectively coupled to a second electrode of the driving transistor DTFT, a second electrode of the sensing transistor M2, and an anode of the light-emitting element;

[0088] The first functional layer 31 includes the active layer in the driving transistor DTFT, the second functional layer 32 includes the second plate C12 of the storage capacitor C1, the target functional layer 33 includes the sensing active layer in the sensing transistor M2, and the target connection portion 20 includes the anode of the light-emitting element.

[0089] Exemplarily, the display substrate includes a plurality of sub-pixels, and the plurality of sub-pixel driving circuits included in the plurality of sub-pixels are distributed in an array. The plurality of sub-pixel driving circuits are divided into a plurality of rows of sub-pixel driving circuits and a plurality of columns of sub-pixel driving circuits. The plurality of rows of sub-pixel driving circuits are arranged along a second direction, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction. The plurality of columns of sub-pixel driving circuits are arranged along a first direction, and each column of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a second direction. Exemplarily, the first direction and the second direction intersect. For example, the first direction includes a transverse direction, and the second direction includes a longitudinal direction.

[0090] Exemplarily, the sub-pixel includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit is coupled to an anode of the light-emitting element and is configured to provide a driving signal to the light-emitting element to drive the light-emitting element to emit light.

[0091] Exemplarily, the display substrate further includes a plurality of power lines VDD, a plurality of data lines DA, a plurality of sensing signal lines Sens, and a plurality of scan lines Scan. The sub-pixel driving circuit includes a driving transistor DTFT, a data writing transistor M1, a sensing transistor M2, and a storage capacitor C1.

[0092] The gate g3 of the driving transistor DTFT is coupled to the first plate C11 of the storage capacitor C1, the first electrode of the driving transistor DTFT is coupled to the corresponding power line VDD, and the second electrode of the driving transistor DTFT is coupled to the anode of the light emitting element.

[0093] A gate g1 of the data writing transistor M1 is coupled to the corresponding scan line Scan, a first electrode of the data writing transistor M1 is coupled to the corresponding data line DA, and a second electrode of the data writing transistor M1 is coupled to the gate g3 of the driving transistor DTFT.

[0094] The gate of the sensing transistor M2 is coupled to the corresponding scan line Scan, the first electrode of the sensing transistor M2 is coupled to the corresponding sensing signal line Sens, and the second electrode of the sensing transistor M2 is coupled to the anode of the light-emitting element. The cathode of the light-emitting element receives the power supply signal VSS. Exemplarily, the sensing transistor M2 includes a top gate g22 and a bottom gate g21.

[0095] As shown in Figure 1, the sensing signal line Sens is coupled to a first signal terminal via a first switch K1, and to a second signal terminal via a second switch K2. The first signal terminal receives a 0V voltage signal, and the second signal terminal includes a sensing signal terminal VSens. Both the first and second sensing signal terminals are coupled to a driver chip included in the display substrate. The on / off state of the first switch K1 is controlled by a first control signal. The on / off state of the second switch K2 is controlled by a second control signal.

[0096] Exemplarily, the sensing transistor M2 includes an oxide transistor, the data writing transistor M1 and the driving transistor DTFT include low-temperature polysilicon transistors, and the driving transistor DTFT, the data writing transistor M1 and the sensing transistor M2 are all N-type transistors, but are not limited thereto.

[0097] As shown in Figure 2, it is a driving timing diagram of the sub-pixel driving circuit. The first control signal, the second control signal, and the scanning signal transmitted by the scanning line Scan are all valid at a high level, that is, when the signal is at a high level, it can control the corresponding switch to close or control the transistor to turn on. The potential V-N2 of the N2 node is 0V in the initial stage, and then gradually rises to the threshold voltage Vth of the driving transistor DTFT. The potential of the data signal transmitted by the data line DA is 5V. In Figure 2, the high level represents the effective level, which controls the corresponding transistor to turn on.

[0098] As shown in FIG. 2 , the process includes three phases: a reset phase t1 , a compensation phase t2 and a sensing phase t3 .

[0099] In the reset phase t1: the first switch K1 is closed, the data writing transistor M1 and the sensing transistor M2 are turned on, and the N1 node and the N2 node are reset; the potential of the N1 node V_N1 = Vdata, where Vdata is the voltage value of the data signal transmitted by the data line DA, and the potential of the N2 node V_N2 = 0V.

[0100] In the compensation stage t2: the gate-source voltage Vgs of the driving transistor DTFT is Vdata-Vref>Vth, the driving transistor DTFT is turned on, and the power line VDD continuously charges the N2 node through the driving transistor DTFT. As the potential of the N2 node rises, the Vgs voltage difference decreases, and the degree of opening of the driving transistor DTFT gradually decreases until the source Vs voltage of the driving transistor is charged to a voltage Vth different from the gate Vg voltage. The driving transistor DTFT is completely turned off, V_N1=Vdata, V_N2=Vdata-Vth.

[0101] During sensing phase t3, the second switch K2 closes, and the sensing signal line Sens reads the voltage Vdata-Vth. The driver IC extracts the value of Vdata-Vth and outputs it to the Field Programmable Gate Array (FPGA). The FPGA then applies the calculated compensation value to the driver IC, which then adds it to the data signal.

[0102] To achieve high resolution, if all three transistors are low-temperature polysilicon transistors, the layout space occupied is large. If two transistors are oxide transistors and one is low-temperature polysilicon transistor, the thickness of the display substrate may be too thick, making it difficult to achieve cross-line connections, and the yield of the display product will be reduced. Therefore, in the display substrate provided in the above embodiment, the sub-pixel drive circuit includes one oxide transistor and two low-temperature polysilicon transistors, which can overcome the above problems while effectively improving the resolution of the display product.

[0103] In more detail, as shown in Figure 3, as the resolution of the display product gradually increases, the size of a single sub-pixel gradually decreases, making the layout of the first source and drain metal layer SD1 in the display substrate more complex. The first source and drain metal layer SD1 is used to form a complex and independent plurality of signal lines, as well as some transfer layers with a transfer function. For example, the signal lines include: power lines VDD, sensing signal lines Sens, and data lines DA; the transfer layers include a top transfer layer 42 and other transfer layers with a transfer function. As the resolution increases, the problem of insufficient routing space gradually emerges. If the line width or line spacing of the signal lines is compressed, problems such as short circuits or open circuits will occur, which in turn affects the further improvement of the display product resolution.

[0104] In the display substrate provided in the above embodiment, the first functional layer 31 includes the active layer of the driving transistor DTFT, the second functional layer 32 includes the second electrode C12 of the storage capacitor C1, the target functional layer 33 includes the sensing active layer of the sensing transistor M2, and the target connection portion 20 includes the anode of the light-emitting element. Exemplarily, the active layer of the driving transistor DTFT includes a polycrystalline silicon active layer Poly, and the sensing active layer of the sensing transistor M2 includes a metal oxide active layer ACT.

[0105] In the display substrate provided in the above embodiment, the first source-drain metal layer SD1 is provided to include the top transfer layer 42. Since the active layer in the driving transistor DTFT, the second electrode C12 of the storage capacitor C1, and the sensing active layer in the sensing transistor M2 can be coupled together through the bottom transfer layer 41, the top transfer layer 42 only needs to be coupled to the sensing active layer and / or the bottom transfer layer 41. This reduces the number of vias required to be provided when the top transfer layer 42 is connected to the bottom film layer, thereby reducing the number of vias that need to be covered by the top transfer layer 42, thereby reducing the area or size of the top transfer layer 42, reducing the area or size of the required first source-drain metal layer SD1, alleviating the problem of insufficient layout space for the first source-drain metal layer SD1, and facilitating further improvement in the resolution of high-resolution display products.

[0106] Furthermore, by directly coupling the top transfer layer 42 to both the sensing active layer and the bottom transfer layer 41, the problem of high contact resistance when the sensing active layer overlaps the bottom transfer layer 41 is resolved, thereby improving the display quality of the display product. Furthermore, the electrical conductivity between the top transfer layer 42 and the bottom transfer layer 41 is enhanced, reducing loading and improving display uniformity.

[0107] As shown in FIG7 , in some embodiments, when the target functional layer 33 includes a first sub-target functional layer 331 and a second sub-target functional layer 332 stacked together, both the first sub-target functional layer 331 and the second sub-target functional layer 332 are made of transparent metal oxide material.

[0108] Exemplarily, the sensing active layer includes a first sub-target function layer 331 and a second sub-target function layer 332 that are stacked.

[0109] Since the carrier mobility of the first sub-target functional layer 331 is greater than the carrier mobility of the second sub-target functional layer 332; the first sub-target functional layer 331 is directly overlapped with the portion of the bottom transfer layer 41 located outside the first set of holes; it not only reduces the contact resistance between the target functional layer 33 and the bottom transfer layer 41, but also effectively improves the problem of large contact resistance between the target functional layer 33 and the bottom transfer layer 41 when overlapping; moreover, the use of the second sub-target functional layer 332 on the top layer can ensure the stability of the characteristics of the sensing transistor M2.

[0110] As shown in Figures 4, 7, 8 and 10, in some embodiments, the display substrate further includes a data line DA; the sub-pixel driving circuit further includes a data writing transistor M1, a first electrode of the data writing transistor M1 is coupled to the corresponding data line DA, and a second electrode of the data writing transistor M1 is coupled to the gate g3 of the driving transistor DTFT; the data writing transistor M1 includes a data writing active layer, and the data line DA is located on the side of the data writing active layer facing the base substrate 10.

[0111] It should be noted that in Figures 4, 7, 8 and 10, g3 is marked on the right side of the figure. This g3 can be a structure coupled to the gate g3 of the driving transistor DTFT, that is, it has the same potential as the gate g3 of the driving transistor DTFT, and may not serve as the gate g3 of the driving transistor DTFT.

[0112] Exemplarily, the data writing active layer includes a polysilicon active layer Poly.

[0113] More specifically, as shown in Figure 3, when the first source / drain metal layer SD1 is used to form multiple, complex, independent signal traces, as well as some transition layers, each signal trace and transition pattern must transmit different signals and therefore must be spaced apart from each other. However, due to the high resolution, the layout space of the first source / drain metal layer SD1 is squeezed, making it difficult to achieve the desired layout, which in turn affects the improvement of pixel resolution.

[0114] In the display substrate provided by the above embodiment, the data line DA is arranged to be located on the side of the data writing active layer facing the base substrate 10, and the data line DA originally made using the first source and drain metal layer SD1 is transferred to the bottom layer of the display substrate, thereby reducing the complexity of the first source and drain metal layer SD1, which is equivalent to improving the layout space of the first source and drain metal layer SD1, reducing the layout difficulty of the first source and drain metal layer SD1, and is conducive to further improving the resolution of high-resolution display products.

[0115] In the display substrate provided in the above embodiment, the data line DA and the first source-drain metal layer SD1 can be arranged in different layers, that is, the data line DA is arranged above or below the first source-drain metal layer SD1, thereby reducing the layout difficulty of the first source-drain metal layer SD1, which is conducive to further improving the resolution of high-resolution display products.

[0116] In some embodiments, the display substrate further includes a light-shielding layer LS, as shown in Figures 4, 7, 8 and 10, the light-shielding layer LS is located on the side of the data line DA facing the base substrate 10; or, as shown in Figure 16, the data line DA is located on the side of the light-shielding layer LS facing the base substrate 10; or, the data line DA and the light-shielding layer LS are set in the same layer and material.

[0117] Disposing the light-shielding layer LS and the data lines DA in separate film layers provides ample layout space for both, thereby reducing the layout complexity of the display substrate. Disposing the data lines DA and the light-shielding layer LS in the same layer and material allows them to be formed simultaneously with the light-shielding layer LS in the same patterning process, thereby significantly simplifying the display substrate manufacturing process and reducing the manufacturing cost of the display substrate.

[0118] The aforementioned arrangement of the data line DA on the side of the light shielding layer LS facing the base substrate 10 further reduces parasitic capacitance between the data line DA and surrounding structures, such as parasitic capacitance between the data line DA and the gate of the data writing transistor. It should be noted that FIG16 also illustrates an isolation layer Bar.

[0119] As shown in FIG4 , FIG7 , FIG8 and FIG10 , in some embodiments, the display substrate further includes a sensing signal line Sens, a second transfer layer 46 and a compensation signal line Sens-B; the first electrode of the sensing transistor M2 is coupled to the corresponding sensing signal line Sens; the sensing signal line Sens is coupled to the corresponding compensation signal line Sens-B through the corresponding second transfer layer 46;

[0120] The compensation signal line Sens-B and the light shielding layer LS are provided in the same layer and made of the same material. At least a portion of the second transfer layer 46 is located between the sensing signal line Sens and the compensation signal line Sens-B.

[0121] Exemplarily, the display substrate includes a second gate metal layer, and the second transfer layer 46 is provided in the same layer and with the same material as the second gate metal layer.

[0122] The compensation signal line Sens-B and the light shielding layer LS are set in the same layer and material, so that the compensation signal line Sens-B can be formed simultaneously with the light shielding layer LS in the same composition process, thereby greatly simplifying the manufacturing process of the display substrate and reducing the manufacturing cost of the display substrate.

[0123] As described above, at least a portion of the second transfer layer 46 is located between the sensing signal line Sens and the compensation signal line Sens-B, so that the second transfer layer 46 can play a transfer role between the corresponding sensing signal line Sens and the compensation signal line Sens-B, which not only ensures the connection performance between the sensing signal line Sens and the compensation signal line Sens-B, but also avoids the production of deep holes for directly connecting the compensation signal line Sens-B and the sensing signal line Sens, thereby improving the production yield of the display substrate.

[0124] As shown in Figures 4, 7, 8 and 10, in some embodiments, the display substrate further includes a second gate metal layer; the sub-pixel driving circuit further includes a third transfer layer 43, and the third transfer layer 43 is coupled to a portion of the data write active layer serving as the first electrode of the data write transistor M1 and the data line DA, respectively; the third transfer layer 43 is arranged in the same layer and material as the second gate metal layer.

[0125] The above arrangement not only ensures the connection performance between the data write transistor M1 and the corresponding data line DA, but also reduces the difficulty of connecting the data write transistor M1 and the data line DA. Furthermore, the third transfer layer 43 and the second gate metal layer are provided in the same layer and material, allowing them to be formed simultaneously in the same patterning process, thereby greatly simplifying the display substrate manufacturing process and reducing the display substrate manufacturing cost.

[0126] As shown in Figures 4, 7, 8 and 10, in some embodiments, the display substrate further includes a fourth transfer layer 44, which is coupled to a portion of the data writing active layer serving as the second electrode of the data writing transistor M1 and the gate g3 of the driving transistor DTFT, respectively; the fourth transfer layer 44 is arranged in the same layer and material as the underlying transfer layer 41.

[0127] The above arrangement not only ensures the connection performance between the data write transistor M1 and the drive transistor DTFT, but also reduces the difficulty of connecting the data write transistor M1 and the drive transistor DTFT. Furthermore, the fourth transfer layer 44 is provided in the same layer and material as the bottom transfer layer 41, so that the fourth transfer layer 44 and the bottom transfer layer 41 can be formed simultaneously in the same patterning process, thereby greatly simplifying the manufacturing process of the display substrate and reducing the manufacturing cost of the display substrate.

[0128] As shown in Figure 10, in some embodiments, the display substrate further includes a third gate insulating layer GI3; the sensing active layer includes a sensing channel portion and a sensing conductor portion, the sensing conductor portion is used to serve as the first electrode and the second electrode of the sensing transistor M2, and at least a portion of the third gate insulating layer GI3 is located between the gate of the sensing transistor M2 and the sensing channel portion; the orthographic projection of the third gate insulating layer GI3 on ​​the base substrate 10 does not overlap with the orthographic projection of the sensing conductor portion on the base substrate 10.

[0129] Illustratively, the orthographic projection of the sensing channel portion on the base substrate 10 overlaps with the orthographic projection of the gate of the sensing transistor M2 on the base substrate 10. The orthographic projection of the sensing conductor portion on the base substrate 10 does not overlap with the orthographic projection of the gate of the sensing transistor M2 on the base substrate 10.

[0130] Exemplarily, the gate of the sensing transistor M2 is located on a side of the third gate insulating layer GI3 facing away from the base substrate 10 .

[0131] In the display substrate provided by the above embodiment, by setting the orthographic projection of the third gate insulation layer GI3 on ​​the base substrate 10 so as not to overlap with the orthographic projection of the sensing conductor part on the base substrate 10, the conductorization effect of the sensing conductor part can be improved, thereby enhancing the connection performance between the target functional layer 33 and the top-layer transition part and the bottom-layer transition part.

[0132] As shown in Figures 4, 7 and 8, in some embodiments, the display substrate further includes a third gate insulating layer GI3; the sensing active layer includes a sensing channel portion and a sensing conductor portion, the sensing conductor portion is used to serve as the first electrode and the second electrode of the sensing transistor M2, and at least a portion of the third gate insulating layer GI3 is located between the gate of the sensing transistor M2 and the sensing channel portion; the orthographic projection of the third gate insulating layer GI3 on ​​the base substrate 10 covers the orthographic projection of the sensing conductor portion on the base substrate 10.

[0133] Exemplarily, the third gate insulating layer GI3 is a whole layer structure covering the base substrate 10 .

[0134] As shown in Figures 4, 7, 8 and 10, in some embodiments, the display substrate further includes a fifth transfer layer 45, which is located on the side of the sensing signal line Sens facing away from the base substrate 10, and the fifth transfer layer 45 is coupled to the sensing signal line Sens.

[0135] Exemplarily, the fifth transfer layer 45 is made of Mo (molybdenum) metal, or a metal stacking structure such as Ti / Al / Ti (titanium / aluminum / titanium).

[0136] The fifth transfer layer 45 is provided to lead out the sensing signal line Sens, thereby achieving coupling with other structures.

[0137] It should be noted that the fifth transfer layer 45 is provided in a separate layer from the first source / drain metal layer SD1. The fifth transfer layer 45 is also provided in a separate layer from the anode of the light-emitting element. In the above-described display substrate, the provision of an independent fifth transfer layer 45 not only allows the sensing signal line Sens to be routed, but also overcomes the layout bottleneck of the first source / drain metal layer SD1 and the film layer containing the anode.

[0138] The present disclosure also provides a method for manufacturing a display substrate. The specific manufacturing process is as follows:

[0139] As shown in Figure 11, a light-shielding layer LS, a barrier layer, a first conductive layer (for forming a data line DA), a first buffer layer BUF1, a polysilicon active layer Poly, a first gate insulating layer GI1, a first gate metal layer gate1, a second gate insulating layer GI2, a via connecting the second gate metal layer to the lower layer, a second gate metal layer, a first interlayer insulating layer ILD1 and a second buffer layer BUF2 are formed in sequence on the base substrate 10. In this way, the data line DA is lowered to the side of the polysilicon active layer Poly facing the base substrate 10, thereby improving the problem of insufficient layout space of the first source and drain metal layer SD1 at high resolution, thereby further improving the resolution of high-resolution display products.

[0140] As shown in Figure 12, the first set of holes is formed, as well as the bottom transfer layer 41 and the fourth transfer layer 44. This method further improves the problem of insufficient space in the first source and drain metal layer SD1 at high resolution, thereby further improving the resolution of high-resolution display products.

[0141] As shown in FIG. 13 , the metal oxide active layer ACT, the third gate insulating layer GI3 , the third gate metal layer, the second interlayer insulating layer ILD2 , and the first connection hole CNT-L are continuously formed.

[0142] As shown in FIG. 14 , the second connecting holes CNT-O (including the second set of holes) are continuously formed.

[0143] As shown in FIG15 , the first source / drain metal layer SD1 is further formed.

[0144] As shown in Figure 8, the first planar layer PLN1, the fifth transfer layer 45, the second planar layer PLN2, the anode layer and the pixel definition layer PDL are further formed. The light-emitting functional layer, the cathode layer and the encapsulation layer can also be formed later, but these layers are not shown in the figure.

[0145] An embodiment of the present disclosure further provides a display device, comprising the display substrate provided by the above embodiment.

[0146] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane.

[0147] In the display substrate provided by the above embodiment, the target functional layer 33 and the non-target functional layer are first connected together through the bottom transfer layer 41, and then the target functional layer 33 and the target connection portion 20 are connected together through the top transfer layer 42. In this way, all functional layers can be coupled to the target connection portion 20 through the top transfer layer 42. Since the top transfer layer 42 only needs to be coupled with the target functional layer 33 among the functional layers, the top transfer layer 42 only needs to cover the vias between the top transfer layer 42 and the target functional layer 33. This reduces the number of vias between the top transfer layer 42 and the functional layers, shrinks the area of ​​the top transfer layer 42, and further improves the resolution of the display product while reducing the layout difficulty of the display substrate.

[0148] The display device provided by the embodiment of the present disclosure also has the above-mentioned beneficial effects when it includes the display substrate provided by the above-mentioned embodiment, which will not be described in detail here.

[0149] It should be noted that, in the display substrate provided in the above embodiment, the function of the second set of holes is to connect the target functional layer 33 and the bottom transfer layer 41 together through the top transfer layer 42. The size or position of the second set of holes can be appropriately optimized to adjust the contact area between the top transfer layer 42 and the upper surface of the target functional layer 33 and the bottom transfer layer 41 to ensure the connection performance of the three. The connection relationship between the top transfer layer 42 and the upper surface of the target functional layer 33 and the bottom transfer layer 41 includes but is not limited to the several embodiments mentioned above. Some changes and improvements can be made without departing from the creative spirit and scope of the present disclosure.

[0150] In the display substrate provided in the above embodiment, the number of both the first set of holes and the second set of holes in each sub-pixel layout area is one. Depending on the needs of the display product, multiple similar vias may be added to each sub-pixel layout area to improve the resolution of the display product. Minor changes and improvements may be made without departing from the spirit and scope of the present disclosure.

[0151] In the display substrate provided in the above embodiment, the target functional layer 33 can be another transparent metal oxide semiconductor active layer, such as IGTO, IGZYO, etc., or can be formed by stacking two or more transparent metal oxide semiconductor active layers. The polycrystalline silicon active layer Poly in the above embodiment can be replaced with an active layer such as IGZO, that is, the IGZO and polycrystalline silicon active layer Poly in the embodiment can also be replaced with other active layers. Minor changes and improvements can be made without departing from the spirit and scope of the invention.

[0152] In the display substrate provided in the above embodiment, the structure originally formed by the first source-drain metal layer SD1 (such as the data line DA) can be placed downward or upward. The purpose is to place the downward or upward structure and the first source-drain metal layer SD1 on different layers to further increase the routing space of the first source-drain metal layer SD1, thereby further improving the resolution of high-resolution display products. Minor changes and improvements may be made without departing from the creative spirit and scope of the present disclosure.

[0153] It should be noted that the "same layer" in the embodiment of the present disclosure may refer to a film layer on the same structural layer. Or, for example, a film layer in the same layer may be a film layer formed by using the same film forming process to form a specific pattern, and then patterning the film layer using the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0154] In the various method embodiments of the present disclosure, the serial numbers of the steps cannot be used to limit the order of the steps. For ordinary technicians in this field, without paying any creative work, changes to the order of the steps are also within the scope of protection of the present disclosure.

[0155] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the product embodiments. For relevant parts, refer to the description of the product embodiments.

[0156] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect", "couple" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0157] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0158] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0159] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate, comprising: A base substrate, and at least three functional layers, at least two first transfer layers and a target connection portion all disposed on the base substrate; At least two of the at least three functional layers are stacked in sequence in a direction away from the substrate, and the at least three functional layers include a target functional layer, which is the functional layer farthest from the substrate among the at least three functional layers; The at least two first switching layers include: a top switching layer and at least one bottom switching layer; The top transfer layer is located on a side of the target functional layer facing away from the substrate, and the top transfer layer is coupled to the target connection portion and the target functional layer respectively; At least a portion of the bottom transfer layer is located between the target functional layer and the base substrate, and the bottom transfer layer is respectively coupled to the target functional layer and at least one non-target functional layer of the at least three functional layers.

2. The display substrate according to claim 1, wherein: The at least three functional layers also include a first functional layer and a second functional layer; at least a portion of the first functional layer is located between the substrate and the second functional layer; the at least two first transfer layers include a bottom transfer layer; the bottom transfer layer is coupled to the first functional layer and the second functional layer, respectively.

3. The display substrate according to claim 2, wherein: The first functional layer includes a protruding portion, and an orthographic projection of the protruding portion on the substrate does not overlap with an orthographic projection of the second functional layer on the substrate; The display substrate comprises a first set of holes, and the bottom transfer layer is coupled to the first functional layer and the second functional layer respectively through the first set of holes; the target functional layer is directly overlapped with a portion of the bottom transfer layer located outside the first set of holes.

4. The display substrate according to claim 3, wherein: The first set of holes includes a first sub-via and a second sub-via that are interconnected, the first sub-via is located between the second sub-via and the base substrate, the aperture of the second sub-via is larger than the aperture of the first sub-via, the bottom transfer layer is coupled to the second functional layer through the second sub-via, and the bottom transfer layer is coupled to the first functional layer through the second sub-via and the first sub-via.

5. The display substrate according to claim 3, wherein: The target functional layer comprises a first sub-target functional layer and a second sub-target functional layer which are stacked, the first sub-target functional layer is located between the second sub-target functional layer and the substrate, and the carrier mobility of the first sub-target functional layer is greater than the carrier mobility of the second sub-target functional layer; The first sub-target functional layer is directly overlapped with a portion of the bottom switching layer located outside the first set of holes.

6. The display substrate according to claim 3, wherein: The top switching layer is also directly coupled to the bottom switching layer.

7. The display substrate according to claim 6, wherein: The display substrate also includes a second set of holes, the second set of holes also includes a third sub-via and a fourth sub-via that are interconnected, the third sub-via is located between the fourth sub-via and the base substrate, the aperture of the fourth sub-via is larger than the aperture of the third sub-via, the top transfer layer is coupled to the target functional layer through the fourth sub-via, and the top transfer layer is coupled to the bottom transfer layer through the fourth sub-via and the third sub-via.

8. The display substrate according to claim 3, wherein: The display substrate comprises a first source-drain metal layer, and the top transfer layer is provided in the same layer and with the same material as the first source-drain metal layer.

9. The display substrate according to any one of claims 3 to 8, wherein: The display substrate comprises a plurality of sub-pixels arranged on the base substrate, the sub-pixels comprise a sub-pixel driving circuit and a light-emitting element, the sub-pixel driving circuit comprises a driving transistor, a sensing transistor and a storage capacitor; a first plate of the storage capacitor is coupled to a gate of the driving transistor, and a second plate of the storage capacitor is respectively coupled to a second electrode of the driving transistor, a second electrode of the sensing transistor and an anode of the light-emitting element; The first functional layer includes an active layer in the driving transistor, the second functional layer includes a second plate of the storage capacitor, the target functional layer includes a sensing active layer in the sensing transistor, and the target connection portion includes an anode of the light emitting element.

10. The display substrate according to claim 9, wherein: In a case where the target functional layer includes a first sub-target functional layer and a second sub-target functional layer which are stacked, the first sub-target functional layer and the second sub-target functional layer are both made of a transparent metal oxide material.

11. The display substrate according to claim 9, wherein: The display substrate further includes a data line; the sub-pixel driving circuit further includes a data writing transistor, a first electrode of the data writing transistor is coupled to the corresponding data line, and a second electrode of the data writing transistor is coupled to the gate of the driving transistor; The data writing transistor comprises a data writing active layer, and the data line is located on a side of the data writing active layer facing the substrate.

12. The display substrate according to claim 11, wherein: The display substrate further comprises a light shielding layer, and the light shielding layer is located on a side of the data line facing the base substrate.

13. The display substrate according to claim 12, wherein: The display substrate further comprises a sensing signal line, a second transfer layer and a compensation signal line; the first electrode of the sensing transistor is coupled to the corresponding sensing signal line; the sensing signal line is coupled to the corresponding compensation signal line through the corresponding second transfer layer; The compensation signal line and the light shielding layer are provided in the same layer and with the same material, and at least a portion of the second transfer layer is located between the sensing signal line and the compensation signal line.

14. The display substrate according to claim 11, wherein: The display substrate further includes a light shielding layer, and the data line is located on a side of the light shielding layer facing the base substrate.

15. The display substrate according to claim 11, wherein: The display substrate further comprises a light shielding layer, and the data line and the light shielding layer are provided in the same layer and with the same material.

16. The display substrate according to claim 11, wherein: The display substrate also includes a second gate metal layer; the sub-pixel driving circuit also includes a third transfer layer, and the third transfer layer is coupled to the part of the data writing active layer serving as the first electrode of the data writing transistor and the data line respectively; the third transfer layer is arranged in the same layer and the same material as the second gate metal layer.

17. The display substrate according to claim 11, wherein: The display substrate further includes a fourth transfer layer, which is respectively coupled to a portion of the data writing active layer serving as the second electrode of the data writing transistor and the gate of the driving transistor; the fourth transfer layer is arranged in the same layer and material as the bottom transfer layer.

18. The display substrate according to claim 9, wherein: The display substrate further includes a third gate insulating layer; The sensing active layer includes a sensing channel portion and a sensing conductor portion, the sensing conductor portion is used as a first electrode and a second electrode of the sensing transistor, and at least a portion of the third gate insulating layer is located between the gate of the sensing transistor and the sensing channel portion; The orthographic projection of the third gate insulating layer on the base substrate does not overlap with the orthographic projection of the sensing conductor portion on the base substrate.

19. The display substrate according to claim 9, wherein: The display substrate further includes a third gate insulating layer; The sensing active layer includes a sensing channel portion and a sensing conductor portion, the sensing conductor portion is used as a first electrode and a second electrode of the sensing transistor, and at least a portion of the third gate insulating layer is located between the gate of the sensing transistor and the sensing channel portion; The orthographic projection of the third gate insulating layer on the base substrate covers the orthographic projection of the sensing conductor portion on the base substrate.

20. A display device comprising the display substrate according to any one of claims 1 to 19.

Images