Neural networks for identifying objects in modified images

Abstract

Devices, systems, and techniques for identifying objects within one or more images. In at least one embodiment, objects in an image are identified using one or more neural networks based, at least partially, on one or more features of the one or more images and one or more features of one or more modified versions of the one or more images.

Description

TECHNICAL AREA At least one embodiment relates to processing resources used for image generation, image processing, computer vision, or other machine learning tasks. For example, at least one embodiment relates to processors or computing systems used to perform 3D or 4D perception tasks using one or more neural networks according to various novel techniques described herein. BACKGROUND Neural networks are often inaccurate when performing computer vision tasks (e.g., object detection) on higher-dimensional images based on low-dimensional images. The accuracy of neural networks performing such computer vision tasks can be improved. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 illustrates an exemplary system that performs computer vision tasks for higher-dimensional images based on lower-dimensional images, according to at least one embodiment; Fig. 2 illustrates an exemplary system that performs computer vision tasks for higher-dimensional images based on lower-dimensional images, according to at least one embodiment; Fig. 3 illustrates an exemplary process that performs computer vision tasks for higher-dimensional images based on lower-dimensional images, according to at least one embodiment; Fig. 4 illustrates an exemplary process that performs computer vision tasks for higher-dimensional images based on lower-dimensional images, according to at least one embodiment; Fig.Figure 5 illustrates an exemplary process that performs computer vision tasks for higher-dimensional images based on lower-dimensional images, according to at least one embodiment; Figure 6 illustrates an exemplary system that performs computer vision tasks for higher-dimensional images based on lower-dimensional images, according to at least one embodiment; Figure 7 illustrates an exemplary system that performs computer vision tasks for higher-dimensional images based on lower-dimensional images, according to at least one embodiment; Figure 8A illustrates logic according to at least one embodiment; Figure 8B illustrates logic according to at least one embodiment; Figure 9 illustrates training and deployment of a neural network according to at least one embodiment; Figure 10 illustrates an exemplary data center system according to at least one embodiment; FigureFigure 11A illustrates an example of an autonomous vehicle according to at least one embodiment; Figure 11B illustrates an example of camera positions and fields of view for the autonomous vehicle of Figure 11A according to at least one embodiment; Figure 11C is a block diagram illustrating an exemplary system architecture for the autonomous vehicle of Figure 11A according to at least one embodiment; Figure 11D is a diagram illustrating a system for communication between cloud-based server(s) and the autonomous vehicle of Figure 11A according to at least one embodiment; Figure 12 is a block diagram illustrating a computer system according to at least one embodiment; Figure 13 is a block diagram illustrating a computer system according to at least one embodiment; Figure 14 illustrates a computer system according to at least one embodiment; FigureFigure 15 illustrates a computer system according to at least one embodiment; Figure 16A illustrates a computer system according to at least one embodiment; Figure 16B illustrates a computer system according to at least one embodiment; Figure 16C illustrates a computer system according to at least one embodiment; Figure 16D illustrates a computer system according to at least one embodiment; Figures 16E and 16F illustrate a shared programming model according to at least one embodiment; Figure 17 illustrates exemplary integrated circuits and associated graphics processors according to at least one embodiment; Figures 18A-18B illustrate exemplary integrated circuits and associated graphics processors according to at least one embodiment; Figures 19A-19B illustrate additional exemplary graphics processor logic according to at least one embodiment; FigureFigure 20 illustrates a computer system according to at least one embodiment; Figure 21A illustrates a parallel processor according to at least one embodiment; Figure 21B illustrates a partition unit according to at least one embodiment; Figure 21C illustrates a processing cluster according to at least one embodiment; Figure 21D illustrates a graphics multiprocessor according to at least one embodiment; Figure 22 illustrates a multi-graphics processing unit (GPU) system according to at least one embodiment; Figure 23 illustrates a graphics processor according to at least one embodiment; Figure 24 is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment; Figure 25 illustrates a deep learning application processor according to at least one embodiment; FigureFigure 26 is a block diagram illustrating an exemplary neuromorphic processor according to at least one embodiment; Figure 27 illustrates at least sections of a graphics processor according to one or more embodiments; Figure 28 illustrates at least sections of a graphics processor according to one or more embodiments; Figure 29 illustrates at least sections of a graphics processor according to one or more embodiments; Figure 30 is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment; Figure 31 is a block diagram of at least sections of a graphics processor core according to at least one embodiment; Figures 32A-32B illustrate thread execution logic comprising an array of processing elements of a graphics processor core according to at least one embodiment; FigureFigure 33 illustrates a parallel processing unit (“PPU”) according to at least one embodiment; Figure 34 illustrates a general-purpose processing cluster (“GPC”) according to at least one embodiment; Figure 35 illustrates a memory partition unit of a parallel processing unit (“PPU”) according to at least one embodiment; Figure 36 illustrates a streaming multiprocessor according to at least one embodiment; Figure 37 is an exemplary data flow diagram for an advanced computing pipeline according to at least one embodiment; Figure 38 is a system diagram for an exemplary system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline according to at least one embodiment; Figure 39 includes an exemplary illustration of an advanced computing pipeline 3810A for processing imaging data, according to at least one embodiment; FigureFigure 40A includes an exemplary data flow diagram of a virtual instrument supporting an ultrasound device according to at least one embodiment; Figure 40B includes an exemplary data flow diagram of a virtual instrument supporting a CT scanner according to at least one embodiment; Figure 41A illustrates a data flow diagram for a process for training a machine learning model according to at least one embodiment; and Figure 41B is an exemplary illustration of a client-server architecture for enhancing annotation tools with pre-trained annotation models according to at least one embodiment. Figure 42 illustrates components of a system for accessing a large language model according to at least one embodiment. DETAILED DESCRIPTION The following descriptions detail various techniques and systems. For explanatory purposes, specific configurations and details are presented to provide a thorough understanding of possible implementations of the techniques. However, it will also be evident that the techniques described below can be practiced in various configurations without these specific details. Furthermore, known aspects may be omitted or simplified to avoid obscuring the described techniques. In at least one embodiment, a processor (e.g., processor 602, used to implement system 100) uses one or more ordinary neural networks to identify objects (e.g., cats, dogs, cars) in a 3D image generated from 2D images using modified features that were inverted prior to object identification in the generated 3D images. In at least one embodiment, the one or more neural networks receive 2D images, modify these images (e.g., by rotating them clockwise), and identify additional features from the modified images. In at least one embodiment, the one or more neural networks then perform an inversion (e.g., a counterclockwise rotation) of additional features to be consistent with an original image (e.g., the 2D images).In at least one embodiment, the one or more neural networks generate a 3D image using the reverse additional features, and the use of additional 2D features enables the one or more neural networks to generate the 3D image that more accurately represents a scene. In at least one embodiment, a neural network repeats the above process using the generated 3D image (e.g., modifying the 3D images, identifying additional features from the modified 3D images, inverting the modified 3D images to preserve the original features of the 3D images) and uses the additional features and the original features of the 3D image to identify objects within the 3D image. In at least one embodiment, the use of additional 3D features enables the neural network to identify objects within the 3D image with high accuracy. Fig. 1 illustrates an exemplary system 100 that performs computer vision tasks for higher-dimensional images based on lower-dimensional images, according to at least one embodiment. In at least one embodiment, system 100 uses one or more neural networks to identify one or more objects within one or more images based, at least partially, on one or more features of the one or more images and one or more features of one or more modified versions of the one or more images. In at least one embodiment, one or more features of the one or more images comprise features extracted from 2D or 3D images, or inverted features from augmented images described herein.In at least one embodiment, one or more modified versions comprise augmented images or inverted augmented images as described herein. In at least one embodiment, a modified image comprises an image that is augmented and inverted or modified based on augmented features and other features. In at least one embodiment, the identification of one or more objects within one or more images based, at least partially, on one or more features of the one or more images and one or more features of one or more modified versions of the one or more images refers to the use of one or more features of the one or more images and one or more features of one or more modified versions of the one or more images for identification.In at least one embodiment, the identification of one or more objects within one or more images, based at least partially on one or more features of the one or more images and one or more features of one or more modified versions of the one or more images, refers to the dependence on one or more values ​​of one or more features of the one or more images and one or more features of one or more modified versions of the one or more images for identification.In at least one embodiment, the identification of one or more objects within one or more images, based at least partially on one or more features of the one or more images and one or more features of one or more modified versions of the one or more images, refers to the processing of one or more values ​​of one or more features of the one or more images and one or more features of one or more modified versions of the one or more images for identification. In at least one embodiment, System 100 comprises one or more processors (e.g., Processor 602), one or more storage devices, and / or a data center (e.g., Data Center 1000). In at least one embodiment, System 100 comprises a combination of the hardware and software described herein. In at least one embodiment, System 100 comprises a 2D acquisition module 102, a 2D-to-3D module 104, and a 3D processing module 106. In at least one embodiment, as used in each implementation described herein, unless otherwise apparent from the context or expressly stated otherwise, terms such as module and substantivized verbs (e.g., 2D Acquisition Module 102, 2D-to-3D Module 104 and 3D Processing Module 106, 2D Image Augmentation Module 202, 2D Feature Generation Module 204, 2D Inversion Module 206, 3D Scene Reconstruction Module 208, 3D Scene Augmentation Module 210, 3D Feature Generation Module 212, 3D Inversion Module 214, 3D Perception Module 216, Image Acquisition Module 610, Higher Dimensions Generation Module 612, Higher Dimensions Modification Module 614) refer to Computer vision module 616), which are described in Fig. 1-42, each to a combination of software logic, hardware logic and / or circuitry configured to provide the functionality described herein. In at least one embodiment, the software described in Figures 1-42 includes, for example, operating systems, device drivers, application software, database software, graphics software (e.g., Radeon, Intel Graphics), web browsers, development software (e.g., integrated development environments, code editors, compilers, interpreters), network software (e.g., Intel PROset, Intel Advanced Network Services), simulation software, real-time operating systems (RTOS), artificial intelligence software (e.g., Scikit-learn, TensorFlow, PyTorch, Accord.NET, Apache Machout), robotics software (ROBEL, MS AirSi, Apollo Baidu, AWS RoboMaker, ROSbot 2.0, Poppy Project), firmware (e.g., BIOS / UEFI, routers, smartphones, consumer electronics, embedded systems, printers, solid-state drives (SSDs)), application programming interfaces (APIs), and containerized software (e.g., Nginx, Apache HTTP Server, MySQL). PostgreSQL, Redis, Memcached, Node.js, Elasticsearch, Gitlab, Jenkins, WordPress), container orchestration platforms (e.g. Kubernetes, Docker Swarm, Apache Mesos, Nomad, Amazon ECS, Microsoft Azure Kubernetes Service, Google Kubernetes Engine, Red Hat OpenShift, Rancher) or any other implementation that is executed as a software package, code and / or instruction set or commands. In at least one embodiment, the API described in Figures 1-42 refers to a set of rules and definitions that enables software to communicate with each other. In at least one embodiment, APIs can define the procedures and data formats that software uses to request and exchange information. In at least one embodiment, the API receives inputs, such as single inputs or any combination thereof, endpoints, types of operations, headers, parameters, and body (e.g., JSON, XML). In at least one embodiment, the API performs one or more of the operations described herein.In at least one embodiment, API includes, for example, individually or in any combination, web APIs, operating system APIs, database APIs, cloud services APIs, Vulkan API, browser APIs, Google Cloud AI APIs, IBM Watson APIs, Microsoft Azure Cognitive Services APIs, Clarifai APIs, Intel APIs from Intel Neural Compressor, Intel AI Analytics Toolkit, Intel Distribution of OpenVINO Toolkit, AMD Ryzen AI Software Platform and AMD APIs from AMD EPYC Server Processors, AMD Alveo Adaptive Accelerators, AMD Adaptive SoCs, AMD Ryzen AI Mobile Processors, AMD Radeon Graphics Cards, AMD Software Tools, AMD ROCm™ Platform, AMD Vitis AI Platform, AMD ZenDNN Library, AMD Ryzen AI Software Platform, Open API or any other API that can be used to perform computer vision, natural language processing and / or 5G operations. In at least one embodiment, the hardware described in Figs. 1-42 comprises, for example, individually or in any combination, a hard-wired circuit arrangement, a programmable circuit arrangement, a state machine circuit arrangement, a fixed-function circuit arrangement, an execution unit circuit arrangement and / or firmware that stores commands executed by a programmable circuit arrangement.In at least one embodiment, the circuit arrangement can form part of a larger system, for example, individually or in any combination, an integrated circuit (IC), system-on-chip (SoC), central processing unit (CPU), graphics processing unit (GPU), data processing unit (DPU), digital signal processor (DSP), tensor processing unit (TPU), accelerated processing unit (APU), application-specific integrated circuits (ASIC), intelligent processing unit (IPU), neural processing unit (NPU), intelligent network interface controller (SmartNIC), video processing unit (VPU), field-programmable gate array (FPGA), and so on. In at least one embodiment, the neural networks described in Figures 1-42 can be based, for example, individually or in any combination, on forward-linked neural networks, convolutional neural networks (CNNs), recurrent neural networks (RNNs), long-short-term memory networks (LSTMs), generative adversarial networks (GANs), restricted Boltzmann machines (RBMs), deep belief networks (DBNs), radial basis function networks (RBFNs), Hopfield networks, self-organizing maps, perceptrons with one or more layers, modular neural networks, spiking neural networks, deep reinforcement learning networks, echo-state networks, time-delayed neural networks, support vector machines, attention-based neural networks, autoencoders, graph neural networks (e.g., graph convolutional networks), and variational autoencoders. and / or transformer neural networks (e.g.Bidirectional Encoder Representations from Transformers (BERT)). In at least one embodiment, the neural networks described herein comprise an untrained neural network 906. In at least one embodiment, the neural networks comprise a trained neural network 908, which is trained using a training dataset 902 and training frameworks 904. In at least one embodiment, in addition to the techniques described in connection with Fig. 9, the neural networks are trained using various neural network training techniques (e.g., supervised learning, unsupervised learning, reinforcement learning, transfer learning, online learning, batch learning, federated learning). In at least one embodiment, in addition to performing various operations described in connection with Figures 1-7 (e.g., feature extraction, 2D-3D upscaling, etc.), the neural networks or sections of the neural networks are to perform various computer vision and natural language processing (NLP) operations. In at least one embodiment, these various computer vision operations include, for example, object recognition, face recognition, image segmentation, object tracking, gesture recognition, optical character recognition, and augmented reality, either individually or in any combination.In at least one embodiment, various NLP operations include, for example, individually or in any combination, sentiment analysis, chatbot generation, speech translation, text detection, text recognition, text summarization, named entity recognition, text classification, speech recognition, text generation, and computer program generation (e.g., sets of code). In at least one embodiment, 2D acquisition module 102 is a module for acquiring one or more 2D images or 2D features. In at least one embodiment, 2D acquisition module 102 generates at least one of 2D image No. 1 112, 2D image No. 2 114, 2D image No. 3 116, and 2D image No. 4 118 using various hardware devices, including, but not limited to, digital cameras (e.g., digital single-lens reflex cameras, mirrorless cameras), smartphones, tablets, webcams, action cameras, CCTV cameras, drones, scanners, X-ray machines, magnetic resonance imaging (MRI) scanners, computed tomography (CT) scanners, ultrasound devices, satellites, space probes, and / or industrial image processing cameras. In at least one embodiment, at least one of 2D image No. 1 112, 2D image No. 2 114, 2D image No. 3 116 and 2D image No. 4 is generated using a combination of the foregoing. In at least one embodiment, 2D acquisition module 102 receives at least one of 2D image No. 1 112, 2D image No. 2 114, 2D image No. 3 116 and 2D image No. 4 118 from, for example without limitation, hard disk drives (HDD), solid-state drives (SSD), USB flash drives, external hard drives, memory cards, network attached storage (NAS), cloud storage (e.g. Dropbox, Google Drive, Microsoft OneDrive, Amazon S3), optical media (e.g. CDs, DVDs, Blu-ray discs), magnetic tape drives and / or random access memory (RAM). In at least one embodiment, at least one of 2D image No. 1 112, 2D image No. 2 114, 2D image No. 3 116 and 2D image No. 4 is generated using a combination of the foregoing. In at least one embodiment, at least two of 2D image No. 1 112, 2D image No. 2 114, 2D image No. 3 116 and 2D image No. 4 118 form a common scene which is to be analyzed by further modules described herein (e.g. 2D-to-3D module 104, 3D processing module 106, 2D image augmentation module 202, 2D feature generation module 204, 2D inversion module 206, 3D scene reconstruction module 208, 3D scene augmentation module 210, 3D feature generation module 212, 3D inversion module 214, 3D perception module 216). In at least one embodiment, 2D-to-3D module 104 is a module for performing 2D-3D uplifting. In at least one embodiment, the 2D-to-3D module 104 comprises a 2D image augmentation module 202 for generating an augmented 2D image 121 using at least one of 2D image No. 1 112, 2D image No. 2 114, 2D image No. 3 116, and 2D image No. 4 118. In at least one embodiment, one or more neural networks (e.g., a 2D feature generation module) use the augmented 2D image 121 to generate features that differ from those extractable from at least one of the original images (e.g., 2D image No. 1 112, 2D image No. 2 114, 2D image No. 3 116, and 2D image No. 4 118). In at least one embodiment, augmented 2D image 121 retains obvious patterns (e.g. cell positions) compared to at least one of 2D image No. 1 112, 2D image No. 2 114, 2D image No. 3 116 and 2D image No. 4 118. In at least one embodiment, the 2D-to-3D module comprises a 2D inversion module 206 for inverting either an augmented 2D image 121 or additional features extracted using the augmented 2D image 121 to generate inverted 2D features 122. In at least one embodiment, the inversion involves performing the opposite operation to that performed to generate the augmented 2D image 121. In at least one embodiment, the 2D-to-3D module comprises a 3D scene reconstruction module 208 for generating a 3D scene 123 using at least one augmented 2D image 121 and / or inverted 2D features 122. In at least one embodiment, the 3D scene 123 is represented in a bird's-eye view (BEV) image. In at least one embodiment, 3D processing module 106 is a module for performing one or more computer vision tasks using at least one 3D scene 123. In at least one embodiment, 3D processing module 106 comprises 3D scene augmentation module 210 for generating an augmented 3D scene 131. In at least one embodiment, 3D processing module 106 comprises 3D feature generation module 212 and 3D inversion module 214 for generating inverted 3D features 132. In at least one embodiment, inversion comprises performing an operation opposite to that performed to generate the augmented 3D scene 131. In at least one embodiment, the 3D processing module 106 uses one or more neural networks described in connection with Fig. 1 and Fig. 2 to perform one or more computer vision tasks (e.g.Object detection, instance segmentation) using at least one augmented 3D scene 131 and / or inverted 3D features 132. In at least one embodiment, the one or more computer vision tasks are further described in connection with Fig. 2. In at least one embodiment, the 3D processing module 106 is part of one or more autonomous vehicles that need to analyze scenes depicting an environment outside the one or more autonomous vehicles. In at least one embodiment, the 3D processing module 106 communicates with the one or more autonomous vehicles via wired and / or wireless communication (e.g., 5G). In at least one embodiment, the 3D processing module 106 outputs information about the results of the one or more computer vision tasks (e.g., detected objects within the scene) to the one or more autonomous vehicles. Fig. 2 illustrates an exemplary System 200 that performs computer vision tasks for higher-dimensional images based on lower-dimensional images, according to at least one embodiment. In at least one embodiment, System 200 uses one or more neural networks to identify one or more objects within one or more images based, at least partially, on one or more features of the one or more images and one or more features of one or more modified versions of the one or more images. In at least one embodiment, the modified versions refer to different images or features (e.g., 2D, 3D) that are augmented or modified. In at least one embodiment, System 200 comprises one or more processors (e.g., Processor 602), one or more storage devices, and / or a data center (e.g., Data Center 1000). In at least one embodiment, System 100 comprises a combination of the hardware and software described herein. In at least one embodiment, System 100 comprises a 2D acquisition module 102, a 2D-to-3D module 104, and a 3D processing module 106. In at least one embodiment, System 200 comprises a 2D image augmentation module 202, a 2D feature generation module 204, a 2D inversion module 206, a 3D scene reconstruction module, a 3D scene augmentation module 210, a 3D feature generation module 212, a 3D inversion module 214, and a 3D perception module 216. In at least one embodiment, the 2D image augmentation module 202 is a module for modifying one or more 2D images or features. In at least one embodiment, the 2D image augmentation module 202 receives one or more 2D images or features. In at least one embodiment, the one or more 2D images or features depict one or more scenes or environments. In at least one embodiment, the one or more 2D images are obtained from the 2D acquisition module 102 and / or the image acquisition module 610. In at least one embodiment, the one or more 2D images or features contain one or more markers that correspond to one or more pixels of the one or more 2D images or features for neural network training. In at least one embodiment, the one or more 2D images or features comprise at least eight images depicting an environment. In at least one embodiment, the 2D image augmentation module modifies one or more 2D images by performing at least one of the following operations, for example, exclusively or in combination: geometric transformations (e.g., rotation, translation, scaling, mirroring, cropping, shearing, perspective transformation), color space adjustments (e.g., brightness modification, contrast adjustment, saturation adjustment, hue modification, grayscale conversion), noise injection (e.g., adding Gaussian noise and / or random noise), affine transformations, blurring (e.g., Gaussian, median, or motion blur), sharpening, filtering (e.g., embossing, edge detection, smoothing), random erasure, occlusion, affine transformations, elastic deformations, image mixing, color dithering, histogram balancing, solarization, channel mixing, fancy PCA, and / or neural network-based modifications (e.g.,Deep learning super-sampling (DLSS), Xe super-sampling (XeSS), AMD FidelityFX Super Resolution (FSR)) and / or anti-aliasing (e.g., multi-sample anti-aliasing (MSAA), fast approximate anti-aliasing (FXAA), temporal anti-aliasing (TAA), super-sampling anti-aliasing (SSAA), conservative morphological anti-aliasing (CMAA)). In at least one embodiment, the modification includes generating one or more synthetic images using one or more neural networks (e.g., GAN) described in connection with Fig. 1. In at least one embodiment, an example of image modification includes performing a horizontal mirroring extension to predict more pedestrians on the left side of an autonomous vehicle, since the autonomous vehicle is likely to detect more pedestrians on its right side because sidewalks are typically located on the right side of the road. In at least one embodiment, another example of image extension includes a color extension to generate some images with a darker appearance, thereby improving the performance of computer vision tasks at night. In at least one embodiment, the modification includes random displacement, which refers to a technique for shifting or offsetting the image horizontally or vertically by a random number of pixels. In at least one embodiment, the random displacement serves to cause pixels that move beyond a boundary of an image on one side to re-enter the image from the opposite side. In at least one embodiment, the random displacement serves to recombine split objects detected across different images (e.g., 2D image #1 112, 2D image #2 114, 2D image #3 116, 2D image #4 118) that share a common scene or environment. In at least one embodiment, the random displacement serves to periodically return the image to its original position.In at least one embodiment, the random displacement serves to support one or more neural networks for learning features that are invariant with respect to position and thus become more robust to displacements in input data. In at least one embodiment, the modification changes at least one feature of the one or more features. In at least one embodiment, the random displacement serves to resolve a discontinuity in a polar coordinate representation that is shared by two or more images depicting a common scene. In at least one embodiment, 2D feature generation module 204 is a module that uses one or more neural networks to extract features from one or more augmented 2D images or features received by 2D image augmentation module 202. In at least one embodiment, additional neural networks for feature extraction, besides various neural networks described in connection with Fig. 1 for performing feature extraction using one or more augmented 2D images, include, without limitation, visual geometry group networks, residual networks, inception networks, densely connected CNNs, EfficientNet, MobileNet, U-Net, SqueezeNet, and / or vision transformers.In at least one embodiment, extracted features include, for example, edges, corners, color blobs, textures, parts of objects, patterns, objects, semantic content, classification, detection, category, and / or boundaries. In at least one embodiment, the one or more neural networks comprise one or more convolutional layers that perform the feature extraction. In at least one embodiment, the one or more neural networks comprise attentional modules or layers for performing the feature extraction. In at least one embodiment, 2D inversion module 206 is a module that performs the inversion of what was done in 2D image augmentation module 202. In at least one embodiment, the inversion refers to a technique for making the extracted features insensitive to positional changes and maintaining the 2D-3D relevance unchanged when the 3D scene reconstruction performs the 2D-3D uplifting. In at least one embodiment, the 2D-3D uplifting is further described in conjunction with 3D scene reconstruction module 208, image acquisition module 610, and higher-dimension generation module 612. In at least one embodiment, the inversion further refers to negating the effect of an augmentation performed by 2D image augmentation module 202. In at least one embodiment, the inversion of an affine transformation performed on a 2D image by 2D image augmentation module 202 is derived from affine properties. In at least one embodiment, the inversion for pixel removal (e.g., deletion, masking) is a zero operation. In at least one embodiment, the inversion for random translation is a translation of the image back by the same number of pixels, but in the opposite direction. In particular, in at least one embodiment, the inversion includes determining the translation amount and direction, performing the translation using various libraries (e.g., OpenCV, NumPy), and managing the periodic pixel translation. In at least one embodiment, inversion is the inverse of a chain of operations performed by 2D image augmentation module 202 to perform 2D image extension. For example, in at least one embodiment, when 2D image augmentation module 202 has performed a series of operations, such as random_resize => random_crop => random_shift, 2D inversion module 206 receives such information associated with the series of operations and performs inverted_random_shift => inverted_random_crop => inverted_random_resize. In at least one embodiment, 2D inversion module 206 determines one or more operations for an extension to be performed on the modified 2D image.In at least one embodiment, a further example of inverting includes shifting features 10 pixels to the right, where a modification performed by 2D image augmentation module 202 is a shifting of features 10 pixels to the left. In at least one embodiment, the inversion comprises P = R(F(A(I))), where A is a feature or image extension and R is an inverted feature extension, F is a feature extraction, I are input features and P are output features. In at least one embodiment, 3D scene reconstruction module 208 is a module that performs 2D-3D uplifting. In at least one embodiment, 2D-3D uplifting comprises using intrinsic and extrinsic camera parameters to combine 2D image coordinates (e.g., polar, Cartesian) and 3D coordinates. In at least one embodiment, 2D-3D uplifting comprises estimating depth using one or more augmented 2D images or features from 2D image augmentation module 202, one or more extracted features from 2D feature generation module 204, and / or one or more inverted 2D images or features from 2D inversion module 206. In at least one embodiment, the depth estimation includes, for example, monocular depth estimation and / or stereoscopic depth estimation.In at least one embodiment, 3D scene reconstruction module 208 generates a point cloud by transforming pixel coordinates and their corresponding depth values ​​into 3D points in space, a mesh model by connecting adjacent points in the point cloud, and / or a voxel grid with depth-based values ​​that references a 3D scene. In at least one embodiment, 3D scene reconstruction module 208 generates a 3D feature map. In at least one embodiment, the 3D scene reconstruction module 208 integrates reconstructed 3D images using data from LiDAR or depth cameras for a more precise and detailed representation. In at least one embodiment, the 3D scene reconstruction module 208 uses one or more neural networks to perform 2D-3D uplifting based on one or more augmented 2D images or features from the 2D image augmentation module 202, one or more extracted features from the 2D feature generation module 204, and / or one or more inverted 2D images or features from the 2D inversion module 206. In at least one embodiment, the 3D scene reconstruction module 208 reconstructs 3D images while retaining information from the one or more features corresponding to the 2D images or features used to reconstruct the 3D images.In at least one embodiment, reconstructed 3D images include stereoscopic images, anaglyph 3D images, volumetric images, 3D-rendered images, point clouds, depth maps, holographic images, lens prints, and / or 360-degree images, as well as BEV (e.g., images or features). In at least one embodiment, reconstructed 3D images include coordinates (e.g., polar, cylindrical, spherical, homogeneous, barycentric, parabolic, Cartesian). In at least one embodiment, a reconstructed 3D image may refer to 3D representations that include 3D scenes, extracted 3D features, BEV features, BEV images, voxels, point clouds, and meshes. In at least one embodiment, the 3D scene reconstruction module 208 uses a lookup table without requiring its recalculation because the 2D inversion module back-inverts extracted 2D features from augmented images or features, whereas recalculating the lookup tables would be computationally expensive and complex. In at least one embodiment, the lookup tables include a mapping of the positions of 2D feature cells onto 3D space. For example, in at least one embodiment, the mapping includes information such as that cell in row 20, column 30 of the front camera features is mapped to BEV features at a distance of 20 meters with an azimuth angle of 10 degrees. In at least one embodiment, the reconstructed 3D scene is represented by the feature map. In at least one embodiment, one or more neural networks are used for 2D-3D uplifting. For example, CNNs can be adapted to understand the spatial hierarchies in images and to help derive 3D structures from 2D data. In at least one embodiment, GANs include a generator that creates 3D images and a discriminator that evaluates the generated 3D images. In at least one embodiment, autoencoders (e.g., variational autoencoders) encode 2D images into a latent space and then decode the representation into a 3D image. In at least one embodiment, GNNs are used to understand relationships between different features extracted by 2D feature generation module 204 and / or 2D inversion module 206. In at least one embodiment, other neural networks, such as 3D CNNs, RNNs, LSTMs, and / or transformers, can be used alone or in combination. In at least one embodiment, 3D scene augmentation module 210 is a module that modifies reconstructed 3D images from 3D scene reconstruction module 208. In at least one embodiment, the modification includes, for example, rotation, translation, scaling, mirroring, cropping, jittering, noise injection, color enhancement, elastic deformation, sampling, affine transformations, mesh deformation, and random occlusion, either exclusively or in combination. In at least one embodiment, 3D feature generation module 212 is a module that extracts features from one or more reconstructed 3D images from the 3D scene reconstruction module 208 and / or one or more augmented reconstructed 3D images from the 3D scene augmentation module 210. In at least one embodiment, 3D feature generation module 212 uses one or more neural networks described in connection with Fig. 1 to extract one or more features from the one or more reconstructed 3D images and / or the one or more augmented reconstructed 3D images. In at least one embodiment, the 3D feature generation module 212 uses additional neural networks for feature extraction, such as, but not limited to, 3D CNNs, PointNet, VoxelNet, graph convolutional networks, multi-view CNNs, submanifold sparse convolutional networks, 3D-U-Net, OctNet, Minkowski engine, and dynamic graph CNN. In at least one embodiment, the extracted features include, for example, edges, corners, surface curvatures, local textures, shapes, structures, relative positioning and orientation, objects, components of a complex structure (e.g., the main body of a vehicle), semantic features (e.g., cars versus pedestrians or different tissues in medical imaging), scene understanding, hierarchical structures, and segmentations. In at least one embodiment, the one or more neural networks comprise one or more convolutional layers that perform 3D feature extraction.In at least one embodiment, the one or more neural networks comprise attention modules or layers to perform 3D feature extraction. In at least one embodiment, 3D inversion module 214 is a module that performs the inversion of what was done in 3D image augmentation module 210. In at least one embodiment, 3D inversion module 214 receives one or more augmented reconstructed 3D images from 3D scene augmentation module 210 and / or extracted 3D features from 3D feature generation module 212. In at least one embodiment, inversion refers to a technique for causing the extracted features to increase the size of the training dataset for 3D image inference, reduce overfitting, and improve the versatility of one or more neural networks for 3D image inference. In at least one embodiment, the inversion further refers to negating an effect of an augmentation performed by 3D scene augmentation module 210 to correspond to features of non-augmented images.For example, in at least one embodiment, a feature cell position that has been modified by 3D inversion module 214 can correspond to a 3D image reconstructed by 3D scene reconstruction module 208. In at least one embodiment, the inversion for an affine transformation performed in a 3D image by 3D image augmentation module 210 is derived from affine properties. In at least one embodiment, the inversion for pixel removal (e.g., deletion, masking) is a zero operation. In at least one embodiment, the inversion comprises P = R(F(A(I))), where A is a feature extension and R is an inverted feature extension, F is a feature extraction, I are input features, and P are output features. In at least one embodiment, if a 3D image or point cloud has been rotated about an axis, the inverse operation would involve rotating it by the same angle but in the opposite direction. In at least one embodiment, for a 3D image that has been translated (offset) in any direction, the inverse operation would involve translating the image back in the opposite direction by the same distance. In at least one embodiment, if the 3D data has been scaled up or down, inverting this extension would involve scaling it by the inverse of the original scaling factor. In at least one embodiment, for a 3D image that has been reflected across a plane, the inverse operation would simply reflect it back across the same plane.In at least one embodiment, the 3D inversion module 214, to perform inverse cropping, places the cropped portion back into its original position in the complete image, with the remainder of the image likely being filled with zeros or some form of background data. In at least one embodiment, if points in a 3D point cloud have been artificially disturbed by the addition of random noise, inverting the noise would involve removing it. In at least one embodiment, for color extensions such as brightness, contrast, or saturation adjustments, inversion would involve applying inverse adjustments, such as decreasing by the same factor during the inversion. In at least one embodiment, the 3D perception module 216 is a module that incorporates various task heads for different 3D perception tasks. In at least one embodiment, the task heads are configured to generate predictions that correspond to the desired 3D perception tasks. In at least one embodiment, the 3D perception module 216 uses one or more neural networks, as described in connection with Fig. 1, to perform one or more computer vision tasks using at least one different input received from the 2D image augmentation module 202, the 2D feature generation module 204, the 2D inversion module 206, the 3D scene reconstruction module 208, the 3D scene augmentation module 210, the 3D feature generation module 212, and / or the 3D inversion module 214.In at least one embodiment, 3D perception module 216 uses inverted 3D features extracted from 3D inversion module 214, 3D features extracted from 3D feature generation module 212, and / or augmented reconstructed 3D images from 3D scene augmentation module 210. In at least one embodiment, 3D perception module 216 uses additional neural networks for various computer vision tasks, such as, but not limited to, 3D object detection, 3D object classification, 3D semantic segmentation, 3D instance segmentation, 3D reconstruction, point cloud processing, depth estimation, human pose estimation, medical image analysis (e.g., tumor detection, organ segmentation, surgical planning), scene understanding, 3D face recognition, 3D texture mapping, motion analysis and tracking in 3D, and / or lidar and radar processing. In at least one embodiment, the further neural networks include, for example, without limitation, 3D-CNNs, PointNet, VoxelNet, graph convolutional networks, multi-view CNNs, submanifold sparse convolutional networks, 3D-U-Net, OctNet, Minkowski engine and dynamic graph CNN. In at least one embodiment, System 200 is a neural network that can be trained as a whole. In at least one embodiment, each module of System 200 is a separate neural network that must be trained individually. In at least one embodiment, different combinations of each module can be trained together as a single neural network. Fig. 3 illustrates an exemplary process 300 that performs computer vision tasks for higher-dimensional images based on lower-dimensional images according to at least one embodiment. In at least one embodiment, process 300 uses one or more neural networks to identify one or more objects within one or more images based, at least partially, on one or more features of the one or more images and one or more features of one or more modified versions of the one or more images.Although exemplary process 300 is presented as a series of steps or operations, it is understood that at least one embodiment of process 300 includes modified or reordered steps or operations, or omits certain steps or operations, except as explicitly noted or logically required, such as when an output of one step or operation is used as input for another. In at least one embodiment, each block of process 300 described herein is performed individually or in any combination by one or more entities described in connection with Figures 1, 2, and 6. In at least one embodiment, one or more entities further include, for example, hardware, firmware, and / or software described herein that, individually or in any combination, performs Process 300. In at least one embodiment, various functions are performed by a processor that executes instructions stored in memory (e.g., computer-readable, machine-readable) to perform Process 300. In at least one embodiment, Process 300 may also be implemented as computer-readable instructions (e.g., macro instruction, micro instruction) stored on computer storage media or provided by a standalone application, service, or hosted service (alone or in combination with another hosted service). In at least one embodiment, the instructions are performed by at least one processor (e.g.,Processor 602) executes computer-readable instructions through one or more programming models (e.g., CUDA, oneAPI, ROCm). In at least one embodiment, Processor 602 executes one or more blocks of Process 300. In at least one embodiment, one or more APIs 710 or a software program 702 executes one or more blocks of Process 300, individually or in combination. In 302, the one or more entities acquire two or more low-dimensional (e.g., 2D) images according to at least one embodiment. In at least one embodiment, the one or more entities use 2D Acquisition Module 102 and / or Image Acquisition Module 610 to acquire the two or more low-dimensional images. In at least one embodiment, two or more low-dimensional images share a common scene. In at least one embodiment, the two or more low-dimensional images comprise one or more feature maps. In 304, the one or more entities generate two or more higher-dimensional (e.g., 3D) images using lower-dimensional images according to at least one embodiment. In at least one embodiment, the one or more entities use 2D-to-3D Module 104 to generate the higher-dimensional images. In at least one embodiment, the higher-dimensional images include BEV features. In at least one embodiment, the one or more entities use 2D Image Augmentation Module 202, 2D Feature Generation Module 204, 2D Inversion Module 206, and / or 3D Scene Reconstruction Module 208 to generate the higher-dimensional images. In at least one embodiment, the one or more entities reconstruct 4D images by adding a temporal dimension to 3D image data, wherein the temporal dimension includes information about how objects detected in the 3D image data change over time. In at least one embodiment, the one or more units acquire or generate 3D data at multiple time points using, for example, 4D CT or MRI scans or motion capture systems. In at least one embodiment, the one or more units align 3D data (e.g., by performing registration or normalization) to maintain consistency. In at least one embodiment, the one or more entities reconstruct 4D images using such inputs or, alternatively, using one or more neural networks (e.g., GAN, CNN). In 306, the one or more entities extend the higher-dimensional features according to at least one embodiment. In at least one embodiment, the one or more entities use the 3D scene augmentation module 210 to modify the higher-dimensional features. In at least one embodiment, the extension for the reconstructed 4D images includes temporal shifts, temporal velocity adjustment, temporal jittering, 4D rotation, temporal slicing, noise injection in temporal and spatial dimensions, 4D elastic deformation, morphological transformations in 4D, temporal interpolation or extrapolation, 4D color extension, synthetic event insertion, and / or 4D mirroring. In at least one embodiment, the one or more entities perform one or more computer vision tasks using augmented higher-dimensional features. In at least one embodiment, the one or more entities use one or more neural networks to perform the computer vision tasks. In at least one embodiment, the computer vision tasks include, for example, object detection, image classification, and / or depth estimation, individually or in any combination. In at least one embodiment, the computer vision tasks include various tasks described in connection with Fig. 1. In at least one embodiment, one or more entities use 3D perception module 216 to perform the computer vision tasks. In at least one embodiment, one or more entities use computer vision module 616 to perform the computer vision tasks.In at least one embodiment, the one or more entities use inputs generated by the 3D feature extraction module 212, the 3D inversion module 214 and / or the 3D perception module 216 to perform the one or more computer vision tasks. In at least one embodiment, the one or more computer vision tasks further include, without limitation, the analysis of medical 4D image data, 4D motion analysis and tracking, 4D scene understanding, the processing of time-dependent point clouds, 4D face recognition and facial expression analysis, temporal segmentation and classification, 4D weather and environmental modeling, and 4D flow visualization and analysis. In at least one embodiment, at least one of steps 302, 304, 306 and / or 308 consists of using one or more neural networks to identify one or more objects within one or more images based, at least partially, on one or more features of the one or more images and one or more features of one or more modified versions of the one or more images. Fig. 4 illustrates an exemplary Process 400 that performs computer vision tasks for higher-dimensional images based on lower-dimensional images according to at least one embodiment. In at least one embodiment, Process 400 uses one or more neural networks to identify one or more objects within one or more images based, at least partially, on one or more features of the one or more images and one or more features of one or more modified versions of the one or more images.Although exemplary process 400 is presented as a sequence of steps or operations, I understand that at least one embodiment of process 400 includes modified or rearranged steps or operations, or omits certain steps or operations unless expressly stated or logically required, for example, when the output of one step or operation is used as input for another. In at least one embodiment, each block of process 400 described herein is performed individually or in any combination by one or more entities described in connection with Figures 1, 2, and 6. In at least one embodiment, one or more entities further comprise, for example, hardware, firmware, and / or software described herein that executes Process 400 individually or in any combination. In at least one embodiment, various functions are performed by a processor that executes instructions stored in memory (e.g., computer-readable, machine-readable) to perform Process 400. In at least one embodiment, Process 400 may also be implemented as computer-readable instructions (e.g., macro instruction, micro instruction) that are stored on computer storage media or provided by a standalone application, service, or hosted service (alone or in combination with another hosted service). In at least one embodiment, the instructions are performed by at least one processor (e.g.,Processor 602) executes computer-readable instructions through one or more programming models (e.g., CUDA, oneAPI, ROCm). In at least one embodiment, Processor 602 executes one or more blocks of Process 400. In at least one embodiment, one or more APIs 710 or a software program 702 executes one or more blocks of Process 400, individually or in combination. In embodiment 402, the one or more entities receive two or more 2D images according to at least one embodiment. In at least one embodiment, the one or more entities use the 2D Acquisition Module 102 or the Image Acquisition Module 610 to receive the two or more 2D images. In embodiment 404, the one or more entities modify two or more received 2D images according to at least one embodiment. In at least one embodiment, the one or more entities use the 2D Image Augmentation Module 202 to modify the received two or more 2D images. In 406, one or more entities according to at least one embodiment generate one or more 2D features using one or more modified 2D images. In at least one embodiment, the one or more entities use the 2D feature generation module 204 to modify the received two or more 2D images. In 408, the one or more entities according to at least one embodiment invert one or more 2D features and one or more modified 2D images. In at least one embodiment, the inversion includes modifying the one or more 2D features to match one or more cell positions of the one or more features with one or more cell features of two or more 2D images.In at least one embodiment, the one or more entities use the 2D inversion module 206 to invert the one or more 2D features and one or more modified 2D images. In 410, the one or more entities, according to at least one embodiment, generate one or more 3D representations using two or more received 2D images, one or more generated 2D features, and / or one or more inverted 2D features. In at least one embodiment, the one or more entities use the 3D scene reconstruction module 208 to generate the one or more 3D representations. In at least one embodiment, the one or more 3D representations include, without limitation, 3D scenes, extracted 3D features, BEV features, BEV images, voxels, cloud points, and meshes.In at least one embodiment, at least one of steps 402, 402, 406, 408 and / or 410 consists of using one or more neural networks to identify one or more objects within one or more images based, at least partially, on one or more features of the one or more images and one or more features of one or more modified versions of the one or more images. Fig. 5 illustrates an exemplary process 500 that performs computer vision tasks for higher-dimensional images based on lower-dimensional images according to at least one embodiment. In at least one embodiment, process 500 uses one or more neural networks to identify one or more objects within one or more images based, at least partially, on one or more features of the one or more images and one or more features of one or more modified versions of the one or more images.Although exemplary process 500 is presented as a sequence of steps or operations, it is understood that at least one embodiment of process 500 includes modified or rearranged steps or operations, or omits certain steps or operations unless expressly stated or logically required, for example, when the output of one step or operation is used as input for another. In at least one embodiment, each block of process 500 described herein is performed individually or in any combination by one or more entities described in connection with Figures 1, 2, and 6. In at least one embodiment, one or more entities further comprise, for example, hardware, firmware, and / or software described herein that executes Process 500 individually or in any combination. In at least one embodiment, various functions are performed by a processor that executes instructions stored in memory (e.g., computer-readable, machine-readable) to perform Process 500. In at least one embodiment, Process 500 may also be implemented as computer-readable instructions (e.g., macro instruction, micro instruction) that are stored on computer storage media or provided by a standalone application, service, or hosted service (alone or in combination with another hosted service). In at least one embodiment, the instructions are performed by at least one processor (e.g.,Processor 602) executes computer-readable instructions through one or more programming models (e.g., CUDA, oneAPI, ROCm). In at least one embodiment, Processor 602 executes one or more blocks of Process 500. In at least one embodiment, one or more APIs 710 or a software program 702 executes one or more blocks of Process 700, individually or in combination. In 502, the one or more entities modify one or more 3D representations according to at least one embodiment. In at least one embodiment, the one or more 3D representations are generated by executing step 410. In at least one embodiment, the one or more 3D representations include, without limitation, 3D scenes, extracted 3D features, BEV features, BEV images, voxels, cloud points, and meshes. In at least one embodiment, the one or more entities use the 3D scene augmentation module 210 to modify the one or more 3D representations. In 504, the one or more entities generate one or more additional 3D features using one or more modified 3D representations, according to at least one embodiment.In at least one embodiment, the one or more entities use the 3D feature generation module 212 to generate the one or more additional 3D features. In 506, according to at least one embodiment, the one or more entities invert one or more modified 3D representations and / or one or more additional 3D features. In at least one embodiment, the one or more entities use the 3D inversion module 214 to invert the one or more modified 3D representations and / or the one or more additional 3D features. In at least one embodiment, the inversion includes modifying the one or more additional 3D features to align one or more cell positions of the one or more additional 3D features with one or more cell positions of the one or more 3D representations prior to the modification performed in step 502. In at least one embodiment, the inversion includes reversing what was done to generate the one or more modified 3D representations on the additional one or more 3D features. In 508, the one or more entities use one or more neural networks to perform one or more computer vision tasks based on the one or more 3D representations (either modified or original), the one or more additional 3D features, and / or one or more inverted versions of either one or both, according to at least one embodiment. In at least one embodiment, the computer vision tasks include, for example, object detection, image classification, and / or depth estimation, individually or in any combination. In at least one embodiment, the computer vision tasks include various tasks described in connection with Fig. 1. In at least one embodiment, the neural networks include various neural networks described in connection with Fig. 1.In at least one embodiment, one or more entities use 3D perception module 216 to perform the computer vision tasks. In at least one embodiment, one or more entities use computer vision module 616 to perform the computer vision tasks. In at least one embodiment, at least one of steps 502, 504, 506, and / or 508 consists of using one or more neural networks to identify one or more objects within one or more images based, at least partially, on one or more features of the one or more images and one or more features of one or more modified versions of the one or more images. Fig. 6 illustrates an exemplary System 600 that performs computer vision tasks for higher-dimensional images based on lower-dimensional images, according to at least one embodiment. In at least one embodiment, System 600 uses one or more non-volatile machine-readable media on which a set of instructions is stored which, when executed by one or more processors (e.g., Processor 602), cause the one or more processors to perform higher-dimensional computer vision tasks using lower-dimensional images.In at least one embodiment, the system 600 comprises a processor 602 which uses one or more neural networks to identify one or more objects within one or more images based, at least partially, on one or more features of the one or more images and one or more features of one or more modified versions of the one or more images. In at least one embodiment, the processor 602 is part of the data center 1000. In at least one embodiment, the processor 602 is part of a CPU (e.g., CPU 1106, CPU 1118) and / or is a processor 1110. In at least one embodiment, the processor 602 is either part of a CPU 1180(A) or a CPU 1180(B). In at least one embodiment, the processor 602 is a processor 1202. In at least one embodiment, the processor 602 is the processor 1310. In at least one embodiment, the processor 602 is part of a CPU 1402. In at least one embodiment, the processor 602 is part of a computer 1510. In at least one embodiment, the processor 602 is one of the multi-core processors 1605(1) ... 1605(M). In at least one embodiment, processor 602 is processor 1607. In at least one embodiment, processor 602 is application processor 1705. In at least one embodiment, processor 602 is processor 2002.In at least one embodiment, processor 602 is processor 2202. In at least one embodiment, processor 602 is processor 2400. In at least one embodiment, processor 602 is processor 2702. In at least one embodiment, processor 602 is processor 2800. In at least one embodiment, the processor 602 is part of the GPU 1118 or the GPU 1120. In at least one embodiment, the processor 602 is part of any one of the GPUs 1184(A) ... 1184(H). In at least one embodiment, the processor 602 is part of the graphics card 1212. In at least one embodiment, the processor 602 is part of the parallel processing unit 1414. In at least one embodiment, the processor 602 is part of any one of the GPUs 1610(1) ... (N). In at least one embodiment, the processor 602 is part of the graphics acceleration module 1646. In at least one embodiment, the processor 602 is part of the graphics processor 1710. In at least one embodiment, the processor 602 is part of the graphics processor 1810. In at least one embodiment, the processor 602 is part of the graphics processor 1840. In at least one embodiment, the processor 602 comprises at least one graphics core 1900.In at least one embodiment, the processor 602 is part of a general-purpose graphics processing unit (GPGPU) 1930. In at least one embodiment, the processor 602 is the parallel processor 2012. In at least one embodiment, the processor 602 is a parallel processor 2100. In at least one embodiment, the processor 602 is a graphics multiprocessor 2132. In at least one embodiment, the processor 602 is part of one of the GPGPUs 2206A ... 2206D. In at least one embodiment, the processor 602 is a graphics processor 2300. In at least one embodiment, the processor 602 is part of the deep learning application processor 2500. In at least one embodiment, the processor 602 is part of the neuromorphic processor 2600. In at least one embodiment, the processor 602 is a graphics processor 2708. In at least one embodiment, the processor 602 is an integrated graphics processor 2808.In at least one embodiment, the processor 602 is a graphics processor 2900. In at least one embodiment, the processor 602 is part of the graphics processing engine 3010 described herein. In at least one embodiment, the processor 602 is one of the shader processors 3107A ... 3107F described herein. In at least one embodiment, the processor 602 is the shader processor 3202. In at least one embodiment, the processor 602 is connected to the graphics execution unit 3208. In at least one embodiment, the processor 602 is part of the parallel processing unit (PPU) 3300. In at least one embodiment, the processor 602 is part of a general-purpose processor cluster (GPC) 3400. In at least one embodiment, the processor 602 is a streaming multiprocessor 3600. In at least one embodiment, the processor 602 is part of the hardware 3722.In at least one embodiment, processor 602 executes the model training system 3704. In at least one embodiment, processor 602 is processor 4206. In at least one embodiment, the processor 602 is used to implement at least one section of system 100 and / or system 200. In at least one embodiment, the processor 602 is used to perform at least one step of process 300, process 400, and / or process 500. In at least one embodiment, the processor 602 comprises an image acquisition module 610, a higher-dimension generation module 612, a higher-dimension modification module 614 and a computer vision module 616. In at least one embodiment, the image acquisition module 610 is a module that acquires and processes one or more images. In at least one embodiment, the image acquisition module 610 comprises the 2D acquisition module 102.In at least one embodiment, the image acquisition module 610 captures 3D images by capturing the 3D structure and appearance of objects or environments. In at least one embodiment, the image acquisition module 610 includes depth sensors such as LiDAR, structured light, and time-of-flight (ToF) sensors for determining depth. In at least one embodiment, the image acquisition module 610 includes one or more cameras arranged at different angles to capture multiple views of a scene, similar to how binocular vision in humans works for depth perception. In at least one embodiment, the image acquisition module 610 includes one or more illumination systems that project a known pattern (e.g., grid, stripes) onto a scene.In at least one embodiment, the image acquisition module 610 uses one or more algorithms that employ depth calculation, image matching, and / or the generation of 3D point clouds to acquire 3D images. In at least one embodiment, the image acquisition module 610 uses software that utilizes techniques such as photogrammetry, noise reduction, and / or smoothing to acquire or modify an acquired 3D image. In at least one embodiment, the image acquisition module 610 uses one or more neural networks, as described in conjunction with Fig. 1, to acquire 3D images. In at least one embodiment, the higher-dimensionality generation module 612 is a module that generates higher-dimensional images (e.g., 3D images). In at least one embodiment, the higher-dimensionality generation module 612 comprises the 2D-to-3D module 104. In at least one embodiment, the higher-dimensionality generation module 612 comprises the 2D image augmentation module 202, the 2D feature generation module 204, the 2D inversion module 206, and / or the 3D scene reconstruction module. In at least one embodiment, the higher-dimensionality generation module 612 performs feature extraction from 2D images. In at least one embodiment, the higher-dimensionality generation module 612 modifies the 2D images or 2D features before performing the feature extraction. In at least one embodiment, the modification includes, for example, affine transformation (e.g., translation, resizing, rotation, cropping, mirroring), pixel removal (e.g., deletion, masking), and color enhancement (e.g., color jittering, color balancing), either alone or in combination. In at least one embodiment, feature extraction is performed using one or more neural networks, as described in connection with Fig. 1. In at least one embodiment, the higher-dimension generation module 612 performs an inverted feature extension using the extracted features generated from the feature extraction. In at least one embodiment, the inverted feature extension can be expressed as P = R(F(A(I))), where F is said feature extraction, A is the image or feature extension, P is the output, and I is the input. In at least one embodiment, the feature extension includes reversing what was done in the extension.In at least one embodiment, the higher-dimensionality generation module 612 reconstructs 3D or 4D images, based at least partially on inverted features, features from augmented images, or augmented features and / or original images, using one or more neural networks as described in conjunction with Fig. 1. In at least one embodiment, the reconstruction of the 3D images is based on extracted features, BEV transformation by considering parameters such as focal length, sensor size, and relative position of cameras, depth estimation, and linking of coordinates between 2D images and the 3D images to be reconstructed. In at least one embodiment, the higher-dimensional modification module 614 is a module that modifies generated or received higher-dimensional images. In at least one embodiment, the higher-dimensional generation module 612 comprises the 2D-to-3D module 104. In at least one embodiment, the higher-dimensional generation module 612 comprises the 3D feature generation module 212 and / or the 3D inversion module 214. In at least one embodiment, the higher-dimension modification module 614 extracts one or more features from reconstructed 3D images or features using one or more neural networks, as described in connection with Fig. 1. In at least one embodiment, the higher-dimension modification module 614 modifies the reconstructed 3D features or images, for example, alone or in combination, by scaling, translation, rotation, jittering, mirroring, inversion, cropping, distortion, sampling, color enhancement, noise injection, volumetric enhancement, mesh deformation, elastic deformation, and random displacement.In at least one embodiment, random displacement parameters include, for example, max_rotation_degree: 5, max_translate_ratio: [0.05; 0.05], and resize_ratio: [0.97; 1.03], where max_rotation_degree refers to the maximum rotation angle when applying a random rotation extension, max_translate_ratio refers to the maximum translation ratios with respect to image height and width when applying a random translation extension, and resize_ratio refers to the maximum scaling ratios when applying a random scaling extension. In at least one embodiment, the random displacement includes adapted extension operations to shift the degrees (from 359 and 0 degrees). In at least one embodiment, the higher-dimension modification module 614 further extracts features based on the modified reconstructed 3D features or images using one or more neural networks described in connection with Fig. 1. In at least one embodiment, the higher-dimension modification module 614 performs an inversion of what was done to the modified reconstructed 3D features or images and applies this inversion to the further extracted features, the further extracted features being available for use by the computer vision module 616 to perform various computer vision tasks. In at least one embodiment, the inversion includes matching cell positions with non-augmented images. In at least one embodiment, the computer vision module 616 is a module that uses one or more neural networks to perform one or more computer vision tasks based on data generated by the image acquisition module 610, higher-dimension generation module 612, and / or the higher-dimension modification module 614. For example, the computer vision module 616 performs one or more computer vision tasks using the reconstructed 3D images or features, the modified reconstructed 3D images or features, the further extracted features, and / or the inverted further extracted features. In at least one embodiment, the computer vision tasks include, for example, object detection, image classification, and / or depth estimation, individually or in any combination. In at least one embodiment, the computer vision tasks include various tasks related to Fig.1. In at least one embodiment, the neural networks comprise various neural networks, which are described in connection with Fig. 1. In at least one embodiment, the computer vision module 616 comprises the 3D processing module 106. In at least one embodiment, the computer vision module 616 comprises the 3D perception module 216. Fig. 7 illustrates an exemplary System 700 that performs computer vision tasks for higher-dimensional images based on lower-dimensional images, according to at least one embodiment. In at least one embodiment, System 700 uses one or more neural networks to identify one or more objects within one or more images based, at least partially, on one or more features of the one or more images and one or more features of one or more modified versions of the one or more images. In at least one embodiment, a software program 702 is a module described in connection with Fig. 1. In at least one embodiment, a software program 702 comprises one or more modules. In at least one embodiment, one or more APIs 710 comprise the API described in connection with Fig. 1. In at least one embodiment, one or more APIs 710 are sets of software instructions that, when executed, cause one or more processors to perform one or more arithmetic operations. In at least one embodiment, one or more APIs 710 refer to a reusable block of code that performs a specific task and is capable of receiving data, processing it, and returning a result.In at least one embodiment, the reusable code block refers to the fact that one or more APIs 710 can be called multiple times within the software program 702, possibly with different input values, to perform their specified action without requiring the same code to be written repeatedly. In at least one embodiment, one or more APIs 710 are distributed or otherwise provided as part of one or more libraries 706, runtimes 704, drivers 704, and / or any other grouping of software and / or executable code further described herein. In at least one embodiment, one or more APIs 710 perform one or more computational operations in response to a call by the software program 702. In at least one embodiment, a software program 702 is a collection of software code, commands, instructions, or other text sequences for instructing a computing device (comprising processors such as processor 702) to perform one or more arithmetic operations and / or to call one or more other sets of instructions, such as APIs 710 or API functions 712, for execution. In at least one embodiment, the functionality provided by one or more APIs 710 includes the software functions 712, such as those that can be used to accelerate one or more sections of software programs 702 using one or more parallel processing units (PPUs), such as graphics processing units (GPUs). In at least one embodiment, a software program is a compiler. In at least one embodiment, one or more APIs 710 are one or more hardware interfaces to one or more circuits for performing one or more arithmetic operations. In at least one embodiment, one or more of the software APIs 710 described herein are implemented as one or more circuits for performing one or more of the techniques described in connection with Figures 1-6. In at least one embodiment, one or more software programs 702 comprise instructions which, when executed, cause one or more hardware devices and / or circuits to perform one or more techniques described above in connection with Figures 1-6. In at least one embodiment, software programs 702, such as user-implemented software programs, utilize one or more APIs 710 to perform various computational operations, such as memory allocation, matrix multiplication, arithmetic operations, or any computational operation performed by parallel processing units (PPUs), such as graphics processing units (GPUs), as further described herein. In at least one embodiment, one or more APIs 710 provide a set of callable functions 712, referred to herein as APIs, API functions, and / or functions, which individually perform one or more computational operations, such as computational operations related to parallel computing.In at least one embodiment, one or more APIs 710 provide functions 712 for using one or more neural networks to identify one or more objects within one or more images based, at least partially, on one or more features of the one or more images and one or more features of one or more modified versions of the one or more images. In at least one embodiment, one or more APIs 710 provide functions 712 for causing a neural network to perform one or more operations, for example, by returning a called function to a processor, wherein the processor calls the neural network. In at least one embodiment, the processor is the processor 702. In at least one embodiment, the neural network is one of the neural networks described in connection with Fig. 1. In at least one embodiment, one or more software programs 702 interact or otherwise communicate with one or more APIs 710 to perform one or more computational operations using one or more PPUs, such as GPUs. In at least one embodiment, one or more computational operations using one or more PPUs comprise at least one or more groups of computational operations that are to be accelerated by at least partial execution by the one or more PPUs. In at least one embodiment, one or more software programs 702 interact with one or more APIs 710 to facilitate parallel computing using a remote or local interface. In at least one embodiment, an interface consists of software instructions that, when executed, provide access to one or more functions 712 provided by one or more of the APIs 710. In at least one embodiment, a software program 702 uses a local interface when a software developer compiles one or more software programs 702 in conjunction with one or more libraries 706 that include or otherwise provide access to one or more APIs 710. In at least one embodiment, one or more software programs 702 are compiled statically in conjunction with precompiled libraries 706 or uncompiled source code that includes instructions for executing one or more APIs 710.In at least one embodiment, one or more software programs 702 are dynamically compiled, and said one or more software programs use a linker to establish a link to one or more precompiled libraries 706 comprising one or more APIs 710. In at least one embodiment, a software program 702 uses a remote interface when a software developer executes a software program that uses or otherwise communicates with a library 706, including one or more APIs 710, over a network or other remote communication medium. In at least one embodiment, one or more libraries 706, comprising one or more APIs 710, are executed by a remote computing service, such as a computing resource provider. In another embodiment, one or more libraries 706, comprising one or more APIs 710, are executed by any other computing host that provides said one or more APIs 710 to one or more software programs 702.In at least one embodiment, one or more libraries include, for example, the Intel Math Kernel Library (MKL), the Intel Data Analytics Acceleration Library (DAAL), the Intel Integrated Performance Primitives (IPP), the Intel Threading Building Blocks (TBB), the Intel oneAPI DPC++ / C++ compiler Zen Software Studio, the ROCm Hub, the Vitis Software Platform and Vitis AI. In at least one embodiment, one or more software programs 702 utilize one or more APIs 710 to allocate and otherwise manage memory to be used by the software programs 702. In at least one embodiment, one or more software programs 702 utilize one or more APIs 710 to allocate and otherwise manage memory to be used by one or more sections of the software programs 702 for acceleration using one or more PPUs, such as GPUs, or any other accelerator or processor further described herein. These software programs 702 instruct a neural network to generate one or more sections of the image based, at least partially, on one or more sections of the image. In at least one embodiment, one or more APIs 710 comprise an API for facilitating parallel computing. In at least one embodiment, an API 710 is any other API described herein. In at least one embodiment, an API 710 is provided by a driver and / or runtime 704. In at least one embodiment, an API 710 is provided by a CUDA user-mode driver. In at least one embodiment, an API 710 is provided by a CUDA runtime. In at least one embodiment, a driver 704 comprises data values ​​and software instructions that, when executed, perform and / or otherwise facilitate the operation of one or more of the functions 712 of an API 710 during the loading and execution of one or more sections of at least one software program 702.In at least one embodiment, the driver 704 includes, for example, Intel graphics drivers, Intel chipset drivers, Intel network adapter drivers, Intel audio drivers, drivers for Intel Movidius VPUs and / or Intel Nervana neural network processors, and drivers that work with ADMD software: PRO Edition, AMD Radeon ProRender, AMD software: Adrenalin Edition, AMD Ryzen Master Utility, AMD StoreMI technology, and AMD ROCm. In at least one embodiment, a runtime 704 comprises data values ​​and software instructions that, when executed, perform one or more functions 712 of an API 710 during the execution of a software program 702 or otherwise facilitate its operation. In at least one embodiment, the runtime X04 includes the Intel Graphics Runtime, the Intel oneAPI Runtime, and the AMD Radeon Open Compute Platform.In at least one embodiment, one or more software programs 702 utilize one or more APIs 710, which are implemented or otherwise provided by a driver and / or a runtime 704, to perform combined arithmetic operations by said one or more software programs 702 during execution by one or more PPUs, such as GPUs. In at least one embodiment, one or more software programs 702 utilize one or more APIs 710 provided by a driver and / or a runtime 704 to perform combined arithmetic operations from one or more PPUs, such as GPUs. In at least one embodiment, one or more APIs 710 provide combined arithmetic operations via a driver and / or a runtime 704, as described above. In at least one embodiment, one or more software programs 702 utilize one or more APIs 710 provided by a driver and / or a runtime 704 to allocate or otherwise reserve one or more blocks of memory 714 of one or more PPUs, such as GPUs.In at least one embodiment, one or more software programs 702 use one or more APIs 710 provided by a driver and / or a runtime 704 to allocate or otherwise reserve blocks of memory. To improve the usability of the software programs 702 and / or to accelerate the optimization of one or more sections of said software programs 702 by one or more PPUs, such as GPUs, in an embodiment, one or more APIs 710 provide one or more API functions 712 to cause 716 that one or more neural networks are used to identify one or more objects within one or more images, based, at least partially, on one or more features of the one or more images and one or more features of one or more modified versions of the one or more images, as described above and further explained in connection with Figures 1-6.In at least one embodiment, System 700 represents a processor comprising one or more circuits for executing one or more software programs to combine two or more APIs into a single API. In at least one embodiment, an exemplary block diagram 700 represents a system comprising one or more processors for executing one or more software programs to combine two or more APIs into a single API. In at least one embodiment, an API is used to instruct a neural network to generate one or more sections of an image, based, at least partially, on one or more sections. In at least one of the embodiments described in Figures 1-7, alone or in combination with at least one of the embodiments described in Figures 8-42, one or more technical improvements are provided. For example, the at least one embodiment described in Figures 1-7 performs a 2D-to-3D conversion without altering the 2D-to-3D relevance and / or the ground truth labels for computer vision tasks on higher-dimensional images. In at least one embodiment described in Figures 1-7, a 2D-to-3D conversion is integrated that is compatible with various feature extractions, which can be coupled with various computer vision tasks on higher-dimensional images without requiring changes to at least image coordinates or cell positions.In the embodiment described in Figures 1-7, any invertible extensions can be used while performing the 2D-to-3D conversion described herein. In at least one embodiment described in Figures 1-7, the accuracy of 3D computer vision tasks is increased while saving additional computing resources (e.g., GPU processing cores, GPU memory) by eliminating the need to convert one or more lookup tables for 2D-to-3D uplifting, while image or feature modifications are used for 2D-to-3D uplifting, a conversion that requires significant time and computing resources. In at least one embodiment described in Figures 1-7, these components can be removed to efficiently deploy one or more neural networks in real-world applications (e.g., autonomous driving).In the embodiment described in 1-7, it is not necessary for one or more neural networks to take camera or data variance into account when performing 3D or 4D perception tasks. LOGIC Fig. 8A illustrates logic 815, which, as described elsewhere herein, can be used in one or more devices to perform operations such as those described herein according to at least one embodiment. In at least one embodiment, logic 815 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, logic 815 is an inference and / or training logic. Details regarding logic 815 are provided below in conjunction with Figs. 8A and / or 8B.In at least one embodiment, logic refers to any combination of software logic, hardware logic and / or firmware logic to provide the functionality or operations described herein, wherein the logic as a whole or individually may be designed as a circuit arrangement that forms part of a larger system, for example an integrated circuit (IC), a system-on-chip (SoC) or one or more processors (e.g. CPU, GPU). In at least one embodiment, logic 815 may, in particular, comprise code and / or data storage 801 for storing forward and / or output weighting and / or input / output data and / or other parameters for setting up neurons or layers of a neural network that is trained in aspects of one or more embodiments and / or used for inference. In at least one embodiment, logic 815 may comprise or be coupled to code and / or data storage 801 for storing graph code or other software for controlling the timing and / or order in which weighting and / or other parameter information is loaded to set up logic, including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)).In at least one embodiment, code, such as graph code, based on the architecture of a neural network to which this code corresponds, loads weighting or other parameter information into processor ALUs. In at least one embodiment, code and / or data memory 801 stores weighting parameters and / or input / output data of each layer of a neural network that is trained or used with one or more embodiments during the forward propagation of input / output data and / or weighting parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data memory 801 may be included in other on-chip or off-chip data memory, including L1, L2, or L3 cache or system memory of a processor. In at least one embodiment, any section of code and / or data memory 801 can be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or code and / or data memory 801 can be a cache memory, a dynamic random-access memory (“DRAM”), a static random-access memory (“SRAM”), a non-volatile memory (e.g., flash memory), or another type of memory.In at least one embodiment, the choice of whether code and / or code and / or data memory 801 is, for example, internal or external to a processor, or comprises DRAM, SRAM, Flash or another type of memory, may depend on the available on-chip versus off-chip memory, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in inferring and / or training a neural network, or a combination of these factors. In at least one embodiment, logic 815 can, without limitation, comprise a code and / or data store 805 for storing backward and / or output weights and / or input / output data corresponding to neurons or layers of a neural network that is trained in aspects of one or more embodiments and / or used for inference. In at least one embodiment, code and / or data store 805 stores weighting parameters and / or input / output data of each layer of a neural network that is trained or used with one or more embodiments during backward propagation of input / output data and / or weighting parameters during training and / or inference using aspects of one or more embodiments.In at least one embodiment, logic 815 may comprise or be coupled to code and / or data storage 805 to store a graph code or other software for controlling the timing and / or sequence in which weight and / or other parameter information is to be loaded to set up logic, including integer and / or floating-point units (collectively arithmetic logic units (ALUs)). In at least one embodiment, code, such as graph code, based on the architecture of a neural network to which this code corresponds, causes weighting or other parameter information to be loaded into processor ALUs. In at least one embodiment, any portion of code and / or data memory 805 may be located in other on-chip or off-chip data memory, including L1, L2, or L3 cache or system memory of a processor. In at least one embodiment, any portion of code and / or data memory 805 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data memory 805 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory.In at least one embodiment, the choice of whether code and / or data storage 805 is, for example, internal or external to a processor, or comprises DRAM, SRAM, flash memory or another type of memory, may depend on the available on-chip versus off-chip memory, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in inferring and / or training a neural network, or a combination of these factors. In at least one embodiment, code and / or data memory 801 and code and / or data memory 805 can be separate memory structures. In at least one embodiment, code and / or data memory 801 and code and / or data memory 805 can be combined memory structures. In at least one embodiment, code and / or data memory 801 and code and / or data memory 805 can be partially combined and partially separate. In at least one embodiment, any portion of code and / or data memory 801 and / or code and / or data memory 805 can be included in other on-chip or off-chip data memory, including L1, L2, or L3 cache or system memory of a processor. In at least one embodiment, logic 815 may, without limitation, comprise one or more arithmetic logic unit(s) (“ALU(s)”) 810, including integer and / or floating-point units, to perform logical and / or mathematical operations that are at least partially based on or specified by a training and / or inference code (e.g., graph code), the result of which may generate activations (e.g., output values ​​of layers or neurons within a neural network) that are stored in an activation memory 820 and may be functions of input / output and / or weight parameter data that are stored in code and / or data memory 801 and / or code and / or data memory 805.In at least one embodiment, the activations stored in activation memory 820 are generated according to linear algebraic and / or matrix-based mathematics, which is performed by the ALU(s) 810 in response to the execution of instructions or other code, using weight values ​​stored in code and / or data memory 805 and / or data memory 801 together with other values, such as bias values, gradient information, momentum values ​​or other parameters or hyperparameters, some or all of which may be stored in code and / or data memory 805 or in code and / or data memory 801 or in another memory on or off the chip. In at least one embodiment, ALU(s) 810 are contained within one or more processors or other hardware logic devices or circuits, while in another embodiment, ALU(s) 810 may be external to a processor or other hardware logic device or circuit that uses it (e.g., a coprocessor). In at least one embodiment, ALU(s) 810 may be contained within execution units of a processor or otherwise within a bank of ALUs that execution units of a processor can access, either within the same processor or distributed across different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.).In at least one embodiment, code and / or data memory 801, code and / or data memory 805, and activation memory 820 can share a processor or other logic hardware device or circuit, while in another embodiment they can be located in different processors or other logic hardware devices or circuits, or in a combination of identical and different processors or other logic hardware devices or circuits. In at least one embodiment, any portion of activation memory 820 can be included in other on-chip or off-chip data memory, including L1, L2, or L3 cache or system memory of a processor.Furthermore, inference and / or training code can be stored together with other code that is accessible to a processor or other hardware logic or circuitry and is retrieved and / or processed using the retrieval, decoding, scheduling, execution, rejection and / or other logic circuitry of a processor. In at least one embodiment, activation memory 820 can be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, activation memory 820 can be located wholly or partially inside or outside of one or more processors or other logic circuits. In at least one embodiment, the choice of whether activation memory 820 is, for example, internal or external to a processor, or whether it comprises DRAM, SRAM, flash memory, or another type of memory, can depend on the available on-chip versus off-chip memory, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in inferring and / or training a neural network, or a combination of these factors. In at least one embodiment, the logic 815 illustrated in Fig. 8A can be used in conjunction with an application-specific integrated circuit (“ASIC”), such as a Google TensorFlow® Processing Unit, a Graphcore™ Inference Processing Unit (IPU), or an Intel Corp. Nervana® processor (e.g., “Lake Crest”). In at least one embodiment, the logic 815 illustrated in Fig. 8A can be used in conjunction with central processing unit (“CPU”), graphics processing unit (“GPU”), or other hardware, such as field-programmable gate arrays (“FPGAs”). Figure 8B illustrates Logic 815 according to at least one embodiment. In at least one embodiment, Logic 815 is inference and / or training logic. In at least one embodiment, Logic 815 can, without limitation, include hardware logic in which computational resources are dedicated or otherwise used exclusively in conjunction with weight values ​​or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, the Logic 815 illustrated in Figure 8B can be used in conjunction with an application-specific integrated circuit (ASIC), such as a Google TensorFlow® Processing Unit, a Graphcore™ Inference Processing Unit (IPU), or an Intel Corp. Nervana® processor (e.g., "Lake Crest"). In at least one embodiment, the Logic 815 illustrated in Figure 8B can be used in conjunction with a computer-based integrated circuit (ASIC), such as a Google TensorFlow® Processing Unit, a Graphcore™ Inference Processing Unit (IPU), or an Intel Corp. Nervana® Processor (e.g., "Lake Crest").Figure 8B illustrates how logic 815 can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware, such as field-programmable gate arrays (FPGAs). In at least one embodiment, logic 815 specifically comprises code and / or data stores 801 and 805, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. In at least one embodiment, illustrated in Figure 8B, each code and / or data store 801 and each code and / or data store 805 is connected to a dedicated data processing resource, such as data processing hardware 802 and data processing hardware 806.In at least one embodiment, each data processing hardware 802 and data processing hardware 806 comprises one or more ALUs that perform mathematical functions, such as linear algebraic functions, only on information that is stored in code and / or data memory 801 and code and / or data memory 805 respectively, and whose result is stored in activation memory 820. In at least one embodiment, the code and / or data storage 801 and 805 and corresponding data processing hardware 802 and 806 each correspond to different layers of a neural network, such that a resulting activation from a memory / data processing pair 801 / 802 consisting of code and / or data storage 801 and data processing hardware 802 is provided as an input for a next memory / data processing pair 805 / 806 consisting of code and / or data storage 805 and data processing hardware 806, in order to reflect a conceptual organization of a neural network. In at least one embodiment, each of the memory / data processing pairs 801 / 802 and 805 / 806 can correspond to more than one layer of the neural network.In at least one embodiment, additional memory / data processing pairs (not shown) may be included in logic 815 following or in parallel to the memory / data processing pairs 801 / 802 and 805 / 806. TRAINING AND DEPLOYMENT OF NEURAL NETWORKS Figure 9 illustrates the training and deployment of a deep neural network according to at least one embodiment. In at least one embodiment, an untrained neural network 906 is trained using a training dataset 902. In at least one embodiment, the training framework 904 is a PyTorch framework, whereas in other embodiments, the training framework 904 is a TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training framework. In at least one embodiment, the training framework 904 trains an untrained neural network 906 and enables it to be trained using the processing resources described herein to generate a trained neural network 908.In at least one embodiment, weights can be selected randomly or pre-trained using a deep-belief network. In at least one embodiment, training can be performed in a supervised, partially supervised, or unsupervised manner. In at least one embodiment, an untrained neural network 906 is trained using supervised learning, wherein the training dataset 902 comprises an input paired with a desired output for that input, or wherein the training dataset 902 comprises an input paired with a known output, and an output of the neural network 906 is manually graded. In at least one embodiment, the untrained neural network 906 is trained in a supervised manner and processes inputs from the training dataset 902 and compares resulting outputs with a set of expected or desired outputs. In at least one embodiment, errors are subsequently propagated back by the untrained neural network 906. In at least one embodiment, a training framework 904 adjusts weights that control the untrained neural network 906.In at least one embodiment, the training framework 904 includes tools for monitoring how well the untrained network 906 converges to a model, such as the trained network 908, which is capable of generating correct answers, such as in result 914, based on input data, such as a new dataset 912. In at least one embodiment, the training framework 904 repeatedly trains the untrained neural network 906 while adjusting weights to refine an output of the untrained neural network 906 using a loss function and a fitting algorithm, such as stochastic gradient descent. In at least one embodiment, the training framework 904 trains the untrained neural network 906 until the untrained neural network 906 achieves a desired accuracy.In at least one embodiment, the trained neural network 908 can then be provided to implement any number of machine learning operations. In at least one embodiment, an untrained neural network 906 is trained using unsupervised learning, wherein the untrained neural network 906 attempts to train itself using unlabeled data. In at least one embodiment, the training dataset for unsupervised learning 902 comprises input data without associated output data or "ground truth data". In at least one embodiment, the untrained neural network 906 can learn groupings within the training dataset 902 and determine how individual inputs relate to the untrained dataset 902. In at least one embodiment, unsupervised learning can be used to generate a self-organizing map in the trained neural network 908, which is capable of performing operations useful in reducing the dimensionality of a new dataset 912.In at least one embodiment, unsupervised learning can also be used to perform anomaly detection, thereby enabling the identification of data points in new data set 912 that deviate from normal patterns of new data set 912. In at least one embodiment, semi-supervised learning can be used, which is a technique in which the training dataset 902 comprises a mixture of labeled and unlabeled data. In at least one embodiment, the training framework 904 can be used to perform incremental learning, such as through techniques of transferred learning. In at least one embodiment, incremental learning enables the trained neural network 908 to adapt to the new dataset 912 without forgetting the knowledge imparted to the trained neural network 908 during the initial training. In at least one embodiment, Training Framework 904 is a framework processed in conjunction with a software development toolkit, such as an OpenVINO (Open Visual Inference and Neural Network Optimization) toolkit. In at least one embodiment, an OpenVINO toolkit is a toolkit such as that developed by Intel Corporation of Santa Clara, CA. In at least one embodiment, OpenVINO includes or uses Logic 815 to perform operations described herein. In at least one embodiment, a SoC, integrated circuit, or processor uses OpenVINO to perform operations described herein. In at least one embodiment, OpenVINO comprises a toolkit for the simplified development of applications, particularly neural network applications, for various tasks and operations, such as human vision emulation, speech recognition, natural language processing, recommendation systems, and / or variations thereof. In at least one embodiment, OpenVINO supports neural networks, such as convolutional neural networks (CNNs), recurrent and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries, such as OpenCV, OpenCL, and / or variants thereof. In at least one embodiment, OpenVINO supports neural network models for various tasks and operations, such as classification, segmentation, object recognition, face recognition, speech recognition, pose estimation (e.g., of people and / or objects), monocular depth estimation, image inpainting, style transfer, action recognition, coloring, and / or variations thereof. In at least one embodiment, OpenVINO comprises one or more software tools and / or modules for model optimization, also referred to as model optimizers. In at least one embodiment, a model optimizer is a command-line tool that facilitates transitions between training and deployment of neural network models. In at least one embodiment, a model optimizer optimizes neural network models for execution on various devices and / or processing units, such as a GPU, CPU, PPU, GPGPU, and / or variants thereof. In at least one embodiment, a model optimizer generates an internal representation of a model and optimizes this model to generate an intermediate representation. In at least one embodiment, a model optimizer reduces the number of layers of a model. In at least one embodiment, a model optimizer removes layers of a model that are used for training.In at least one embodiment, a model optimizer performs various operations in the neural network, such as modifying inputs to a model (e.g., changing the size of inputs to a model), modifying the size of inputs to a model (e.g., modifying the stack size of a model), modifying a model structure (e.g., modifying layers of a model), normalization, standardization, quantization (e.g., converting weights of a model from a first representation, such as floating point, to a second representation, such as integer), and / or variations thereof. In at least one embodiment, OpenVINO comprises one or more software libraries for inference, also referred to as an inference engine. In at least one embodiment, an inference engine is a C++ library or any suitable programming language library. In at least one embodiment, an inference engine is used to infer input data. In at least one embodiment, an inference engine implements various classes to infer input data and generate one or more results. In at least one embodiment, an inference engine implements one or more API functions to process an intermediate representation, set input and / or output formats, and / or execute a model on one or more devices. In at least one embodiment, OpenVINO provides various capabilities for the heterogeneous execution of one or more neural network models. In at least one embodiment, heterogeneous execution or heterogeneous data processing refers to one or more computing processes and / or one or more systems using one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions for executing a program on one or more devices. In at least one embodiment, OpenVINO provides various software functions for executing a program and / or sections of a program on different devices.In at least one embodiment, OpenVINO provides various software functions to execute, for example, a first section of code on a CPU and a second section of code on a GPU and / or FPGA. In at least one embodiment, OpenVINO provides various software functions to execute one or more layers of a neural network on one or more devices (e.g., a first set of layers on a first device, such as a GPU, and a second set of layers on a second device, such as a CPU). In at least one embodiment, OpenVINO includes various functionalities similar to those associated with a CUDA programming model, such as various operations for neural network models associated with frameworks like TensorFlow, PyTorch, and / or variations thereof. In at least one embodiment, one or more CUDA programming model operations are performed using OpenVINO. In at least one embodiment, various systems, methods, and / or techniques described herein are implemented using OpenVINO. DATA CENTER Fig. 10 illustrates an example of a data center 1000 in which at least one embodiment can be used. In at least one embodiment, data center 1000 comprises a data center infrastructure layer 1010, a framework layer 1020, a software layer 1030, and an application layer 1040. In at least one embodiment, as shown in Fig. 10, the data center infrastructure layer 1010 can comprise a resource coordinator 1012, clustered computing resources 1014 and node computing resources (“node CRs”) 1016(1)-1016(N), where “N” represents any positive integer (where “N” can be a different integer than used in other figures). In at least one embodiment, the node CRs 1016(1)-1016(N) may include any number of central processing units (“CPUs”) or other processors (including accelerators, field-programmable gate arrays (FPGAs), graphics processors, etc.), memory devices 1018(1)-1018(N) (e.g., dynamic read-only memories, solid-state or hard disk drives), network input / output (“NW-I / O”) devices, network switches, virtual machines (“VMs”), power supply modules and / or cooling modules, etc.In at least one embodiment, one or more node CRs from node CRs 1016(1)-1016(N) can be a server with one or more of the aforementioned computing resources. In at least one embodiment, grouped compute resources can comprise 1014 separate groupings of node compute resources (CRs) located within one or more racks (not shown) or in many racks housed in data centers at different geographic locations (also not shown). In at least one embodiment, separate groupings of node CRs within grouped compute resources can comprise grouped compute, network, memory, or data storage resources that can be configured or allocated to support one or more workloads. In at least one embodiment, multiple node CRs, including CPUs or processors, can be grouped within one or more racks to provide compute resources for supporting one or more workloads.In at least one embodiment, one or more racks can also include any number of power supply modules, cooling modules and network switches in any combination. In at least one embodiment, the resource coordinator 1012 can configure or otherwise control one or more node CRs 1016(1)-1016(N) and / or grouped computing resources 1014. In at least one embodiment, the resource coordinator 1012 can comprise a software design infrastructure (SDI) management unit for data center 1000. In at least one embodiment, the resource coordinator 1012 can comprise hardware, software, or a combination thereof. In at least one embodiment, as shown in Fig. 10, framework layer 1020 comprises a job scheduler 1022, a configuration manager 1024, a resource manager 1026, and a distributed file system 1028. In at least one embodiment, framework layer 1020 may comprise a framework for supporting the software 1032 of software layer 1030 and / or one or more application(s) 1042 of application layer 1040. In at least one embodiment, software 1032 or application(s) 1042 may each comprise web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 1020, without being limited thereto, can be a type of free and open-source software for a web application framework, such as Apache Spark™ (hereinafter “Spark”), which is a distributed file system 1028 for large-scale data processing (e.g."Big Data"). In at least one embodiment, the job scheduler 1022 can include a Spark driver to facilitate the scheduling of workloads supported by different layers of the data center 1000. In at least one embodiment, the configuration manager 1024 can be able to configure different layers, such as the software layer 1030 and the framework layer 1020, including Spark and the distributed file system 1028, to support data processing at scale. In at least one embodiment, the resource manager 1026 can be able to manage clustered or grouped computing resources that are associated with or allocated to support the distributed file system 1028 and the job scheduler 1022. In at least one embodiment, clustered or grouped computing resources can include grouped computing resources 1014 on the data center infrastructure layer 1010.In at least one embodiment, Resource Manager 1026 can coordinate with Resource Orchestrator 1012 to manage these mapped or allocated computing resources. In at least one embodiment, the software included in software layer 1030 may include software 1032 that is used by at least sections of the node CRs 1016(1)-1016(N), grouped computing resources 1014, and / or the distributed file system 1028 of framework layer 1020. In at least one embodiment, one or more types of software may include, but are not limited to, internet website search software, email virus scanning software, database software, and video streaming software. In at least one embodiment, the application(s) 1042 included in application layer 1040 may comprise one or more types of applications used by at least sections of the node CRs 1016(1)-1016(N), grouped compute resources 1014, and / or the distributed file system 1028 of framework layer 1020. In at least one embodiment, one or more types of applications may include, but are not limited to, any number of genetic research applications, cognitive computing applications, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments. In at least one embodiment, Configuration Manager 1024, Resource Manager 1026, or Resource Orchestrator 1012 can implement any number and type of self-modifying actions based on any set and type of data collected in any technically feasible manner. In at least one embodiment, self-modifying actions can relieve a data center operator of Data Center 1000 of potentially poor configuration decisions and potentially prevent underutilization and / or poor performance of parts of a data center. In at least one embodiment, the data center 1000 may comprise tools, services, software, or other resources for training one or more machine learning models or for predicting or inferring information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weighting parameters according to a neural network architecture using software and computing resources as described above with respect to data center 1000.In at least one embodiment, trained machine learning models corresponding to one or more neural networks can be used, using the resources described above with respect to Data Center 1000, to infer or predict information using weighting parameters calculated by one or more training techniques described herein. In at least one embodiment, the data center can use CPUs, application-specific integrated circuits (ASICs), GPUs, FPGAs, or other hardware to perform training and / or inference using the resources described above. Furthermore, one or more of the software and / or hardware resources described above can be configured as a service to allow users to train or infer information, such as image recognition, speech recognition, or other artificial intelligence services. Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding Logic 815 are provided herein in conjunction with Figures 8A and / or 8B. In at least one embodiment, Logic 815 can be used in Computing Center 1000 for inference or prediction operations based, at least partially, on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein. In at least one embodiment, Figs. 1-10 show the performance, using one or more neural networks, of one or more perception tasks for higher-dimensional (e.g., 3D, 4D) images based on an extension of the higher-dimensional images and / or an extension of lower-dimensional images (e.g., 2D, 3D). AUTONOMOUS VEHICLE Fig. 11A illustrates an example of an autonomous vehicle 1100 according to at least one embodiment. In at least one embodiment, autonomous vehicle 1100 (here alternatively referred to as "vehicle 1100") can be, without limitation, a passenger vehicle, such as a car, truck, bus, and / or any other type of vehicle that carries one or more passengers. In at least one embodiment, vehicle 1100 can be a semi-trailer truck used for transporting goods. In at least one embodiment, vehicle 1100 can be an aircraft, a robotic vehicle, or any other type of vehicle. Autonomous vehicles can be described in terms of automation levels defined by the National Highway Traffic Safety Administration (“NHTSA”), a division of the U.S. Department of Transportation, and the Society of Automotive Engineers (“SAE”) Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-201806, published June 15, 2018, Standard No. J3016-201609, published September 30, 2016, and earlier and future versions of this standard). In at least one embodiment, Vehicle 1100 can be capable of functions corresponding to one or more of the Levels 1 through 5 of autonomous driving levels. For example, in at least one embodiment, depending on the specific embodiment, Vehicle 1100 can be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5). In at least one embodiment, vehicle 1100 can, without limitation, comprise components such as a chassis, a vehicle body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. In at least one embodiment, vehicle 1100 can, without limitation, comprise a drive system 1150, such as an internal combustion engine, a hybrid electric power plant, a pure electric motor, and / or another type of drive system. In at least one embodiment, drive system 1150 can be connected to a drivetrain of vehicle 1100, which, without limitation, can include a transmission to enable the propulsion of vehicle 1100. In at least one embodiment, drive system 1150 can be controlled in response to receiving signals from a throttle / accelerator pedal(s) 1152. In at least one embodiment, a steering system 1154, which may include a steering wheel without limitation, can be used to steer the vehicle 1100 (e.g., along a desired path or route) when the drive system 1150 is in operation (e.g., when the vehicle 1100 is in motion). In at least one embodiment, a steering system 1154 can receive signals from steering actuator(s) 1156. In at least one embodiment, a steering wheel can be optional for full automation functionality (Level 5). In at least one embodiment, a brake sensor system 1146 can be used to actuate the vehicle brakes in response to receiving signals from the brake actuator(s) 1148 and / or brake sensors. In at least one embodiment, the controller(s) 1136, which may, without limitation, comprise one or more system-on-chips (“SoCs”) (not shown in Fig. 11A) and / or graphics processing units (“GPUs”), can provide signals (e.g., representative of commands) to one or more components and / or systems of the vehicle 1100. For example, in at least one embodiment, the controller(s) 1136 can send signals to actuate vehicle brakes via brake actuator(s) 1148, to actuate steering system 1154 via steering actuator(s) 1156, and to actuate drive system 1150 via throttle / accelerator pedal(s) 1152. In at least one embodiment, the controller(s) 1136 can comprise one or more in-vehicle (e.g., integrated) computing devices that process sensor signals and issue operating commands (e.g.,Signals representing commands) to enable autonomous driving and / or to assist a human driver in driving the vehicle 1100. In at least one embodiment, the controller(s) 1136 may comprise a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functionality (e.g., computer vision), a fourth controller for infotainment functionality, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the above functionalities, two or more controllers may handle a single functionality, and / or any combination thereof. In at least one embodiment, the controller(s) 1136 provide signals for controlling one or more components and / or systems of the vehicle 1100 in response to sensor data received from one or more sensors (e.g. sensor inputs). In at least one embodiment, the sensor data can be obtained, for example, without limitation, from one or more sensors of a global navigation satellite system (“GNSS”) 1158 (e.g., GPS sensor(s) of the Global Positioning System), radar sensor(s) 1160, ultrasonic sensor(s) 1162, lidar sensor(s) 1164, inertial measurement unit (IMU) sensor(s) 1166 (e.g., accelerometer(s), gyroscope(s), a magnetic compass or magnetic compasses, magnetometer(s), etc.), microphone(s) 1196, stereo camera(s) 1168, wide-angle camera(s) 1170 (e.g., fisheye cameras), infrared camera(s) 1172, omnidirectional camera(s) 1174 (e.g., 360-degree cameras), long-range cameras (not shown in Fig. 11A), Mid-range camera(s) (in Fig.11A not shown), speed sensor(s) 1144 (e.g. for measuring the speed of the vehicle 1100), vibration sensor(s) 1142, steering sensor(s) 1140, brake sensor(s) (e.g. as part of the brake sensor system 1146) and / or other sensor types. In at least one embodiment, one or more of the controller(s) 1136 can receive inputs (e.g., represented by input data) from a combination instrument 1132 of the vehicle 1100 and provide outputs (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 1134, an acoustic alarm, a loudspeaker, and / or via other components of the vehicle 1100. In at least one embodiment, outputs can include information such as vehicle speed, velocity, time, map data (e.g., a high-definition map (not shown in Fig. 11A)), position data (e.g., the position of the vehicle 1100, as shown on a map), direction, position of other vehicles (e.g., an occupancy grid), information about objects and the status of objects as perceived by the controller(s) 1136, etc.For example, in at least one embodiment, the HMI display 1134 can display information about the presence of one or more objects (e.g., road sign, warning sign, traffic light phase change, etc.) and / or information about driving maneuvers that the motor vehicle has performed, is performing, or will perform (e.g., change lanes now, take exit 34B in two miles, etc.). In at least one embodiment, vehicle 1100 further comprises a network interface 1124, which can use one or more wireless antennas 1126 and / or one or more modems for communication over one or more networks. For example, in at least one embodiment, the network interface 1124 can be capable of communication over Long-Term Evolution (“LTE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile Communication (“GSM”), IMT-CDMA Multi-Carrier (“CDMA2000”) networks, etc. In at least one embodiment, the wireless antenna(s) 1126 can also enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using a local network(s) such as Bluetooth, Bluetooth Low Energy (“LE”), Z-Wave, ZigBee protocols, etc.and / or enable Low Power Wide Area Networks (“LPWANs”) such as LoRaWAN, SigFox protocols, etc. Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding Logic 815 are provided herein in conjunction with Figures 8A and / or 8B. In at least one embodiment, Logic 815 can be used in the vehicle 1100 for inference or prediction of operations based, at least partially, on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein. In at least one embodiment, Figs. 1-11 show the performance, using one or more neural networks, of one or more perception tasks for higher-dimensional (e.g., 3D, 4D) images based on an extension of the higher-dimensional images and / or an extension of lower-dimensional images (e.g., 2D, 3D). Fig. 11B illustrates an example of camera positions and fields of view for the autonomous vehicle 1100 of Fig. 11A according to at least one embodiment. In at least one embodiment, the cameras and respective fields of view are exemplary and not intended to be limiting. For example, at least one embodiment may include additional and / or alternative cameras and / or cameras may be arranged at different locations on the vehicle 1100. In at least one embodiment, the camera types may include, but are not limited to, digital cameras designed for use with components and / or systems of the vehicle 1100. In at least one embodiment, the camera(s) may operate at Vehicle Safety Integrity Level (ASIL) B and / or another ASIL. In at least one embodiment, the camera types may be capable of any desired image acquisition speed, e.g., 60 frames per second (fps), 1220 fps, 240 fps, etc. In at least one embodiment, the cameras may be capable of using rolling shutters, global shutters, another type of shutter, or a combination thereof.In at least one embodiment, the color filter arrangement may comprise a red-clear-clear-clear ("RCCC") color filter arrangement, a red-clear-clear-blue ("RCCB") color filter arrangement, a red-blue-green-clear ("RBGC") color filter arrangement, a Foveon X3 color filter arrangement, a Bayer sensor ("RGGB") color filter arrangement, a monochrome sensor color filter arrangement, and / or another type of color filter arrangement. In at least one embodiment, clear pixel cameras, such as cameras with an RCCC, an RCCB, and / or an RBGC color filter arrangement, may be used in an effort to increase light sensitivity. In at least one embodiment, one or more of the camera(s) can be used to perform functions of an advanced driver assistance system (ADAS) (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function monocular camera can be installed to provide functions including lane keeping assist, traffic sign recognition, and intelligent headlight control. In at least one embodiment, one or more camera(s) (e.g., all cameras) can simultaneously capture and provide image data (e.g., video). In at least one embodiment, one or more cameras can be mounted in a mounting arrangement, such as a custom-designed (three-dimensionally ("3D") printed) arrangement, to exclude stray light and reflections from inside the vehicle 1100 (e.g., reflections from the dashboard reflected in the windshield mirrors) that could impair the camera's ability to capture image data. With reference to exterior mirror mounting arrangements, in at least one embodiment, exterior mirror assemblies can be custom 3D printed such that a camera mounting plate conforms to the shape of an exterior mirror. In at least one embodiment, one or more cameras can be integrated into the exterior mirrors. In at least one embodiment, for side-view cameras, camera(s) can also be integrated within four pillars at each corner of a cabin. In at least one embodiment, cameras with a field of view encompassing portions of the environment in front of the vehicle 1100 (e.g., forward-facing cameras) can be used for all-around vision to help identify forward paths and obstacles, and to provide, with the aid of one or more of the controller(s) 1136 and / or control SoCs, information crucial for generating an occupancy grid and / or determining preferred vehicle paths. In at least one embodiment, forward-facing cameras can be used to perform many similar ADAS functions as LiDAR, including, without limitation, emergency braking, pedestrian detection, and collision avoidance.In at least one embodiment, forward-facing cameras can also be used for ADAS functions and systems, including lane departure warning (“LDW”), adaptive cruise control (“ACC”) and / or other functions, including, without limitation, traffic sign recognition. In at least one embodiment, a plurality of cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform comprising a complementary CMOS (Complementary Metal Oxide Semiconductor) color imager. In at least one embodiment, a wide-angle camera 1170 can be used to detect objects entering the field of view from the periphery (e.g., pedestrians, crossing vehicles, or bicycles). Although only one wide-angle camera 1170 is illustrated in Fig. 11B, the vehicle 1100 can have any number (including zero) wide-angle cameras in other embodiments. In at least one embodiment, any number of long-range cameras 1198 (e.g., a pair of long-range stereo cameras) can be used to perform depth-based object detection, particularly for objects for which a neural network has not yet been trained.In at least one embodiment, the long-range camera(s) 1198 can also be used for object detection and classification as well as for basic object tracking. In at least one embodiment, any number of stereo cameras 1168 can also be included in a forward-facing configuration. In at least one embodiment, one or more of the stereo camera(s) 1168 can include an integrated control unit comprising a scalable processing unit that can provide programmable logic (“FPGA”) and a multi-core microprocessor with an integrated controller area network (“CAN”) or Ethernet interface on a single chip. In at least one embodiment, such a unit can be used to generate a 3D map of the environment of vehicle 1100, including a distance estimate for all points in an image.In at least one embodiment, one or more of the stereo camera(s) 1168 may, without limitation, comprise a compact stereo vision sensor(s) comprising two camera lenses (one each on the left and right) and an image processing chip that measures the distance between the vehicle 1100 and the target object and uses the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo camera(s) 1168 may be used in addition to or as an alternative to those described herein. In at least one embodiment, cameras with a field of view that includes sections of the environment to the sides of the vehicle 1100 (e.g., side-view cameras) can be used for all-around vision and provide information that is used to create and update an occupancy grid and to generate side-impact collision warnings. For example, in at least one embodiment, all-around camera(s) 1174 (e.g., four all-around cameras, as illustrated in Fig. 11B) can be positioned on the vehicle 1100. In at least one embodiment, the all-around camera(s) 1174 can, without limitation, comprise any number and combination of wide-angle camera(s), fisheye camera(s), 360-degree camera(s), and / or similar cameras. For example, in at least one embodiment, four fisheye cameras can be positioned at the front, rear, and sides of the vehicle 1100.In at least one embodiment, vehicle 1100 can use three surround-view cameras 1174 (e.g. left, right and rear) and use one or more other camera(s) (e.g. a forward-facing camera) as a fourth surround-view camera. In at least one embodiment, cameras with a field of view that includes sections of the environment behind the vehicle 1100 (e.g., reversing cameras) can be used as parking aids, for all-round visibility, rear collision warnings, and for creating and updating the occupancy grid. In at least one embodiment, a plurality of cameras can be used, including, but not limited to, cameras that are also suitable as forward-facing cameras (e.g., long-range cameras 1198 and / or mid-range cameras 1176, stereo cameras 1168, infrared cameras 1172, etc.), as described herein. In at least one embodiment, Fig. 1-11B shows the performance, using one or more neural networks, of one or more perception tasks for higher-dimensional (e.g., 3D, 4D) images based on an extension of the higher-dimensional images and / or an extension of lower-dimensional images (e.g., 2D, 3D). Figure 11C is a block diagram illustrating an exemplary system architecture for the autonomous vehicle 1100 of Figure 11A according to at least one embodiment. In at least one embodiment, all components, features, and systems of the vehicle 1100 are illustrated in Figure 11C as being connected via a bus 1102. In at least one embodiment, the bus 1102 can, without limitation, comprise a CAN data interface (alternatively referred to herein as the "CAN bus"). In at least one embodiment, a CAN bus can be a network within the vehicle 1100 used to support the control of various features and functions of the vehicle 1100, such as actuation of brakes, acceleration, braking, steering, windshield wipers, etc. In at least one embodiment, the CAN bus 1102 can be configured to have dozens or even hundreds of nodes, each of which has its own unique identifier (e.g., a CAN ID).In at least one embodiment, bus 1102 can be read to determine the steering wheel angle, vehicle speed, engine revolutions per minute (rpm), switch positions, and / or other vehicle status information. In at least one embodiment, bus 1102 can be a CAN bus that is ASIL B compliant. In at least one embodiment, FlexRay and / or Ethernet can be used in addition to, or as an alternative to, CAN. In at least one embodiment, any number of buses can form the bus 1102, which, without limitation, can include zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using a different protocol. In at least one embodiment, two or more buses can be used to perform different functions and / or they can be used for redundancy. For example, a first bus can be used for collision avoidance functionality and a second bus for drive control. In at least one embodiment, each bus of the bus 1102 can communicate with any components of the vehicle 1100, and two or more buses of the bus 1102 can communicate with corresponding components.In at least one embodiment, each of any number of system-on-chip(s) (“SoC(s)”) 1104 (such as SoC 1104(A) and SoC 1104(B)), each of the controller(s) 1136 and / or each computer within the vehicle has access to the same input data (e.g. inputs from sensors of the vehicle 1100) and can be connected to a common bus, such as a CAN bus. In at least one embodiment, vehicle 1100 can comprise one or more controllers 1136 as described herein with reference to Fig. 11A. In at least one embodiment, the controller(s) 1136 can be used for a variety of functions. In at least one embodiment, the controller(s) 1136 can be coupled with any of the various other components and systems of vehicle 1100 and used for controlling vehicle 1100, the artificial intelligence of vehicle 1100, the infotainment system of vehicle 1100, and / or other functions. In at least one embodiment, the vehicle 1100 can comprise any number of SoCs 1104. In at least one embodiment, each of the SoCs 1104 can, without limitation, comprise central processing units (“CPU(s)”) 1106, graphics processing units (“GPU(s)”) 1108, processor(s) 1110, cache(s) 1112, accelerators 1114, data storage 1116, and / or other components and features not illustrated. In at least one embodiment, the SoC(s) 1104 can be used for controlling the vehicle 1100 in a variety of platforms and systems. For example, in at least one embodiment, SoC(s) 1104 can be combined in a system (e.g., system of vehicle 1100) with a high-definition ("HD") card 1122, which can receive map refreshes and / or updates via network interface 1124 from one or more servers (not shown in Fig. 11C). In at least one embodiment, the CPU(s) 1106 may comprise a CPU cluster or CPU complex (alternatively referred to herein as "CCPLEX"). In at least one embodiment, the CPU(s) 1106 may comprise multiple cores and / or Level Two ("L2") caches. For example, in at least one embodiment, the CPU(s) 1106 may comprise eight cores in a coherent multiprocessor configuration. In at least one embodiment, the CPU(s) 1106 may comprise four dual-core clusters, each cluster having a dedicated L2 cache (e.g., a 2-megabyte (MB) L2 cache). In at least one embodiment, the CPU(s) 1106 (e.g., CCPLEX) can be configured to support the simultaneous operation of clusters, so that any combination of clusters of the CPU(s) 1106 can be active at any given time. In at least one embodiment, one or more of the CPU(s) can implement 1106 power management functions which, without limitation, include one or more of the following features: individual hardware blocks can be clock-gate controlled in idle mode to save dynamic power; each core clock can be gate-gate controlled when a core is not actively executing instructions due to the execution of Wait-for-Interrupt ("WFI") / Wait-for-Event ("WFE") instructions; each core can be independently power-gate controlled; each core cluster can be independently clock-gate controlled when all cores are clock-gate controlled or power-gate controlled; and / or each core cluster can be independently power-gate controlled when all cores are power-gate controlled.In at least one embodiment, the CPU(s) 1106 can further implement an extended power state management algorithm in which permissible power states and expected wake-up times are specified, and hardware / microcode determines the best power state for the core, cluster, and CCPLEX to enter. In at least one embodiment, the processing cores can support simplified power state entry sequences in software, offloading the work to the microcode. In at least one embodiment, the GPU(s) 1108 may include an integrated GPU (hereafter referred to alternatively as an "iGPU"). In at least one embodiment, the GPU(s) 1108 may be programmable and efficient for parallel workloads. In at least one embodiment, the GPU(s) 1108 may use an extended Tensor instruction set. In at least one embodiment, the GPU(s) 1108 may include one or more streaming microprocessors, each streaming microprocessor including a Level 1 ("L1") cache (e.g., an L1 cache with a minimum storage capacity of 96 KB), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with a storage capacity of 512 KB). In at least one embodiment, the GPU(s) 1108 may include at least eight streaming microprocessors.In at least one embodiment, the GPU(s) 1108 can use computer application programming interface(s) (API(s)). In at least one embodiment, the GPU(s) 1108 can use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model). In at least one embodiment, one or more of the GPU(s) 1108 can be power-optimized for best performance in automotive and embedded applications. For example, in at least one embodiment, the GPU(s) 1108 can be manufactured on a Fin field-effect transistor (“FinFET”) circuit array. In at least one embodiment, each streaming microprocessor can have a number of mixed-precision processing cores divided into multiple blocks. For example, and without limitation, 64 FP32 cores and 32 FP64 cores can be divided into four processing blocks. In at least one embodiment, each processing block can contain 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA TENSOR cores for deep learning matrix arithmetic, a level zero (“L0”) instruction cache, a scheduler (e.g.,The streaming microprocessors may be allocated a warp scheduler or sequencer, a dispatch unit, and / or a 64 KB register file. In at least one embodiment, the streaming microprocessors may include independent parallel integer and floating-point data paths to provide efficient execution of workloads with a mixture of computations and addressing calculations. In at least one embodiment, the streaming microprocessors may include independent thread scheduling capability to enable finer-grained synchronization and collaboration between parallel threads. In at least one embodiment, the streaming microprocessors may include a combined L1 data cache and a shared memory unit to improve performance while simplifying programming. In at least one embodiment, one or more of the GPU(s) 1108 may include high-bandwidth memory (“HBM”) and / or a 16 GB HBM2 memory subsystem to provide a peak memory bandwidth of approximately 900 GB / second in some examples. In at least one embodiment, synchronous graphics random-access memory (“SGRAM”), such as type 5 synchronous graphics dual-data-rate random-access memory (“GDDR5”), may be used in addition to or as an alternative to HBM memory. In at least one embodiment, GPU(s) 1108 can comprise a unified memory technology. In at least one embodiment, support for address translation services (“ATS”) can be used so that GPU(s) 1108 can directly access page tables of CPU(s) 1106. In at least one embodiment, if a memory management unit (“MMU”) of GPU(s) 1108 experiences a failure, an address translation request can be sent to CPU(s) 1106. In response, in at least one embodiment, two CPUs of CPU(s) 1106 can search their page tables for a virtual-to-physical mapping for an address and send the translation back to GPU(s) 1108.In at least one embodiment, unitary memory technology can enable a single unified virtual address space for the memory of both the CPU(s) 1106 and the GPU(s) 1108, thereby simplifying the programming of the GPU(s) 1108 and the porting of applications to the GPU(s) 1108. In at least one embodiment, the GPU(s) 1108 can include any number of access counters that can track the frequency of GPU(s) 1108 accesses to the memory of other processors. In at least one embodiment, access counters can help ensure that memory pages are moved to the physical memory of a processor that accesses pages most frequently, thereby improving the efficiency of memory areas shared by processors. In at least one embodiment, one or more SoC(s) 1104 can include any number of cache(s) 1112, including those described herein. For example, in at least one embodiment, the cache(s) 1112 can include a Level 3 ("L3") cache that is available to both CPU(s) 1106 and GPU(s) 1108 (e.g., one connected to CPU(s) 1106 and GPU(s) 1108). In at least one embodiment, the cache(s) 1112 can include a write-back cache capable of tracking row states, such as by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, an L3 cache can comprise 4 MB of memory or more, depending on the embodiment, although smaller cache sizes can also be used. In at least one embodiment, one or more of the SoC(s) 1104 can include one or more accelerators 1114 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, the SoC(s) 1104 can include a hardware acceleration cluster, which may include optimized hardware accelerators and / or a large on-chip memory. In at least one embodiment, the large on-chip memory (e.g., 4 MB SRAM) can enable a hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, a hardware acceleration cluster can be used to complement GPU(s) 1108 and offload some of the tasks of the GPU(s) 1108 (e.g., to free up more GPU cycles for performing other tasks). In at least one embodiment, the accelerator(s) 1114 can be used for targeted workloads (e.g.Perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.) are used, which are stable enough to be amenable to acceleration. In at least one embodiment, a CNN may include area-based or regional convolutional neural networks (“RCNNs”) and fast RCNNs (e.g., as used for object recognition) or other types of CNNs. In at least one embodiment, the accelerator(s) 1114 (e.g., hardware acceleration cluster) may comprise one or more deep learning accelerators (“DLA”). In at least one embodiment, the DLA(s) may, without limitation, comprise one or more tensor processing units (“TPUs”), which may be configured to provide an additional ten trillion operations per second for deep learning applications and inference. In at least one embodiment, the TPUs may be accelerators configured and optimized to perform image processing functions (e.g., for CNNs, RCNNs, etc.). In at least one embodiment, the DLA(s) may further be optimized for a specific set of neural network types and floating-point operations, as well as for inference.In at least one embodiment, a DLA(s) configuration can provide more performance per millimeter than a typical general-purpose GPU and generally far surpasses the performance of a CPU. In at least one embodiment, the TPU(s) can perform multiple functions, including a single-instance convolution function that supports, for example, INT8, INT16, and FP16 data types for both features and weights, as well as post-processor functions.In at least one embodiment, the DLA(s) can execute neural networks, in particular CNNs, quickly and efficiently on processed or unprocessed data for a variety of functions, including, for example, but not limited to: a CNN for object identification and detection using camera sensor data; a CNN for distance estimation using camera sensor data; a CNN for emergency vehicle detection and identification using microphone data; a CNN for facial recognition and vehicle owner identification using camera sensor data; and / or a CNN for safety-related and / or security-related events. In at least one embodiment, the DLA(s) can perform any function of the GPU(s) 1108, and using, for example, an inference accelerator, a developer can provide either the DLA(s) or the GPU(s) 1108 for each function. For example, in at least one embodiment, a developer can focus on the DLA(s) for processing CNNs and floating-point operations and leave other functions to the GPU(s) 1108 and / or one or more accelerators 1114. In at least one embodiment, accelerator(s) 1114 may comprise a programmable vision accelerator (“PVA”), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 1138, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, the PVA may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may, by way of example and without limitation, comprise any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors. In at least one embodiment, the RISC cores can interact with image sensors (e.g., image sensors of one of the cameras described herein), image signal processor(s), etc. In at least one embodiment, each RISC core can include any amount of memory. In at least one embodiment, the RISC cores can use any number of protocols, depending on the embodiment. In at least one embodiment, the RISC cores can run a real-time operating system (“RTOS”). In at least one embodiment, RISC cores can be implemented using one or more integrated circuits, application-specific integrated circuits (ASICs), and / or memory devices. For example, in at least one embodiment, the RISC cores could include an instruction cache and / or tightly coupled RAM. In at least one embodiment, DMA can enable components of the PVA to access system memory independently of the CPU(s) 1106. In at least one embodiment, DMA can support any number of features used to optimize a PVA, including, but not limited to, support for multidimensional addressing and / or circular addressing. In at least one embodiment, DMA can support up to six or more dimensions of addressing, which may include, without limitation, block width, block height, block depth, horizontal block gradation, vertical block gradation, and / or depth gradation. In at least one embodiment, vector processors can be programmable processors designed to efficiently and flexibly execute programming for computer vision algorithms and to provide signal processing capabilities. In at least one embodiment, a PVA can comprise a PVA core and two vector processing subsystem partitions. In at least one embodiment, a PVA core can comprise a processor subsystem, DMA engine(s) (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, a vector processing subsystem can operate as a primary processing engine of a PVA and can comprise a vector processing unit (VPU), an instruction cache, and / or vector memory (e.g., VMEM).In at least one embodiment, the VPU core can include a digital signal processor, such as a single-instruction, multiple-data (“SIMD”), or very-long instruction word (“VLIW”) digital signal processor. In at least one embodiment, a combination of SIMD and VLIW can increase throughput and speed. In at least one embodiment, each of the vector processors can include an instruction cache and can be coupled to dedicated memory. Consequently, in at least one embodiment, each of the vector processors can be configured to operate independently of the other vector processors. In at least one embodiment, the vector processors included in a given PVA can be configured to employ data parallelism. For example, in at least one embodiment, a plurality of vector processors included in a single PVA can execute a common computer vision algorithm, but on different image regions. In at least one embodiment, the vector processors included in a given PVA can simultaneously execute different computer vision algorithms for an image, or even different algorithms for successive images or sections of an image.In at least one embodiment, the hardware acceleration cluster can include any number of PVAs, and each PVA can include any number of vector processors. In at least one embodiment, the PVA can also include additional memory with error correction code (“ECC”) to increase the overall security of the system. In at least one embodiment, accelerator(s) 1114 may include a computer vision network on-chip and a static random-access memory (“SRAM”) to provide a high-bandwidth, low-latency SRAM for the accelerator(s). In at least one embodiment, the on-chip memory may include at least 4 MB of SRAM, consisting, for example, and without limitation, of eight field-configurable memory blocks accessible to both a PVA and a DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus (APB) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, a PVA and a DLA may access memory via a backbone that provides high-speed access to the memory for both the PVA and the DLA.In at least one embodiment, the backbone can include an on-chip computer vision network that connects a PVA and a DLA with memory (e.g., using APB). In at least one embodiment, a computer vision network-on-chip may include an interface that determines, prior to the transmission of control signals / addresses / data, that both a PVA and a DLA are provided with ready-to-use and valid signals. In at least one embodiment, such an interface may provide separate phases and separate channels for the transmission of control signals / addresses / data, as well as burst communication for continuous data transmission. In at least one embodiment, an interface may conform to the standards of the International Organization for Standardization (“ISO”) 26262 or the International Electrotechnical Commission (“IEC”) 61508, although other standards and protocols may also be used. In at least one embodiment, one or more of the SoC(s) 1104 can include a real-time ray-tracing hardware accelerator. In at least one embodiment, the real-time ray-tracing hardware accelerator can be used for the fast and efficient determination of the positions and extents of objects (e.g., within a world model), for generating real-time visualization simulations, for radar signal interpretation, for sound propagation synthesis and / or analysis, for the simulation of SONAR systems, for general wave propagation simulation, for comparison with lidar data for localization purposes, and / or for other functions and / or other uses. In at least one embodiment, the accelerator(s) 1114 can offer a variety of applications for autonomous driving. In at least one embodiment, a PVA can be used for key processing steps in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of a PVA are well suited for algorithmic domains that require predictable processing with low power consumption and low latency. In other words, a PVA works well with partial-density or dense regular computations, even with small datasets, which may require predictable runtimes with low latency and low power consumption. In at least one embodiment, such as in vehicle 1100, PVAs could be designed to execute classical computer vision algorithms, as they are efficient at object detection and can work with integer mathematics. For example, according to at least one embodiment of the technology, a PVA is used to perform computer stereo vision. In at least one embodiment, an algorithm based on semi-global matching can be used, although this is not intended as a limitation. In at least one embodiment, applications for Level 3-5 autonomous driving use on-the-fly motion estimation / stereo matching (e.g., structure of motion, pedestrian detection, lane detection, etc.). In at least one embodiment, a PVA can perform computer stereo vision functions on input from two monocular cameras. In at least one embodiment, a PVA can be used to perform a dense optical flow. For example, in at least one embodiment, a PVA could process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, a PVA is used for time-of-flight depth processing, for example, by processing raw time-of-flight data to provide processed time-of-flight data. In at least one embodiment, a DLA can be used to operate any type of network to improve control and driving safety, including, but not limited to, a neural network that outputs a measure of confidence for each object detection. In at least one embodiment, confidence can be represented or interpreted as providing a probability or a relative "weighting" of each detection compared to other detections. In at least one embodiment, a confidence measurement enables a system to make further decisions about which detections should be considered true positives rather than false positives. In at least one embodiment, a system can set a confidence threshold and consider only detections that exceed the threshold as true positives.In at least one embodiment, when an automatic emergency braking (“AEB”) system is used, false positive detections would cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, high-confidence detections can be considered as triggers for the AEB. In at least one embodiment, a DLA can execute a neural network for confidence regression. In at least one embodiment, a neural network can take as input at least a subset of parameters, such as dimensions of the bounding frame (e.g., from another subsystem), a obtained estimate of the ground plane, outputs from inertial measurement unit (IMU) sensor(s) 1166 that correlate with a vehicle orientation 1100, distance, 3D position estimates of the object obtained from the neural network and / or other sensors (e.g.,LIDAR sensor(s) 1164 or RADAR sensor(s) 1160) are obtained and used. In at least one embodiment, one or more of the SoC(s) 1104 may comprise data storage 1116 (e.g., memory). In at least one embodiment, the data storage 1116 may be on-chip memory of the SoC(s) 1104 capable of storing neural networks to be executed on the GPU(s) 1108 and / or a DLA. In at least one embodiment, the capacity of the data storage 1116 may be large enough to store multiple instances of neural networks for redundancy and security. In at least one embodiment, the data storage 1116 may include L2 or L3 cache(s). In at least one embodiment, one or more of the SoC(s) 1104 can comprise any number of processor(s) 1110 (e.g., embedded processors). In at least one embodiment, the processor(s) 1110 can comprise a boot and power management processor, which can be a dedicated processor and a subsystem that handles the boot power and management functions and the associated security enforcement. In at least one embodiment, a boot and power management processor can be part of the boot sequence of the SoC(s) 1104 and provide runtime power management services.In at least one embodiment, a boot power and management processor can provide clock and voltage programming, support for system transitions to a low-power state, management of the thermal and temperature sensors of the SoC(s) 1104, and / or management of the power states of the SoC(s) 1104. In at least one embodiment, each temperature sensor can be implemented as a ring oscillator whose output frequency is proportional to the temperature, and the SoC(s) 1104 can use ring oscillators to detect temperatures of the CPU(s) 1106, GPU(s) 1108, and / or accelerator(s) 1114.In at least one embodiment, when it is determined that temperatures exceed a threshold, a boot and power management processor can enter a temperature fault routine and put the SoC(s) 1104 into a lower power state and / or put the vehicle 1100 into a drive-to-safe-stop mode (e.g., bring the vehicle 1100 to a safe stop). In at least one embodiment, the processor(s) 1110 may further comprise a set of embedded processors that can serve as an audio processing engine, which may be an audio subsystem enabling full hardware support for multi-channel audio over multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, an audio processing engine is a dedicated processor core with a digital signal processor and dedicated RAM. In at least one embodiment, processor(s) 1110 may further comprise an "always-on" processor engine, which provides the necessary hardware features to support low-power sensor management and to enable use cases. In at least one embodiment, the "always-on" processor engine may, without limitation, comprise a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O control peripherals, and routing logic. In at least one embodiment, the processor(s) 1110 may further comprise a security cluster engine which, without limitation, includes a dedicated processor subsystem for handling security management for automotive applications. In at least one embodiment, a security cluster engine may, without limitation, comprise two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, an interrupt controller, etc.), and / or routing logic. In a security mode, in at least one embodiment, two or more cores may operate in a lockstep mode and function as a single core with comparison logic to detect any differences between their operations.In at least one embodiment, the processor(s) 1110 may further comprise a real-time camera engine, which may, without limitation, include a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, the processor(s) 1110 may further comprise a high dynamic range signal processor, which may, without limitation, include an image signal processor that is a hardware engine that is part of a camera processing pipeline. In at least one embodiment, processor(s) 1110 may include a video image compositor, which may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions required by a video playback application to generate a final image for a player window. In at least one embodiment, a video image compositor may perform lens distortion correction on the wide-angle camera(s) 1170, the omnidirectional camera(s) 1174, and / or the cabin surveillance camera sensor(s). In at least one embodiment, the cabin surveillance camera sensor(s) may preferably be monitored by a neural network running on another instance of the SoC 1104 and configured to detect events in the cabin and respond accordingly.In at least one embodiment, without limitation, a system in the cabin can perform lip-reading to activate the mobile phone service and make a call, dictate emails, change a vehicle's destination, activate or change a vehicle's infotainment system and settings, or enable voice-controlled internet browsing. In at least one embodiment, certain functions are available to a driver when the vehicle is operating in autonomous mode and are otherwise deactivated. In at least one embodiment, a video image compositor can include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, if motion occurs in a video, the noise reduction weights the spatial information accordingly and reduces the weighting of information provided by adjacent frames. In at least one embodiment, if an image or a portion of an image does not contain motion, the temporal noise reduction performed by the video image compositor can use information from a previous image to reduce noise in the current image. In at least one embodiment, a video image compositor can also be configured to perform stereo rectification on input stereo lens images. In at least one embodiment, a video image compositor can further be used for assembling the user interface when an operating system desktop is in use, and the GPU(s) 1108 are not required for continuously rendering new surfaces. In at least one embodiment, when the GPU(s) 1108 are powered on and actively performing 3D rendering, a video image compositor can be used to offload the GPU(s) 1108 and improve performance and responsiveness. In at least one embodiment, one or more SoCs of SoC(s) 1104 may further comprise a serial camera interface with a mobile industrial processor interface (“MIPI”) for receiving video and camera inputs, a high-speed interface, and / or a video input block that can be used for a camera and related pixel input functions. In at least one embodiment, the SoC(s) 1104 may further comprise an input / output controller that can be controlled by software and used for receiving I / O signals that are not tied to a specific role. In at least one embodiment, one or more SoCs of the SoC(s) 1104 can further comprise a wide range of peripheral interfaces to enable communication with peripheral devices, audio encoders / decoders (“codecs”), power management, and / or other devices. In at least one embodiment, the SoC(s) 1104 can be used to process data from cameras (e.g., connected via Gigabit Multimedia Serial Link and Ethernet channels), sensors (e.g., LiDAR sensor(s) 1164, radar sensor(s) 1160, etc., which may be connected via Ethernet channels), data from bus 1102 (e.g., vehicle speed 1100, steering wheel position, etc.), and data from GNSS sensor(s) 1158 (e.g., connected via Ethernet bus or CAN bus).In at least one embodiment, one or more SoCs of the SoC(s) 1104 may further include dedicated high-performance mass storage controllers, which may include their own DMA engines and may be used to relieve CPU(s) 1106 of routine data management tasks. In at least one embodiment, the SoC(s) 1104 can be an end-to-end platform with a flexible architecture that covers automation levels 3-5, thereby providing a comprehensive functional safety architecture that utilizes computer vision and ADAS techniques for diversity and redundancy, and provides a platform for a flexible, reliable driving software stack along with deep learning tools. In at least one embodiment, the SoC(s) 1104 can be faster, more reliable, and even more energy-efficient and compact than conventional systems. For example, in at least one embodiment, accelerator(s) 1114 in combination with CPU(s) 1106, GPU(s) 1108, and data storage(s) 1116 can provide a fast, efficient platform for autonomous vehicles of levels 3-5. In at least one embodiment, computer vision algorithms can be executed on CPUs that can be configured, using a higher-level programming language such as C, to perform a variety of processing algorithms on a variety of visual data. However, in at least one embodiment, CPUs are often unable to meet the performance requirements of many computer vision applications, such as those relating to execution time and power consumption. In at least one embodiment, many CPUs are unable to execute complex object recognition algorithms in real time, such as those used in in-vehicle ADAS applications and in practical Level 3-5 autonomous vehicles. The embodiments described herein allow multiple neural networks to be executed simultaneously and / or sequentially, and the results to be combined to enable autonomous driving functions of levels 3-5. For example, in at least one embodiment, a CNN running on a DLA or a discrete GPU (e.g., GPU(s) 1120) can include text and word recognition that enables the reading and understanding of traffic signs, including signs for which a neural network has not been specifically trained. In at least one embodiment, a DLA can further include a neural network capable of identifying and interpreting a character, providing a semantic understanding, and passing this semantic understanding to the path planning modules running on a CPU complex. In at least one embodiment, several neural networks can be executed simultaneously, as for driving stages 3, 4, or 5. For example, in at least one embodiment, a warning sign indicating "Caution: Flashing lights indicate black ice" together with an electric light can be interpreted independently or jointly by several neural networks. In at least one embodiment, such a warning sign itself can be identified as a traffic sign by a first neural network (e.g., a trained neural network), while the text "Flashing lights indicate black ice" can be interpreted by a second neural network, which informs a vehicle's path planning software (preferably executed on a CPU complex) that black ice is present when flashing lights are detected.In at least one embodiment, a flashing light can be identified by a third neural network operating across multiple images and informing a vehicle's path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can be executed simultaneously, such as within a DLA and / or on the GPU(s) 1108. In at least one embodiment, a CNN for facial recognition and vehicle owner identification can use data from camera sensors to identify the presence of an authorized driver and / or owner of the vehicle 1100. In at least one embodiment, an "always-on" sensor processing engine can be used to unlock a vehicle when an owner approaches a driver's door and turns on the lights, and, in a security mode, to disable the vehicle when an owner leaves it. In this way, SoC(s) 1104 can provide security against theft and / or carjacking. In at least one embodiment, a CNN for emergency vehicle detection and identification can use data from microphones 1196 to detect and identify emergency vehicle sirens. In at least one embodiment, the SoC(s) 1104 uses a CNN for classifying environmental and urban noise, as well as for classifying visual data. In at least one embodiment, a CNN running on a DLA is trained to identify the relative approach speed of an emergency vehicle (e.g., using a Doppler effect). In at least one embodiment, a CNN can also be trained to identify emergency vehicles specific to the local area in which the vehicle operates, as identified by the GNSS sensor(s) 1158.In at least one embodiment, a CNN, when operating in Europe, attempts to detect European sirens, and in North America, a CNN attempts to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used to execute an emergency vehicle safety routine, slow down a vehicle with the aid of ultrasonic sensor(s) 1162, pull over to the side of the road, park a vehicle, and / or put a vehicle into neutral until emergency vehicles have passed. In at least one embodiment, the vehicle can comprise 1100 CPU(s) 1118 (e.g., discrete CPU(s) or dCPU(s)) which can be coupled to the SoC(s) 1104 via a high-speed connection (e.g., PCIe). In at least one embodiment, the CPU(s) 1118 can, for example, comprise an x86 processor. CPU(s) 1118 can be used to perform any of a variety of functions, including, for example, arbitrating potentially inconsistent results between ADAS sensors and SoC(s) 1104 and / or monitoring the status and health of the controller(s) 1136 and / or an infotainment system-on-a-chip (“infotainment SoC”) 1130. In at least one embodiment, SoC(s) 1104 can include one or more interconnects, and an interconnect can include a Peripheral Component Interconnect Express (PCIe). In at least one embodiment, the vehicle 1100 can include one or more GPU(s) 1120 (e.g., discrete GPU(s) or dGPU(s)) which can be coupled to the SoC(s) 1104 via a high-speed connection (e.g., NVIDIA's NVLINK Channel). In at least one embodiment, the GPU(s) 1120 can provide additional artificial intelligence functions, such as by running redundant and / or different neural networks, and can be used to train and / or update neural networks, at least partially, based on input (e.g., sensor data) from sensors of the vehicle 1100. In at least one embodiment, the vehicle 1100 may further comprise a network interface 1124, which may (without limitation) include wireless antenna(s) 1126 (e.g., one or more wireless antennas for various communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, the network interface 1124 may be used to establish a wireless connection to internet cloud services (e.g., to servers and / or other network devices), to other vehicles, and / or to computing devices (e.g., passenger client devices). In at least one embodiment, to communicate with other vehicles, a direct connection may be established between the vehicle 1100 and another vehicle, and / or an indirect connection may be established (e.g., via networks and the internet).In at least one embodiment, direct transmission links can be provided using a vehicle-to-vehicle communication link. In at least one embodiment, a vehicle-to-vehicle communication link can provide vehicle 1100 with information about vehicles in the vicinity of vehicle 1100 (e.g., vehicles in front of, beside, and / or behind vehicle 1100). In at least one embodiment, such functionality can be part of a cooperative adaptive cruise control function of vehicle 1100. In at least one embodiment, the network interface 1124 can include a SoC that provides modulation and demodulation functions and enables the controller(s) 1136 to communicate via wireless networks. In at least one embodiment, the network interface 1124 can include a high-frequency front end for upconversion from baseband to high frequency and downconversion from high frequency to baseband. In at least one embodiment, frequency conversions can be performed in any technically feasible way. For example, frequency conversions can be performed by known processes and / or using superheterodyne processes. In at least one embodiment, high-frequency front-end functionality can be provided by a separate chip.In at least one embodiment, network interfaces may include wireless functionality for communication via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN and / or other wireless protocols. In at least one embodiment, vehicle 1100 may further comprise one or more data storage devices 1128, which, without limitation, may include an off-chip memory (e.g., outside the SoC(s) 1104). In at least one embodiment, the data storage device(s) 1128 may, without limitation, comprise one or more memory elements, including RAM, SRAM, dynamic random-access memory (“DRAM”), video random-access memory (“VRAM”), flash memory, hard disks, and / or other components and / or devices capable of storing at least one data bit. In at least one embodiment, vehicle 1100 may further comprise GNSS sensor(s) 1158 (e.g., GPS and / or GPS-enabled sensors) to support imaging, perception, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1158 may be used, including, for example, and without limitation, a GPS using a USB connector with an Ethernet-to-serial bridge (e.g., an RS-232 bridge). In at least one embodiment, the vehicle 1100 may further comprise RADAR sensor(s) 1160. In at least one embodiment, the RADAR sensor(s) 1160 of the vehicle 1100 may be used for long-range vehicle detection, even in darkness and / or adverse weather conditions. In at least one embodiment, the functional RADAR safety levels may be ASIL B. In at least one embodiment, the RADAR sensor(s) 1160 may use a CAN bus and / or bus 1102 (e.g., for transmitting data generated by the RADAR sensor(s) 1160) for controlling and accessing object tracking data, with some examples of raw data access occurring via Ethernet channels. In at least one embodiment, a variety of RADAR sensor types may be used. For example, and without limitation, the RADAR sensor(s) 1160 can be suitable for front, rear and side RADAR use.In at least one embodiment, one or more sensors of RADAR sensor(s) 1160 are a pulse Doppler RADAR sensor. In at least one embodiment, the RADAR sensor(s) 1160 can comprise various configurations, such as long-range with a narrow field of view, near-range with a wide field of view, near-range with lateral coverage, etc. In at least one embodiment, long-range RADAR can be used for adaptive cruise control functionality. In at least one embodiment, long-range RADAR systems can provide a wide field of view, achieved by two or more independent scans, such as within a range of 250 m (meters). In at least one embodiment, the RADAR sensor(s) 1160 can help distinguish between static and moving objects and can be used by ADAS system 1138 for emergency braking assistance and forward collision warning.In at least one embodiment, sensor(s) 1160 included in long-range radar systems can, without limitation, comprise a monostatic multimodal radar with multiple (e.g., six or more) fixed radar antennas and a high-speed CAN and FlexRay interface. In at least one embodiment with six antennas, four antennas in the center can generate a focused beam pattern designed to detect the surroundings of vehicle 1100 at higher speeds with minimal interference from traffic in adjacent lanes. In at least one embodiment, two additional antennas can extend the field of view, enabling the rapid detection of vehicles entering or leaving the lane of vehicle 1100. In at least one embodiment, mid-range radar systems can, for example, have a range of up to 160 m (front) or 80 m (rear) and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, short-range radar systems can, without limitation, include any number of radar sensor(s) 1160 designed to be installed at both ends of a rear bumper. When installed at both ends of a rear bumper, in at least one embodiment, a radar sensor system can generate two beams that continuously monitor a blind spot behind and beside a vehicle. In at least one embodiment, short-range radar systems can be used in the ADAS system 1138 for blind spot detection and / or lane change assistance. In at least one embodiment, the vehicle 1100 may further comprise ultrasonic sensor(s) 1162. In at least one embodiment, the ultrasonic sensor(s) 1162, which may be positioned at the front, rear, and / or side of the vehicle 1100, may be used for parking assistance and / or for creating and updating an occupancy grid. In at least one embodiment, a variety of ultrasonic sensor(s) 1162 may be used, and different ultrasonic sensor(s) 1162 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensor(s) 1162 may operate at functional safety levels of ASIL B. In at least one embodiment, the vehicle 1100 can include the LIDAR sensor(s) 1164. In at least one embodiment, the LIDAR sensor(s) 1164 can be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the LIDAR sensor(s) 1164 can be operated at functional safety level ASIL B. In at least one embodiment, the vehicle 1100 can include multiple LIDAR sensors 1164 (e.g., two, four, six, etc.) that can use an Ethernet channel (e.g., to provide data to a Gigabit Ethernet switch). In at least one embodiment, the LIDAR sensor(s) 1164 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available LIDAR sensors 1164 may, for example, have an advertised range of approximately 100 m, with an accuracy of 2 cm to 3 cm, and with support for a 100 Mbit / s Ethernet connection. In at least one embodiment, one or more non-protruding LIDAR sensors may be used. In such an embodiment, the LIDAR sensor(s) 1164 may comprise a small device that can be embedded in a front, rear, side, and / or corner position of the vehicle 1100.In at least one embodiment, the LIDAR sensor(s) 1164 can provide a horizontal field of view of up to 120 degrees and a vertical field of view of up to 35 degrees with a range of 200 m, even for objects with low reflectivity. In at least one embodiment, the front-mounted LIDAR sensor(s) 1164 can be configured for a horizontal field of view between 45 degrees and 135 degrees. In at least one embodiment, LIDAR technologies, such as 3D flash LIDAR, can also be used. In at least one embodiment, 3D flash LIDAR uses a laser pulse as a transmission source to illuminate the environment of the vehicle 1100 up to a distance of approximately 200 m. In at least one embodiment, a flash LIDAR unit can, without limitation, include a receiver that records the travel time of the laser pulse and the reflected light on each pixel, which in turn corresponds to the distance between the vehicle 1100 and objects. In at least one embodiment, flash LIDAR can enable the generation of highly accurate and distortion-free images of environments with each laser pulse. In at least one embodiment, four flash LIDAR sensors can be used, one on each side of the vehicle 1100.In at least one embodiment, 3D flash LiDAR systems comprise, without limitation, a solid-state 3D staring array LiDAR camera with no moving parts other than a fan (e.g., a non-scanning LiDAR device). In at least one embodiment, the flash LiDAR device can use a 5-nanosecond Class I (eye-safe) laser pulse per frame and capture reflected laser light as a 3D area point cloud and co-registered intensity data. In at least one embodiment, the vehicle 1100 may further comprise IMU sensor(s) 1166. In at least one embodiment, the IMU sensor(s) 1166 may be arranged in the center of the rear axle of the vehicle 1100. In at least one embodiment, the IMU sensor(s) 1166 may, for example, and without limitation, comprise accelerometers, magnetometers, gyroscope(s), a magnetic compass, magnetic compasses, and / or other sensor types. In at least one embodiment, such as in six-axis applications, the IMU sensor(s) 1166 may, without limitation, comprise accelerometers and gyroscopes. In at least one embodiment, such as in nine-axis applications, the IMU sensor(s) 1166 may, without limitation, comprise accelerometers, gyroscopes, and magnetometers. In at least one embodiment, the IMU sensor(s) 1166 can be implemented as a miniaturized, high-performance GPS-based inertial navigation system (“GPS / INS”) that combines microelectromechanical (“MEMS”) inertial sensors, a high-sensitivity GPS receiver, and advanced Kalman filter algorithms to provide estimates of position, speed, and orientation. In at least one embodiment, the IMU sensor(s) 1166 can enable the vehicle 1100 to estimate its course without requiring input from a magnetic sensor by directly observing changes in speed from a GPS and correlating them with the IMU sensor(s) 1166. In at least one embodiment, the IMU sensor(s) 1166 and GNSS sensor(s) 1158 can be combined in a single integrated unit. In at least one embodiment, vehicle 1100 can include microphone(s) 1196, which is / are arranged in and / or around the vehicle 1100. In at least one embodiment, the microphone(s) 1196 can be used, among other things, for emergency vehicle detection and identification. In at least one embodiment, the vehicle 1100 may further comprise any number of camera types, including stereo camera(s) 1168, wide-angle camera(s) 1170, infrared camera(s) 1172, surround-view camera(s) 1174, long-range camera(s) 1198, mid-range camera(s) 1176, and / or other camera types. In at least one embodiment, cameras may be used to capture image data around the entire circumference of the vehicle 1100. In at least one embodiment, the type of cameras used depends on the vehicle 1100. In at least one embodiment, any combination of camera types may be used to provide the required coverage around the vehicle 1100. In at least one embodiment, the number of cameras provided may vary depending on the embodiment.For example, in at least one embodiment, the vehicle 1100 may include six cameras, seven cameras, ten cameras, twelve cameras, or any other number of cameras. In at least one embodiment, cameras may, for example, and without limitation, support Gigabit Multimedia Serial Link (“GMSL”) and / or Gigabit Ethernet. In at least one embodiment, each camera could be described in more detail, as shown here with reference to Figures 11A and 11B. In at least one embodiment, the vehicle 1100 may further comprise vibration sensor(s) 1142. In at least one embodiment, the vibration sensor(s) 1142 may measure vibrations of components of the vehicle 1100, such as the axle(s). For example, in at least one embodiment, changes in vibration may indicate a change in road surfaces. In at least one embodiment, if two or more vibration sensors 1142 are used, differences between the vibrations may be used to determine friction or slippage of the road surface (e.g., if there is a difference in vibration between a driven axle and a freely rotating axle). In at least one embodiment, the vehicle 1100 may include the ADAS system 1138. In at least one embodiment, the ADAS system 1138 may, without limitation, include a system of control (SoC) in some examples. In at least one embodiment, the ADAS system 1138 may, without limitation, include any number and combination of an autonomous / adaptive / automatic cruise control (“ACC”), a cooperative adaptive cruise control (“CACC”), a forward collision warning (“FCW”) system, an automatic emergency braking (“AEB”) system, a lane keeping assist (“LKA”) system, a blind spot warning (“BSW”) system, a rear cross traffic alert (“RCTW”) system, a collision warning (“CW”) system, a lane centering (“LC”) system, and / or other systems, features, and / or functions. In at least one embodiment, the ACC system can use RADAR sensor(s) 1160, LIDAR sensor(s) 1164, and / or any number of cameras. In at least one embodiment, the DACC system can comprise a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, a longitudinal ACC system monitors and controls the distance to a vehicle immediately in front of vehicle 1100 and automatically adjusts the speed of vehicle 1100 to maintain a safe distance from vehicles ahead. In at least one embodiment, a lateral ACC system maintains the distance and instructs vehicle 1100 to change lanes if necessary. In at least one embodiment, a lateral ACC refers to other ADAS applications, such as LC and CW. In at least one embodiment, a CACC system uses information from other vehicles that can be received via network interface 1124 and / or wireless antenna(s) 1126 from other vehicles via a wireless connection or indirectly via a network connection (e.g., via the Internet). In at least one embodiment, direct connections can be provided via a vehicle-to-vehicle (“V2V”) communication link, while indirect connections can be provided via an infrastructure-to-vehicle (“I2V”) communication link. In general, V2V communication provides information about vehicles immediately ahead (e.g., vehicles that are directly in front of vehicle 1100 and in the same lane), while I2V communication provides information about traffic further ahead.In at least one embodiment, a CACC system can include both I2V and V2V information sources. In at least one embodiment, given the information about the vehicles ahead of vehicle 1100, a CACC system can be more reliable and has the potential to improve traffic flow and reduce congestion on the road. In at least one embodiment, an FCW system is designed to alert a driver to a hazard so that the driver can take corrective action. In at least one embodiment, an FCW system uses a forward-facing camera and / or one or more radar sensors 1160 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback, such as a display, a speaker, and / or a vibrating component. In at least one embodiment, an FCW system can provide a warning, such as a sound, a visual warning, a vibration, and / or a rapid braking pulse. In at least one embodiment, an AEB system detects an impending forward collision with another vehicle or object and can brake automatically if a driver does not intervene within a specific time or distance parameter. In at least one embodiment, an AEB system can use forward-facing camera(s) and / or radar sensor(s) 1160 coupled with a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when an AEB system detects a hazard, it will typically first warn a driver to take corrective action to avoid a collision. If the driver does not take corrective action, the AEB system can brake automatically with the intention of preventing or at least mitigating the effects of a predicted collision.In at least one embodiment, an AEB system may include techniques such as dynamic brake support and / or emergency braking. In at least one embodiment, an LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to warn the driver when the vehicle crosses lane markings. In at least one embodiment, an LDW system is not activated if a driver indicates an intentional lane departure, for example, by activating a turn signal. In at least one embodiment, an LDW system may use forward-facing cameras coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically connected to provide feedback to the driver, for example, via a display, a speaker, and / or a vibration component. In at least one embodiment, an LKA system is a variant of an LDW system.In at least one embodiment, an LKA system provides steering inputs or braking to correct vehicle 1100 when vehicle 1100 begins to leave its lane. In at least one embodiment, a BSW system detects vehicles in the vehicle's blind spot and warns the driver of their presence. In at least one embodiment, a BSW system can provide visual, audible, and / or tactile warnings to indicate that merging or changing lanes is unsafe. In at least one embodiment, a BSW system can provide an additional warning when a driver uses a turn signal. In at least one embodiment, a BSW system can use rear-facing camera(s) and / or radar sensor(s) 1160 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically connected to driver feedback, such as a display, a speaker, and / or an oscillating component. In at least one embodiment, an RCTW system can provide visual, audible, and / or tactile notification when an object is detected outside the field of view of the reversing camera while the vehicle 1100 is reversing. In at least one embodiment, an RCTW system includes an AEB system to ensure that the vehicle brakes are applied to avoid a collision. In at least one embodiment, an RCTW system can use one or more rear-facing radar sensors 1160 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback, such as a display, a speaker, and / or a vibrating component. In at least one embodiment, conventional ADAS systems can be prone to false positives, which can be annoying and distracting for a driver, but are generally not catastrophic, since conventional ADAS systems warn the driver and give the driver the opportunity to decide whether a safety condition actually exists and to act accordingly. In at least one embodiment, in the event of conflicting results, the vehicle 1100 decides for itself whether to consider a result from a primary computer or a secondary computer (e.g., a first controller or a second controller of controllers 1136). For example, in at least one embodiment, the ADAS system 1138 can be a backup and / or secondary computer that provides perceptual information to a rationality module of the backup computer.In at least one embodiment, a backup computer plausibility monitor can run redundant, diverse software on hardware components to detect errors in perception and dynamic driving tasks. In at least one embodiment, outputs from the ADAS system 1138 can be provided to a higher-level MCU. In at least one embodiment, if outputs from a primary computer and outputs from a secondary computer conflict, a monitoring MCU determines how to resolve the conflict to ensure safe operation. In at least one embodiment, a primary computer can be configured to provide a monitoring MCU with a confidence level indicating the primary computer's confidence in a chosen outcome. In at least one embodiment, if the confidence level exceeds a threshold, the monitoring MCU can follow the primary computer's instruction, regardless of whether the secondary computer provides a contradictory or inconsistent outcome. In at least one embodiment, if a confidence level does not meet a threshold and the primary and secondary computers report different outcomes (e.g., a conflict), a monitoring MCU can mediate between the computers to determine a suitable outcome. In at least one embodiment, a monitoring MCU can be configured to execute one or more neural networks that are trained and configured to determine, at least partially based on outputs from a primary computer and outputs from a secondary computer, the conditions under which the latter will provide false alarms. In at least one embodiment, neural network(s) in a monitoring MCU can learn when an output from a secondary computer can be trusted and when it cannot. For example, in at least one embodiment, if the secondary computer is a radar-based FCW system, one or more neural networks in this monitoring MCU can learn when an FCW system identifies metallic objects that do not actually pose a hazard, such as a drain grate or manhole cover, which trigger an alarm.In at least one embodiment, if a secondary computer is a camera-based LDW system, a neural network in a monitoring MCU can learn to override the LDW when cyclists or pedestrians are present and leaving the lane is indeed the safest maneuver. In at least one embodiment, a monitoring MCU can include at least one DLA or GPU suitable for running one or more neural networks with allocated memory. In at least one embodiment, the higher-level MCU can include and / or comprise a component of the SoC(s) 1104. In at least one embodiment, the ADAS system 1138 can include a secondary computer that performs ADAS functionality using conventional computer vision rules. In at least one embodiment, this secondary computer can use classic computer vision (if-then) rules, and the presence of a neural network(s) in the monitoring MCU can improve reliability, safety, and performance. For example, in at least one embodiment, the diverse implementation and intentional non-identity of the entire system makes it more fault-tolerant, e.g., but not limited to, errors caused by software (or software-hardware interfaces).For example, if, in at least one embodiment, a software bug or error exists in software running on a primary computer, and non-identical software code running on a secondary computer provides a consistent overall result, then a monitoring MCU can have greater confidence that the overall result is correct and that a bug in software or hardware on that primary computer will not cause a material error. In at least one embodiment, an output from the ADAS system 1138 can be fed into a perception block of a primary computer and / or into a dynamic driving task block of a primary computer. For example, if, in at least one embodiment, the ADAS system 1138 issues a forward collision warning due to an object immediately ahead, a perception block can use this information when identifying objects. In at least one embodiment, a secondary computer can have its own trained neural network, thus reducing the risk of false positives, as described herein. In at least one embodiment, vehicle 1100 may further comprise infotainment SoC 1130 (e.g., an onboard infotainment system (IVI)). Although illustrated and described as a single SoC, in at least one embodiment, the infotainment system 1130 need not be an SoC and may, without limitation, comprise two or more discrete components. In at least one embodiment, infotainment SoC 1130 may, without limitation, comprise a combination of hardware and software that can be used to provide audio (e.g., music, a personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., television, movies, streaming, etc.), telephone (e.g., hands-free calling), network connectivity (e.g., LTE, Wi-Fi, etc.), and / or information services (e.g.,Navigation systems, reversing parking assistance, a radio data system, vehicle-related information such as fuel level, total distance traveled, brake fluid level, oil level, door open / closed, air filter information, etc.) to be provided to the vehicle 1100. For example, the infotainment SoC 1130 could include radios, CD / DVD players, navigation systems, video players, USB and Bluetooth connectivity, car computers, in-vehicle entertainment, Wi-Fi, steering wheel audio controls, hands-free voice control, a head-up display (“HUD”), HMI display 1134, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, the infotainment SoC 1130 can further be used to provide information (e.g., visual and / or audible) to a user(s) of the vehicle 1100, such as...Information from the ADAS system 1138, autonomous driving information such as planned vehicle maneuvers, trajectories, environmental information (e.g. intersection information, vehicle information, road information, etc.) and / or other information. In at least one embodiment, the infotainment SoC 1130 can include any quantity and type of GPU functionality. In at least one embodiment, the infotainment SoC 1130 can communicate with other devices, systems, and / or components of the vehicle 1100 via bus 1102. In at least one embodiment, the infotainment SoC 1130 can be coupled with a monitoring MCU so that the GPU of the infotainment system can perform some self-driving functions if the primary controller(s) 1136 (e.g., the primary and / or backup computers of the vehicle 1100) fails. In at least one embodiment, the infotainment SoC 1130 can place the vehicle 1100 into a drive-to-safe-stop mode, as described herein. In at least one embodiment, vehicle 1100 may further comprise a combination instrument 1132 (e.g., a digital dashboard, an electronic combination instrument, a digital instrument panel, etc.). In at least one embodiment, the combination instrument 1132 may, without limitation, comprise a controller and / or a supercomputer (e.g., a discrete controller or a supercomputer). In at least one embodiment, the combination instrument 1132 may, without limitation, comprise any number and combination of a set of instruments, such as a speedometer, fuel gauge, oil pressure gauge, tachometer, odometer, turn signals, gear indicator, seat belt warning light(s), parking brake warning light(s), engine malfunction light(s), information on additional restraint systems (e.g., airbags), lighting controls, safety system controls, navigation information, etc.In some examples, information can be displayed and / or shared between the infotainment SoC 1130 and the instrument cluster 1132. In at least one embodiment, the instrument cluster 1132 can be included as part of the infotainment SoC 1130, or vice versa. In at least one embodiment, Fig. 1-11C shows the performance, using one or more neural networks, of one or more perception tasks for higher-dimensional (e.g., 3D, 4D) images based on an extension of the higher-dimensional images and / or an extension of lower-dimensional images (e.g., 2D, 3D). Fig. 11D is a diagram of a system for communication between cloud-based server(s) and autonomous vehicle 1100 of Fig. 11A according to at least one embodiment. In at least one embodiment, the system may include, among other things, one or more servers 1178, one or more networks 1190, and any number and type of vehicles, including the vehicle 1100. In at least one embodiment, the server(s) 1178 may, without limitation, include a plurality of GPUs 1184(A)-1184(H) (hereinafter collectively referred to as GPUs 1184), PCIe switches 1182(A)-1182(D) (hereinafter collectively referred to as PCIe switches 1182), and / or CPUs 1180(A)-1180(B) (hereinafter collectively referred to as CPUs 1180).In at least one embodiment, the GPUs 1184, the CPUs 1180, and the PCIe switches 1182 can be interconnected via high-speed interconnects, such as, but not limited to, NVIDIA's NVLink interfaces 1188 and / or PCIe connections 1186. In at least one embodiment, GPUs 1184 are connected via an NVLink and / or NVSwitch SoC, and GPUs 1184 and PCIe switches 1182 are connected via PCIe interconnects. Although eight GPUs 1184, two CPUs 1180, and four PCIe switches 1182 are illustrated, this is not to be understood as a limitation. In at least one embodiment, each of the server(s) 1178 can, without limitation, comprise any number of GPUs 1184, CPUs 1180, and / or PCIe switches 1182 in any combination. For example, in at least one embodiment, the server(s) 1178 may / could comprise eight, sixteen, thirty-two and / or more GPUs 1184. In at least one embodiment, the server(s) 1178 can receive image data from the vehicles via the network(s) 1190, representing images showing unexpected or changed road conditions, such as recently commenced roadworks. In at least one embodiment, the server(s) 1178 can transmit neural networks 1192, updated neural networks, and / or map information 1194, including, without limitation, information about traffic and road conditions, to the vehicles via the network(s) 1190. In at least one embodiment, updates to the map information 1194 can, without limitation, include updates to the HD map 1122, such as information about construction sites, potholes, detours, floods, and / or other obstacles.In at least one embodiment, the neural networks 1192 and / or the map information 1194 can result from new training and / or experience represented in data received from any number of vehicles in an environment, and / or be based on training performed in a data center (e.g. using the server(s) 1178 and / or other servers). In at least one embodiment, the server(s) 1178 can be used to train machine learning models (e.g., neural networks) at least partially based on training data. In at least one embodiment, training data can be generated from vehicles and / or in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is tagged (e.g., if the connected neural network benefits from supervised learning) and / or subjected to other preprocessing. In at least one embodiment, any amount of training data is not tagged and / or preprocessed (e.g., if the connected neural network does not require supervised learning). In at least one embodiment, once machine learning models are trained, machine learning models of vehicles (e.g.,(transmitted via network(s) 1190 to vehicles) and / or machine learning models can be used by server(s) 1178 for remote monitoring of vehicles. In at least one embodiment, Server 1178 can receive data from vehicles and apply that data to current real-time neural networks for intelligent real-time inference. In at least one embodiment, Server 1178 can include deep learning supercomputers and / or dedicated AI computers powered by GPU(s) 1184, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, Server 1178 can include deep learning infrastructure that uses CPU-powered data centers. In at least one embodiment, the deep learning infrastructure of server(s) 1178 can be capable of performing fast, real-time inference and can use this capability to assess and verify the state of the processors, software, and / or associated hardware in vehicle 1100. For example, in at least one embodiment, the deep learning infrastructure can receive periodic updates from vehicle 1100, such as a sequence of images and / or objects that vehicle 1100 has located within that sequence of images (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure can execute its own neural network to identify objects and compare them with objects identified by vehicle 1100.If the results do not match and the deep learning infrastructure concludes that AI in vehicle 1100 is not functioning correctly, the server(s) 1178 can send a signal to vehicle 1100 instructing a fail-safe computer in vehicle 1100 to take over control, notify the passengers, and perform a safe parking maneuver. In at least one embodiment, the server(s) 1178 may include the GPU(s) 1184 and one or more programmable inference accelerators (e.g., NVIDIA TensorRT 3 devices) for inference. In at least one embodiment, a combination of GPU-powered servers and inference acceleration may enable real-time responsiveness. In at least one embodiment, for example, where performance is less critical, servers powered by CPUs, FPGAs, and other processors may be used to perform inference. In at least one embodiment, hardware structures 815 are used to implement one or more embodiments. Details regarding the hardware structure(s) 815 are provided herein in conjunction with Figures 8A and / or 8B. COMPUTER SYSTEMS Fig. 12 is a block diagram illustrating an exemplary computer system, which may be a system with interconnected devices and components, a system-on-a-chip (SoC), or a combination thereof, configured with a processor that may include execution units for executing an instruction according to at least one embodiment. In at least one embodiment, the computer system 1200 may, without limitation, include a component such as a processor 1202 to utilize execution units, including logic, for executing algorithms for processing data according to the present disclosure, for example, in the embodiment described herein. In at least one embodiment, the computer system 1200 may include processors such as, for example,The system may feature the PENTIUM®, Xeon™, Itanium®, XScale™ and / or StrongARM™ processor family, Intel® Core™ or Intel® Nervana™ microprocessors available from Intel Corporation in Santa Clara, California, although other systems (including PCs with other microprocessors, technical workstations, set-top boxes, and the like) may also be used. In at least one embodiment, the Computer System 1200 may run a version of the WINDOWS operating system available from Microsoft Corporation in Redmond, Washington, although other operating systems (for example, UNIX and Linux), embedded software, and / or graphical user interfaces may also be used. Embodiments can be used in other devices, such as portable devices and embedded applications. Some examples of portable devices include mobile phones, Internet Protocol devices, digital cameras, personal digital assistants (PDAs), and portable PCs. In at least one embodiment, embedded applications can include a microcontroller, a digital signal processor (DSP), a system-on-a-chip, network computers (NetPCs), set-top boxes, network hubs, wide-area network switches (WAN switches), or any other system capable of executing one or more instructions according to at least one embodiment. In at least one embodiment, computer system 1200 can, without limitation, comprise processor 1202, which can, without limitation, include one or more execution units 1208 for performing machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, computer system 1200 is a desktop or server system with a single processor; however, in another embodiment, computer system 1200 can be a multiprocessor system. In at least one embodiment, processor 1202 can, without limitation, comprise a complex instruction set computer microprocessor (“CISC” microprocessor), a reduced instruction set computing microprocessor (“RISC” microprocessor), a very long instruction word microprocessor (“VLIW” microprocessor), a processor implementing a combination of instruction sets, or any other device, such as a digital signal processor.In at least one embodiment, processor 1202 can be coupled to a processor bus 1210, which can transmit data signals between processor 1202 and other components in computer system 1200. In at least one embodiment, processor 1202 can have an internal Level 1 cache memory (“L1” cache memory) (“cache”) 1204 without restriction. In at least one embodiment, processor 1202 can have a single internal cache or multiple levels of an internal cache. In at least one embodiment, cache memory can be located outside of processor 1202. Other embodiments can also include a combination of internal and external cache memories, depending on the specific implementation and requirements. In at least one embodiment, a register file 1206 can store different data types in different registers, including, in particular, integer registers, floating-point registers, status registers, and an instruction pointer register. In at least one embodiment, processor 1202 also includes an execution unit 1208, in particular logic for performing integer and floating-point operations. In at least one embodiment, processor 1202 may also include a read-only memory (“ROM”) for microcode (“ucode”) that stores microcode for specific macro instructions. In at least one embodiment, execution unit 1208 may include logic for handling a packed instruction set 1209. By including a packed instruction set 1209 in an instruction set of a general-purpose processor together with associated circuitry, operations used by many multimedia applications can be performed using packed data in a processor 1202, according to at least one embodiment.In at least one embodiment, many multimedia applications can be accelerated and run more efficiently by using an entire width of a processor's data bus to perform operations on packed data, which can eliminate the need to transfer smaller data units across the processor's data bus to perform one or more operations sequentially on individual data elements. In at least one embodiment, the execution unit 1208 can also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, the computer system 1200 can include a memory 1220 without restriction. In at least one embodiment, the memory 1220 can be a dynamic random access memory device (“DRAM” device), a static random access memory device (“SRAM” device), a flash memory device, or another type of memory device. In at least one embodiment, the memory 1220 can store instructions 1219 and / or data 1221, which are represented by data signals that can be executed by the processor 1202. In at least one embodiment, a system logic chip can be coupled to the processor bus 1210 and the memory 1220. In at least one embodiment, the system logic chip can, without restriction, include a memory control hub (“MCH”) 1216, and the processor 1202 can communicate with the MCH 1216 via the processor bus 1210. In at least one embodiment, the MCH 1216 can provide a high-bandwidth memory path 1218 to memory 1220 for instruction and data storage, as well as for storing graphics instructions, data, and textures. In at least one embodiment, the MCH 1216 can route data signals between the processor 1202, memory 1220, and other components in the computer system 1200, and bridge data signals between the processor bus 1210, memory 1220, and a system I / O interface 1222. In at least one embodiment, a system logic chip can provide a graphics port for coupling with a graphics controller.In at least one embodiment, MCH 1216 can be coupled to memory 1220 via a high-bandwidth memory path 1218, and graphics / video card 1212 can be coupled to MCH 1216 via an Accelerated Graphics Port (“AGP”) intermediate connection 1214. In at least one embodiment, computer system 1200 can use system I / O interface 1222 as a proprietary hub interface bus to couple MCH 1216 to an I / O control hub (“ICH”) 1230. In at least one embodiment, ICH 1230 can provide direct connections to some I / O devices via a local I / O bus. In at least one embodiment, a local I / O bus can, without limitation, include a high-speed I / O bus for connecting peripheral devices to memory 1220, a chipset, and a processor 1202. Examples may include an audio control 1229, a firmware hub (“Flash BIOS”) 1228, a wireless transceiver 1226, a data storage device 1224, a legacy I / O control 1223 with user input and keyboard interfaces 1225, a serial expansion port 1227, such as a Universal Serial Bus port (“USB”), and a network control 1234.In at least one embodiment, the data storage device 1224 may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device or another mass storage device. In at least one embodiment, Fig. 12 illustrates a system comprising interconnected hardware devices or “chips,” while in other embodiments, Fig. 12 may illustrate an exemplary SoC. In at least one embodiment, the devices illustrated in Fig. 12 may be interconnected by proprietary interconnects, standardized interconnects (e.g., PCIe), or a combination thereof. In at least one embodiment, one or more components of Computer System 1200 are interconnected by Compute Express Link (CXL) interconnects. Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding Logic 815 are provided herein in conjunction with Figures 8A and / or 8B. In at least one embodiment, Logic 815 can be used in the computer system 1200 for inference or prediction operations based, at least partially, on weighting parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein. In at least one embodiment, Figs. 1-12 show the performance, using one or more neural networks, of one or more perception tasks for higher-dimensional (e.g., 3D, 4D) images based on an extension of the higher-dimensional images and / or an extension of lower-dimensional images (e.g., 2D, 3D). Fig. 13 is a block diagram illustrating an electronic device 1300 for using a processor 1310 according to at least one embodiment. In at least one embodiment, the electronic device 1300 can be, for example, and without limitation, a notebook, a tower server, a rack server, a blade server, a laptop, a desktop computer, a tablet, a mobile device, a telephone, an embedded computer, or any other suitable electronic device. In at least one embodiment, the electronic device 1300 can, without limitation, comprise a processor 1310, which is communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor 1310 is coupled via a bus or interface, such as an I2C bus, a system management bus (“SMBus”), a low-pin-count (LPC) bus, a serial peripheral interface (“SPI”), a high-definition audio (“HDA”) bus, a serial advance technology attachment (“SATA”) bus, a universal serial bus (“USB”) (versions 1, 2, 3, etc.), or a universal asynchronous receiver / transmitter (“UART”) bus. In at least one embodiment, Fig. 13 illustrates a system comprising interconnected hardware devices or “chips,” while in other embodiments, Fig. 13 may illustrate an exemplary SoC.In at least one embodiment, the devices illustrated in Fig. 13 can be interconnected using proprietary interconnects, standardized interconnects (e.g., PCIe), or a combination thereof. In at least one embodiment, one or more components from Fig. 13 are interconnected via Compute Express Link (CXL) interconnects. In at least one embodiment, Fig. 13 can show a display 1324, a touchscreen 1325, a touchpad 1330, a near field communication (“NFC”) 1345, a sensor hub 1340, a temperature sensor 1346, an Express chipset (“EC”) 1335, a Trusted Platform Module (“TPM”) 1338, BIOS / Firmware / Flash memory (“BIOS, FW Flash”) 1322, a DSP 1360, a drive 1320 such as a solid-state drive (“SSD”) or a hard disk drive (“HDD”), a wireless local area network (“WLAN”) 1350, a Bluetooth unit 1352, a wireless wide area network (“WWAN”) 1356, a global positioning system (GPS) unit 1355, a camera (“USB 3.0 camera”) 1354, These components include, for example, a USB 3.0 camera and / or a Low-Power Double Data Rate (LPDDR) memory unit (LPDDR3), implemented, for example, in the LPDDR3 standard. Each of these components can be implemented in any suitable way. In at least one embodiment, other components can be communicatively coupled to processor 1310 via the components described herein. In at least one embodiment, an accelerometer 1341, an ambient light sensor (“ALS”) 1342, a compass 1343, and a gyroscope 1344 can be communicatively coupled to the sensor hub 1340. In at least one embodiment, a temperature sensor 1339, a fan 1337, a keyboard 1336, and a touchpad 1330 can be communicatively coupled to EC 1335. In at least one embodiment, loudspeakers 1363, headphones 1364, and a microphone (“Mic”) 1365 can be communicatively coupled to an audio unit (“audio codec and Class-D amplifier”) 1362, which in turn can be communicatively coupled to DSP 1360. In at least one embodiment, audio unit 1362 can, for example and without limitation, comprise an audio encoder / decoder (“codec”) and a class-D amplifier.In at least one embodiment, a SIM card (“SIM”) 1357 can be communicatively coupled with a WWAN unit 1356. In at least one embodiment, components such as a WLAN unit 1350 and a Bluetooth unit 1352, as well as a WWAN unit 1356, can be implemented in a Next Generation Form Factor (“NGFF”). Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding Logic 815 are provided herein in conjunction with Figures 8A and / or 8B. In at least one embodiment, Logic 815 can be used in electronic devices 1300 for inference or prediction of operations based, at least partially, on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein. In at least one embodiment, Figs. 1-13 show the performance, using one or more neural networks, of one or more perception tasks for higher-dimensional (e.g., 3D, 4D) images based on an extension of the higher-dimensional images and / or an extension of lower-dimensional images (e.g., 2D, 3D). Fig. 14 illustrates a computer system 1400 according to at least one embodiment. In at least one embodiment, the computer system 1400 is configured to implement various processes and procedures described in this disclosure. In at least one embodiment, the computer system 1400 comprises, without limitation, at least one central processing unit (“CPU”) 1402 connected to a communication bus 1410 implemented using any suitable protocol, such as PCI (“Peripheral Component Interconnect”), Peripheral Component Interconnect Express (“PCI Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or one or more other bus or point-to-point communication protocols. In at least one embodiment, the computer system 1400 comprises, without limitation, main memory 1404 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in main memory 1404, which may be in the form of random-access memory (“RAM”).In at least one embodiment, a network interface subsystem (“network interface”) 1422 provides an interface to other computing devices and networks to receive data from other systems and to transmit data to other systems using computer system 1400. In at least one embodiment, the computer system 1400 comprises, without limitation, input devices 1408, a parallel processing system 1412, and display devices 1406, which may be implemented using a conventional cathode ray tube (“CRT”), a liquid crystal display (“LCD”), a light-emitting diode (“LED”), a plasma display, or other suitable display technologies. In at least one embodiment, user input is received from input devices 1408 such as a keyboard, mouse, touchpad, microphone, etc. In at least one embodiment, all the modules described herein may be arranged on a single semiconductor platform to form a processing system. Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 815 are provided herein in conjunction with Figures 8A and / or 8B. In at least one embodiment, logic 815 can be used in the computer system 1400 for inference or prediction of operations based, at least partially, on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein. In at least one embodiment, Figs. 1-14 show the performance, using one or more neural networks, of one or more perception tasks for higher-dimensional (e.g., 3D, 4D) images based on an extension of the higher-dimensional images and / or an extension of lower-dimensional images (e.g., 2D, 3D). Fig. 15 illustrates a computer system 1500 according to at least one embodiment. In at least one embodiment, the computer system 1500 comprises, without limitation, a computer 1510 and a USB stick 1520. In at least one embodiment, the computer 1510 can comprise, without limitation, any number and type of processor(s) (not shown) and memory (not shown). In at least one embodiment, the computer 1510 comprises, without limitation, a server, a cloud instance, a laptop, and a desktop computer. In at least one embodiment, the USB stick 1520 comprises, without limitation, a processing unit 1530, a USB interface 1540, and USB interface logic 1550. In at least one embodiment, the processing unit 1530 can be any instruction execution system, instruction execution device, or instruction execution device capable of executing instructions. In at least one embodiment, the processing unit 1530 can comprise, without limitation, any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1530 comprises an application-specific integrated circuit (“ASIC”) optimized to perform any number and type of operations associated with machine learning.For example, in at least one embodiment, the processing unit 1530 is a tensor processing unit (“TPC”) optimized to perform machine learning inference operations. For example, in at least one embodiment, the processing unit 1530 is a tensor processing unit (“TPC”) optimized to perform machine vision and machine learning inference operations. In at least one embodiment, the USB interface 1540 can be any type of USB connector or USB socket. For example, in at least one embodiment, the USB interface 1540 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, the USB interface 1540 is a USB 3.0 Type-A connector. In at least one embodiment, the USB interface logic 1550 can comprise any amount and type of logic that enables the processing unit 1530 to interface with devices (e.g., computers 1510) via the USB connector 1540. Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding Logic 815 are provided herein in conjunction with Figures 8A and / or 8B. In at least one embodiment, Logic 815 can be used in the computer system 1500 for inference or prediction of operations based, at least partially, on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein. In at least one embodiment, Figs. 1-15 show the performance, using one or more neural networks, of one or more perception tasks for higher-dimensional (e.g., 3D, 4D) images based on an extension of the higher-dimensional images and / or an extension of lower-dimensional images (e.g., 2D, 3D). Figure 16A illustrates an exemplary architecture in which a plurality of GPUs 1610(1)-1610(N) are communicatively coupled to a plurality of multi-core processors 1605(1)-1605(M) via high-speed transmission links 1640(1)-1640(N) (e.g., buses, point-to-point links, etc.). In at least one embodiment, the high-speed transmission links 1640(1)-1640(N) support a communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or higher. In at least one embodiment, various interconnect protocols can be used, including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0. In various figures, “N” and “M” represent positive integers, the values ​​of which can differ from figure to figure. In at least one embodiment, one or more GPUs in a plurality of GPUs 1610(1)-1610(N) comprise one or more graphics cores (also simply referred to as ‘cores’) 1900, as shown in Fig. 19A and Fig.19B disclosed. In at least one embodiment, one or more graphics cores 1900 can be designated as streaming multiprocessors (“SMs”), stream processors (“SPs”), stream processing units (“SPUs”), compute units (“CUs”), execution units (“EUs”) and / or slices, wherein a slice in this context can refer to a section of the processing resources in a processing unit (e.g. 16 cores, a ray tracing unit, a thread director or scheduler). Additionally, in at least one embodiment, two or more GPUs 1610 are interconnected via high-speed transmission links 1629(1)-1629(2), which may be implemented using similar or different protocols / transmission links than those used for high-speed transmission links 1640(1)-1640(N). Similarly, two or more multi-core processors 1605 may be interconnected via a high-speed transmission link 1628, which may be a symmetric multi-processor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s or higher. Alternatively, all communication between different system components shown in Fig. 16A may be performed using similar protocols / transmission links (e.g., via a common interconnection fabric). In at least one embodiment, each multi-core processor 1605 is communicatively coupled to a processor memory 1601(1)-1601(M) via memory interconnects 1626(1)-1626(M), and each GPU 1610(1)-1610(N) is communicatively coupled to a GPU memory 1620(1)-1620(N) via GPU memory interconnects 1650(1)-1650(N). In at least one embodiment, the memory interconnects 1626 and 1650 can utilize similar or other memory access technologies. By way of example and without limitation, the processor memory 1601(1)-1601(M) and the GPU memory 1620 can be volatile memory such as dynamic random access memory (DRAMs) (including stacked DRAMs), Graphics DDR SDRAM (GDDR) (e.g. GDDR5, GDDR6) or High Bandwidth Memory (HBM) and / or can be non-volatile memory such as 3D XPoint or Nano-RAM.In at least one embodiment, part of the processor memory 1601 can be volatile memory and another part can be non-volatile memory (e.g. using a two-level memory hierarchy (2LM hierarchy)). As described herein, although different multi-core processors 1605 and GPUs 1610 can each be physically coupled to a specific memory 1601, 1620, and / or a unified memory architecture can be implemented in which a virtual system address space (also called the "effective address space") is distributed among different physical memories, the processor memories 1601(1)-1601(M) can each have 64 GB of system memory address space, and the GPU memories 1620(1)-1620(N) can each have 32 GB of system memory address space, leaving a total of 256 GB of addressable memory if M=2 and N=4. Other values ​​for N and M are possible. Fig. 16B illustrates further details of an interconnection between a multi-core processor 1607 and a graphics acceleration module 1646 according to an exemplary embodiment. In at least one embodiment, the graphics acceleration module 1646 can comprise one or more GPU chips integrated on a circuit board, which is coupled to the processor 1607 via a high-speed transmission link 1640 (e.g., a PCIe bus, NVLink, etc.). Alternatively, in at least one embodiment, the graphics acceleration module 1646 can be integrated in a single package or chip with the processor 1607. In at least one embodiment, the processor 1607 comprises a plurality of cores 1660A-1660D (which may be referred to as "execution units"), each with a translation lookaside buffer ("TLB") 1661A-1661D and one or more caches 1662A-1662D. In at least one embodiment, the cores 1660A-1660D may include various other components for executing instructions and processing data, which are not illustrated. In at least one embodiment, the caches 1662A-1662D may include Level 1 (L1) and Level 2 (L2) caches. Additionally, one or more shared caches 1656 may be included in the caches 1662A-1662D and shared by sets of cores 1660A-1660D. For example, one embodiment of the 1607 processor comprises 24 cores, each with its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches.In this embodiment, one or more L2 and L3 caches are shared by two adjacent cores. In at least one embodiment, the processor 1607 and the graphics acceleration module 1646 are connected to the system memory 1614, which may include the processor memories 1601(1)-1601(M) from Fig. 16A. In at least one embodiment, coherence for data and instructions stored in various caches 1662A-1662D, 1656, and system memory 1614 is maintained via inter-core communication over a coherence bus 1664. In at least one embodiment, for example, each cache can have its own associated cache coherence logic / circuit arrangement to communicate over the coherence bus 1664 in response to detected read or write operations on specific cache rows. In at least one embodiment, a cache snooping protocol is implemented over the coherence bus 1664 to monitor cache accesses. In at least one embodiment, a proxy circuit 1625 communicatively couples the graphics acceleration module 1646 to the coherence bus 1664, thereby enabling the graphics acceleration module 1646 to participate in a cache coherence protocol as a peer of cores 1660A-1660D. In particular, in at least one embodiment, an interface 1635 provides connectivity to the proxy circuit 1625 via the high-speed transmission link 1640, and an interface 1637 connects the graphics acceleration module 1646 to the high-speed transmission link 1640. In at least one embodiment, an accelerator integration circuit 1636 provides cache management, memory access, context management, and interrupt management services on behalf of a plurality of graphics processing engines 1631(1)-1631(N) of the graphics acceleration module 1646. In at least one embodiment, the graphics processing engines 1631(1)-1631(N) can each include a separate graphics processing unit (GPU). In at least one embodiment, the plurality of graphics processing engines 1631(1)-1631(N) of the graphics acceleration module 1646 comprise one or more graphics cores 1900, as described in conjunction with Figures 19A and 19B. In at least one embodiment, the graphics processing engines 1631(1)-1631(N) may alternatively comprise different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g.Video encoder / decoder), sampler and blith engines. In at least one embodiment, the graphics acceleration module 1646 can be a GPU with a plurality of graphics processing engines 1631(1)-1631(N) or the graphics processing engines 1631(1)-1631(N) can be individual GPUs integrated in a common package, line card or chip. In at least one embodiment, the accelerator integration circuit 1636 comprises a memory management unit (MMU) 1639 for performing various memory management functions, such as virtual-to-physical memory translations (also referred to as effective-to-real memory translations) and memory access protocols for accessing the system memory 1614. In at least one embodiment, the MMU 1639 may further comprise a translation lookaside buffer (TLB) (not shown) for temporarily storing virtual / effective-to-physical / real address translations. In at least one embodiment, a cache 1638 may store instructions and data for efficient access by the graphics processing engines 1631(1)-1631(N).In at least one embodiment, coherence is maintained for data stored in the cache 1638 and the graphics memories 1633(1)-1633(M) with core caches 1662A-1662D, 1656 and the system memory 1614, possibly using a retrieval unit 1644. As mentioned, this can be done via the proxy circuit 1625 on behalf of the cache 1638 and the memories 1633(1)-1633(M) (e.g., sending updates to the cache 1638 regarding modifications / accesses of cache lines on processor caches 1662A-1662D, 1656 and receiving updates from the cache 1638). In at least one embodiment, a set of registers 1645 stores context data for threads executed by the graphics processing engines 1631(1)-1631(N), and a context management circuit 1648 manages thread contexts. For example, a context management circuit 1648 can perform backup and restore operations to save and restore the contexts of different threads during context switches (e.g., saving a first thread and saving a second thread so that a second thread can be executed by a graphics processing engine). For example, during a context switch, the context management circuit 1648 can store current register values ​​in a specific region of memory (e.g., identified by a context pointer). It can then restore register values ​​upon returning to a context.In at least one embodiment, an interrupt management circuit 1647 receives and processes interruptions received from system devices. In at least one embodiment, virtual / effective addresses from a graphics processing engine 1631 are translated by an MMU 1639 to real / physical addresses in system memory 1614. In at least one embodiment, an accelerator integration circuit 1636 supports multiple (e.g., 4, 8, 16) graphics acceleration modules 1646 and / or other accelerator devices. In at least one embodiment, the graphics acceleration module 1646 can be dedicated to a single application running on the processor 1607 or can be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is provided in which resources from the graphics processing engines 1631(1)-1631(N) are shared with multiple applications or virtual machines (VMs).In at least one embodiment, resources can be divided into “slices” that are assigned to different VMs and / or applications based on processing requirements and assigned priorities of VMs and / or applications. In at least one embodiment, the accelerator integration circuit 1636 acts as a bridge to a system for the graphics acceleration module 1646 and provides address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integration circuit 1636 can provide virtualization facilities for a host processor to manage virtualization of the graphics processing engines 1631(1)-1631(N), interrupts, and memory management. In at least one embodiment, because hardware resources from the graphics processing engines 1631(1)-1631(N) are explicitly mapped to a real address space seen by the host processor 1607, each host processor can directly address these resources using an effective address value. In at least one embodiment, a function of the accelerator integration circuit 1636 is a physical separation of the graphics processing engines 1631(1)-1631(N), so that they appear to a system as independent units. In at least one embodiment, one or more graphics memories 1633(1)-1633(M) are coupled to each of the graphics processing engines 1631(1)-1631(N), and N=M. In at least one embodiment, the graphics memories 1633(1)-1633(M) store instructions and data that are processed by each of the graphics processing engines 1631(1)-1631(N). In at least one embodiment, the graphics memories 1633(1)-1633(M) can be volatile memory such as DRAMs (including stacked DRAMs), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memory such as 3D XPoint or NanoRAM. In at least one embodiment, to reduce data traffic over the high-speed transmission path 1640, biasing techniques can be used to ensure that the data stored in the graphics memories 1633(1)-1633(M) is that which is most frequently used by the graphics processing engines 1631(1)-1631(N) and preferably is not used (or at least not frequently) by the cores 1660A-1660D. Similarly, in at least one embodiment, a biasing mechanism attempts to keep the data required by the cores (and preferably not by the graphics processors 1631(1)-1631(N)) in the caches 1662A-1662D, 1656, and in system memory 1614. Fig. 16C illustrates another exemplary embodiment in which the accelerator integration circuit 1636 is integrated within the processor 1607. In this embodiment, the graphics processing engines 1631(1)-1631(N) communicate directly with the accelerator integration circuit 1636 via the interface 1637 and the interface 1635 (which, again, can be any type of bus or interface protocol) over the high-speed transmission link 1640. In at least one embodiment, the accelerator integration circuit 1636 can perform similar operations to those described with reference to Fig. 16B, but possibly with a higher throughput due to its immediate proximity to the coherence bus 1664 and the caches 1662A-1662D, 1656.In at least one embodiment, an accelerator integration circuit supports various programming models, including a dedicated process programming model (no graphics acceleration module virtualization) and shared programming models (with virtualization), which may include programming models controlled by the accelerator integration circuit 1636 and programming models controlled by the graphics acceleration module 1646. In at least one embodiment, the graphics processing engines 1631(1)-1631(N) are permanently assigned to a single application or process under a single operating system. In at least one embodiment, a single application can direct further application requests to the graphics processing engines 1631(1)-1631(N), thereby providing virtualization within a VM / partition. In at least one embodiment, the graphics processing engines 1631(1)-1631(N) can be shared by multiple VM / application partitions. In at least one embodiment, shared models can use a system hypervisor to virtualize the graphics processing engines 1631(1)-1631(N) to allow access by any operating system. In at least one embodiment, for single-partition systems without a hypervisor, the graphics processing engines 1631(1)-1631(N) are part of an operating system. In at least one embodiment, an operating system can virtualize the graphics processing engines 1631(1)-1631(N) to provide access to any process or application. In at least one embodiment, the graphics acceleration module 1646 or a single graphics processing engine 1631(1)-1631(N) selects a process element using a process handle. In at least one embodiment, process elements are stored in the system memory 1614 and are addressable using an effective address-to-real address translation technique described herein. In at least one embodiment, a process handle can be an implementation-specific value provided to a host process when it registers its context with the graphics processing engines 1631(1)-1631(N) (that is, calls system software to add a process element to a linked list of process elements). In at least one embodiment, lower 16 bits of a process handle can be an offset of a process element within a linked list of process elements. Fig. 16D illustrates an exemplary accelerator integration slice 1690. In at least one embodiment, a "slice" comprises a specified section of the processing resources of an accelerator integration circuit 1636. In at least one embodiment, an effective address space 1682 of an application stores process elements 1683 within the system memory 1614. In at least one embodiment, process elements 1683 are stored in response to GPU calls 1681 from applications 1680 running on processor 1607. In at least one embodiment, a process element 1683 contains a process state for the corresponding application 1680. In at least one embodiment, a work descriptor (WD) 1684 contained in the process element 1683 can be a single job requested by an application or can contain a pointer to a queue of jobs.In at least one embodiment, WD 1684 is a pointer to a job queue in an application effective address space 1682. In at least one embodiment, the graphics acceleration module 1646 and / or individual graphics processing engines 1631(1)-1631(N) can be shared by all or a subset of processes in a system. In at least one embodiment, an infrastructure for setting process states and sending a WD 1684 to a graphics acceleration module 1646 to start a job in a virtualized environment can be included. In at least one embodiment, a dedicated process programming model is implementation-specific. In at least one embodiment, in this model, a single process owns the graphics acceleration module 1646 or a single graphics processing engine 1631. In at least one embodiment, when the graphics acceleration module 1646 belongs to a single process, a hypervisor initializes an accelerator integration circuit 1636 for an associated partition, and an operating system initializes an accelerator integration circuit 1636 for an associated process when the graphics acceleration module 1646 is allocated. In at least one embodiment, a WD retrieval unit 1691 operating in an accelerator integration slice 1690 retrieves the nearest WD 1684, which includes a specification of the work to be performed by one or more graphics processing engines of the graphics acceleration module 1646. In at least one embodiment, data from the WD 1684 can be stored in the registers 1645 and used by the MMU 1639, the interrupt management circuit 1647, and / or the context management circuit 1648, as illustrated. For example, one embodiment of the MMU 1639 includes a segment / page table pass-through circuit for accessing segment / page tables 1686 within a virtual OS address space 1685. In at least one embodiment, the interrupt management circuit 1647 can process interrupt events 1692 received from the graphics acceleration module 1646.In at least one embodiment, when graphics operations are performed, an effective address 1693 generated by a graphics processing engine 1631(1)-1631(N) is translated into a real address by the MMU 1639. In at least one embodiment, registers 1645 are duplicated for each graphics processing engine 1631(1)-1631(N) and / or each graphics acceleration module 1646 and can be initialized by a hypervisor or an operating system. In at least one embodiment, each of these duplicated registers can be included in an accelerator integration slice 1690. Examples of registers that can be initialized by a hypervisor are shown in Table 1. Table 1 - Registers initialized by hypervisor 1Slice tax register 2 Pointers to the Real Address (RA) area of ​​planned processes 3. Authorization mask override register 4. Offset of an interruption vector table entry 5. Limit value of an interruption vector table entry 6. State Register 7 Logical Partition ID 8 pointers to a Real Address (RA) hypervisor accelerator usage record 9 Data storage description register Examples of registers that can be initialized by an operating system are shown in Table 2. Table 2 - Registers initialized by the operating system 1. Process and Thread Identification 2 Pointers for saving / restoring the Effective Address (IA) context 3 pointers to a Virtual Address (VA) accelerator usage record 4 pointers to a virtual address (VA) memory segment table 5. Authorization mask 6. Work descriptor In at least one embodiment, each WD 1684 is specific to a particular graphics acceleration module 1646 and / or a particular graphics processing engine 1631(1)-1631(N). In at least one embodiment, it contains all the information that a graphics processing engine 1631(1)-1631(N) needs to perform its work, or it can be a pointer to a memory location where an application has established a command queue of tasks to be executed. Fig. 16E illustrates further details for an exemplary embodiment of a shared model. This embodiment includes a hypervisor real address space 1698 in which a process element list 1699 is stored. In at least one embodiment, the hypervisor real address space 1698 is accessible via a hypervisor 1696, which virtualizes graphics acceleration module engines for an operating system 1695. In at least one embodiment, shared programming models allow all or a subset of processes from all or a subset of partitions in a system to use a 1646 graphics acceleration module. In at least one embodiment, there are two programming models in which the 1646 graphics acceleration module is shared by multiple processes and partitions: time-slotted sharing and graphics-controlled sharing. In at least one embodiment, the system hypervisor 1696 in this model includes the graphics acceleration module 1646 and makes its functions available to all operating systems 1695. In at least one embodiment, for a graphics acceleration module 1646 to support virtualization by a system hypervisor 1696, the graphics acceleration module 1646 may meet certain requirements, such as (1) an application job request must be autonomous (that is, state does not need to be maintained between jobs), or the graphics acceleration module 1646 must provide a context backup and recovery mechanism, (2) the graphics acceleration module 1646 guarantees that an application job request completes within a specified time period, including any translation errors.or the Graphics Acceleration Module 1646 provides a capability to displace one processing of a job, and (3) the Graphics Acceleration Module 1646 must be guaranteed fairness between processes when operating in a controlled, shared programming model. In at least one embodiment, the application 1680 must make a system call to an operating system 1695 with a graphics acceleration module type, a work descriptor (WD), an authorization mask register value (AMR value), and a context backup / restore area pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes a targeted acceleration function for a system call. In at least one embodiment, a graphics acceleration module type can be a system-specific value.In at least one embodiment, a WD is formatted specifically for the Graphics Acceleration Module 1646 and can be in the form of an instruction of the Graphics Acceleration Module 1646, an effective address pointer to a user-defined structure, an effective address pointer to a queue of instructions, or any other data structure for describing work to be performed by the Graphics Acceleration Module 1646. In at least one embodiment, an AMR value is an AMR state to be used for a current process. In at least one embodiment, a value passed to an operating system is similar to an application setting of an AMR. In at least one embodiment, if implementations of the accelerator integration circuit 1636 (not shown) and the graphics acceleration module 1646 do not support a user authority mask override register (UAMOR), an operating system can apply a current UAMOR value to an AMR value before an AMR is passed in a hypervisor call. In at least one embodiment, the hypervisor 1696 can optionally apply a current authority mask override register value (AMOR value) before an AMR is introduced into the process element 1683.In at least one embodiment, a CSRP is one of the registers 1645 that contains an effective address of a portion of the effective address space 1682 of an application of the graphics acceleration module 1646 for saving and restoring a context state. In at least one embodiment, this pointer is optional if no state needs to be retained between jobs or when a job is evicted. In at least one embodiment, a context memory / restore area can be locked system memory. Upon receiving a system call, the operating system 1695 can verify that the application 1680 is registered and has been granted permission to use the graphics acceleration module 1646. In at least one embodiment, the operating system 1695 then calls the hypervisor 1696 with the information shown in Table 3. Table 3 - Operating system-to-hypervisor call parameters 1Work Descriptor (WD) 2An Authority Mask Register value (AMR value) (potentially masked) 3 Effective Address Pointers (EA) for the Context Backup / Restore Area (CSRP) 4. A process ID (PID) and optional thread ID (TID) 5A virtual address pointer (VA) for the accelerator usage record area (AURP) 6. Virtual address of the segment table pointer (SSTP) 7A Logical Interrupt Service Number (LISN) In at least one embodiment, after receiving a hypervisor call, the hypervisor 1696 verifies that the operating system 1695 is registered and has been granted permission to use the graphics acceleration module 1646. In at least one embodiment, the hypervisor 1696 then adds the process element 1683 to a linked list of process elements for a corresponding type of graphics acceleration module 1646. In at least one embodiment, a process element may include information shown in Table 4. Table 4 - Process element information 1Work Descriptor (WD) 2An Authority Mask Register value (AMR value) (potentially masked). 3 Effective Address Pointers (EA) for the Context Backup / Restore Area (CSRP) 4. A process ID (PID) and optional thread ID (TID) 5A virtual address pointer (VA) for the accelerator usage record area (AURP) 6. Virtual address of the segment table pointer (SSTP) 7A Logical Interrupt Service Number (LISN) 8. Interruption vector table derived from hypervisor call parameters 9A status register value (SR value) 10A logical partition ID (LPID) 11 Pointers to a hypervisor accelerator usage record for a real address (RA) 12Storage Descriptor Register (SDR) In at least one embodiment, the hypervisor initializes a plurality of registers 1645 of an accelerator integration slice 1690. As illustrated in Fig. 16F, at least one embodiment uses a unified memory addressable using a common virtual memory address space for accessing physical processor memories 1601(1)-1601(N) and GPU memories 1620(1)-1620(N). In this implementation, operations performed on the GPUs 1610(1)-1610(N) use the same virtual / effective memory address space to access processor memories 1601(1)-1601(M), and vice versa, thus simplifying programmability. In at least one embodiment, a first section of a virtual / effective address space is allocated to processor memory 1601(1), a second section is allocated to the second processor memory 1601(N), a third section is allocated to GPU memory 1620(1), and so on.In at least one embodiment, an entire virtual / effective memory space (occasionally referred to as an effective address space) is distributed across each of the processor memory 1601 and the GPU memory 1620, allowing each processor or GPU to access any physical memory whose virtual address is mapped to that memory. In at least one embodiment, the biasing / coherence management circuit 1694A-1694E within one or more MMUs 1639A-1639E ensures cache coherence between caches of one or more host processors (e.g., 1605) and GPUs 1610 and implements biasing techniques that specify physical memory locations where certain types of data should be stored. In at least one embodiment, while multiple instances of the biasing / coherence management circuit 1694A-1694E are illustrated in Fig. 16F, a biasing / coherence circuit can be implemented within an MMU of one or more host processors 1605 and / or within an accelerator integration circuit 1636. One embodiment allows GPU memory 1620 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology, but without suffering the performance drawbacks associated with full system cache coherence. In at least one embodiment, the ability to access GPU memory 1620 as system memory without the burdensome cache coherence overhead provides an advantageous operating environment for GPU offloading. In at least one embodiment, this arrangement allows host processor 1605 software to set up operands and access computation results without the overhead of traditional I / O DMA data copying.In at least one embodiment, such traditional copies include driver calls, interrupts, and memory-mapped I / O accesses (MMIO accesses), all of which are inefficient compared to simple memory accesses. In at least one embodiment, the ability to access the GPU 1620 memory without cache coherence overhead for the execution time of an offloaded computation may be critical. For example, in at least one embodiment, in cases with significant streaming write memory traffic, cache coherence overhead may significantly reduce the effective write bandwidth perceived by a GPU 1610. In at least one embodiment, operand facility efficiency, result access efficiency, and GPU computation efficiency may play a role in determining the effectiveness of GPU offloading. In at least one embodiment, the selection of a GPU bias and a host processor bias is controlled by a bias tracker data structure. In at least one embodiment, for example, a bias table can be used, which may be a page-fine granular structure (e.g., controlled by a memory page granularity) comprising 1 or 2 bits per memory page connected to a GPU. In at least one embodiment, a bias table can be implemented in a stolen memory area of ​​one or more GPU memories 1620, with or without a bias cache in a GPU 1610 (e.g., for caching frequently / recently used entries of a bias table). Alternatively, in at least one embodiment, an entire bias table can be maintained within a GPU. In at least one embodiment, a biasing table entry, which is associated with each access to a GPU-connected memory 1620, is accessed before an actual access to a GPU memory, thereby causing subsequent operations. In at least one embodiment, local requests from a GPU 1610 that find their page in a GPU biasing are forwarded directly to a corresponding GPU memory 1620. In at least one embodiment, local requests from a GPU that find their page in a host biasing are forwarded to the processor 1605 (e.g., via a high-speed transmission link described herein). In at least one embodiment, requests from the processor 1605 that find a requested page in a host processor biasing complete a request like a normal memory read.Alternatively, requests directed to a GPU 1610 can be forwarded to a GPU-preset page. In at least one embodiment, a GPU can transition a page to host-processor biasing if it is not currently using that page. In at least one embodiment, a biasing state of a page can be changed either by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of cases, a purely hardware-based mechanism. In at least one embodiment, a mechanism for changing a biasing state applies an API call (e.g., OpenCL) which in turn calls a GPU device driver, which in turn sends a message to a GPU (or queues a command descriptor) instructing it to change a biasing state and, for some transitions, to perform a cache flushing operation on a host. In at least one embodiment, a cache flushing operation is used for a transition from host processor 1605 biasing to GPU biasing, but is not used for a reverse transition. In at least one embodiment, cache coherence is maintained by temporarily preventing the host processor 1605 from caching pages pre-loaded on the GPU. In at least one embodiment, the processor 1605 can request access to these pages from the GPU 1610, which may grant this request immediately or with some delay. Therefore, in at least one embodiment, to reduce communication between the processor 1605 and the GPU 1610, it is advantageous to ensure that pages pre-loaded on the GPU are those required by a GPU but not by the host processor 1605, and vice versa. The hardware structure(s) 815 are used to implement one or more embodiments. Details regarding a hardware structure 815 may be provided herein in conjunction with Figures 8A and / or 8B. Fig. 17 illustrates exemplary integrated circuits and associated graphics processors that can be manufactured using one or more IP cores according to various embodiments described herein. In addition to what is illustrated, at least one embodiment may include further logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores. Fig. 17 is a block diagram illustrating an exemplary integrated system-on-a-chip circuit 1700, which can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1700 comprises one or more application processor(s) 1705 (e.g., CPUs), at least one graphics processor 1710, and may additionally include an image processor 1715 and / or a video processor 1720, each of which may be a modular IP core. In at least one embodiment, the integrated circuit 1700 comprises peripheral or bus logic, including a USB controller 1725, a UART controller 1730, an SPI / SDIO controller 1735, and an I22S / I22C controller 1740.In at least one embodiment, the integrated circuit 1700 can include a display device 1745 coupled to one or more high-definition multimedia interface (HDMI) controllers 1750 and mobile industry processor interface (MIPI) display interfaces 1755. In at least one embodiment, mass storage can be provided by a flash memory subsystem 1760 comprising flash memory and a flash memory controller. In at least one embodiment, a memory interface can be provided via a memory controller 1765 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits additionally include an embedded security engine 1770. Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding Logic 815 are provided herein in conjunction with Figures 8A and / or 8B. In at least one embodiment, Logic 815 can be used in the integrated circuit 1700 for inference or prediction operations based, at least partially, on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein. In at least one embodiment, Figs. 1-17 show the performance, using one or more neural networks, of one or more perception tasks for higher-dimensional (e.g., 3D, 4D) images based on an extension of the higher-dimensional images and / or an extension of lower-dimensional images (e.g., 2D, 3D). Figures 18A-18B illustrate exemplary integrated circuits and associated graphics processors that can be fabricated using one or more IP cores according to various embodiments described herein. In addition to what is illustrated, at least one embodiment may include further logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores. Figures 18A-18B are block diagrams illustrating exemplary graphics processing units (GPUs) for use within a system-on-a-chip (SoC) according to various embodiments described herein. Figure 18A illustrates an exemplary GPU 1810 of an integrated system-on-a-chip (SoC) circuit, which can be fabricated using one or more IP cores according to at least one embodiment. Figure 18B illustrates an additional exemplary GPU 1840 of an integrated system-on-a-chip (SoC) circuit, which can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, the GPU 1810 of Figure 18A is a low-power GPU core. In at least one embodiment, the GPU 1840 of Figure 18B is a high-power GPU core.In at least one embodiment, the graphics processors 1810, 1840 can be variants of the graphics processor 1710 from Fig. 17. In at least one embodiment, the graphics processor 1810 comprises a vertex processor 1805 and one or more fragment processors 1815A-1815N (e.g., 1815A, 1815B, 1815C, 1815D to 1815N-1 and 1815N). In at least one embodiment, the graphics processor 1810 can execute different shader programs via separate logic, such that the vertex processor 1805 is optimized for executing operations for vertex shader programs, while one or more fragment processors 1815A-1815N execute fragment shading operations (e.g., pixel shading operations) for fragment or pixel shader programs. In at least one embodiment, the Vertex Processor 1805 performs a vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data.In at least one embodiment, fragment processor(s) 1815A-1815N use the primitive and vertex data generated by vertex processor 1805 to create a framebuffer that is displayed on a display device. In at least one embodiment, fragment processor(s) 1815A-1815N are optimized to execute fragment shader programs as provided in an OpenGL API, which can be used to perform operations similar to a pixel shader program as provided in a Direct3D API. In at least one embodiment, the graphics processor 1810 additionally comprises one or more memory management units (MMUs) 1820A-1820B, cache(s) 1825A-1825B, and circuit interconnect(s) 1830A-1830B. In at least one embodiment, one or more MMUs (1820A-1820B) provide the mapping of virtual to physical addresses for the graphics processor (1810), including for the vertex processor (1805) and / or fragment processor(s) 1815A-1815N, which, in addition to the vertex or image / texture data stored in one or more caches 1825A-1825B, can refer to vertex or image / texture data stored in memory. In at least one embodiment, one or more MMU(s) 1820A-1820B can be synchronized with other MMUs within a system, including one or more MMUs connected to one or more application processor(s) 1705, image processors 1715 and / or video processors 1720 of Fig.17 are assigned, so that each processor 1705-1720 can participate in a common or unified virtual memory system. In at least one embodiment, one or more circuit interconnect(s) 1830A-1830B enable the graphics processor 1810 to connect to other IP cores within the SoC, either via an internal bus of the SoC or via a direct connection. In at least one embodiment, the 1840 graphics processor comprises one or more shader cores 1855A-1855N (e.g., 1855A, 1855B, 1855C, 1855D, 1855E, 1855F to 1855N-1 and 1855N), as shown in Fig. 18B, which provide a unified shader core architecture in which a single core or core type can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary.In at least one embodiment, the graphics processor 1840 comprises a cross-core task manager 1845, which acts as a thread distributor to distribute execution threads to one or more shader cores 1855A-1855N, and a tiling unit 1858 to accelerate tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in the image space, for example to take advantage of local spatial coherence within a scene or to optimize the use of internal caches. Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding Logic 815 are provided herein in conjunction with Figures 8A and / or 8B. In at least one embodiment, Logic 815 can be used in the graphics processor 1810 and / or 1840 for inference or prediction operations based, at least partially, on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein. In at least one embodiment, Figs. 1-18 show the performance, using one or more neural networks, of one or more perception tasks for higher-dimensional (e.g., 3D, 4D) images based on an extension of the higher-dimensional images and / or an extension of lower-dimensional images (e.g., 2D, 3D). Figures 19A-19B illustrate additional exemplary graphics processing logic according to various embodiments described herein. In at least one embodiment, components illustrated and described in connection with Figures 19A-19B are integrated into a single system, such as a graphics processing unit (GPU), a system-on-a-chip (SoC), or another type of processor. Figure 19A illustrates a graphics core 1900, which in at least one embodiment may be contained within the graphics processor 1710 of Figure 17 and in at least one embodiment may be a unified shader core 1855A-1855N as shown in Figure 18B. Figure 19B illustrates a highly parallel general-purpose graphics processing unit (“GPGPU,” which may also be referred to as a “graphics processing unit”) 1930, which in at least one embodiment is suitable for deployment on a multi-chip module.In at least one embodiment, the graphics processing unit 1930 is a GPGPU comprising a graphics processor. In at least one embodiment, the integrated circuit 1700 comprises the graphics core 1900, e.g., to form an integrated circuit and / or a SoC, wherein such an integrated circuit and / or such a SoC performs the operations described herein. In at least one embodiment, the graphics core 1900 comprises a shared instruction cache 1902, a texture unit 1918, and a cache / shared memory 1920 (e.g., including L1, L2, L3, last-level cache, or other caches) that are common execution resources within the graphics core 1900. In at least one embodiment, the graphics core 1900 can comprise multiple slices 1901A-1901N or partitions for each core, and a graphics processor can comprise multiple instances of the graphics core 1900. In at least one embodiment, each slice 1901A-1901N refers to the graphics core 1900. In at least one embodiment, the slices 1901A-1901N have sub-slices that are part of a slice 1901A-1901N. In at least one embodiment, the slices 1901A-1901N are independent of other slices or dependent on other slices.In at least one embodiment, the slices 1901A-1901N can include support logic including a local instruction cache 1904A-1904N, a thread scheduler (sequencer) 1906A-1906N, a thread dispatcher 1908A-1908N and a set of registers 1910A-1910N. In at least one embodiment, the slices 1901A-1901N can comprise a set of additional functional units (AFUs 1912A-1912N), floating-point units (FPUs 1914A-1914N), integer arithmetic logic units (ALUs 1916-1916N), address calculation units (ACUs 1913A-1913N), double-precision floating-point units (DPFPUs 1915A-1915N), and matrix processing units (MPUs 1917A-1917N). In at least one embodiment, the MPUs 1917A-1917N are referred to as matrix engines. In at least one embodiment, each slice 1901A-1901N comprises one or more engines for floating-point and integer vector operations and one or more engines for accelerating convolution and matrix operations in AI, machine learning, or large dataset workloads. In at least one embodiment, one or more slices 1901A-1901N comprise one or more vector engines for computing a vector (e.g., for computing mathematical operations on vectors). In at least one embodiment, a vector engine can compute a vector operation in 16-bit floating-point (also referred to as "FP16"), 32-bit floating-point (also referred to as "FP32"), or 64-bit floating-point (also referred to as "FP64").In at least one embodiment, one or more slices 1901A-1901N comprise 16 vector engines paired with 16 matrix math units to compute matrix / tensor operations, the vector engines and math units being accessible via matrix extensions. In at least one embodiment, a slice is a specified section of processing resources of a processing unit, e.g., 16 cores and a ray tracing unit, or 8 cores, a thread scheduler, a thread dispatcher, and additional functional units for a processor. In at least one embodiment, the graphics core 1900 comprises one or more matrix engines for computing matrix operations, e.g., when computing tensor operations. In at least one embodiment, one or more slices 1901A-1901N comprise one or more ray tracing units for computing ray tracing operations (e.g., 16 ray tracing units per slice of slices 1901A-1901N). In at least one embodiment, a ray tracing unit computes a ray traverse, a triangle intersection, a boundary box intersection, or other ray tracing operations. In at least one embodiment, one or more slices 1901A-1901N comprise a media slice that encodes, decodes and / or transcodes data; scales and / or formats data; and / or performs video quality operations on video data. In at least one embodiment, one or more slices 1901A-1901N are linked to an L2 cache and a memory fabric, interconnects, high-bandwidth memory (HBM) stacks (e.g., HBM2e, HDM3), and a media engine. In at least one embodiment, one or more slices 1901A-1901N comprise multiple cores (e.g., 16 cores) and multiple ray tracing units (e.g., 16) paired with each core. In at least one embodiment, one or more slices 1901A-1901N have one or more L1 caches. In at least one embodiment, one or more slices 1901A-1901N comprise one or more vector engines; one or more instruction caches for storing instructions; one or more L1 caches for temporary data storage. one or more shared local storage devices (SLMs) for storing data, e.g.according to commands; one or more samplers for sampling data; one or more ray tracing units for performing ray tracing operations; one or more geometry units for performing operations in geometry pipelines and / or for applying geometric transformations to vertices or polygons; one or more rasterizers for describing an image in a vector graphics format (e.g., shape) and for converting it into a raster image (e.g., a series of pixels, points, or lines that, when displayed together, produce an image represented by shapes); one or more hierarchical depth buffers (Hiz) for buffering data; and / or one or more pixel backends. In at least one embodiment, a slice 1901A-1901N includes a memory fabric, e.g., an L2 cache. In at least one embodiment, FPUs 1914A-1914N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while DPFPUs 1915A-1915N perform double-precision (64-bit) floating-point operations. In at least one embodiment, ALUs 1916A-1916N can perform variable-precision integer operations with a precision of 8-bit, 16-bit, and 32-bit and can be configured for mixed-precision operations. In at least one embodiment, MPUs 1917A-1917N can also be configured for mixed-precision matrix operations, including half-precision floating-point and 8-bit integer operations. In at least one embodiment, MPUs 1917-1917N can perform a variety of matrix operations to accelerate machine learning application frameworks, including support for accelerated general matrix-matrix multiplication (GEMM).In at least one embodiment, AFUs 1912A-1912N can perform additional logic operations not supported by floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.). Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding Logic 815 are provided herein in conjunction with Figures 8A and / or 8B. In at least one embodiment, Logic 815 can be used in the graphics kernel 1900 for inference or prediction operations based, at least partially, on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein. In at least one embodiment, the graphics core 1900 comprises an interconnect and a connection fabric sublayer attached to a switch and a GPU-to-GPU bridge, thereby enabling multiple graphics processors 1900 (e.g., 8) to be interconnected across multiple graphics processors 1900 using load / store units (LSUs), data transfer units, and synchronization semantics without glue logic. In at least one embodiment, interconnects comprise standardized interconnects (e.g., PCIe) or a combination thereof. In at least one embodiment, the 1900 graphics core comprises multiple tiles. In at least one embodiment, a tile is a single die or one or more dies, wherein individual dies may be interconnected (e.g., an embedded multi-die interconnect bridge (EMIB)). In at least one embodiment, the 1900 graphics core comprises a compute tile, a memory tile (e.g., wherein a memory tile can be accessed exclusively by different tiles or different chipsets, such as a Rambo tile), a substrate tile, a base tile, an HBM tile, a link tile, and an EMIB tile, wherein all tiles in the 1900 graphics core are housed together in a single package as part of a GPU. In at least one embodiment, the 1900 graphics core may comprise multiple tiles in a single package (also referred to as a "multi-tile package").In at least one embodiment, a compute tile can comprise eight 1900 graphics cores and an L1 cache; and a base tile can comprise a host interface with PCIe 5.0, HBM2e, MDFI, and EMIB, a link tile with eight transmission paths, and eight ports with an embedded switch. In at least one embodiment, tiles are connected via face-to-face (F2F) chip-on-chip bonds by finely graduated 36-micrometer microbumps (e.g., copper pillars). In at least one embodiment, the 1900 graphics core comprises a memory fabric containing memory and is a tile accessible by multiple tiles. In at least one embodiment, the 1900 graphics core stores, accesses, or loads its own hardware contexts in memory, wherein a hardware context is a set of data that is loaded from registers before a process continues, and wherein a hardware context represents a state of hardware (e.g.,can specify the state of a GPU. In at least one embodiment, the graphics kernel 1900 comprises a serializer / deserializer circuit arrangement (SERDES circuit arrangement) that converts a serial data stream into a parallel data stream or converts a parallel data stream into a serial data stream. In at least one embodiment, the graphics core 1900 comprises a coherent, unified high-speed fabric (GPU to GPU), load / store units, mass data transfer and synchronization semantics, and GPUs connected via an embedded switch, wherein a GPU-GPU bridge is controlled by a controller. In at least one embodiment, the graphics kernel 1900 executes an API, wherein the API abstracts hardware of the graphics kernel 1900 and access libraries containing instructions for performing mathematical operations (e.g., a math kernel library), deep neural network operations (e.g., a deep neural network library), vector operations, collective communications, thread building blocks, video processing, a data analysis library, and / or ray tracing operations. In at least one embodiment, Fig. 1-19A shows the performance, using one or more neural networks, of one or more perception tasks for higher-dimensional (e.g., 3D, 4D) images based on an extension of the higher-dimensional images and / or an extension of lower-dimensional images (e.g., 2D, 3D). Figure 19B illustrates a GPGPU 1930, which in at least one embodiment can be configured to allow highly parallel computing operations to be performed by an array of graphics processing units. In at least one embodiment, the GPGPU 1930 can be directly linked with further instances of the GPGPU 1930 to create a multi-GPU cluster to improve the training speed for deep neural networks. In at least one embodiment, the GPGPU 1930 includes a host interface 1932 to enable communication with a host processor. In at least one embodiment, the host interface 1932 is a PCI Express interface. In at least one embodiment, the host interface 1932 can be a vendor-specific communication interface or communication fabric.In at least one embodiment, the GPGPU 1930 receives instructions from a host processor and applies a global scheduler 1934 (which can be described as a thread sequencer and / or an asynchronous computing engine) to distribute execution threads associated with these instructions to a set of computing clusters 1936A-1936H. In at least one embodiment, the computing clusters 1936A-1936H share a cache memory 1938. In at least one embodiment, the cache memory 1938 can serve as a higher-level cache for cache memory within the computing clusters 1936A-1936H. In at least one embodiment, the computing clusters 1936A-1936H comprise a slice or are referred to as "slices". In at least one embodiment, the GPGPU 1930 is part of a SoC, such as part of the integrated circuit 1700 (Fig. 17). In at least one embodiment, GPGPU 1930 comprises memory 1944A-1944B coupled to compute clusters 1936A-1936H via a set of memory controllers 1942A-1942B (e.g., one or more controllers for HBM2e). In at least one embodiment, memory 1944A-1944B can comprise various types of memory devices, including dynamic random-access memory (DRAM) or graphics random-access memory, such as synchronous graphics random-access memory (SGRAM), including double-data-rate graphics memory (GDDR). In at least one embodiment, computing clusters 1936A-1936H each comprise a set of graphics cores, such as the graphics core 1900 from Fig. 19A, which may include several types of integer and floating-point logic units capable of performing arithmetic operations with a range of precisions, including those suitable for machine learning calculations. For example, in at least one embodiment, at least one subset of floating-point units in each of the computing clusters 1936A-1936H may be configured to perform 16-bit or 32-bit floating-point operations, while another subset of floating-point units may be configured to perform 64-bit floating-point operations. In at least one embodiment, multiple instances of GPGPU 1930 can be configured to operate as a computing cluster. In at least one embodiment, the communication used by the computing clusters 1936A-1936H for synchronization and data exchange varies across embodiments. In at least one embodiment, multiple instances of GPGPU 1930 communicate via host interface 1932. In at least one embodiment, GPGPU 1930 includes an I / O hub 1939 that couples GPGPU 1930 to a GPU link 1940, enabling a direct connection to other instances of GPGPU 1930. In at least one embodiment, the GPU link 1940 is coupled to a dedicated GPU-to-GPU bridge, enabling communication and synchronization between multiple instances of GPGPU 1930.In at least one embodiment, the GPU transmission link 1940 is coupled to a high-speed interconnect to send and receive data to and from other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1930 are located in separate data processing systems and communicate via a network device accessible through the host interface 1932. In at least one embodiment, the GPU connection 1940 can be configured to provide a connection to a host processor in addition to, or as an alternative to, the host interface 1932. In at least one embodiment, the GPGPU 1930 can be configured to train neural networks. In at least one embodiment, the GPGPU 1930 can be used within an inference platform. In at least one embodiment where the GPGPU 1930 is used for inference, the GPGPU 1930 can comprise fewer compute clusters 1936A-1936H compared to when the GPGPU 1930 is used to train a neural network. In at least one embodiment, the memory technology assigned to the memory 1944A-1944B can differ between inference and training configurations, with higher-bandwidth memory technologies being reserved for training configurations. In at least one embodiment, an inference configuration of the GPGPU 1930 can support specific inference instructions.For example, in at least one embodiment, an inference configuration can provide support for one or more 8-bit integer scalar product instructions that can be used during inference operations for deployed neural networks. Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding Logic 815 are provided herein in conjunction with Figures 8A and / or 8B. In at least one embodiment, Logic 815 can be used in the GPGPU 1930 for inference or prediction operations based, at least partially, on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein. In at least one embodiment, Fig. 1-19B shows the performance, using one or more neural networks, of one or more perception tasks for higher-dimensional (e.g., 3D, 4D) images based on an extension of the higher-dimensional images and / or an extension of lower-dimensional images (e.g., 2D, 3D). Figure 20 is a block diagram illustrating a computer system 2000 according to at least one embodiment. In at least one embodiment, the computer system 2000 comprises a processing subsystem 2001, which has one or more processors 2002 and a system memory 2004, which communicate via a link path that may include a memory hub 2005. In at least one embodiment, the memory hub 2005 may be a separate component within a chipset component or be integrated into one or more processors 2002. In at least one embodiment, the memory hub 2005 is coupled to an I / O subsystem 2011 via a communication link 2006. In at least one embodiment, the I / O subsystem 2011 comprises an I / O hub 2007, which enables the computer system 2000 to receive inputs from one or more input devices 2008.In at least one embodiment, the I / O hub 2007 can enable a display controller, which may be included in one or more processors 2002, to provide outputs to one or more display devices 2010A. In at least one embodiment, one or more display devices 2010A coupled to the I / O hub 2007 can comprise a local, internal, or embedded display device. In at least one embodiment, the processing subsystem 2001 comprises one or more parallel processors 2012 coupled to the memory hub 2005 via a bus or other communication link 2013. In at least one embodiment, the communication link 2013 can use any number of standards-based communication link technologies or protocols, such as, but not limited to, PCI Express, or it can be a vendor-specific communication interface or communication fabric. In at least one embodiment, one or more parallel processors 2012 form a computationally aligned parallel or vector processing system that can include a large number of processing cores and / or processing clusters, for example, a many-integrated-core (MIC) processor.In at least one embodiment, some or all of the parallel processors 2012 form a graphics processing subsystem that can output pixels to one or more display devices 2010A coupled via an I / O hub 2007. In at least one embodiment, the parallel processor(s) 2012 may also include a display controller and a display interface (not shown) to enable a direct connection to one or more display devices 2010B. In at least one embodiment, the parallel processor(s) 2012 comprise one or more cores, such as the graphics cores 1900 discussed herein. In at least one embodiment, a system storage unit 2014 can be connected to the I / O hub 2007 to provide a mass storage mechanism for the computing system 2000. In at least one embodiment, an I / O switch 2016 can be used to provide an interface mechanism that enables connections between the I / O hub 2007 and other components, such as a network adapter 2018 and / or a wireless network adapter 2019, which may be integrated into a platform, as well as various other devices that may be added via one or more add-on devices 2020. In at least one embodiment, the network adapter 2018 can be an Ethernet adapter or another wired network adapter.In at least one embodiment, the wireless network adapter 2019 may include one or more Wi-Fi, Bluetooth, Near Field Communication (NFC) or other network devices that incorporate one or more wireless radio devices. In at least one embodiment, the computing system 2000 may include other components not explicitly shown, including USB or other connectors, optical data storage drives, video capture devices, and the like, which may also be connected to the I / O hub 2007. In at least one embodiment, communication paths connecting various components in Fig. 20 may be implemented using any suitable protocols, for example, PCI (Peripheral Component Interconnect)-based protocols (e.g., PCI Express) or other bus or point-to-point communication interfaces and / or protocols, such as NVLink high-speed interconnects or interconnect protocols. In at least one embodiment, the parallel processor(s) 2012 integrate a circuit arrangement optimized for graphics and video processing, including, for example, a video output circuit arrangement, and constitute a graphics processing unit (GPU); for example, the parallel processor(s) 2012 include the graphics core 1900. In at least one embodiment, one or more parallel processors 2012 integrate a circuit arrangement optimized for general-purpose processing. In at least one embodiment, components of a computing system 2000 can be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 2012, the memory hub 2005, processor(s) 2002, and an I / O hub 2007 can be integrated into a system-on-a-chip (SoC) integrated circuit.In at least one embodiment, components of the Computing System 2000 can be integrated into a single enclosure to form a system-in-package (SIP) configuration. In at least one embodiment, at least some components of the Computing System 2000 can be integrated into a multi-chip module (MCM) that can be connected to other multi-chip modules to form a modular computing system. Logic 815 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding Logic 815 are provided herein in conjunction with Figures 8A and / or 8B. In at least one embodiment, Logic 815 can be used in the Computing System 2000 for inference or prediction operations based, at least partially, on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein. In at least one embodiment, Figs. 1-20 show the performance, using one or more neural networks, of one or more perception tasks for higher-dimensional (e.g., 3D, 4D) images based on an extension of the higher-dimensional images and / or an extension of lower-dimensional images (e.g., 2D, 3D). PROCESSORS Fig. 21A illustrates a parallel processor 2100 according to at least one embodiment. In at least one embodiment, various components of the parallel processor 2100 can be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits (“ASICs”), or field-programmable gate arrays (FPGAs). In at least one embodiment, the illustrated parallel processor 2100 is a variant of one or more parallel processor(s) 212 shown in Fig. 20 according to an exemplary embodiment. In at least one embodiment, a parallel processor 2100 comprises one or more graphics cores 1900. In at least one embodiment, the parallel processor 2100 comprises a parallel processing unit 2102. In at least one embodiment, the parallel processing unit 2102 comprises an I / O unit 2104, which enables communication with other devices, including other instances of the parallel processing unit 2102. In at least one embodiment, the I / O unit 2104 can be directly connected to other devices. In at least one embodiment, the I / O unit 2104 is connected to other devices via a hub or switch interface, for example, a memory hub 2105. In at least one embodiment, connections between the memory hub 2105 and the I / O unit 2104 form a communication link 2113.In at least one embodiment, the I / O unit 2104 is connected to a host interface 2106 and a memory matrix 2116, wherein the host interface 2106 receives commands for performing processing operations and the memory matrix 2116 receives commands for performing storage operations. In at least one embodiment, when host interface 2106 receives a command buffer via I / O unit 2104, host interface 2106 can forward work operations to a frontend 2108 for the execution of these commands. In at least one embodiment, frontend 2108 is coupled to a scheduler 2110 (which can also be called a sequencer) configured to distribute commands or other work items to a processing cluster array 2112. In at least one embodiment, the scheduler 2110 ensures that the processing cluster array 2112 is properly configured and in a valid state before tasks are distributed to a cluster of the processing cluster array 2112. In at least one embodiment, the scheduler 2110 is implemented via firmware logic running on a microcontroller.In at least one embodiment, the microcontroller-implemented scheduler 2110 can be configured to perform complex scheduling and workload distribution operations with coarse and fine granularity, enabling fast preemption and context switching of threads running on processing array 2112. In at least one embodiment, host software can propose workloads for scheduling on the processing cluster array 2112 via one of several graphics processing paths. In at least one embodiment, workloads can then be automatically distributed across processing array cluster 2112 by the logic of the scheduler 2110 within a microcontroller, including the scheduler 2110. In at least one embodiment, the processing cluster array 2112 can comprise up to "N" processing clusters (e.g., cluster 2114A, cluster 2114B to cluster 2114N), where "N" is a positive integer (which may be a different integer "N" than used in other figures). In at least one embodiment, each cluster 2114A-2114N of the processing cluster array 2112 can execute a large number of concurrent threads. In at least one embodiment, scheduler 2110 can allocate work to clusters 2114A-2114N of the processing cluster array 2112 using various scheduling and / or work distribution algorithms, which can vary depending on the workload generated by each type of program or computation.In at least one embodiment, the planning can be handled dynamically by the planner 2110 or partially supported by compiler logic during the compilation of program logic configured to be executed by a processing cluster array 2112. In at least one embodiment, different clusters 2114A-2114N of the processing cluster array 2112 can be assigned to process different types of programs or to perform different types of data processing. In at least one embodiment, the processing cluster array 2112 can be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster array 2112 is configured to perform general parallel computing operations. For example, in at least one embodiment, the processing cluster array 2112 can include logic for executing processing tasks, including filtering video and / or audio data, performing modeling operations, including physical operations, and performing data transformations. In at least one embodiment, the processing cluster array 2112 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2112 may include additional logic to support the execution of such graphics processing operations, including, but not limited to, texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2112 may be configured to execute graphics processing-related shader programs, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2102 may transfer data from system memory via the I / O unit 2104 for processing.In at least one embodiment, data transmitted during processing can be stored in an on-chip memory (e.g., parallel processor memory 2122) and then written back to the system memory. In at least one embodiment, when parallel processing unit 2102 is used to perform graphics processing, the scheduler 2110 can be configured to divide a processing workload into approximately equal tasks to enable better distribution of graphics processing operations across multiple clusters 2114A-2114N of the processing cluster array 2112. In at least one embodiment, sections of the processing cluster array 2112 can be configured to perform different types of processing. For example, in at least one embodiment, a first section can be configured to perform vertex shading and topology generation, a second section can be configured to perform tessellation and geometry shading, and a third section can be configured to perform pixel shading or other screen area operations to produce a rendered image for display.In at least one embodiment, intermediate data generated by one or more clusters 2114A-2114N can be stored in buffers to allow intermediate data to be transferred between clusters 2114A-2114N for further processing. In at least one embodiment, the processing cluster array 2112 can receive processing tasks to be executed via the scheduler 2110, which receives commands from the frontend 2108 that define the processing tasks. In at least one embodiment, processing tasks can include indices of the data to be processed, e.g., surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands that define how data is to be processed (e.g., which program is to be executed). In at least one embodiment, the scheduler 2110 can be configured to retrieve indices corresponding to the tasks, or it can receive indices from the frontend 2108. In at least one embodiment, the frontend 2108 can be configured to ensure that the processing cluster array 2112 is set up in a valid state before an incoming command buffer (e.g., batch buffer, push buffer, etc.) is executed.) specified workload is initiated. In at least one embodiment, each instance of the parallel processing unit 2102 can be coupled to the parallel processor memory 2122. In at least one embodiment, the parallel processor memory 2122 can be accessed via a memory matrix 2116, which can receive memory requests from the processing cluster array 2112 and from the I / O unit 2104. In at least one embodiment, the memory matrix 2116 can access the parallel processor memory 2122 via a memory interface 2118. In at least one embodiment, the memory interface 2118 can comprise several partition units (e.g., partition unit 2120A, partition unit 2120B to partition unit 2120N), each of which can be coupled to a section (e.g., a memory unit) of the parallel processor memory 2122.In at least one embodiment, a number of partition units 2120A-2120N is configured to be equal to a number of storage units, such that a first partition unit 2120A has a corresponding first storage unit 2124A, a second partition unit 2120B has a corresponding storage unit 2124B, and an Nth partition unit 2120N has a corresponding Nth storage unit 2124N. In at least one embodiment, a number of partition units 2120A-2120N cannot be equal to a number of storage devices. In at least one embodiment, memory units 2124A-2124N can comprise various types of memory devices, including dynamic random-access memory (DRAM) or graphics random-access memory, such as synchronous graphics random-access memory (SGRAM), including double-data-rate graphics memory (GDDR). In at least one embodiment, memory units 2124A-2124N can also comprise 3D stacked memory, including, but not limited to, high-bandwidth memory (HBM), HBM2, or HDM3. In at least one embodiment, render targets, such as frame buffers or texture maps, can be stored in the memory units 2124A-2124N, so that the partition units 2120A-2120N can write sections of each render target in parallel to efficiently utilize the available bandwidth of the parallel processor memory 2122.In at least one embodiment, a local instance of the parallel processor memory 2122 can be excluded in favor of a unified memory design that uses the system memory in conjunction with the local cache memory. In at least one embodiment, each of the clusters 2114A-2114N of processing cluster array 2112 can process data written to one of the storage units 2124A-2124N within the parallel processor memory 2122. In at least one embodiment, the memory matrix 2116 can be configured to transfer an output from each cluster 2114A-2114N to any partition unit 2120A-2120N or to another cluster 2114A-2114N, which can perform additional processing operations on the output. In at least one embodiment, each cluster 2114A-2114N with memory interface 2118 can communicate via the memory matrix 2116 to read from or write to various external storage devices.In at least one embodiment, the memory matrix 2116 has a connection to memory interface 2118 for communication with I / O unit 2104, and a connection to a local instance of the parallel processor memory 2122, which allows the processing units within the various processing clusters 2114A-2114N to communicate with system memory or other memory that is not local to parallel processing unit 2102. In at least one embodiment, the memory matrix 2116 can use virtual channels to separate data traffic flows between the clusters 2114A-2114N and the partition units 2120A-2120N. In at least one embodiment, multiple instances of the Parallel Processing Unit 2102 can be provided on a single add-in card, or multiple add-in cards can be interconnected. In at least one embodiment, different instances of the Parallel Processing Unit 2102 can be configured to work together, even if the different instances have a different number of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of the Parallel Processing Unit 2102 can include higher-precision floating-point units compared to other instances.In at least one embodiment, systems incorporating one or more instances of the Parallel Processing Unit 2102 or the Parallel Processor 2100 can be implemented in a variety of configurations and form factors, including, but not limited to, desktop, laptop or handheld PCs, servers, workstations, game consoles and / or embedded systems. Fig. 21B is a block diagram of a partition unit 2120 according to at least one embodiment. In at least one embodiment, the partition unit 2120 is an instance of one of the partition units 2120A-2120N of Fig. 21A. In at least one embodiment, the partition unit 2120 comprises an L2 cache 2121, a framebuffer interface 2125, and a ROP 2126 (raster operation unit). In at least one embodiment, the L2 cache 2121 is a read / write cache configured to execute load and write operations received from the memory matrix 2116 and the ROP 2126. In at least one embodiment, read errors and urgent write-back requests are output by the L2 cache 2121 to the framebuffer interface 2125 for processing. In at least one embodiment, updates can also be sent to a framebuffer for processing via the framebuffer interface 2125.In at least one embodiment, framebuffer interface 2125 forms an interface with one of the storage units in parallel processor memory, such as storage units 2124A-2124N of Fig. 21A (e.g. within parallel processor memory 2122). In at least one embodiment, the ROP 2126 is a processing unit that performs raster operations such as stenciling, Z-testing, blending, etc. In at least one embodiment, the ROP 2126 then outputs processed graphics data, which is stored in graphics memory. In at least one embodiment, the ROP 2126 includes compression logic to compress depth or color data written to memory and to decompress depth or color data read from memory. In at least one embodiment, the compression logic can be lossless compression logic that uses one or more of several compression algorithms. In at least one embodiment, the type of compression performed by the ROP 2126 can vary based on statistical properties of the data to be compressed.For example, in at least one embodiment, delta color compression is performed for depth and color data on a per-tile basis. In at least one embodiment, ROP 2126 is contained within each processing cluster (e.g., clusters 2114A-2114N of Fig. 21A) instead of within the partition unit 2120. In at least one embodiment, read and write requests for pixel data are transmitted via the memory matrix 2116 instead of pixel fragment data. In at least one embodiment, processed graphics data can be displayed on a display device, such as one or more display devices 2010 of Fig. 20, forwarded for further processing by the processor(s) 2002, or forwarded for further processing by one of the processing units within the parallel processor 2100 of Fig. 21A. Figure 21C is a block diagram of a processing cluster 2114 within a parallel processing unit according to at least one embodiment. In at least one embodiment, a processing cluster is an instance of one of the processing clusters 2114A-2114N of Figure 21A. In at least one embodiment, processing cluster 2114 can be configured to execute many threads in parallel, where "thread" refers to an instance of a particular program that is executed on a particular set of input data. In at least one embodiment, single-instruction-multi-data (SIMD) instruction output techniques are used to support the parallel execution of a large number of threads without providing multiple independent instruction units.In at least one embodiment, single-instruction multi-thread (SIMT) techniques are used to support the parallel execution of a large ...

Claims

A processor comprising: one or more circuits for using one or more neural networks to identify one or more objects within one or more images based, at least partially, on one or more features of the one or more images and one or more features of one or more modified versions of the one or more images. The processor according to claim 1, wherein the one or more circuits are further configured to generate one or more additional images based, at least partially, on one or more features of the one or more images and one or more features of one or more modified versions of the one or more images. The processor according to claim 1, wherein the one or more circuits are further configured to generate one or more features of one or more modified versions of the one or more images using one or more convolutional layers of the one or more neural networks. The processor according to claim 1, wherein the one or more circuits are further configured to generate the modified versions of the one or more images using at least one of random displacement, affine transformation or pixel removal. The processor according to claim 1, wherein one or more features of the one or more images are generated based, at least partially, on an inversion of one or more modified versions of the one or more images. The processor according to claim 1, wherein the one or more images represent a scene. The processor according to claim 1, wherein the one or more circuits are further configured to send information about the one or more identified objects to one or more autonomous vehicles. The processor according to claim 1, wherein at least one of the one or more images is a three-dimensional (3D) image. A method comprising: identifying, using one or more neural networks, one or more objects within one or more images based, at least partially, on one or more features of the one or more images and one or more features of one or more modified versions of the one or more images. The method according to claim 9, further comprising: generating one or more additional images based, at least partially, on one or more features of one or more modified versions of the one or more images. The method according to claim 9, further comprising generating one or more features of the one or more images using one or more convolutional layers of the one or more neural networks. The method according to claim 9, wherein the one or more modified versions of the one or more images are generated by using at least one of random displacement, color modification or affine transformation. The method according to claim 9, wherein the one or more neural networks are provided in one or more autonomous vehicles. The method according to claim 9, wherein at least one of the one or more images is a bird's-eye view image. A system comprising: one or more processors for using one or more neural networks to identify one or more objects within one or more images based, at least partially, on one or more features of the one or more images and one or more features of one or more modified versions of the one or more images. The system according to claim 15, wherein the one or more processors are further configured to generate one or more additional images based, at least partially, on one or more features of the one or more images and one or more features of one or more modified versions of the one or more images. The system according to claim 15, wherein the one or more processors are further configured to generate one or more features of one or more modified versions of the one or more images using one or more attention modules of the one or more neural networks. The system according to claim 15, wherein one or more first cell positions of one or more features of the one or more images correspond to one or more second cell positions of one or more features of one or more modified versions of the one or more images. The system according to claim 15, wherein the one or more processors are further configured to generate the modified versions of the one or more images using at least one of random displacement, affine transformation or pixel removal. The system according to claim 15, wherein at least one of the one or more images is a three-dimensional (3D) image.

Images