SEMICONDUCTOR DEVICE

Abstract

A semiconductor device is provided with a floating region of a second conductivity type located below the lower end of a first gate trench section and not extending to a region below the lower end of a first blind trench section on an upper surface side of a semiconductor substrate, wherein a first mesa section has an emitter region of a first conductivity type located in contact with the first gate trench section and having a higher concentration than that of a drift region, and a base region of the second conductivity type located between the emitter region and the drift region and contacting the first gate trench section, and the lower end of the first blind trench section contacting a region of the first conductivity type.

Description

BACKGROUND 1. TECHNICAL AREA

[0001] The present invention relates to a semiconductor device. 2. STATE OF THE ART

[0002] In the prior art, a semiconductor device is known which has a transistor such as an insulated gate bipolar transistor (IGBT) (see, for example, patent documents 1 to 4). State-of-the-art documents, patent documents Patent document 1: Japanese patent no. 6472714 Patent document 2: Japanese patent no. 4456013 Patent document 3: Japanese patent application publication no. 2020-21941 Patent document 4: Japanese patent application publication no. 2010-232627 GENERAL DISCLOSURE (Technical Task)

[0003] In a semiconductor device, it is preferable to suppress a snapback phenomenon. (Solution to the problem)

[0004] To solve the problems described above, one aspect of the present invention provides a semiconductor device comprising an IGBT. The semiconductor device can have a semiconductor substrate having an upper surface and a lower surface and having a drift region of a first conductivity type;

[0005] Each of the semiconductor devices described above can have a first gate-trench section located on the upper surface of the semiconductor substrate. Each of the semiconductor devices described above can have a first blind-trench section located on the upper surface of the semiconductor substrate, adjacent to the first gate-trench section on the upper surface. Each of the semiconductor devices described above can have a first mesa section located between the first gate-trench section and the first blind-trench section within the semiconductor substrate.Each of the semiconductor devices described above can have a floating region of a second conductivity type located below a lower end of the first gate-trench section, which does not extend to a region below a lower end of the first blind-trench section on an upper surface face of the semiconductor substrate. In each of the semiconductor devices described above, the first mesa section can have an emitter region of the first conductivity type located in contact with the first gate-trench section and exhibiting a higher concentration than that of the drift region. In each of the semiconductor devices described above, the first mesa section can have a base region of the second conductivity type located between the emitter region and the drift region, and which touches the first gate-trench section.In each of the semiconductor devices described above, the lower end of the first blind trench section can touch a region of the first conductivity type.

[0006] In each of the semiconductor devices described above, the floating region cannot touch the lower end of the gate trench section.

[0007] In each of the semiconductor devices described above, the floating region can touch the lower end of the gate trench section.

[0008] In each of the semiconductor devices described above, the first mesa section can further comprise a collection region of the first conductivity type, which is located between the base region and the drift region and which has a higher concentration than that of the drift region.

[0009] In each of the semiconductor devices described above, the collecting region can touch the levitation region.

[0010] In each of the semiconductor devices described above, a lower end of the collecting region can be arranged below a lower end of the levitating region.

[0011] In each of the semiconductor devices described above, a lower end of the collecting region can be arranged above a lower end of the levitating region.

[0012] In each of the semiconductor devices described above, the first mesa section can further include a contact area of ​​the second conductivity type, which touches the upper surface of the semiconductor substrate and has a higher concentration than that of the base area.

[0013] In each of the semiconductor devices described above, the first mesa section may further comprise a contact section that extends from the upper surface of the semiconductor substrate to an inside of the first mesa section and is filled with a conductive material.

[0014] In each of the semiconductor devices described above, a lower end of the contact section can touch the contact area.

[0015] In each of the semiconductor devices described above, the first blind trench section can be located on either side of the first gate trench section.

[0016] In each of the semiconductor devices described above, the floating area can touch a side wall of the first blind trench section.

[0017] In each of the semiconductor devices described above, the first blind trench section can include a polysilicon electrode doped with an impurity of the first conductivity type.

[0018] Each of the semiconductor devices described above may further include: a lower end region of the first conductivity type, which is in contact with the lower end of the first blind trench section and which has a higher concentration than that of the drift region.

[0019] Each of the semiconductor devices described above can have two blind-trough sections arranged on the upper surface of the semiconductor substrate, positioned side by side on the upper surface. In each of the semiconductor devices described above, the distance between the first gate-trough section and the first blind-trough section can be the same as the distance between the two blind-trough sections.

[0020] Each of the semiconductor devices described above may further comprise: a plurality of diode sections, each of which is arranged alternately adjacent to the IGBT in a first direction. In each of the semiconductor devices described above, the IGBT, which is arranged to be enclosed between the diode sections, may comprise a plurality of trench sections arranged adjacent to each other in the first direction, comprising the first gate trench section and the first blind trench section. In each of the semiconductor devices described above, the spacing between the respective trench sections of the plurality of trench sections may be equal.

[0021] The summary section does not necessarily describe all necessary features of the embodiments of the present invention. The present invention may also be a subcombination of the features described above. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Fig. Figure 2 shows an enlarged view of area D in Fig. 1. Fig. 3 is a view that shows an example of a cross-section ee in Fig. 2 shows. Fig. 4 is a view that shows an example of a cross-section ff in Fig. 2 shows. Fig. Figure 5 is a diagram showing a collector voltage-collector current characteristic curve in an example and a reference example. Fig. Figure 6 is a diagram showing a collector voltage-collector current characteristic curve in an example and a reference example. Fig. Figure 7 is a diagram showing a measurement example of a voltage and current of an example semiconductor device. Fig. Figure 8 is a diagram showing another measurement example of the voltage and current of the semiconductor device of a reference example. Fig. Figure 9 is a diagram showing another measurement example of the voltage and current of the semiconductor device of an example. Fig. Figure 10 is a diagram showing a trade-off property between a turn-on loss and a reverse recovery dV / dt in a reference example and an example. Fig. Figure 11 is a view showing another example of the cross-section ff. Fig. Figure 12 is a view showing another example of the cross-section ff. Fig. Figure 13 is a view showing another example of the cross-section ff. Fig. Figure 14 is a view showing another example of the cross-section ff. Fig. Figure 15 is a view showing another example of the cross-section ff. Fig. Figure 16 is a view showing another example of the cross-section ff. Fig. Figure 17 is a view showing another example of the cross-section ee. DESCRIPTION OF EXAMPLE FORMS OF EXECUTION

[0022] The present invention is described below by means of embodiments of the invention, but these embodiments do not limit the invention according to the claims. Furthermore, not all combinations of features described in the embodiments are essential for a solution of the invention.

[0023] As used herein, one side in a direction parallel to a depth direction of a semiconductor substrate is referred to as a "top" side, and another side is referred to as a "bottom" side. A surface of two principal surfaces of a substrate, layer, or other element is referred to as an upper surface, and another surface is referred to as a lower surface. "Top" and "bottom" directions are not limited to a direction of gravity or a direction in which a semiconductor device is mounted.

[0024] In this description, technical situations can be described using orthogonal coordinate axes: an X-axis, a Y-axis, and a Z-axis. These orthogonal coordinate axes only indicate the relative positions of components and do not restrict any specific direction. For example, the Z-axis is not limited to indicating an elevation direction relative to the ground. It should be noted that a +Z-axis direction and a -Z-axis direction are opposite directions to each other. When a Z-axis direction is described without specifying the symbols, it means that the direction is parallel to both the +Z-axis and the -Z-axis.

[0025] In this description, orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are referred to as the X-axis and the Y-axis, respectively. Additionally, an axis perpendicular to the upper and lower surfaces of the semiconductor substrate is referred to as the Z-axis. In this description, the direction of the Z-axis can be described as a depth direction. Furthermore, in this description, a direction parallel to the upper and lower surfaces of the semiconductor substrate can be described as a horizontal direction, encompassing both an X-axis and a Y-axis direction.

[0026] A region extending from the center of the semiconductor substrate in the depth direction to the upper surface of the semiconductor substrate can be referred to as an upper surface face. Similarly, a region extending from the center of the semiconductor substrate in the depth direction to the lower surface of the semiconductor substrate can be referred to as a lower surface face.

[0027] In the present description, a case where a term such as "equal" or "same" is used may include a case where a defect is present due to a variation in manufacturing or the like. The defect is, for example, within 10%.

[0028] In this description, the conductivity type of a doped region containing impurities is described as P-like or N-like. In this description, the impurities can specifically be either N-like donors or P-like acceptors and can be described as dopants. In this description, doping means introducing the donor or acceptor into the semiconductor substrate and transforming it into a semiconductor exhibiting an N-like conductivity type or a semiconductor exhibiting a P-like conductivity type.

[0029] In this description, a doping concentration means a concentration of the donor or a concentration of the acceptor in a thermal equilibrium state. In this description, a net doping concentration means a net concentration obtained by adding the donor concentration, set as a positive ion concentration, to the acceptor concentration, set as a negative ion concentration, taking charge polarities into account. For example, if the donor concentration N D is and the acceptor concentration N A is the net doping concentration at any position as N D - N A As specified. In the present description, the net doping concentration can simply be described as the doping concentration.

[0030] In this description, P+-like or N+-like signifies a higher doping concentration than that of P-like or N-like, and P-like or N-like signifies a lower doping concentration than that of P-like or N-like. Furthermore, P++-like or N++-like signifies a higher doping concentration than that of P+-like or N+-like. In this description, a system of units is an SI system of units unless otherwise stated. Although a unit of length can be expressed in cm, various calculations can be performed after conversion to meters (m).

[0031] In this description, a chemical concentration refers to the atomic density of an impurity, measured independently of any electrical activation state. The chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be measured by capacitance-voltage profiling (CV profiling). Alternatively, a carrier concentration measured by spreading resistance profiling (SRP profiling) can be set as the net doping concentration. The carrier concentration measured by either CV or SRP can be a value in a thermal equilibrium state. Furthermore, in an N-like region, the donor concentration is sufficiently higher than the acceptor concentration, and thus the carrier concentration of the region can be set as the donor concentration.Similarly, in a P-like region, the carrier concentration can be set as the acceptor concentration. In the present description, the doping concentration of the N-like region can be referred to as the donor concentration, and the doping concentration of the P-like region can be referred to as the acceptor concentration.

[0032] If a concentration distribution of donor, acceptor, or net doping exhibits a peak in a region, a value of the peak can be defined as the concentration of donor, acceptor, or net doping in that region. In a case where the concentration of donor, acceptor, or net doping in a region is substantially uniform, or the like, a mean donor, acceptor, or net doping concentration in that region can be defined as the donor, acceptor, or net doping concentration. In the present description, atoms / cm² are used. 3 or / cm 3 Used to express concentration per unit volume. This unit is used for the donor or acceptor concentration, or the chemical concentration in the semiconductor substrate. The number of atoms can be omitted.

[0033] The carrier concentration measured by the SRP method may be lower than the concentration of the donor or the acceptor. In a region where current is flowing when spreading resistance is measured, the carrier mobility of the semiconductor substrate may be lower than its value in a crystalline state. This reduction in carrier mobility occurs when carriers are scattered due to a disturbance (perturbation) of the crystal structure caused by a lattice defect or similar factor.

[0034] The donor or acceptor concentration, calculated from the carrier concentration measured by the CV or SRP method, can be lower than the chemical concentration of the element representing the donor or acceptor. For example, in a silicon semiconductor, the donor concentration of phosphorus or arsenic, acting as the donor, or the acceptor concentration of boron, acting as the acceptor, is approximately 99% of their respective chemical concentrations. Conversely, in the same silicon semiconductor, the donor concentration of hydrogen, acting as the donor, is approximately 0.1% to 10% of its chemical concentration.

[0035] Fig. Figure 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Fig. Figure 1 shows the position of each element projected onto a top surface of a semiconductor substrate 10. In Fig. Figure 1 shows only some elements of the semiconductor device 100, and illustrations of some elements have been omitted.

[0036] The semiconductor device 100 comprises the semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed from a semiconductor material. For example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has an end face 162 in plan view. When referred to simply as the plan view in this description, this means that the semiconductor substrate 10 is viewed from a top surface. In this example, the semiconductor substrate 10 has two sets of end faces 162, which are opposite each other in plan view. Fig. 1 The X-axis and the Y-axis are parallel to each of the end faces 162. Additionally, the Z-axis is perpendicular to the upper surface of the semiconductor substrate 10.

[0037] The semiconductor substrate 10 is provided with an active section 160. The active section 160 is a region in which a main current flows in the depth direction between the upper surface and a lower surface of the semiconductor substrate 10 when the semiconductor device 100 is operating. An emitter electrode is arranged above the active section 160, but an illustration of this is shown in Fig. 1 omitted. The active section 160 can refer to an area that overlaps with the emitter electrode in plan view. Additionally, an area enclosed between active sections 160 in plan view can also be included in the active section 160.

[0038] The active section 160 has transistor sections 70 containing transistor elements such as an insulated-gate bipolar transistor (IGBT). The active section 160 may also have diode sections 80 containing diode elements such as a freewheeling diode (FWD). In the Fig. In the example shown, transistor sections 70 and diode sections 80 are arranged alternately along a predetermined orientation (in this example, the X-axis direction) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 in this example is a reverse conduction IGBT (RC-IGBT).

[0039] In Fig. 1 is a region in which each of the transistor sections 70 is arranged, indicated by a symbol “I”, and a region in which each of the diode sections 80 is arranged is indicated by a symbol “F”. In the present description, a direction perpendicular to the arrangement direction in the top view can be referred to as an extent direction (in Fig. 1 the Y-axis direction). Each of the transistor sections 70 and the diode sections 80 can have a longitudinal dimension in the extension direction. In other words, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The extension directions of the transistor section 70 and the diode section 80, and a longitudinal direction of each trench section described below, can be the same.

[0040] Each of the diode sections 80 has an N+-type cathode region in an area that contacts the lower surface of the semiconductor substrate 10. In this description, an area in which the cathode region is located is referred to as a diode section 80. In other words, the diode section 80 is an area that overlaps the cathode region in a top view. A P+-type collector region may be located on the lower surface of the semiconductor substrate 10 in a region other than the cathode region. In this description, the diode section 80 may also have an extension region 81 in which the diode section 80 extends in the Y-axis direction to a gate rotor described below. The collector region is located on a lower surface of the extension region 81.

[0041] The transistor section 70 has a P+-like collector region in an area that contacts the lower surface of the semiconductor substrate 10. Furthermore, in the transistor section 70, an N-like emitter region, a P-like base region, and a gate structure with a gate conduction section and a dielectric gate film are regularly arranged on the upper surface of the semiconductor substrate 10.

[0042] The semiconductor device 100 can have one or more contact fields above the semiconductor substrate 10. In this example, the semiconductor device 100 has a gate field 164. The semiconductor device 100 can have a contact field, such as an anode field, a cathode field, and a current-sensing field. Each contact field is located in a region around the end face 162. The region around the end face 162 refers to an area between the end face 162 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each contact field can be connected to an external circuit via a wiring connection, such as a wire.

[0043] A gate potential is applied to the gate array 164. The gate array 164 is electrically connected to a conductive section of a gate trench section of the active section 160. The semiconductor device 100 includes the gate runner, which connects the gate array 164 to the gate trench section. Fig. 1 is the gate runner hatched with diagonal lines.

[0044] The gate rotor in this example comprises an outer gate rotor 130 and an active-side gate rotor 131. The outer gate rotor 130 is located, in plan view, between the active section 160 and the end face 162 of the semiconductor substrate 10. In this example, the outer gate rotor 130 encloses the active section 160 in plan view. An area enclosed by the outer gate rotor 130 in plan view can be defined as the active section 160. Furthermore, a trough region is formed below the gate rotor. The trough region is a P-shaped region with a higher concentration than the base region described below and extends from the upper surface of the semiconductor substrate 10 to a position lower than that of the base region. An area enclosed by the trough region in plan view can be defined as the active section 160.

[0045] The outer gate rotor 130 is connected to the gate array 164. The outer gate rotor 130 is arranged above the semiconductor substrate 10. The outer gate rotor 130 can be a metal wiring conductor containing aluminum or the like.

[0046] The active-side gate rotor 131 is located in the active section 160. Locating the active-side gate rotor 131 in the active section 160 can reduce variations in the wiring length from the gate array 164 for each region of the semiconductor substrate 10.

[0047] The outer gate rotor 130 and the active-side gate rotor 131 are connected to the gate trench section of the active section 160. The outer gate rotor 130 and the active-side gate rotor 131 are arranged above the semiconductor substrate 10. The outer gate rotor 130 and the active-side gate rotor 131 can form a wiring conductor made of a semiconductor, such as polysilicon doped with an impurity.

[0048] The active-side gate rotor 131 can be connected to the outer-encircling gate rotor 130. In this example, the active-side gate rotor 131 is arranged to extend in the X-axis direction to intersect the active section 160 substantially at the midpoint of the Y-axis direction, from one outer-encircling gate rotor 130 to another outer-encircling gate rotor 130 that have enclosed the active section 160. When the active section 160 is divided by the active-side gate rotor 131, the transistor sections 70 and the diode sections 80 can be arranged alternately in the X-axis direction in each divided region.

[0049] The semiconductor device 100 can include a temperature sensing section (not shown) which is a PN junction diode formed from polysilicon or the like, and a current sensing section (not shown) which simulates an operation of the transistor section which is arranged in the active section 160.

[0050] In this example, the semiconductor device 100 has an edge termination section 90 between the active section 160 and the end face 162 in a top view. The edge termination section 90 is arranged between the outer gate rotor 130 and the end face 162. The edge termination section 90 reduces the electric field strength at the upper surface of the semiconductor substrate 10. The edge termination section 90 can include a guard ring, a field plate, and / or a RESURF, arranged in a ring to enclose the active section 160.

[0051] Fig. Figure 2 shows an enlarged view of area D in Fig. 1. Region D is a region comprising a transistor section 70, a diode section 80, and the active-side gate rotor 131. The semiconductor device 100 in this example comprises a gate trench section 40, a blind trench section 30, a well section 11, an emitter section 12, a base section 14, and a contact section 15, which are arranged within the upper surface of the semiconductor substrate 10. Each of the gate trench section 40 and the blind trench sections 30 is an example of the trench section. Additionally, the semiconductor device 100 in this example comprises an emitter electrode 52 and the active-side gate rotor 131, which are arranged above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active-side gate rotor 131 are arranged to be separated from each other.

[0052] A dielectric interlayer film is arranged between the emitter electrode 52 and the active-side gate rotor 131 and the upper surface of the semiconductor substrate 10; however, the dielectric interlayer film is in Fig. 2 omitted. In the dielectric interlayer film in the present example, a contact section 54 is arranged such that it extends through the dielectric interlayer film. The contact section 54 can have a contact hole arranged in the dielectric interlayer film and a conductive element with which the contact hole is filled. In Fig. 2 each contact section 54 is hatched with the diagonal lines.

[0053] The emitter electrode 52 is positioned above the gate trench section 40, the blind trench section 30, the trough section 11, the emitter section 12, the base section 14, and the contact section 15. The emitter electrode 52 is connected to the emitter section 12, the contact section 15, and the base section 14 at the upper surface of the semiconductor substrate 10 via the contact section 54. Furthermore, the emitter electrode 52 is connected to a blind conductor section in the blind trench section 30 via the contact hole located in the dielectric interlayer film. The emitter electrode 52 can also be connected to the blind conductor section of the blind trench section 30 at an edge of the blind trench section 30 in the Y-axis direction.

[0054] The active-side gate runner 131 is connected to the gate trench section 40 via the contact hole located in the dielectric interlayer film. The active-side gate runner 131 can be connected to a gate conductor section of the gate trench section 40 at an edge section 41 of the gate trench section 40 in the Y-axis direction. The active-side gate runner 131 is not connected to the blind conductor section in the blind trench section 30.

[0055] The emitter electrode 52 is made of a material that contains metal. Fig. Figure 2 shows a region in which the emitter electrode 52 is arranged. For example, at least a portion of the emitter electrode 52 is made of aluminum or an aluminum-silicon alloy, such as AlSi or AlSiCu. The emitter electrode 52 may have a barrier metal formed of titanium, a titanium compound, or the like, beneath a region formed of aluminum or the like. Furthermore, a plug formed by embedding tungsten or the like, to be in contact with the barrier metal and aluminum or the like, may be contained in the contact hole.

[0056] The trough region 11 is arranged such that it overlaps the active-side gate rotor 131. The trough region 11 is arranged such that it extends with a predetermined width into a region that does not overlap with the active-side gate rotor 131. In this example, the trough region 11 is arranged such that it is spaced from one end of the contact section 54 in the Y-axis direction relative to the active-side gate rotor 131. The trough region 11 is a region of a second conductivity type with a higher doping concentration than that of the base region 14. In this example, the base region 14 is P-type, and the trough region 11 is P+-type.

[0057] Each transistor section 70 and diode section 80 has a plurality of trench sections arranged in a specific orientation. In the transistor section 70 of this example, one or more gate trench sections 40 and one or more blind trench sections 30 are arranged alternately along the orientation. In the diode section 80 of this example, a plurality of blind trench sections 30 are arranged along the orientation. In the diode section 80 of this example, no gate trench section 40 is arranged.

[0058] The ditch section 40 in the present example can have two straight pieces 39 extending along the direction of extension perpendicular to the arrangement direction (pieces of a ditch that are straight along the direction of extension), and the edge section 41 connecting the two straight pieces 39. The direction of extension in Fig. 2 is the Y-axis direction.

[0059] At least part of the edge section 41 is preferably arranged in a curved shape in the top view. The edge section 41, which connects the end sections of the two straight pieces 39 in the Y-axis direction, makes it possible to reduce the electric field strength at the end sections of the straight pieces 39.

[0060] In the transistor section 70, the blind trench sections 30 are arranged between the respective straight sections 39 of the gate trench sections 40. A single blind trench section 30 can be arranged between each straight section 39, or multiple blind trench sections 30 can be arranged. The blind trench section 30 can have a straight shape extending in the direction of travel, or it can have straight sections 29 and an edge section 31 similar to the gate trench section 40.

[0061] The diffusion depth of the trough area 11 can be greater than the depths of the gate trench section 40 and the blind trench section 30. The end sections in the Y-axis direction of the gate trench section 40 and the blind trench section 30 are arranged in the trough area 11 in plan view. In other words, at the end section of each trench section in the Y-axis direction, a bottom section of each trench section is covered by the trough area 11 in the depth direction. This configuration allows the electric field strength at the bottom section of each trench section to be reduced.

[0062] A mesa section is arranged between the respective trench sections in the arrangement direction. The mesa section refers to a region located between the trench sections within the semiconductor substrate 10. For example, the upper end of the mesa section is the upper surface of the semiconductor substrate 10. The depth position of a lower end of the mesa section is the same as the depth position of a lower end of the trench section. In this example, the mesa section is arranged such that it extends along the trench on the upper surface of the semiconductor substrate 10 in the extent direction (the Y-axis direction). In this example, a mesa section 60 is located in the transistor section 70, and a mesa section 61 is located in the diode section 80.As referred to in the present description simply as the mesa section, it specifies both mesa section 60 and mesa section 61.

[0063] Each mesa section is provided with the base region 14. In the mesa section, a region that is positioned such that it is closest to the active-side gate rotor 131 is defined as base region 14-e in the base region 14 that is exposed to the upper surface of the semiconductor substrate 10. Fig. Figure 2 shows the base region 14-e, which is located at one end of each mesa section in the extension direction. The base region 14-e is also located at another end of each mesa section. Each mesa section can be located with the emitter region 12 of a first conductivity type and / or the contact region 15 of the second conductivity type in a region enclosed in the top view between the base regions 14-e. In the present example, the emitter region 12 is N+-like and the contact region 15 is P+-like with a higher concentration than that of the base region 14. The emitter region 12 and the contact region 15 can be located in the depth direction between the base region 14 and the top surface of the semiconductor substrate 10.

[0064] The mesa section 60 of the transistor section 70 has the emitter region 12, which is exposed to the upper surface of the semiconductor substrate 10. The emitter region 12 contacts the gate trench section 40. The mesa section 60, which contacts the gate trench section 40, may have the contact region 15, which is exposed to the upper surface of the semiconductor substrate 10.

[0065] The emitter area 12 in mesa section 60 touches the gate ditch section 40. The emitter area 12 either touches the blind ditch section 30 or does not touch it. The emitter area 12 is also located in an area that overlaps with the contact section 54.

[0066] Contact area 15 in mesa section 60 is located in the area that overlaps with contact section 54. Contact area 15 either touches or does not touch gate ditch section 40. Contact area 15 either touches or does not touch blind ditch section 30.

[0067] In the example of Fig. In section 2, the emitter area 12 is located in the mesa section 60, extending from one trench section to another in the X-axis direction. The contact area 15 in the mesa section 60 can also be located from one trench section to another in the X-axis direction. The contact area 15 does not touch either of the two trench sections enclosing the mesa section 60. In this case, the base area 14 can be located between the contact area 15 and the trench section.

[0068] In the example of Fig. In one example, the contact area 15 and the emitter area 12 in the mesa section 60 are arranged alternately along the extension direction of the trench section (the Y-axis direction). In another example, the contact area 15 and the emitter area 12 in the mesa section 60 can be arranged in a strip shape along the extension direction of the trench section (the Y-axis direction). For example, the emitter area 12 is located in an area touching the trench section, and the contact area 15 is located in an area situated between the emitter areas 12. Furthermore, the mesa section 60 can be provided with the emitter area 12 instead of the contact area 15. For example, the emitter area 12 can be located in an entire area situated between the base areas 14-e in the Y-axis direction.

[0069] The mesa section 61 of the diode section 80 is not provided with the emitter section 12. The base sections 14 and the contact sections 15 can be arranged on an upper surface of the mesa section 61. In the region enclosed between the base sections 14-e on the upper surface of the mesa section 61, the contact section 15 can be in contact with each of the base sections 14-e. The base section 14 can be arranged in a region enclosed between the contact sections 15 on the upper surface of the mesa section 61. The base section 14 can be arranged in the entire region enclosed between the contact sections 15.

[0070] The contact section 54 is arranged above each mesa section. The contact section 54 is arranged in the area enclosed between the base areas 14-e. In this example, the contact section 54 is arranged above each area of ​​the contact area 15, the base area 14, and the emitter area 12. The contact section 54 is not arranged in areas corresponding to the base area 14-e and the basin area 11. The contact section 54 can be arranged in the center of the mesa section 60 in the arrangement direction (X-axis direction).

[0071] In the diode section 80, an N+-type cathode region 82 is arranged in a region adjacent to the lower surface of the semiconductor substrate 10. The P+-type collector region 22 can be arranged on the lower surface of the semiconductor substrate 10 in a region where the cathode region 82 is not located. The cathode region 82 and the collector region 22 are arranged between a lower surface 23 of the semiconductor substrate 10 and a buffer region 20. Fig. 2 is a boundary between the cathode area 82 and the collector area 22, represented by a dotted line.

[0072] The cathode region 82 is arranged such that it is spaced away from the well region 11 in the Y-axis direction. This configuration ensures sufficient distance between a P-shaped region (the well region 11), which has a comparatively high doping concentration and extends to the deep position, and the cathode region 82, thus improving the breakdown voltage. In the present example, an end section of the cathode region 82 in the Y-axis direction is arranged such that it is spaced further away from the well region 11 than an end section of the contact section 54 in the Y-axis direction. In another example, the end section of the cathode region 82 in the Y-axis direction can be arranged between the well region 11 and the contact section 54.

[0073] Fig. 3 is a view that shows an example of a cross-section ee in Fig. Figure 2 shows the cross-section ee, which is an XZ plane passing through an emitter region 12 and a cathode region 82. The semiconductor device 100 in this example includes the semiconductor substrate 10, a dielectric interlayer film 38, the emitter electrode 52, and a collector electrode 24 in cross-section.

[0074] The dielectric interlayer film 38 is arranged on the upper surface of the semiconductor substrate 10. The dielectric interlayer film 38 is a film comprising at least one layer of a dielectric film, such as silicate glass, to which an impurity, such as boron or phosphorus, is added, a thermal oxide film, or other dielectric films. The dielectric interlayer film 38 is provided with the contact section 54, which is described with reference to Fig. 2 is described.

[0075] The contact section 54 is arranged such that it extends through the dielectric interlayer film 38. The contact section 54 can be formed from a metal that differs from that of the emitter electrode 52. The contact section 54 can contain tungsten. A lower section of the contact section 54 can be provided with a barrier metal layer containing at least one titanium film or a titanium nitride film. The contact section 54 can extend to an upper surface 21 of the semiconductor substrate 10 or to an inner surface of the semiconductor substrate 10. In the example of Fig. In section 3, the contact section 54 is a contact groove that extends from the upper surface 21 of the semiconductor substrate 10 to an inner side of each mesa section. This allows for an increased contact area between the contact section 54 and the semiconductor substrate 10. In cross-section, a lower end of the contact section 54 of the transistor section 70 is in contact with the emitter region 12. In cross-section, a lower end of the contact section 54 of the diode section 80 is in contact with the base region 14.

[0076] The emitter electrode 52 is arranged above the dielectric interlayer film 38. The emitter electrode 52 is connected to the semiconductor substrate 10 via the contact section 54. The collector electrode 24 is arranged on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a metallic material such as aluminum. In this description, the direction (the Z-axis direction) in which the emitter electrode 52 is connected to the collector electrode 24 is referred to as the depth direction.

[0077] The semiconductor substrate 10 has an N-type or N--type drift region 18. The drift region 18 is located in the transistor section 70 and in the diode section 80, respectively.

[0078] In the mesa section 60 of the transistor section 70, the N+-type emitter region 12 and the P-type base region 14 are arranged sequentially, starting from one side of the upper surface 21 of the semiconductor substrate 10. The drift region 18 is located below the base region 14. The mesa section 60 may include an N+-type collector region 16. The collector region 16 is located between the base region 14 and the drift region 18.

[0079] The emitter region 12 is exposed to the upper surface 21 of the semiconductor substrate 10 and touches the gate trench section 40. The emitter region 12 touches the trench sections on both sides of the mesa section 60. The emitter region 12 has a higher doping concentration than that of the drift region 18.

[0080] Base area 14 is located below emitter area 12. In this example, base area 14 touches emitter area 12. Base area 14 touches the trench sections on both sides of mesa section 60.

[0081] The collection area 16 is located below the base area 14. The collection area 16 is an N+-like region with a higher doping concentration than that of the drift area 18. That is, the collection area 16 has a higher donor concentration than that of the drift area 18. Positioning the collection area 16 with its high concentration between the drift area 18 and the base area 14 can enhance the charge carrier injection (IE) effect and reduce the turn-on voltage. The collection area 16 can be positioned to cover the entire lower surface of the base area 14 in each mesa section 60.

[0082] In the mesa section 61 of the diode section 80, the P-like base region 14 is in contact with the upper surface 21 of the semiconductor substrate 10. The drift region 18 is located below the base region 14. The collector region 16 can also be located below the base region 14 in the mesa section 61.

[0083] In transistor section 70 and diode section 80, the N+-like buffer region 20 can each be located below the drift region 18. The doping concentration of the buffer region 20 is higher than that of the drift region 18. The buffer region 20 can exhibit a concentration peak with a higher doping concentration than that of the drift region 18. A doping concentration at a concentration peak refers to a doping concentration at a local maximum of the concentration peak. Additionally, the doping concentration of the drift region 18 can be defined as the average of doping concentrations in a region where the doping concentration distribution is essentially flat.

[0084] The buffer region 20 can have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peak of the buffer region 20 can, for example, be located at the same depth position as a chemical concentration peak of hydrogen (a proton) or phosphorus. The buffer region 20 can act as a field-stopping layer, preventing a depletion layer extending from a lower end of the base region 14 from reaching the P+-like collector region 22 and the N+-like cathode region 82.

[0085] In transistor section 70, the P+-like collector region 22 is located below the buffer region 20. The acceptor concentration of the collector region 22 is higher than that of the base region 14. The collector region 22 can have an acceptor that is the same as or different from an acceptor of the base region 14. The acceptor of the collector region 22 is, for example, boron.

[0086] The N+-like cathode region 82 is located below the buffer region 20 in the diode section 80. The donor concentration in the cathode region 82 is higher than the donor concentration in the drift region 18. A donor in the cathode region 82 could be, for example, hydrogen or phosphorus. It should be noted that an element acting as both a donor and an acceptor in each region is not limited to the example described above. The collector region 22 and the cathode region 82 are exposed to the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24.

[0087] The collector electrode 24 can contact the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a metallic material such as aluminum.

[0088] One or more gate trench sections 40 and one or more blind trench sections 30 are arranged on the side of the upper surface 21 of the semiconductor substrate 10. Each trench section extends through the base region 14 and is arranged from the upper surface 21 of the semiconductor substrate 10 to a region below the base region 14. In a region where the emitter region 12 and / or the contact region 15 and / or the collector region 16 are located, each trench section also extends through the doping regions of these regions. A structure in which the trench section extends through the doping region is not limited to a structure formed by forming the doping region and subsequently forming the trench section in that sequence.A structure in which the trench section is formed and subsequently the doping area between the trench sections is formed is also included in the structure in which the trench section runs through the doping area.

[0089] As described above, transistor section 70 is equipped with gate-trough section 40 and blind-trough section 30. Diode section 80 is equipped with blind-trough section 30 but not with gate-trough section 40. In this example, the boundary between diode section 80 and transistor section 70 in the X-axis direction is the boundary between cathode region 82 and collector region 22.

[0090] The gate trench section 40 comprises a gate trench located in the upper surface 21 of the semiconductor substrate 10, a dielectric gate film 42, and a gate conductor section 44. The dielectric gate film 42 is arranged to cover an inner wall of the gate trench. The dielectric gate film 42 can be formed by oxidizing or nitriding a semiconductor on the inner wall of the gate trench. The gate conductor section 44 is located further inside the gate trench than the dielectric gate film 42. In other words, the dielectric gate film 42 insulates the gate conductor section 44 from the semiconductor substrate 10. The gate conductor section 44 is formed from a conductive material such as polysilicon.

[0091] The gate conduction section 44 can be arranged to be longer in the depth direction than the base region 14. The gate trench section 40 in cross-section is covered by the dielectric interlayer film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conduction section 44 is electrically connected to the gate rotor. When a predetermined gate voltage is applied to the gate conduction section 44, a channel is formed through an electron inversion layer in a surface layer of the base region 14 at a boundary in contact with the gate trench section 40.

[0092] The blind trench sections 30 can have the same cross-sectional structure as the gate trench sections 40. The blind trench section 30 comprises a blind trench located in the upper surface 21 of the semiconductor substrate 10, a dielectric dummy film 32, and a dummy conductor section 34. The dummy conductor section 34 is electrically connected to the emitter electrode 52. The dielectric dummy film 32 is arranged to cover an inner wall of the blind trench. The dummy conductor section 34 is located within the blind trench and further inward than the dielectric dummy film 32. The dielectric dummy film 32 insulates the dummy conductor section 34 from the semiconductor substrate 10. The dummy conductor section 34 can be made of the same material as the gate conductor section 44. For example, the dummy conductor section 34 is made of a conductive material such as polysilicon.The dummy line section 34 can have the same length in the depth direction as the gate line section 44.

[0093] In this example, the gate trench section 40 and the blind trench section 30 are covered with the dielectric interlayer film 38 on the upper surface 21 of the semiconductor substrate 10. It should be noted that bottom sections of the blind trench section 30 and the gate trench section 40 may have curved surfaces that are convex downwards (curved shapes in the cross-sections). In this description, a depth position of a lower end 43 of the gate trench section 40 is defined as Zt.

[0094] The semiconductor device 100 in the present example has a P-shaped floating region 202 located below the lower end 43 of the gate trench section 40. The lower end 43 of the gate trench section 40 refers to a portion of the gate trench section 40 that is closest to the lower surface 23 of the semiconductor substrate 10. In the example of Fig. 3 is the lower end 43 of the gate trench section 40, located in the X-axis direction at the center of the gate trench section 40. Furthermore, a lower end 33 of the blind trench section 30 refers to a portion within the blind trench section 30 that is closest to the lower surface 23 of the semiconductor substrate 10. In the example of Fig. 3 is the lower end 33 of the blind trench section 30 in the X-axis direction in the middle of the blind trench section 30.

[0095] At least a portion of the floating area 202 is positioned in a location that overlaps the lower end 43 in plan view and is located below the lower end 43 in the Z-axis direction. The floating area 202 may have a portion that does not overlap the lower end 43 in plan view. The floating area 202 may have a portion that is located above the lower end 43. The floating area 202 may touch the lower end 43 or be spaced apart from the lower end 43. In the example of Fig. 3 The floating area 202 touches the entire curved surface part including the lower end 43 in the gate trench section 40. The floating area 202 can be formed after the formation of a trench structure of the gate trench section 40 and before the formation of the gate conduit section 44 by implanting the P-like dopant in the vicinity of a lower end of the trench structure.

[0096] The levitation region 202 is electrically levitated with respect to an electrode made of metal, polysilicon, or the like. An N-type region and / or a dielectric film is arranged between the levitation region 202 and the electrode. In other words, the levitation region 202 and the electrode are not connected to each other by a P-type region or a conductive material. The doping concentration of the levitation region 202 can be lower than or equal to the doping concentration of the base region 14, or it can be higher than the doping concentration of the base region 14. In the present example, the doping concentration of the levitation region 202 is higher than the doping concentration of the base region 14. The doping concentration can be higher than or equal to 1 × 10⁻⁶ 15 cm -3 and less than or equal to 1 × 10 17 cm -3 be.

[0097] The floating area 202 is arranged such that it is spaced apart from the base area 14. An N-shaped area (in this example the collection area 16 and / or the drift area 18) is arranged between the floating area 202 and the base area 14.

[0098] In this description, among the gate trench sections 40, the one that has the suspended area 202 arranged below it is designated as the first gate trench section 40-1. Additionally, among the blind trench sections 30, the one that is arranged side by side with the first gate trench section 40-1 in the X-axis direction on the upper surface 21 is designated as the first blind trench section 30-1. The first gate trench section 40-1 and the first blind trench section 30-1 are two trench sections adjacent in the X-axis direction. In this example, the first blind trench sections 30-1 are arranged on both sides of the first gate trench section 40-1 in the X-axis direction. Additionally, among the mesa sections 60, the one that is arranged between the first gate trench section 40-1 and the first blind trench section 30-1 is designated as the first mesa section 60-1.Among the mesa sections 60, the one located between two blind trench sections 30 is designated as the second mesa section 60-2. The second mesa section 60-2 may have the same structure as the first mesa section 60-1.

[0099] Each transistor section 70 has one or more first gate-trench sections 40-1. Each transistor section 70 can have a plurality of first gate-trench sections 40-1. In each transistor section 70, 50% or more of the gate-trench sections 40 can be the first gate-trench sections 40-1, 80% or more of the gate-trench sections 40 can be the first gate-trench sections 40-1, or all of the gate-trench sections 40 can be the first gate-trench sections 40-1.

[0100] The floating area 202 is located below the lower end 43 of the first gate trench section 40-1 and does not extend to an area below the lower end 33 of the adjacent first blind trench section 30-1. The lower end 33 touches an N-type area (in this example, the drift area 18). Additionally, no P-type area is provided on the side of the upper surface 21 of the semiconductor substrate 10 below the lower end 33, and an N-type area (in this example, the drift area 18) is provided.

[0101] By arranging the floating region 202, it is possible to prevent electrons from flowing to the lower end 43 of the first gate trench section 40-1 when the transistor section 70 is turned on, thus causing a depletion layer to remain near the lower end 43. The reverse recovery dV / dt is the slope of a time waveform of an anode-cathode voltage at a given point in the reverse recovery of the diode section 80. Furthermore, when the semiconductor device 100 is used in a circuit such as a three-phase inverter, it is possible to reduce one end of a voltage waveform of the IGBT, which is arranged in opposite branches. Therefore, it is possible to improve a compromise property between turn-on loss and the reverse recovery dV / dt.

[0102] If, on the other hand, the floating region 202 extends to a region below the lower end 33 of the first blind trench section 30-1, it becomes difficult for the electron current to flow to the collector region 22 if a channel is formed in the base region 14 of the first mesa section 60-1 and an electron current flows. Therefore, a snapshot may occur when the transistor section 70 is turned on. Furthermore, the turn-on time of the transistor section 70 may be longer. In the semiconductor device 100 in the present example, the floating region 202 does not extend to the region below the lower end 33 of the first blind trench section 30-1. Therefore, if a channel is formed in the base region 14 of the first mesa section 60-1 and an electron current flows, it becomes easy for the electron current to flow to the collector region 22.This makes it possible to suppress the occurrence of the snapshot and to reduce the power-on delay.

[0103] The suspended area 202 in the present example is arranged such that it does not overlap the first blind trench section 30-1 in plan view. The suspended area 202 can be arranged so that it is not in contact with the first blind trench section 30-1. In the present example, an N-shaped area is arranged between the suspended area 202 and the first blind trench section 30-1. The suspended area 202 can be arranged so that it overlaps the first mesa section 60-1 in plan view. The first mesa section 60-1 can have an area that does not overlap the suspended area 202 in plan view. In the first mesa section 60-1 in the present example, an area that is in contact with the first blind trench section 30-1 does not overlap the suspended area 202.The floating area 202 can extend to a position that overlaps with the contact section 54 of the first mesa section 60-1, or it can be arranged so that it does not overlap.

[0104] The suspended section 202 is arranged such that it extends in the Y-axis direction in plan view. The length of the suspended section 202 in the Y-axis direction can be 50% or more of the length of the straight section 39 of the first gate trench section 40-1 in the Y-axis direction, 70% or more, or 90% or more. If the suspended section 202 is arranged over the entire first gate trench section 40-1, an end section of the suspended section 202 in the Y-axis direction is positioned below the base section 14-e.

[0105] A distance in the X-axis direction between the first gate trench section 40-1 and the first blind trench section 30-1 is defined as X1. A distance between the trench sections is a distance between the centers of the trench sections in the X-axis direction. A distance in the X-axis direction between the two blind trench sections 30 in the transistor section 70 is defined as X2. In this example, a distance between the first two blind trench sections 30-1 is equal to X2. The distance X1 and the distance X2 can be equal. A distance in the X-axis direction between the two blind trench sections 30 in the diode section 80 is defined as X3. The distances X1, X2, and X3 can be equal.

[0106] In at least one transistor section 70, which is arranged such that it is enclosed between two diode sections 80 in the X-axis direction, the distances between all trench sections can be the same. Furthermore, the distances between all trench sections in the semiconductor device 100 can be the same.

[0107] Fig. 4 is a view that shows an example of a cross-section ff in Fig. Figure 2 shows that the cross-section ff is an XZ plane passing through the contact area 15 and the cathode area 82. The semiconductor device 100 in cross-section ff has the contact area 15 instead of the emitter area 12 of the mesa section 60 in the structure of the semiconductor device 100 in cross-section ee. In addition, the contact area 15 is also arranged in the mesa section 61. Other structures are similar to those of the semiconductor device 100 in cross-section ee.

[0108] The contact area 15 is exposed to the upper surface 21 of the semiconductor substrate 10. The contact area 15 is located between the upper surface 21 and the base area 14. In this example, the contact area 15 does not touch the trench sections on either side in each mesa section. In the example of Fig. In section 4, the base region 14 is arranged between the contact region 15 and each trench section. In this example, the contact region 15 is connected to the emitter electrode 52 via the contact section 54. The contact region 15 can be provided with a trench section into which the contact section 54 is inserted. In cross-section, the lower ends of the contact sections 54 of the transistor section 70 and the diode section 80 are in contact with the contact region 15.

[0109] Fig. Figure 5 is a diagram showing a collector voltage-collector current characteristic in an example and a reference example. The reference example is one in which the floating region 202 is caused to extend to a region below the lower end 33 of the first blind trench section 30-1. The example is the semiconductor device 100, which, with reference to Fig. 1 to Fig. 4 is described.

[0110] In the reference example, the suspension region 202 makes it difficult for the electron current from the first mesa section 60-1 to flow to the collector region 22. Therefore, in the reference example, as in Fig. Figure 5 shows the snapshot, in which almost no collector current flows until the collector voltage exceeds a predetermined voltage. In contrast, in the semiconductor device 100 according to the example, the electron current from the first mesa section 60-1 flows easily to the collector region 22. Therefore, the snapshot does not occur.

[0111] Fig. Figure 6 is a diagram showing a measurement example of a voltage and current of the semiconductor device of the reference example. The semiconductor device of the reference example in Fig. 6 exhibits a structure similar to that of the semiconductor device of the reference example in Fig. 5 up. Fig. Figure 6 shows time waveforms of a collector voltage Vce, a collector current Ic, and a gate voltage Vge of the semiconductor device. Fig. 6 represents Vbus a voltage of a bus wiring connected to the collector of the semiconductor device, Ic represents a steady-state value of the collector current, Rg represents a gate resistance, and Tj represents a temperature of a measurement environment.

[0112] In Fig. 6 is the time at which a predetermined turn-on voltage is applied to a gate of the semiconductor device, set as reference time zero. Additionally, the time until the collector voltage Vce is reduced to 10% of a voltage value (600 V) in an off state is set as a turn-on time of the semiconductor device.

[0113] When a gate capacitance is charged, the gate voltage Vge increases. In the present example, when the gate voltage Vge reaches approximately 440 V, a channel is formed in the base region 14. It should be noted that in the reference example, it is difficult for the electron current from the first mesa section 60-1 to flow to the collector region 22, thus delaying the rise of the collector current Ic and also delaying the fall of the collector voltage Vce. Therefore, the turn-on time becomes comparatively long, which increases the loss during turn-on.

[0114] Fig. Figure 7 is a diagram showing a measurement example of a voltage and current of a semiconductor device. The semiconductor device of the example is shown in Fig. 7 is the semiconductor device 100, which is described with reference to Fig. 1 to Fig. As described in section 4. In this example, the electron current from the first mesa section 60-1 flows easily to the collector region 22. Therefore, the delay in the rise of the collector current Ic and the fall of the collector voltage Vce are small. In this way, the turn-on time is comparatively short, which makes it possible to reduce losses during turn-on.

[0115] Fig. Figure 8 is a diagram showing another measurement example of the voltage and current of the semiconductor device of a reference example. In the present example, the steady-state value of the collector current Ic (150 A) differs from the steady-state value of the collector current Ic (15 A) in the reference example. Fig. 6. Other conditions are similar to those in the reference example of Fig. 6. Also in the reference example of Fig. 8. The rise of the collector current Ic is delayed, and the fall of the collector voltage Vce is also delayed. Therefore, the turn-on time becomes comparatively long, which increases the loss during turn-on.

[0116] Fig. Figure 9 is a diagram showing another measurement example of the voltage and current of the semiconductor device. In the present example, the steady-state value of the collector current Ic (150 A) differs from the steady-state value of the collector current Ic (15 A) in the example of Fig. 7. Other conditions are similar to those in the example of Fig. 7. Also in the example of Fig. 9. The delay in the rise of the collector current Ic and the fall of the collector voltage Vce are small. In this way, the turn-on time is comparatively short, which makes it possible to reduce losses during turn-on.

[0117] Fig. Figure 10 is a diagram showing a trade-off property between a turn-on loss and a reverse recovery dV / dt in a reference example and an example. Fig. Figure 10 shows the trade-off relationship in which the turn-on loss is increased when the reverse recovery dV / dv is reduced.

[0118] The reference example in Fig. 10 is a semiconductor device that does not have a levitation region 202. The semiconductor device of the example is the semiconductor device 100, which is described with reference to Fig. 1 to Fig. As described in section 4, the semiconductor device 100 of the example has the floating range 202, which improves the compromise property. For example, if the reverse recovery dV / dt is set to the same value, the turn-on loss in the example is smaller than in the reference example.

[0119] As with reference to Fig. As described in section 10, it is possible with the semiconductor device 100 to improve the compromise property between the turn-on loss and the reverse recovery dV / dt. As described in section 10, Fig. 6 to Fig. As described in section 9, it is possible to reduce the turn-on delay in the transistor section 70 using the semiconductor device 100.

[0120] Fig. Figure 11 is a view showing another example of the cross-section ff. The semiconductor device 100 in the present example differs from the one in Fig. 3 and Fig. 4 Semiconductor device 100 shown in the structure of collection area 16. Other structures are similar to those of semiconductor device 100 in every aspect described in the present description.

[0121] The collection area 16 in the present example touches the suspension area 202. The collection area 16 may or may not touch the base area 14. In each mesa section, a lower end of the collection area 16 may be located at the same depth. The lower end of the collection area 16 may be located closer to the side of the upper surface 21 than the lower end 43 of the first gate trench section 40-1, may be located closer to the lower surface 23 than the lower end 43, or may be located at the same depth as the lower end 43. In the present example, the lower end of the collection area 16 is located above a lower end of the suspension area 202.

[0122] According to the present example, the collection area 16 is located in a high concentration in the vicinity of the suspended area 202, so that it is possible to suppress excessive diffusion of the P-type dopant in the suspended area 202, and it is possible to prevent the entire first mesa section 60-1 from being covered by the suspended area 202. For example, an N-type area easily remains in the vicinity of the first blind trench section 30-1. Therefore, it is easy to further suppress the occurrence of snapshots or the like.

[0123] Fig. Figure 12 is a view showing another example of the cross-section ff. The semiconductor device 100 in the present example differs from the one in Fig. 11 Semiconductor device 100 shown in the structure of the collection area 16. Other structures are similar to those of semiconductor device 100 in every aspect described in the present description.

[0124] In the present example, the lower end of the collection area 16 is located below the lower end of the floating area 202. The floating area 202 in this example is surrounded by the collection area 16, except for a portion that contacts the trench section. The lower end of the collection area 16 can be located on the side of the upper surface 21 of the semiconductor substrate 10. A distance in the Z-axis direction between the lower end of the floating area 202 and the lower end of the collection area 16 can be 10 µm or less, 5 µm or less, or 3 µm or less.

[0125] According to the present example, the suspended area 202 is surrounded by the collecting area 16. Therefore, excessive diffusion of the P-type dopant in the suspended area 202 can be suppressed, so that the entire first mesa section 60-1 is covered by the suspended area 202. For example, an N-type area easily remains in the vicinity of the first blind trench section 30-1. Therefore, it becomes easy to further suppress the occurrence of snapshots or the like.

[0126] Fig. Figure 13 is a view showing another example of the cross-section ff. The semiconductor device 100 in the present example differs from the semiconductor device 100 in other examples in the arrangement of the levitation regions 202. Other structures are similar to those of the semiconductor device 100 in every aspect described in the present description.

[0127] The floating region 202 in this example does not touch the first gate trench section 40-1. The floating region 202 is located below and spaced from the lower end 43 of the first gate trench section 40-1. Also in this example, the floating region 202 is located on the side of the upper surface 21 of the semiconductor substrate 10. The distance between the floating region 202 and the lower end 43 in the Z-axis direction can be 10 µm or less, 5 µm or less, or 3 µm or less. With this example, it becomes easy to ensure a path in which the electron current flows from the first mesa section 60-1 to the collector region 22. Therefore, it is possible to further suppress the occurrence of snapshots or similar phenomena.

[0128] Fig. Figure 14 is a view showing another example of the cross-section ff. The semiconductor device 100 in the present example differs from the semiconductor device 100 in other examples in the arrangement of the levitation regions 202. Other structures are similar to those of the semiconductor device 100 in every aspect described in the present description.

[0129] In this example, the suspended area 202 is in contact with the first blind trench section 30-1. If the first blind trench sections 30-1 are arranged on both sides of the first gate trench section 40-1 in the X-axis direction, the suspended area 202 can be in contact with both of the first blind trench sections 30-1.

[0130] In the present example as well, the suspended area 202 does not extend to the area below the lower end 33 of the first blind trench section 30-1. The suspended area 202 can be in contact with a side wall of the first blind trench section 30-1. The side wall is a different part of an outer wall section of the first blind trench section 30-1 than the lower end 33. The side wall of the first blind trench section 30-1 can be a flat surface section in the outer wall of the first blind trench section 30-1. It is also possible in the present example to improve the compromise property described above.

[0131] The dummy conductor section 34 of the first blind trench section 30-1 in the present example can be a polysilicon electrode doped with an N-type impurity. If the dummy conductor section 34 is P-type polysilicon, the side wall of the first blind trench section 30-1 has the same potential as the suspension region 202. In this case, a path in which the electron current flows from the channel is cut off by an equipotential region, and it becomes difficult for the electron current to flow. By making the dummy conductor section 34 N-type, the side wall of the first blind trench section 30-1 has a different potential than that of the suspension region 202. In this case, the path in which the electron current flows remains in a neighborhood of the side wall of the first blind trench section 30-1.In other words, it is possible to suppress the occurrence of the snapshot or the like and to improve the compromise property of the semiconductor device 100.

[0132] The other conduit sections of the trench sections, besides the first blind trench section 30-1, can also be N-type polysilicon. A doping concentration of the N-type impurity in the dummy conduit section 34 of the first blind trench section 30-1 can be higher than a doping concentration of the N-type impurity in the gate conduit section 44 of the first gate trench section 40-1. This makes it easy to ensure a path in which the electron current flows in a neighborhood of the side wall of the first blind trench section 30-1. In another example, the conduit sections of at least some of the trench sections other than the first blind trench section 30-1 can be P-type polysilicon. For example, the conduit section of the first gate trench section 40-1 can be P-type polysilicon.

[0133] Fig. Figure 15 is a view showing another example of the cross-section ff. The semiconductor device 100 in the present example differs from the semiconductor device 100 in other examples in the arrangement pattern of the trench sections of the transistor section 70 in the X-axis direction. Structures other than the arrangement pattern of the trench sections are similar to those of the semiconductor device 100 in every aspect described in this description.

[0134] The transistor section 70 in the present example has two first gate-trough sections 40-1 arranged so that they are adjacent to each other in the X-axis direction. As an example, in transistor section 70, two first gate-trough sections 40-1 and two first blind-trough sections 30-1 are arranged alternately in the X-axis direction.

[0135] The suspension area 202 is located below the lower end 43 of each of the first gate trench sections 40-1. The suspension areas 202 below the two first gate trench sections 40-1, which are adjacent to each other in the X-axis direction, can be separated from each other, as shown in Fig. 15 are shown, or can be linked together.

[0136] The mesa section 60, which is arranged between the two first gate ditch sections 40-1, is designated as the third mesa section 60-3. The third mesa section 60-3 can have the same structure as the first mesa section 60-1. In another example, the third mesa section 60-3 can have a different structure than the first mesa section 60-1. The third mesa section 60-3 can be arranged between the first mesa sections 60-1 in the X-axis direction. In the present example, three or more first gate ditch sections 40-1 are not arranged continuously in the X-axis direction.

[0137] Fig. Figure 16 is a view showing another example of the cross-section ff. The semiconductor device 100 in the present example differs from the semiconductor device 100 in the other examples in that it includes a lower end region 204. Structures other than the lower end region 204 are similar to those of the semiconductor device 100 in every aspect described in this description.

[0138] The lower end region 204 is an N-like region located below the lower end 33 of the first blind trench section 30-1. The doping concentration of the lower end region 204 is higher than that of the drift region 18. The doping concentration of the lower end region 204 can be two or more times, five or more times, or ten or more times that of the drift region 18. The doping concentration of the lower end region 204 can be higher or lower than that of the float region 202. By providing the lower end region 204, it is possible to prevent the environment around the lower end 33 of the first blind trench section 30-1 from becoming P-like, and it is easier to ensure the path for the electron flow.

[0139] The lower end section 204 can touch or be spaced apart from the lower end 33 of the first blind trench sections 30-1. A lower end of the lower end section 204 can be positioned above or below the lower end of the suspended area 202. The lower end section 204 can be spaced apart from or touching the collection area 16.

[0140] Fig. Figure 17 is a view showing another example of the cross-section ee. The semiconductor device 100 in the present example further has a contact area 19 with respect to the in Fig. The structure shown in Figure 3 is also shown. Furthermore, the arrangement of contact section 54 is different. Other structures are similar to those in the example in Figure 3. Fig. 3 similar.

[0141] The contact area 19 is in contact with the lower end of the contact section 54 and is a P+-like region with a higher doping concentration than that of the base region 14. The doping concentration of the contact area 19 can be the same as that of the contact area 15. At least part of the contact area 19 can be located within the base region 14. The contact section 54 in the transistor section 70 can be arranged to extend through the emitter region 12 or not. In the present example, the contact area 19 in the transistor section 70 is located below the emitter region 12. Furthermore, the entire contact area 19 in the diode section 80 is located within the base region 14.

[0142] In each mesa section in cross-section ff, the contact area 19 can be arranged at a depth position similar to that in cross-section ee. Furthermore, if the emitter area 12 is arranged instead of the contact area 15, cross-section ff has a structure similar to that in Fig. 17 is similar.

[0143] Although the present invention has been described with reference to the embodiments described above, its technical scope is not limited to these embodiments. It is obvious to those skilled in the art that various modifications or improvements can be made to the embodiments described above. It is also evident from the scope of the claims that embodiments added by such modifications or improvements can be included in the technical scope of the present invention.

[0144] The operations, procedures, steps, stages, or the like of any process performed by a device, system, program, or method shown in the claims, embodiments, or diagrams may be performed in any order, provided that the order is not specified by "before," "before," or the like, and provided that the output of a preceding process is not used in a subsequent process. Even if, for the sake of simplicity, the process flow is described in the claims, embodiments, or diagrams using expressions such as "first" or "next," this does not necessarily mean that the process must be performed in that order. REFERENCE MARK LIST 10 Semiconductor substrate 11 Bathtub area 12 emitter area 14 Basic area 15 Contact area 16 Collection area 18 Drift range 19 Contact area 20 Buffer area 21 upper surface 22 Collector area 23 lower surface 24 Collector electrode 29 even pieces 30 Blind trench section 30-1 first blind trench section 31 Marginal section 32 dielectric blind film 33 lower end 34 Blind line section 38 dielectric interlayer film 39 even pieces 40 Gattergraben section 40-1 first gate ditch section 41 marginal section 42 dielectric gate film 43 lower end 44 Gate line section 45 trench 52 Emitter electrode 54 Contact section 60, 61 Mesa section 60-1 first mesa section 60-2 second mesa section 60-3 third mesa section 70 Transistor section 80 diode section 81 Extension area 82 Cathode area 90 edge finish structure section 100 semiconductor devices 130 outer-circumference gate runner 131 active-side gate runner 160 active section 162 Front 164 Gatterfeld 202 Floating area 204 lower end range. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2020-21941

[0002] JP 2010-232627

[0002]

Claims

[1] Semiconductor device comprising an IGBT, wherein the semiconductor device comprises: a semiconductor substrate having an upper surface and a lower surface and having a drift region of a first conductivity type; a first gate trench section located on the upper surface of the semiconductor substrate; a first blind trench section located on the upper surface of the semiconductor substrate and arranged side by side with the first gate trench section on the upper surface; a first mesa section located between the first gate trench section and the first blind trench section within the semiconductor substrate; and a floating region of a second conductivity type located below a lower end of the first gate trench section and not extending to a region below a lower end of the first blind trench section on an upper surface side of the semiconductor substrate, wherein the first mesa section comprises an emitter area of ​​the first conductivity type, which is located in contact with the first gate trench section and which has a higher concentration than that of the drift area, and a base region of the second conductivity type, located between the emitter region and the drift region, touching the first gate trench section, and the lower end of the first blind trench section touches an area of ​​the first conductivity type. [2] Semiconductor device according to claim 1, wherein the floating area does not touch the lower end of the first gate trench section. [3] Semiconductor device according to claim 1, wherein the floating area touches the lower end of the first gate trench section. [4] Semiconductor device according to one of claims 1 to 3, wherein the first mesa section further comprises a collection area of ​​the first conductivity type, which is arranged between the base area and the drift area and which has a higher concentration than that of the drift area. [5] Semiconductor device according to claim 4, wherein the collecting area touches the levitation area. [6] Semiconductor device according to claim 5, wherein a lower end of the collecting area is arranged below a lower end of the floating area. [7] Semiconductor device according to claim 5, wherein a lower end of the collecting area is arranged above a lower end of the floating area. [8] Semiconductor device according to claim 1, wherein the first mesa section further comprises a contact area of ​​the second conductivity type which touches the upper surface of the semiconductor substrate and which has a higher concentration than that of the base area. [9] Semiconductor device according to claim 8, wherein the first mesa section further comprises a contact section which is arranged from the upper surface of the semiconductor substrate to an inside of the first mesa section and which is filled with a conductive material. [10] Semiconductor device according to claim 9, wherein a lower end of the contact section touches the contact area. [11] Semiconductor device according to one of claims 1 to 3, wherein the first blind trench section is arranged on each of the two sides of the first gate trench section. [12] Semiconductor device according to one of claims 1 to 3, wherein the floating area touches a side wall of the first blind trench section. [13] Semiconductor device according to claim 12, wherein the first blind trench section has a polysilicon electrode doped with an impurity of the first conductivity type. [14] Semiconductor device according to any one of claims 1 to 3, further comprising: a lower end region of the first conductivity type, which is located in contact with the lower end of the first blind trench section and which has a higher concentration than that of the drift area. [15] Semiconductor device according to any one of claims 1 to 3, further comprising: two blind trench sections arranged on the upper surface of the semiconductor substrate and arranged side by side on the upper surface, wherein The distance between the first gate ditch section and the first blind ditch section is the same as the distance between the two blind ditch sections. [16] Semiconductor device according to any one of claims 1 to 3, further comprising: a plurality of diode sections, each of which is arranged alternately next to the IGBT in a first direction, wherein The IGBT, which is arranged so that it is enclosed between the diode sections, has a plurality of trench sections arranged side by side in the first direction and includes the first gate trench section and the first blind trench section, and The distances between the respective trench sections are the same for the multitude of trench sections.

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