STACKED FELDEFFECT TRANSITION TOWER

Abstract

A semiconductor device with stacked field-effect transistors (FETs) is provided. The stacked FETs are formed using a process that optimizes the thermal budget without negatively impacting the front and / or back-side contact structures. The stacked FETs can be designed to have different exit metals, and a front / back-side deep through-hole plating structure with low sheet resistance can be provided.

Description

BACKGROUND

[0001] The present application relates to semiconductor technology and in particular to a semiconductor device comprising stacked field-effect transistors (FETs).

[0002] Stacking devices, such as FETs, is an attractive architecture for the future scaling of complementary metal oxide semiconductors (CMOS) and potentially for ultimate scaled technology. Direct stacking of devices on top of each other (for example, pFETs on top of nFETs, nFETs on top of pFETs, pFETs on top of pFETs, or nFETs on top of nFETs) can achieve significant area scaling. SUMMARY

[0003] A semiconductor device incorporating stacked FETs is provided. The stacked FETs are formed using a process that optimizes the thermal budget without negatively affecting the front and / or back-side contact structures. The stacked FETs of the present application can be designed to have different exit metals, and a front / back-side deep through-hole plating structure exhibiting low sheet resistance can be provided.

[0004] In one aspect of the present application, a semiconductor device is provided. In one embodiment, the semiconductor device comprises a first FET having a first gate structure and a pair of first source / drain regions, and a second FET stacked above the first FET having a second gate structure and a pair of second source / drain regions. The semiconductor device further comprises a dielectric pillar located beneath the first FET and directly contacting one of the first source / drain regions of the pair of first source / drain regions, and a dielectric back-gate cap located adjacent to the dielectric pillar. In the present application, the dielectric back-gate cap directly contacts a surface of a first gate electrode of the first gate structure.

[0005] In another aspect of the present application, a process for forming a semiconductor device is provided. In one aspect of the present application, the process includes forming at least one first precursor gate structure comprising a first gate dielectric layer located on a surface of at least one first semiconductor channel material and a first gate placeholder structure located on the first gate dielectric layer, wherein the at least one first precursor gate structure comprises a pair of first source / drain regions, and wherein a dielectric pillar is located under one of the first source / drain regions of the pair of first source / drain regions, and a sacrificial placeholder structure is located under the other first source / drain region of the pair of first source / drain regions.Next, at least one second gate structure is formed on top of the at least one first precursor gate structure, wherein the at least one second gate structure includes a second gate dielectric layer located on the surface of at least one second semiconductor channel material, a second gate electrode located on the second gate dielectric layer, and a pair of second source / drain regions. At least front-side contact structures and a front-side BEOL structure are then formed on the second gate structure. Next, the first gate placeholder structure is replaced from a rear side of the device by a first gate electrode, wherein the replacement transforms the at least one first precursor gate structure into at least one first gate structure, and subsequently, the sacrificial placeholder structure is replaced by a rear-side source / drain contact structure.Next, at least VSS power supplies and VDD power supplies and a rear-side BEOL structure are formed. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a top view of an exemplary semiconductor device layout that can be used according to an embodiment of the present application, wherein the semiconductor device layout includes a plurality of active regions oriented along a first direction and a plurality of functional gate structures oriented in a second direction perpendicular to the first direction; section AA, section BB and section CC are shown in the drawing. Fig. 2A, Fig. 2B and Fig. 2C are cross-sectional views of an exemplary semiconductor structure, corresponding to sections AA, BB and CC respectively, which are shown in Fig. 1 shown, which can be used in the present application, wherein the semiconductor structure comprises a semiconductor substrate, an etch stop layer and at least one first structured material stack comprising alternating first sacrificial semiconductor material layers and first semiconductor channel material layers. Fig. 3A, Fig. 3B and Fig. Figure 3C shows cross-sectional views of the exemplary semiconductor structure shown in Fig. 2A, Fig. 2B or Fig. Figure 2C shows that, after forming at least one first sacrificial gate structure and at least one first gate spacer, nano-structure the at least one first structured material stack to form at least one first nano-stack comprising alternating first sacrificial semiconductor material nanolayers and first semiconductor channel material nanolayers, depression of each first sacrificial semiconductor material nanolayer and formation of a first inner spacer adjacent to each depression of the first sacrificial semiconductor material nanolayer. Fig. 4A, Fig. 4B and Fig. Figures 4C are cross-sectional views of the exemplary semiconductor structure shown in Fig. 3A, Fig. 3B or Fig. 3C is shown after forming a sacrificial placeholder recess within the semiconductor substrate using each first sacrificial gate structure and each first gate spacer as a combined etch mask. Fig. 5A, Fig. 5B and Fig. Figures 5C are cross-sectional views of the exemplary semiconductor structure shown in Fig. 4A, Fig. 4B or Fig. 4C is shown after forming a dielectric column in each sacrificial placeholder recess. Fig. 6A, Fig. 6B and Fig. Figure 6C shows cross-sectional views of the exemplary semiconductor structure shown in Fig. 5A, Fig. 5B or Fig. 5C is shown after the removal of at least one of the dielectric columns. Fig. 7A, Fig. 7B and Fig. Figures 7C are cross-sectional views of the exemplary semiconductor structure shown in Fig. 6A, Fig. 6B or Fig. Figure 6C shows the formation of a sacrificial placeholder structure in the area previously occupied by the removed at least one dielectric column. Fig. 8A, Fig. 8B and Fig. Figures 8C are cross-sectional views of the exemplary semiconductor structure shown in Fig. 7A, Fig. 7B or Fig. 7C is shown after the formation of first source / drain regions and a first front-side interlayer dielectric (ILD) layer. Fig. 9A, Fig. 9B and Fig. Figures 9C are cross-sectional views of the exemplary semiconductor structure shown in Fig. 8A, Fig. 8B or Fig. Figure 8C shows that after removing at least one first sacrificial gate structure and each first sacrificial semiconductor nanolayer, a section of each first semiconductor channel material nanolayer is suspended. Fig. 10A, Fig. 10B and Fig. Figures 10C are cross-sectional views of the exemplary semiconductor structure shown in Fig. 9A, Fig. 9B or Fig. 9C is shown after forming a first gate dielectric layer that is wrapped around the floating section of each first semiconductor channel material nanolayer. Fig. 11A, Fig. 11B and Fig. Figures 11C are cross-sectional views of the exemplary semiconductor structure shown in Fig. 10A, Fig. 10B or Fig. 10C is shown, after forming a first gate placeholder structure on the first gate dielectric layer and forming first gate cut structures, each first gate cut structure comprising a first inner core dielectric material and a first outer dielectric material lining. Fig. 12A, Fig. 12B and Fig. Figures 12C are cross-sectional views of the exemplary semiconductor structure shown in Fig. 11A, Fig. 11B or Fig. Figure 11C shows the removal of the first inner core dielectric material from some of the first gate cut structures and the formation of a first deep through-hole via structure in each area previously occupied by a removed first inner core dielectric material. Fig. 13A, Fig. 13B and Fig. Figures 13C are cross-sectional views of the exemplary semiconductor structure shown in Fig. 12A, Fig. 12B or Fig. 12C is shown after forming a bond dielectric layer and a second material stack of alternating second sacrificial semiconductor material layers and second semiconductor channel material layers. Fig. 14A, Fig. 14B and Fig. Figures 14C are cross-sectional views of the exemplary semiconductor structure shown in Fig. 13A, Fig. 13B or Fig. Figure 13C shows that after forming the second device, which includes structuring the second material stack to form at least one second structured material stack, forming at least one second sacrificial gate structure, forming second gate spacers, structuring the at least one second structured material stack to form at least one second nanolayer stack, forming second inner spacers, forming second source / drain regions, forming a second front-side ILD layer, removing the at least one second sacrificial gate structure and every second sacrificial semiconductor material nanolayer of the at least one second nanolayer stack, forming a second gate dielectric layer and a second gate electrode wound around floating sections of every second semiconductor channel material nanolayer of the at least one second nanolayer stack, and forming second gate cut structures,wherein every second gate-cut structure includes a second inner core dielectric material and a second outer dielectric material lining. Fig. 15A, Fig. 15B and Fig. Figures 15C are cross-sectional views of the exemplary semiconductor structure shown in Fig. 14A, Fig. 14B or Fig. Figure 14C shows that after removing the second inner core dielectric material from some of the second gate cut structures, an underlying first deep via structure is exposed and a second deep via structure is formed that touches the exposed first deep via structure. Fig. 16A, Fig. 16B and Fig. Figure 16C shows cross-sectional views of the exemplary semiconductor structure shown in Fig. 15A, Fig. 15B or Fig. Figure 15C shows, after forming additional front-side ILD layers, the front-side contact structures, metal vias and metal conductors embedded therein, a front-side back-end-of-the-line (BEOL) structure and a support wafer. Fig. 17A, Fig. 17B and Fig. Figures 17C are cross-sectional views of the exemplary semiconductor structure shown in Fig. 16A, Fig. 16B or Fig. 16C is shown after removal of the semiconductor substrate. Fig. 18A, Fig. 18B and Fig. Figure 18C shows cross-sectional views of the exemplary semiconductor structure shown in Fig. 17A, Fig. 17B or Fig. 17C is shown after the removal of the etch stop layer to physically expose a section of the first gate dielectric layer. Fig. 19A, Fig. 19B and Fig. Figures 19C are cross-sectional views of the exemplary semiconductor structure shown in Fig. 18A, Fig. 18B or Fig. 18C is shown after the removal of the physically exposed section of the first gate dielectric layer and the subsequent removal of each first gate placeholder structure. Fig. 20A, Fig. 20B and Fig. Figures 20C are cross-sectional views of the exemplary semiconductor structure shown in Fig. 19A, Fig. 19B or Fig. 19C is shown after forming a first gate electrode and forming a rear gate dielectric cap. Fig. 21A, Fig. 21B and Fig. Figures 21C are cross-sectional views of the exemplary semiconductor structure shown in Fig. 20A, Fig. 20B or Fig. Figure 20C shows the removal of each sacrificial placeholder structure to provide a rear contact opening that physically exposes some of the first source / drain regions. Fig. 22A, Fig. 22B and Fig. Figures 22C are cross-sectional views of the exemplary semiconductor structure shown in Fig. 21A, Fig. 21B or Fig. 21C is shown after lateral deepening of a physically exposed side wall of the first gate electrode and forming an asymmetric internal spacer in the notched region of the first gate electrode. Fig. 23A, Fig. 23B and Fig. Figures 23C are cross-sectional views of the exemplary semiconductor structure shown in Fig. 22A, Fig. 22B or Fig. 22C is shown, after the formation of backside contact structures. Fig. 24A, Fig. 24B and Fig. Figures 24C are cross-sectional views of the exemplary semiconductor structure shown in Fig. 23A, Fig. 23B or Fig. Figure 23C shows the formation of a backside ILD layer containing backside VDD and VSS current structures embedded within it, and a backside BEOL structure. DETAILED DESCRIPTION

[0006] The present application will now be described in more detail with reference to the following discussion and the drawings attached to the present application. It is noted that the drawings of the present application are provided for illustrative purposes only and are not drawn to scale. It is also noted that identical and corresponding elements are designated by the same reference numerals.

[0007] The following description sets out numerous specific details, such as certain structures, components, materials, dimensions, processing steps, and techniques, to provide an understanding of the various embodiments of the present application. However, the person skilled in the art will recognize that the various embodiments of the present application can be carried out without these specific details. In other cases, well-known structures or processing steps have not been described in detail to avoid obscuring the present application.

[0008] It is understood that when an element is described as a layer, area, or substrate located "on" or "above" another element, it may be located directly on top of the other element, or there may be elements in between. Conversely, when an element is described as being "directly on" or "directly above" another element, there are no elements in between. It is also understood that when an element is described as being "under" or "below" another element, it may be located directly under or beneath the other element, or there may be elements in between. Conversely, when an element is described as being "directly under" or "directly beneath" another element, there are no elements in between.

[0009] The present application describes and illustrates a semiconductor device comprising stacked nanofilm transistors. A transistor (or FET) includes a source region, a drain region, a semiconductor channel region located between the source region and the drain region, and a gate structure located above the semiconductor channel region. Together, the source region and the drain region can be referred to as a source / drain region. A nanofilm transistor is a non-planar transistor comprising a vertical stack of spaced semiconductor channel material nanolayers as the semiconductor channel region, with a pair of source / drain regions located at each end of the vertical stack of spaced semiconductor channel material nanolayers. The gate structure comprises a gate dielectric and a gate electrode. The gate structure wraps around each of the spaced semiconductor channel material nanolayers.Stacked nanofilm transistors comprise a second nanofilm transistor stacked on top of a first nanofilm transistor. Although nanofilm transistors are described and illustrated, the present application may provide planar transistors or other non-planar transistors, such as semiconductor nanowire transistors and / or FinFET transistors; each transistor being arranged in a stacked manner, i.e., first and second transistors stacked on top of each other. In the present application, the semiconductor channel region may comprise at least one semiconductor channel material (the channel material may be planar, fin-shaped, nanowire-shaped, or nanofilm-shaped).

[0010] In the present application, the semiconductor device comprises a front and a back. The front of the semiconductor device in the present application comprises a side of the device that includes the stacked transistors, front-side contact structures, and a front-side BEOL structure. The back of the semiconductor device in the present application is the side of the device that faces the front (i.e., faces the bottommost transistor of the stacked transistor configuration). The back comprises a back-side contact structure, VSS and VDD power supplies, and a back-side BEOL structure.

[0011] As stated above and in one aspect of the present application, a semiconductor device is provided. An embodiment of the semiconductor device of the present application is described in the Fig. 24A, Fig. 24B and Fig. 24C shown. The semiconductor device includes a first FET, which comprises a first gate structure (including the first gate dielectric layer 40 and the first gate electrode 80) and a pair of first source / drain regions (i.e., the first source / drain regions 36, which are located in the Fig. 24A-24C) and a second FET stacked above the first FET. In the present application, the first FET can be referred to as a bottom FET, while the second FET can be referred to as an top FET. The second FET has a second gate structure (including the second gate dielectric layer 64 and the second gate electrode 66) and a pair of second source / drain regions (i.e., the second source / drain regions 60 shown in the Fig. 24A-24C). The semiconductor device further includes a dielectric column 28 located below the first FET and one of the first source / drain regions (i.e., the first source / drain region 36 located to the left of the central first gate electrode 80, which is shown in Fig. (as shown in Figure 24A) of the pair of first source / drain regions directly contacts, and a backside dielectric gate cap 82 is located adjacent to the dielectric column 28. In the present application, the backside dielectric gate cap 82 directly contacts a surface of the first gate electrode 80 of the first gate structure. By recessing the first gate electrode 80 from the back side of the wafer and forming the backside gate dielectric cap 82, a short circuit between the backside source / drain contact structure 88 and the first gate electrode 80 can be effectively prevented by effectively forming a symmetrical internal spacer 86 (this cannot be achieved if the gate is not recessed). By forming the dielectric column 28 surrounding a sacrificial placeholder structure 34, backside self-aligned contact formation is enabled.

[0012] In embodiments of the present application and as in the Fig. 24A- Fig. As illustrated in Figure 24C, the dielectric column 28 further comprises a side wall with a first section that directly contacts a side wall of the first gate electrode 80, and a second section that directly contacts a side wall of the rear gate dielectric cap 82. Such a configuration provides electrical insulation for a section of the first gate electrode 80 that extends beneath the lowest first inner spacer 24.

[0013] In embodiments of the present application and as in the Fig. 24A- Fig. As illustrated in Figure 24C, the dielectric column 28 has a height greater than the height of the back-side gate dielectric cap 82. This ensures that the first gate electrode 80 is electrically isolated from the first source / drain region 36 (see, for example, Figure 24C). Fig. 24A; if the dielectric column 28 is lower than the rear gate dielectric cap 82, a short circuit occurs between the first gate electrode 80 and the first source / drain region 36).

[0014] In embodiments of the present application and as in the Fig. 24A- Fig. As illustrated in Figure 24C, the semiconductor device further includes a rear-side source / drain contact structure 88, which connects to the other first source / drain region (i.e., the first source / drain region 36 located to the right of the central first gate electrode 80, which is located in Fig. (as shown in 24A) of the pair of first source / drain regions is touched. This establishes a backside connection to the first source / drain regions 36 of the first FET.

[0015] In embodiments of the present application and as in the Fig. As illustrated in Figures 24A-24C, the semiconductor device further includes an asymmetrical internal spacer 86 that separates the backside source / drain contact structure 88 from the first gate electrode 80; the asymmetrical internal spacer 86 is present only on one side of the first gate electrode 80, where the backside source / drain contact structure 88 is located. The presence of the asymmetrical internal spacer 86 prevents a short circuit that would occur if the backside source / drain contact structure 88 and the first gate electrode 80 were in contact with each other. It should be noted that the dielectric column 28 provides electrical insulation on the other side of the first gate electrode 80.

[0016] In embodiments of the present application and as in the Fig. As illustrated in Figures 24A-24C, the semiconductor device further includes a backside BEOL structure 94 located beneath the first FET and connected to the backside source / drain contact structure 88 by a backside VSS current source (which is shown in the Fig. 24A-24C is designated as VSS; VDD current sources that are in the Fig. 24A-24C, which are labelled VDD, are also shown. The backside VSS power source provides current to the first FET and provides an electrical connection between the first FET and the backside BEOL structure 94.

[0017] In embodiments of the present application and as in the Fig. As illustrated in Figures 24A-24C, the semiconductor device further includes a common front-side source / drain contact structure 74A, which forms the first source / drain region (i.e., the first source / drain region 36 to the left of the central first gate electrode 80, which is located in Fig. 24A) of the pair of first source / drain regions located on the dielectric column 28, and one of the second source / drain regions (i.e., the second source / drain region 60 to the left of the middle second gate electrode 66, which is in Fig. (24A shown) of the pair of second source / drain regions is touched. The common front-side source / drain contact structure 74A establishes an electrical front-side connection of both the first and second FETs.

[0018] In embodiments of the present application and as in the Fig. As illustrated in Figures 24A-24C, the common front-side source / drain contact structure 74A is connected to the front-side BEOL structure 76 by a metal via, V0, and a metal trace, M1. This connection allows the first FET and the second FET to be electrically connected to the front-side BEOL structure 76.

[0019] In embodiments of the present application and as in the Fig. As illustrated in Figures 24A-24C, the semiconductor device further includes a front-side source / drain contact structure 74B, which contacts the other second source / drain region (i.e., the second source / drain region 60 to the right of the middle gate structure) of the pair of second source / drain regions and is connected to the front-side BEOL structure 76 by another metal via (the rightmost V0, which is shown in Figure 24A-24C). Fig. 24A) and at least one other metal conductor (the rightmost M1, which is shown in Fig. 24A is shown). This connection allows the second FET to be electrically connected to the front-side BEOL structure 76.

[0020] In embodiments of the present application and as in the Fig. As illustrated in Figure 24A-24C, the semiconductor device further includes a common front-side first / second-gate electrode contact structure 74C, which contacts both the first gate electrode 80 of the first gate structure and the second gate electrode 66 of the second gate electrode and is connected to the front-side BEOL structure 76 by yet another metal via and yet another metal conductor (see, for example, V0 and M1, which are shown in Figure 24A-24C). Fig. (shown in 24B) is connected. This establishes a combined gate-electrode connection to the front-side BEOL structure 76.

[0021] In embodiments of the present application and as in the Fig. 24A- Fig. As illustrated in Figure 24C, the second gate structure includes the second gate electrode 66. In embodiments, the second gate electrode 66 consists of a different work-discharge metal than the first gate electrode 80. This aspect demonstrates that the present application provides stacked FETs with different work-discharge metals, which is difficult to achieve using conventional stacked FET processes.

[0022] In embodiments of the present application and as in the Fig. 24A- Fig. As illustrated in Figure 24C, the first gate structure (i.e., the first gate dielectric layer 40 and the first gate electrode 80) is wound around a section of at least one first semiconductor channel material nanolayer 16 of a first nanolayer stack, and the second gate structure (i.e., the second gate dielectric layer 64 and the second gate electrode 66) is wound around a section of at least one second semiconductor channel material nanolayer 54 of a second nanolayer stack. Nanolayer devices offer a larger effective device width (Weff) per active footprint and improved performance compared to FinFETs with a less complex photolithography strategy utilizing extreme ultraviolet (EUV) lithography.Nanolayer devices offer a better power / energy operating point due to superior electrostatic control in devices where the gate surrounds the channel on all sides, compared to only three sides in FinFETs. Therefore, nanolayers should be a fundamental building block structure for stacked transistors in future-generation technology.

[0023] In embodiments of the present application and as in the Fig. 24A- Fig. As illustrated in Figure 24C, the first FET is spaced from the second FET by the bonding dielectric layer 50. The bonding dielectric layer 50 allows for separation of the stacked FETs and enables the use of different exit metals for the gate electrodes of the stacked FETs.

[0024] In embodiments of the present application and as in the Fig. 24A- Fig. As illustrated in Figure 24C, the semiconductor device can further include a first gate-cutting structure (combination of elements 44 / 46, defined below) located adjacent to the first FET, and a second gate-cutting structure (combination of elements 68 / 70, defined below) located adjacent to the second FET. Gate-cutting structures are used to cut the gate structures between different active device regions and to provide insulation between the cut gates. In the present application, a second gate-cutting structure is stacked on top of a first gate-cutting structure.

[0025] In embodiments of the present application and as in the Fig. 24A- Fig. As illustrated in Figure 24C, the first gate-cut structure includes a first outer dielectric material liner 44 that encases the first inner core dielectric material 46, and the second gate-cut structure includes a second outer dielectric material liner 68 that encases the second inner core dielectric material 70. Gate-cut structures composed of such two-layer dielectric materials are more robust and provide greater electrical insulation than gate-cut structures composed of a single dielectric material.

[0026] In embodiments of the present application and as in the Fig. 24A- Fig. As illustrated in Figure 24C, the first gate structure and the second gate structure are spaced apart by the bonding dielectric layer 50.

[0027] In embodiments of the present application and as in the Fig. 24A- Fig. As illustrated in Figure 24C, the semiconductor device further includes a front-side / back-side via structure (combination of the first via structure 48 and the second via structure 72) which has a first end electrically connected to one of the second source / drain regions 60 of the pair of second source / drain regions through the front-side second gate-source / drain contact structure 74D, and a second end electrically connected to the back-side BEOL structure 94 through a VDD current source (see, for example, Figure 24C). Fig. 24C). This connection electrically connects the second FET to the backside BEOL structure 94.

[0028] In embodiments of the present application and as in the Fig. 24A- Fig. As illustrated in Figure 24C, the front / back via structure (combination of the first via structure 48 and the second via structure 72) has an upper via section encased in the second outer dielectric material liner 68, a lower section encased in the first outer dielectric material liner 44, and a middle section encased in the bonding dielectric layer 50 located between the first and second FETs. This dielectric material encasement electrically isolates the front / back via structure from a short circuit with other elements of the stacked FETs.

[0029] In embodiments of the present application and as in the Fig. 24A- Fig. As illustrated in Figure 24C, the first FET and the second FET are present in a first active area, and wherein at least one other second FET, stacked above at least one other first FET, is located in a second active area spaced apart from the first active area, wherein a first source / drain region 36 of the at least one other first FET (see the far right of Figure 24C) is located in a second active area spaced apart from the first active area. Fig. 24C) electrically with the front-side BEOL structure 76 by a combination of the back-side source / drain contact structure 88, the back-side metal connector 90, a front-side / back-side deep via structure, a metal via and a metal conductor (i.e. the rightmost V0 / M1 combination shown in Fig. 24C is shown) connected. This provides an electrical connection of at least one other first FET to the front-side BEOL structure 76.

[0030] In embodiments of the present application and as in Fig. As illustrated in Figure 24C, the rear metal connector 90 directly contacts a side wall of a lower section of the front / rear through-hole plating structure and a side wall of the rear source / drain contact structure.

[0031] In another aspect of the present application, as in the Fig. 2A- Fig. As described in 24C, a process is provided which includes forming at least one first precursor gate structure comprising a first gate dielectric layer located on a surface of at least one first semiconductor channel material, and a first gate placeholder structure on the first gate dielectric layer, wherein the at least one first precursor gate structure comprises a pair of first source / drain regions, and wherein a dielectric column is located under one of the first source / drain regions of the pair of first source / drain regions, and a sacrificial placeholder structure is located under the other first source / drain region of the pair of first source / drain regions. Fig. 2A- Fig. 12C form the at least one first precursor gate structure. Next, at least one second gate structure is formed above the at least one first precursor gate structure, the at least one second gate structure comprising a second gate dielectric layer located on a surface of at least one second semiconductor channel material, a second gate electrode located on the second gate dielectric layer, and a pair of second source / drain regions; see the Fig. 13A- Fig. 14C. At least front-side contact structures and a front-side BEOL structure are then formed on the second gate structure; see the Fig. 15A- Fig. 16C. Next, the first gate placeholder structure from a back side of the device is replaced by a first gate electrode, the replacement converting the at least one first precursor gate structure into at least one first gate structure, and then the sacrificial placeholder structure is replaced by a back-side source / drain contact structure. These steps are described in the Fig. 17A- Fig. 23C is shown. Next, at least VSS power supplies and VDD power supplies and a rear-side BEOL structure are formed; see the Fig. 24A- Fig. 24C. Stacked FETs are formed by this process. The process of the present application optimizes the thermal budget without negatively affecting the front and / or back contact structures.

[0032] These and other aspects of the present application will now be discussed with reference to Fig. 1 described in more detail. In particular illustrated Fig. 1 An exemplary semiconductor device layout that can be used according to an embodiment of the present application. The semiconductor device layout includes a plurality of active regions, AA, oriented along a first direction, and a plurality of functional gate structures, e.g., GS1, GS2, and GS3, oriented in a second direction perpendicular to the first direction; section AA, section BB, and section CC are shown in the drawing. As an example, three functional gate structures, GS1, GS2, and GS3, and two active regions, AA1 and AA2, are shown. Section AA passes through a longitudinal direction of one of the active regions, e.g., AA1, and through each of GS1, GS2, and GS3; section BB passes through a longitudinal direction of one of the gate structures, e.g., GS2, and through two active regions, AA1 and AA2; and section CC is located between two adjacent gate structures, e.g.,GS2 and GS3, and runs through source / drain (S / D) regions of the two adjacent gate structures and spans two active areas, AA1 and AA2. In the present application, each of the . Fig. 2A, Fig. 3A, ..., Fig. 24A through cut AA, while each of the Fig. 2B, Fig. 3B, ... Fig. 24B through cut BB and each of the Fig. 2C, Fig. 3C, ... Fig. 24C runs through section CC.

[0033] It will now be referred to as Fig. 2A, Fig. 2B and Fig. Reference is made to Section 2C, which illustrates an exemplary semiconductor structure that can be used in the present application. The illustrated semiconductor structure comprises a semiconductor substrate 10, an etch stop layer 12, and at least one first structured material stack (two of which are shown as an example in the Fig. 2B and Fig. 2C are shown). Each first structured material stack includes alternating first sacrificial semiconductor material layers 14L and first semiconductor channel material layers 16L.

[0034] The semiconductor substrate 10 consists of a first semiconductor material. The term "semiconductor material" is used throughout this application to refer to a material with semiconducting properties. Examples of first semiconductor materials that may be used in the present application for providing the semiconductor substrate 10 include, but are not limited to, silicon (Si), a silicon-germanium alloy (SiGe alloy), a silicon-germanium carbide alloy (SiGeC alloy), germanium (Ge), III / V compound semiconductors, or II / VI compound semiconductors. The semiconductor substrate 10 typically consists of one of the above first semiconductor materials. In one example, the semiconductor substrate 10 consists of Si.

[0035] The etch stop layer 12 of the in the Fig. 2A- Fig. The exemplary semiconductor structure illustrated in 2C can consist of a dielectric material, such as silicon dioxide and / or boron nitride.

[0036] As mentioned above, each first structured material stack comprises alternating first sacrificial semiconductor material layers 14L and first semiconductor channel material layers 16L. In some embodiments and as described in the Fig. 2A- Fig. As illustrated in Figure 2C, there is an equal number of first sacrificial semiconductor material layers 14L and first semiconductor channel material layers 16L. That is, each material stack can contain a number n of first sacrificial semiconductor material layers 14L and a number n of first semiconductor channel material layers 16L, where n is an integer starting from one. As an example, each first structured material stack contains three first sacrificial semiconductor material layers 14L and three first semiconductor channel material layers 16L.

[0037] Each first sacrificial semiconductor material layer 14L consists of a second semiconductor material, while each first semiconductor channel material layer 16L consists of a third semiconductor material that differs in composition from the second semiconductor material. The second semiconductor material provided by each first sacrificial semiconductor material layer 14L and the third semiconductor material provided by each first semiconductor channel material layer 16L can include any of the semiconductor materials mentioned above for the semiconductor substrate 10. In one example, each first sacrificial semiconductor material layer 14L consists of a silicon-germanium alloy with a germanium content of 20 to 40 atomic percent, and each first semiconductor channel material layer 16L consists of silicon. Other combinations of semiconductor materials are possible, as long as the second semiconductor material differs in composition from the third semiconductor material.In some embodiments, the third semiconductor material provided by each first semiconductor channel material layer 16L can provide high channel mobility for n-type field-effect transistor (FET) devices. In other embodiments, the third semiconductor material provided by each first semiconductor channel material layer 16L can provide high channel mobility for p-type FET devices.

[0038] Each first sacrificial semiconductor material layer 14L can have a first thickness, and each first semiconductor channel material layer 16L can have a second thickness. In the present application, the first thickness can be equal to, greater than, or less than the second thickness. The first sacrificial semiconductor material layers 14L and the first semiconductor channel material layers 16L have the same widths at this point in the process of the present application.

[0039] The in the Fig. 2A- Fig. The exemplary semiconductor structure shown in section 2C can be formed using techniques well known to those skilled in the art. In one example, the structure shown in the Fig. 2A- Fig. The exemplary semiconductor structure shown in Figure 2C is formed by depositing the etch stop layer 12 onto the semiconductor substrate 10, depositing a first material stack of alternating first sacrificial semiconductor material layers 14L and first semiconductor channel material layers 16L onto the etch stop layer 12, and then structuring the deposited first material stack. The deposition of the etch stop layer 12 can involve chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). The deposition of the first material stack can involve CVD, PECVD, or epitaxial growth.Throughout this application, the terms “epitaxial growth” or “epitaxial growth” mean the growth of a semiconductor material on a growth surface of another semiconductor material, wherein the semiconductor material being grown has the same crystalline properties as the growth surface of the other semiconductor material. In an epitaxial deposition process, the chemical reactants supplied by the source gases are controlled, and the system parameters are adjusted so that the deposition atoms arrive at the growth surface of the other semiconductor material with sufficient energy to move on the growth surface and align themselves with the crystal arrangement of the atoms on the growth surface. Examples of various epitaxial growth process devices that may be used in this application include, for example,Rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). The temperature for epitaxial deposition is typically in the range of 550 °C to 900 °C. Although a higher temperature typically results in faster deposition, this faster deposition can lead to crystal defects and film cracking.

[0040] Structuring can involve lithography and etching (dry etching and / or wet chemical etching). Dry etching can include, for example, reactive ion etching (RIE), ion beam etching (IBE), and plasma etching. Wet chemical etching involves the use of a suitable chemical etchant that exhibits a high etch rate for one material compared to at least one other material.

[0041] With reference to the Fig. 3A, Fig. 3B and Fig. 3C is the one in the Fig. 2A, Fig. 2B or Fig. Figure 2C illustrates the exemplary semiconductor structure, after forming at least one first sacrificial gate structure 18 and at least one first gate spacer 22, nanolayer structuring of the at least one first structured material stack to form at least one first nanolayer stack (of which three are shown as an example in Figure 2C). Fig. (as shown in Figure 3A), comprising alternating first sacrificial semiconductor material nanolayers 14 and first semiconductor channel material nanolayers 16, recessing each first sacrificial semiconductor material nanolayer 14, and forming a first inner spacer 24 adjacent to each recessed first sacrificial semiconductor material nanolayer 14. In some embodiments, a first sacrificial hard mask 20 may be located on a surface of the first sacrificial gate structure 18. In other embodiments, the first sacrificial hard mask 20 may be omitted.

[0042] The at least one first sacrificial gate structure 18 includes at least one sacrificial gate material. In some embodiments, the at least one first sacrificial gate structure 18 may also include a sacrificial gate dielectric material. In such embodiments, the sacrificial gate dielectric material would be located beneath the sacrificial gate material. The optional sacrificial gate dielectric material may consist of a dielectric material, such as silicon dioxide. The sacrificial gate material may consist, for example, of polysilicon, amorphous silicon, amorphous silicon germanium, or amorphous germanium. The first sacrificial hard mask 20 consists of a hard mask material, such as silicon nitride.

[0043] The at least one first sacrificial gate structure 18, which includes the optional first sacrificial hard mask 20, can be formed by depositing the optional sacrificial gate dielectric material, depositing the sacrificial gate material, and, if the first sacrificial hard mask 20 is present, depositing the hard mask material, followed by subjecting the material layers thus deposited to a structuring process. The structuring includes lithography and etching, as defined above. Each first sacrificial gate structure 18 is arranged overlapping over a section of the at least one first structured material stack. The term "arranged overlapping" means that one material layer is located on a top surface and opposite sidewall surfaces of another material layer.

[0044] The first gate spacer 22, which is present along a side wall of the at least one first sacrificial gate structure 18 and, if present, the first sacrificial hard mask 20, can consist of a dielectric spacer material, including but not limited to silicon dioxide, SiN, SiBCN, SiOCN, or SiOC. The first gate spacer 22 can be formed by deposition of the dielectric spacer material followed by spacer etching.

[0045] Next, the first structured material stack undergoes nanolayer structuring to form at least one initial nanolayer stack (of which three are shown as an example in Fig. (as shown in Figure 3A). The at least one first nanolayer stack comprises alternating first sacrificial semiconductor material nanolayers 14 (i.e., remaining unetched portions of each first sacrificial semiconductor material layer 14L) and first semiconductor channel material nanolayers 16 (i.e., remaining unetched portions of each first semiconductor channel material layer 16L). The nanolayer structuring utilizes the at least one first sacrificial gate structure 18, the optional first sacrificial hard mask 20, and the first gate spacer 22, which is present along at least the sidewalls of the at least one first sacrificial gate structure 18, as a combined etch mask. Etching, such as RIE, is then used to remove portions of the first structured material stack that are not protected by the combined etch mask.Immediately after nanolayer structuring, the first sacrificial semiconductor material nanolayers 14 and the first semiconductor channel material nanolayers 16 have the same width.

[0046] Each first sacrificial semiconductor material nanolayer 14 is then recessed using a lateral etching process that removes an end section of each first sacrificial semiconductor material nanolayer 14. After recession, the width along cut AA, which is in Fig. As shown in Figure 3A, each first sacrificial semiconductor material nanolayer 14 is smaller than the original width of each first sacrificial semiconductor material nanolayer 14. Lateral etching forms depressions within the at least one first nanolayer stack. The first inner spacer 24 is then formed in each depression. The first inner spacer 24 consists of one of the dielectric spacer materials mentioned above for the first gate spacer 22. The dielectric spacer material providing each first inner spacer 24 can be the same or different in composition from the dielectric spacer material from which the first gate spacer is formed.

[0047] With reference to Fig. 4A, Fig. 4B and Fig. 4C is the exemplary semiconductor structure used in Fig. 3A, Fig. 3B or Fig. Figure 3C illustrates the formation of a sacrificial placeholder recess 26 within the semiconductor substrate 10 using the combined etching mask and etching process described above. The term "sacrificial placeholder recess" is used in this application to define an etched area of ​​the semiconductor substrate 10 in which a sacrificial structure is subsequently formed. In the illustrated embodiment, two sacrificial placeholder recesses 26 are formed, as shown in Figure 3C. Fig. Figure 4A shows that the etching removes portions of the etch stop layer 12 and portions of the semiconductor substrate 10 that are not protected by the combined etch mask. The etching does not extend completely through the semiconductor substrate 10. Instead, the etching stops on a subsurface of the semiconductor substrate 10. The term "subsurface" is used throughout this application to refer to a surface of a material layer that lies between a top surface of the material layer and a bottom surface of the material layer. The etching that provides the sacrificial placeholder recess 26 may involve a timed RIE process.

[0048] With reference to Fig. 5A, Fig. 5B and Fig. 5C is the exemplary semiconductor structure used in Fig. 4A, Fig. 4B or Fig. Figure 4C illustrates the formation of a dielectric column 28 in each sacrificial placeholder recess 26. The dielectric column 28 can be formed by first depositing a dielectric material and then subjecting the deposited dielectric material to recess etching. The dielectric column 28 consists of a dielectric material that differs in composition from the etch stop layer 12 and the dielectric spacer material(s) of which the first gate spacer 22 and the first inner spacer 24 are made. Examples of dielectric materials that can be used in providing the dielectric column 28 include SiC and SiOC.The dielectric column 28 has a bottom surface that directly contacts the underside of the semiconductor substrate 10, and a top surface that may be coplanar with a top surface of the etch stop layer 12, but does not necessarily have to be.

[0049] With reference to Fig. 6A, Fig. 6B and Fig. 6C is the exemplary semiconductor structure used in Fig. 5A, Fig. 5B or Fig. Figure 5C illustrates the removal of at least one of the dielectric columns 28; not all dielectric columns 28 are removed during this step of the present application. In the illustrated embodiment, the dielectric column 28 in the source / drain regions between GS2 and GS3, which is shown in Figure 5C, is removed. Fig. 1 are illustrated. The removal of the dielectric column involves the formation of a structured organic planarization layer (OPL) 30, which has openings on the exemplary structure shown in Fig. 5A- Fig. Figure 5C shows that the structured OPL 30 can be formed by depositing an OPL material followed by lithography and etching. After forming the structured OPL 30, a further etching process, such as RIE, is used to remove dielectric columns 28 that are not protected by the structured OPL 30. Openings 32 are formed as shown in Figure 5C. Fig. 6A and Fig. 6C shown. It should be noted that in the Fig. In the source / drain region shown in Figure 6C, this etching removed sections of the dielectric column 28 that is present in this area of ​​the structure.

[0050] With reference to Fig. 7A, Fig. 7B and Fig. 7C is the exemplary semiconductor structure used in Fig. 6A, Fig. 6B or Fig. Figure 6C illustrates the formation of a sacrificial placeholder structure 34 in the area previously occupied by the removed at least one dielectric column 28 (i.e., within the openings 32). The sacrificial placeholder structure 34 can be formed by first depositing a sacrificial material and then subjecting the deposited sacrificial material to a recess etching process. The sacrificial placeholder structure 34 consists of a sacrificial material that differs in composition from the etch stop layer 12 and each dielectric spacer material from which the first gate spacer 22 and the first inner spacer 24 are formed, as well as from the dielectric material from which the dielectric column 28 is formed. Examples of sacrificial materials that can be used as the sacrificial placeholder structure 34 include SiGe and AlO. x and TiO xThe sacrificial placeholder structure 34 has a bottom surface that directly contacts the bottom surface of the semiconductor substrate 10, and a top surface that may be coplanar with a top surface of the etch stop layer 12, but does not necessarily have to be.

[0051] After the sacrificial placeholder structure 34 is formed, the structured OPL 30 is removed from the structure. The structured OPL 30 can be removed using any material removal process that selectively removes the OPL material from which the structured OPL 30 is formed.

[0052] With reference to Fig. 8A, Fig. 8B and Fig. 8C is the exemplary semiconductor structure used in Fig. 7A, Fig. 7B or Fig. Figure 7C illustrates the formation of first source / drain regions 36 and a first front-side interlayer dielectric (ILD) layer 38. In the present application, each first sacrificial gate structure 18 includes a pair of first source / drain regions 36; this is illustrated by the middle first sacrificial gate structure 18 shown in Fig. 8A is shown.

[0053] The first source / drain regions 36 are typically formed by an epitaxial growth process, as defined above. The first source / drain regions 36 extend outwards from a sidewall of each first semiconductor channel material nanolayer 16. Within each pair of first source / drain regions 36 (and as described in Fig. (As illustrated in Figure 8A), one of the first source / drain regions 36 is located on an upper surface of the dielectric column 28, while another of the first source / drain regions 36 is located on an upper surface of the sacrificial placeholder structure 34. Each of the first source / drain regions 36 consists of a fourth semiconductor material and a first dopant. As used herein, a "source / drain" region can be either a source region or a drain region, depending on the subsequent wiring and the application of voltages during transistor operation. The fourth semiconductor material provided by each first source / drain region 36 is one of the semiconductor materials mentioned above for the semiconductor substrate 10.The fourth semiconductor material providing the first source / drain regions 36 can be identical in composition to, or different in composition from, the third semiconductor material from which each first semiconductor channel material nanolayer 16 is formed. However, the fourth semiconductor material from which each first source / drain region 36 is formed differs in composition from the second semiconductor material from which each first sacrificial semiconductor material nanolayer 14 is formed. The first dopant present in the first source / drain regions 36 can be either a p-type or an n-type dopant. The term "p-type" refers to the addition of impurities to an intrinsic semiconductor that creates deficiencies in valence electrons. In a silicon-containing semiconductor material, examples of p-type dopants include, i.e.,Examples of impurities include boron, aluminum, gallium, phosphorus, and indium, but these are not limited to them. "N-type" refers to the addition of impurities that contribute free electrons to an intrinsic semiconductor. In a silicon-containing semiconductor material, examples of n-type dopants (i.e., impurities) include antimony, arsenic, and phosphorus, but these are not limited to them. In one example, each first source / drain region can have a dopant concentration of 4 × 10⁻⁶. 20 atoms / cm² 3 up to 3 × 10 21 atoms / cm² 3 exhibit.

[0054] The first front-side ILD layer 38 consists of a dielectric material that includes, for example, silicon oxide, silicon nitride, undoped silicate glass (USG), fluorosilicate glass (FSG), boron phosphosilicate glass (BPSG), a low-k spin-on dielectric layer, a low-k chemical vapor deposition (CVD) dielectric layer, or any combination thereof. The term "low k," as used throughout this application, refers to a dielectric material having a dielectric constant of less than 4.0 (all dielectric constants mentioned herein are relative to a vacuum unless otherwise stated). The first front-side ILD layer 38 may be formed by a deposition process involving CVD, PECVD, or spin-on coating, but is not limited to such processes. A planarization process, such as chemical-mechanical polishing (CMP), follows the deposition process.The planarization process removes the first sacrificial hard mask 20 (if present) and an upper section of each first gate spacer 22. The at least one first sacrificial gate structure 18 is physically exposed after this planarization process. Note that the first front-side ILD layer 38 is formed adjacent to and on top of each first source / drain region 36.

[0055] With reference to Fig. 9A, Fig. 9B and Fig. 9C is the exemplary semiconductor structure used in Fig. 8A, Fig. 8B or Fig. Figure 8C illustrates the process after removing the at least one first sacrificial gate structure 18 and each first sacrificial semiconductor nanolayer 14 to suspend a portion of each first semiconductor channel material nanolayer 16. The physically exposed at least one first sacrificial gate structure 18 is removed using any material removal process, such as etching, that is selective in removing the at least one first sacrificial gate structure 18. Removing the at least one first sacrificial gate structure 18 exposes an underlying first nanolayer material stack. Next, each first sacrificial semiconductor material nanolayer 14 is removed using any material removal process, such as etching, that is selective in removing the first sacrificial semiconductor material nanolayers 14.

[0056] With reference to Fig. 10A, Fig. 10B and Fig. 10C is the exemplary semiconductor structure used in Fig. 9A, Fig. 9B or Fig. Figure 9C illustrates the formation of a first gate dielectric layer 40, which is wound around the floating portion of each first semiconductor channel material nanolayer 16. The first gate dielectric layer 40 is also formed along the side walls of the first gate spacer 22 and the first inner spacer 24, as well as on the first gate spacer 22 and the first front-side ILD layer 38. The first gate dielectric layer 40 consists of a first gate dielectric material having a dielectric constant greater than 4.0. Illustrative examples of first gate dielectric materials that can be used in providing the first gate dielectric layer 40 include hafnium dioxide (HfO2), hafnium silicon dioxide (HfSiO), hafnium silicon oxynitride (HfSiO), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium dioxide (ZrO2), zirconium silicon oxide (ZrSiO4), and zirconium silicon oxynitride (ZrSiO). x N y), tantalum oxide (TaO x Titanium dioxide (TiO₂), barium strontium titanium dioxide (BaO₆SrTi₂), barium titanium dioxide (BaTiO₃), strontium titanium dioxide (SrTiO₃), yttrium oxide (Yb₂O₃), aluminum oxide (Al₂O₃), lead scandium tantalum oxide (Pb(Sc,Ta)O₃), and / or lead zinc niobite (Pb(Zn,Nb)O) are, but not limited to, the first gate dielectric material. The first gate dielectric material can also contain dopants such as lanthanum (La), aluminum (Al), and / or magnesium (Mg). The first gate dielectric layer 40 can be formed by a deposition process such as CVD, PECVD, or ALD.

[0057] In some embodiments of the present application, a dielectric annealing step can now be performed. In other embodiments of the present application, the dielectric annealing step can be omitted. When performed, the dielectric annealing reduces the defects present in the first gate dielectric layer 40. The dielectric annealing step can be performed in an environment such as helium, argon, and / or neon. The dielectric annealing step can be performed at a temperature of 700 °C to 1000 °C.

[0058] With reference to Fig. 11A, Fig. 11B and Fig. 11C is the exemplary semiconductor structure used in Fig. 10A, Fig. 10B or Fig. Figure 10C illustrates the formation of a first gate placeholder structure 42 on the first gate dielectric layer 40 and the formation of first gate cut structures, each of which includes a first inner core dielectric material 46 and a first outer dielectric material lining 44. The first gate placeholder structure 42 can consist of one of the sacrificial gate materials mentioned above and can also include a diffusion barrier lining, such as TaN or TiN. The first gate placeholder structure 42 can be formed by deposition followed by a planarization process. The planarization process removes any sacrificial gate material, diffusion barrier material, and the first gate dielectric layer 40, which is located on the first front-side ILD layer 38.At this point in the present application, first precursor gate structures are formed, comprising the first gate dielectric layer 40 and the first gate placeholder structure 42.

[0059] First gate-cut structures are then formed, extending upwards from a subsurface of the semiconductor substrate 10. These first gate-cut structures have a top surface that is typically coplanar with the top surface of each of the first gate placeholder structures 42 and the first front-side ILD layer 38. The first gate-cut structures are formed by first creating gate-cut grooves by lithography and etching. A first outer dielectric material layer, consisting of a first gate-cut lining dielectric material, is first formed in each gate-cut groove by a first deposition process, such as CVD, PECVD, or ALD. The first outer dielectric material layer thus deposited lines the sidewalls of each gate-cut groove and is located on top of the first gate placeholder structure 42 and the first front-side ILD layer 38.A first inner core dielectric is then formed on the first outer dielectric material layer deposited in this way by a second deposition process, such as CVD, PECVD, or ALD. A planarization process is then used to remove any first inner core dielectric and first gate-cut lining dielectric material present outside the gate-cut grooves. The remaining first outer dielectric material layer present in each gate-cut groove provides the first outer dielectric material lining 44, while the remaining first inner core dielectric present in each gate-cut groove provides the first inner core dielectric material 46.

[0060] The first gate-cut lining dielectric material consists of a dielectric material that differs in composition from the first inner core dielectric. In one embodiment, the first gate-cut lining dielectric material, which provides the first outer dielectric material lining 44, consists of silicon nitride, while the first inner core dielectric, which provides the first inner core dielectric material 46, consists of silicon dioxide. Other dielectric materials, such as SiOCN or SiBCN, can be used in providing the first outer dielectric material lining 44 and the first inner core dielectric material 46, as long as the dielectric used in forming the first outer dielectric material lining 44 and the first inner core dielectric material 46 differs in composition and thus exhibits different etch rates.

[0061] With reference to Fig. 12A, Fig. 12B and Fig. 12C is the exemplary semiconductor structure used in Fig. 11A, Fig. 11B or Fig. Figure 11C illustrates the process after removing the first inner core dielectric material 46 from some of the first gate-cut structures and forming a first deep via structure 48 in each area previously occupied by a removed first inner core dielectric material 46. At this point in the present application, the first outer dielectric material lining 44 is located along the side wall and the lower surface of the first deep via structure 48.

[0062] Removing the first inner core dielectric material 46 from some of the first gate-cut structures involves forming a structured mask (not shown) on the exemplary structure described in Fig. 11A- Fig. Figure 11C shows that the structured mask has openings that physically include some of the first gate-cut structures. With this structured mask in place, an etching process is used that selectively removes the first inner core dielectric material 46 relative to the first outer dielectric material lining 44. First deep via holes are formed. The structured mask is then typically removed from the structure. The first deep via structure 48 is then formed into each of the first deep via holes using a metallization process that involves filling (including deposition and planarization) each of the first deep via holes with at least one contact conductor material. The contact conductor material may, for example, be a conductive metal such as W, Cu, Al, Co, Ru, Mo, Os, Ir, Rh, or an alloy thereof.

[0063] With reference to Fig. 13A, Fig. 13B and Fig. 13C is the exemplary semiconductor structure used in Fig. 12A, Fig. 12B or Fig. Figure 12C illustrates the formation of a bonding dielectric layer 50 and a second material stack consisting of alternating second sacrificial semiconductor material layers 52L and second semiconductor channel material layers 54L. The bonding dielectric layer 50 typically consists of a bonding dielectric oxide, such as silicon dioxide. In the present application, the bonding dielectric layer 50 is used to electrically isolate each stacked FET from the others. As mentioned above, the second material stack comprises alternating second sacrificial semiconductor material layers 52L and second semiconductor channel material layers 54L. In some embodiments, and as shown in the Fig. 13A- Fig. Figure 13C illustrates that there is an equal number of second sacrificial semiconductor material layers 52L and second semiconductor channel material layers 54L. That is, the second material stack can contain a number m of second sacrificial semiconductor material layers 52L and a number m of second semiconductor channel material layers 54L, where m is an integer starting from one. As an example, every second material stack contains three second sacrificial semiconductor material layers 52L and three second semiconductor channel material layers 54L. It is noted that 'm' can be less than, equal to, or greater than 'n'.

[0064] Every second sacrificial semiconductor material layer 52L consists of a fifth semiconductor material, while every second semiconductor channel material layer 54L consists of a sixth semiconductor material that differs in composition from the fifth semiconductor material. It is noted that the fifth semiconductor material from which every second sacrificial semiconductor material layer 52L is formed may be the same or different in composition from the second semiconductor material from which every first sacrificial semiconductor material layer 14L is formed. It is also noted that the sixth semiconductor material from which every second semiconductor channel material layer 54L is formed may be the same or different in composition from the third semiconductor material from which every first semiconductor channel material layer 16L is formed.The fifth semiconductor material, from which every second sacrificial semiconductor material layer 52L is formed, and the sixth semiconductor material, from which every second semiconductor channel material layer 54L is formed, can comprise any of the semiconductor materials mentioned above for the semiconductor substrate 10. In one example, every second sacrificial semiconductor material layer 52L is a silicon-germanium alloy with a germanium content of 20 to 40 atomic percent, and every second semiconductor channel material layer 54L is silicon. Other combinations of semiconductor materials are possible, as long as the fifth semiconductor material differs in composition from the sixth semiconductor material. In some embodiments, the sixth semiconductor material, from which every second semiconductor channel material layer 54L is formed, can provide high channel mobility for n-type FET devices.In other embodiments, the sixth semiconductor material, from which every second semiconductor channel material layer 54L is formed, can provide high channel mobility for p-type FET devices. In embodiments, the aforementioned first semiconductor channel material layers 16L provide optimized mobility for a first-conductivity-type FET, while the second channel material layers 54L provide optimized mobility for a second-conductivity-type FET, the first-conductivity-type FET differing in conductivity from the second-conductivity-type FET.

[0065] Every second sacrificial semiconductor material layer 52L can have a third thickness, and every second semiconductor channel material layer 54L can have a fourth thickness. In the present application, the third thickness can be equal to, greater than, or less than the fourth thickness.

[0066] The in the Fig. 13A- Fig. The exemplary semiconductor structure shown in Figure 13C can be formed using techniques well known to those skilled in the art. In one example, the bonding dielectric layer 50 can be applied to the structure shown in the Fig. 12A- Fig. The structure shown in Figure 12C can be formed using a deposition process such as CVD, PECVD, ALD, or PVD. The second material stack can then be deposited onto the bond dielectric layer 50 thus deposited. In other embodiments, a wafer bonding process can be employed. The wafer bonding process involves depositing the bond dielectric layer 50 onto a surface of a handling substrate (not shown) and then forming the second material stack on the bond dielectric layer 50. After the formation of the second material stack, the handling substrate can be removed from the structure containing the bond dielectric layer 50 and the second material stack, and then the bond dielectric layer 50 attached to the second material stack is brought into close contact with the structure shown in the figure. Fig. 12A- Fig. 12C brought the structure shown. In some embodiments, wafer bonding can involve heating to a temperature sufficient to establish a bond between the bond oxide layer 50 and the structure shown in the Fig. 12A- Fig. to cause the structure shown in 12C.

[0067] With reference to Fig. 14A, Fig. 14B and Fig. 14C is the exemplary semiconductor structure used in Fig. 13A, Fig. 13B or Fig. Figure 13C illustrates the formation of the second device. Forming the second device involves structuring the second material stack to form at least one second structured material stack. The structuring may include lithography and etching. Next, at least one second sacrificial gate structure (not shown in the drawings) may be formed, arranged over a section of the at least one structured second material stack. The at least one second sacrificial gate structure includes materials as mentioned above for the at least one first sacrificial gate structure 18, and the at least one second sacrificial gate structure may be formed using the process mentioned above for forming the at least one first sacrificial gate structure 18. An optional second sacrificial hard mask, not shown, may also be formed.The optional second sacrificial hard mask consists of one of the hard mask materials mentioned above for the first sacrificial hard mask 20.

[0068] Next, second gate spacers 56 are formed. The second gate spacers 56 consist of one of the gate dielectric spacer materials mentioned above for the first gate spacers 22. The second gate spacers 56 can be formed by depositing the gate spacer dielectric material followed by spacer etching.

[0069] The at least one second structured material stack is structured to form at least one second nanolayer stack. This structuring step, which involves etching, such as RIE, uses the at least one sacrificial gate structure, if the second sacrificial hard mask is present, and the second gate spacers 56 as a combined etch mask. The at least one second nanolayer stack comprises alternating second sacrificial semiconductor material nanolayers (remaining, i.e., unetched portions of the second sacrificial semiconductor material layers 52L) and second semiconductor channel material nanolayers 54 (remaining, i.e., unetched portions of the second semiconductor channel material layers 54L). The second sacrificial semiconductor material nanolayers are in Fig. 14A- Fig. 14C is not shown because it is subsequently removed from the structure.

[0070] Second inner spacers 58 are then formed using the same technique as described above for forming the first inner spacers 22. In particular, forming the second inner spacer involves lateral etching, i.e., removing, every second sacrificial semiconductor material nanolayer, and then filling the gaps created by this etching with a dielectric spacer material, as defined above. The filling involves deposition and spacer etching.

[0071] Next, second source / drain regions 60 are formed by an epitaxial growth process, as defined above. The second source / drain regions 60 extend outward from a sidewall of each second semiconductor channel material nanolayer 54. Each second source / drain region 60 is located on a surface of the bonding dielectric layer 50. Each of the second source / drain regions 60 consists of a seventh semiconductor material and a second dopant. The seventh semiconductor material providing each second source / drain region 60 is one of the semiconductor materials mentioned above for the semiconductor substrate 10. The seventh semiconductor material from which the second source / drain regions 60 are formed may be the same or different in composition from the sixth semiconductor material from which each second semiconductor channel material nanolayer 54 is formed.The seventh semiconductor material, from which every second source / drain region 60 is formed, differs in composition from the fifth semiconductor material, from which every second sacrificial semiconductor nanolayer is formed. The second dopant present in the second source / drain regions 60 can be of the same conductivity type or a different conductivity type than the first dopant present in the first source / drain regions 36. In the present application, it is possible to form stacked FETs of the same conductivity type or stacked FETs of different conductivity types.

[0072] The second front-side ILD layer 62 is then formed laterally adjacent to and on each of the second source / drain regions 60; the second front-side ILD layer 62 also contacts a surface of the bond dielectric layer 50. The second front-side ILD layer 62 consists of one of the dielectric materials mentioned above for the first front-side ILD layer 38. The second front-side ILD layer 62 can be formed by deposition followed by a planarization process. The planarization process can remove the optional second sacrificial hard mask and an upper portion of the second gate spacers 56.

[0073] After forming the second front-side layer 62, the at least one second sacrificial gate structure is removed using a material removal process that is selective in removing the at least one second sacrificial gate structure. This step exposes the at least one second nanolayer stack. Next, every second sacrificial semiconductor material nanolayer of the at least one second nanolayer stack is removed using a material removal process that is selective in removing the second sacrificial semiconductor material nanolayers. Sections of every second semiconductor channel material nanolayer 54 are now physically exposed.

[0074] A second gate structure, comprising the second gate dielectric layer 64 and the second gate electrode 66, is then formed by wrapping around the floating sections of each second semiconductor channel material nanolayer 54 of the at least one second nanolayer stack; a first gate electrode of a first gate structure is formed later in the process of the present application. The second gate dielectric layer 60 consists of a second gate dielectric material having a dielectric constant greater than 4.0. Illustrative examples of second gate dielectric materials that can be used in providing the second gate dielectric layer 60 include hafnium dioxide (HfO2), hafnium silicon dioxide (HfSiO), hafnium silicon oxynitride (HfSiO), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium dioxide (ZrO2), zirconium silicon oxide (ZrSiO4), and zirconium silicon oxynitride (ZrSiO). x N y ), tantalum oxide (TaO xTitanium dioxide (TiO₂), barium strontium titanium dioxide (BaO₆SrTi₂), barium titanium dioxide (BaTiO₃), strontium titanium dioxide (SrTiO₃), yttrium oxide (Yb₂O₃), aluminum oxide (Al₂O₃), lead scandium tantalum oxide (Pb(Sc,Ta)O₃), and / or lead zinc niobite (Pb(Zn,Nb)O) are, but not limited to, the following materials. The first gate dielectric material may also contain dopants such as lanthanum (La), aluminum (Al), and / or magnesium (Mg). The second gate dielectric material may be identical or different in composition from the first gate dielectric material.

[0075] The second gate electrode 66 consists of a second gate electrode material. The second gate electrode material can include a work-effect metal (WFM) and optionally a conductive metal. The WFM can be used to adjust the transistor's threshold voltage to a desired value. In some embodiments, the WFM can be selected to effect an n-type threshold voltage shift. "n-type threshold voltage shift," as used herein, means a shift of the effective work function of the metal-containing work-effect material toward a conduction band of silicon in a silicon-containing material. In one embodiment, the work function of the n-type work-effect metal is in the range of 4.1 eV to 4.3 eV.Examples of such materials that can effect an n-type threshold voltage shift include, but are not limited to, titanium aluminum, titanium aluminum carbide, tantalum nitride, titanium nitride, hafnium nitride, hafnium silicon, or combinations thereof. In other embodiments, the WFM can be selected to effect a p-type threshold voltage shift. In one embodiment, the p-type work function of the work function is in the range of 4.9 eV to 5.2 eV. As used herein, "threshold voltage" is the lowest achievable gate voltage that turns on a semiconductor device, such as a transistor, by making the device's channel conductive. The term "p-type threshold voltage shift," as used herein, signifies a shift in the effective work function of the metal-containing work function toward a valence band of silicon in the silicon-containing material.Examples of such materials that can induce a p-type threshold voltage shift include titanium nitride and tantalum carbide, hafnium carbide, and combinations thereof. The optional conductive metal can include aluminum (Al), tungsten (W), or cobalt (Co). The second gate structure, comprising the second gate dielectric layer 64 and the second gate electrode 66, can be formed by depositing the second gate dielectric material and the second gate electrode material, followed by a planarization process.

[0076] In some embodiments of the present application, a dielectric annealing step, as defined above, can now be performed after the formation of the second gate dielectric material to reduce defects present in the second gate dielectric layer 64. If no dielectric annealing has been performed on the first gate dielectric layer 40, the dielectric annealing used here can also reduce the defects in the first gate dielectric layer 40.

[0077] Next, second gate-cut structures are formed using the same materials and techniques mentioned above for forming the first gate structures. The second gate-cut structures include a second inner core dielectric material 70 and a second outer dielectric material lining 68. The second inner core dielectric material 70 includes one of the dielectric materials mentioned above for the first inner core dielectric material 46, and the second outer dielectric material lining 68 includes one of the dielectric materials mentioned above for the first outer dielectric material lining 44.

[0078] With reference to Fig. 15A, Fig. 15B and Fig. 15C is the exemplary semiconductor structure used in Fig. 14A, Fig. 14B or Fig. Figure 14C illustrates the process of exposing an underlying first deep via structure 48 after removing the second inner core dielectric material 70 from some of the second gate cut structures and forming a second deep via structure 72 that contacts the exposed first deep via structure 48. Together, the first deep via structure contacting the second deep via structure 72 provides a front-side / back-side deep via structure.

[0079] Removing the second inner core dielectric material 70 from some of the second gate cut structures involves forming a structured mask (not shown) on the exemplary structure shown in Fig. 14A- Fig. Figure 14C shows that the structured mask has openings that physically intersect some of the second-gate cut structures. With this structured mask in place, an etch is used that selectively removes the second inner-core dielectric material 70 relative to the second outer dielectric material liner 68. Another etch, stopping on a surface of the first deep via structure, is then used to break through the horizontal section of the second outer dielectric material liner 68 and the bond dielectric layer 50. Second deep via openings are formed. The structured mask is then typically removed from the structure.The second deep via structure 72 is then formed in each of the second deep via holes using a metallization process that involves filling (including deposition and planarization) each of the second deep via holes with at least one contact conductor material. The contact conductor material can, for example, be a conductive metal such as W, Cu, Al, Co, Ru, Mo, Os, Ir, Rh, or an alloy thereof. The contact conductor material used in providing the second deep via structure 72 can be the same or different in composition from the contact conductor material used in providing the first deep via structure 72. Typically, the second deep via structure 72 and the first deep via structure 48 consist of a contact conductor material of the same composition.

[0080] With reference to Fig. 16A, Fig. 16B and Fig. 16C is the exemplary semiconductor structure used in Fig. 15A, Fig. 15B or Fig. Figure 15C illustrates, after the formation of additional front-side ILD layers, the front-side contact structures, metal vias and metal conductors embedded therein, a front-side BEOL structure 76, and a support wafer 78. The front-side contact structures that are formed include a common front-side first / second source / drain contact structure 74A, a front-side source / drain contact structure 74B, a common front-side first / second gate electrode contact structure 74C, and a front-side second gate source / drain contact structure 74D.

[0081] In the present application, the additional front-side ILD layers and the first front-side ILD layer 38 provide a front-side dielectric layer 63. The additional front-side ILD layers can consist of dielectric materials that are identical or different in composition from the dielectric material provided by the first front-side ILD layer 38. Typically, the dielectric materials providing the additional ILD layers are identical in composition to the dielectric material providing the first front-side ILD layer 38, so that no material interface would exist within the front-side dielectric layer 63 between the additional front-side ILD layers and the first front-side ILD layer 38; such an embodiment is shown in the drawings of the present application.The additional front-side ILD layers can be formed using one of the deposition processes mentioned above in connection with the formation of the first front-side ILD layer 38.

[0082] Front-side contact structures, including the common front-side first / second source / drain contact structure 74A, the front-side source / drain contact structure 74B, the common front-side first / second gate electrode contact structure 74C, the front-side second gate source / drain contact structure 74D, and the front-side second gate electrode contact structure (not illustrated in the drawings), metal vias V0, and metal conductors M1 are formed using metallization processes. In the present application, a lower section of the front-side dielectric layer 63 is formed, and then the front-side contact structures are formed using a first metallization process. An upper section of the front-side dielectric layer 63 is then formed, and subsequently the V0 and metal conductors M1 can be formed using a second metallization process.Each of the first and second metallization processes involves forming openings within the front-side dielectric layer 63, followed by filling (including deposition and planarization) each of the openings with at least one contact conductor material. The contact conductor material that can be used to provide the front-side contact structures V0 and M1 includes, for example, a silicide lining such as Ni, Pt, or NiPt; an adhesive metal lining such as TiN; and conductive metals such as W, Cu, Al, Co, Ru, Mo, Os, Ir, Rh, or an alloy thereof. The front-side contact structures V0 and M1 can also include one or more contact linings (not shown). In one or more embodiments, the contact lining (not shown) can include a diffusion barrier material.Examples of diffusion barrier materials include, but are not limited to, Ti, Ta, Ni, Co, Pt, W, Ru, TiN, TaN, WN, WC, an alloy thereof, or a stack thereof such as Ti / TiN and Ti / WC. In one or more embodiments where a contact lining is present, the contact lining (not shown) may comprise a silicide lining, such as Ti, Ni, NiPt, etc., and a diffusion barrier material as defined above.

[0083] Next, the front-side BEOL structure 76 is formed on the top surface of the front-side dielectric layer 63, so that the metal wires M1 are in contact with the front-side BEOL structure 76. The front-side BEOL structure 76 can include one or more interleaving dielectric material layers (including one of the dielectric materials mentioned above for the first front-side ILD layer 38) containing front-side metal wires (the metal wires can be made of any electrically conductive metal or metal alloy) embedded therein.

[0084] The carrier wafer 78 can contain one of the semiconductor materials mentioned above for the semiconductor substrate 10. After the formation of the front-side BEOL structure 76, the carrier wafer 78 is bonded to the front-side BEOL structure 76.

[0085] With reference to Fig. 17A, Fig. 17B and Fig. 17C is the exemplary semiconductor structure used in Fig. 16A, Fig. 16B or Fig. Figure 16C illustrates the process after removal of the semiconductor substrate 10. Removing the semiconductor substrate 10 typically involves rotating the wafer 180° to physically expose one side of the semiconductor substrate 10. This rotation step is not shown in the drawings of the present application for clarity. This rotation step enables backside processing of the exemplary structure. Backside processing is performed on one side of a wafer opposite the side containing the stacked transistors. The rotation of the structure can be performed manually or using a mechanical means, such as a robotic arm. Removing the physically exposed semiconductor substrate 10 physically exposes the etch stop layer 12.The removal of the semiconductor substrate 10 can be carried out using a material removal process that is selective in removing the first semiconductor material from which the semiconductor substrate 10 is formed.

[0086] With reference to Fig. 18A, Fig. 18B and Fig. 18C is the exemplary semiconductor structure used in Fig. 17A, Fig. 17B or Fig. Figure 17C illustrates the removal of the etch stop layer 12 to physically expose a section of the first gate dielectric layer 40. The removal of the etch stop layer 12 involves a material removal process that is selective in its removal.

[0087] With reference to Fig. 19A, Fig. 19B and Fig. 19C is the exemplary semiconductor structure used in Fig. 18A, Fig. 18B or Fig. Figure 18C illustrates the removal of the physically exposed portion of the first gate dielectric layer 40 and the subsequent removal of each first gate placeholder structure 42. The physically exposed portion of the first gate dielectric layer 40 can be removed using a material removal process that is selective in removing the first gate dielectric material from which the first gate dielectric layer 40 is formed. This material removal process physically exposes the first gate placeholder structures 42. The physically exposed first gate placeholder structures 42 can be removed using a material removal process that is selective in removing the first gate placeholder structures 42.

[0088] With reference to Fig. 20A, Fig. 20B and Fig. 20C is the exemplary semiconductor structure used in Fig. 19A, Fig. 19B or Fig. Figure 19C illustrates the formation of a first gate electrode 80, the depression of the first gate electrode 80, and the formation of a back-side gate dielectric cap 82. The first gate electrode 80 wraps around each first semiconductor channel material nanolayer 16 and is present on the first gate dielectric layer 40. The first gate electrode 80 can be formed by deposition followed by depression etching. Together, the first gate electrode 80 and the first gate dielectric layer 40 provide a first gate structure of a first FET.

[0089] The first gate electrode 80 consists of a first gate electrode material. The first gate electrode material may comprise one of the second gate electrode materials mentioned above. In some embodiments of the present application, the first gate electrode material may be identical in composition to the second gate electrode material. In other embodiments, the first gate electrode material differs in composition from the second gate electrode material. For example, the first gate electrode material providing the first gate electrode 80 may consist of an n-type WFM, while the second gate electrode material providing the second gate electrode 66 may consist of an n-type WFM.

[0090] The dielectric back-gate cap 82 consists of a dielectric material that differs in composition from the dielectric material providing the dielectric column 28 and the dielectric material providing the first outer dielectric material lining 44. Examples of dielectric materials that can be used in providing the dielectric back-gate cap 82 include silicon dioxide, SiOCH, SiC, silicon nitride, and silicon oxynitride. The dielectric back-gate cap 82 can be formed by deposition followed by a planarization process. At this stage of the present application, each of the dielectric column 28, the dielectric back-gate cap 82, the first outer dielectric material lining 44, and the sacrificial placeholder structure 34 has a bottom surface that is coplanar with each other, as shown in Fig. 20A shown.

[0091] With reference to Fig. 21A, Fig. 21B and Fig. 21C is the exemplary semiconductor structure used in Fig. 20A, Fig. 20B or Fig. Figure 20C illustrates the removal of each sacrificial placeholder structure 34 to provide a rear contact opening 84, which physically exposes some of the first source / drain regions 36. The sacrificial placeholder structure 34 can be removed using a material removal process, such as etching, which is selective in removing the sacrificial placeholder structure 34 from the structure. Other first source / drain regions 36 that contact the dielectric column 28 are not physically exposed by this step of the present application.

[0092] With reference to Fig. 22A, Fig. 22B and Fig. 22C is the exemplary semiconductor structure used in Fig. 21A, Fig. 21B or Fig. Figure 21C illustrates the process of laterally recessing a physically exposed sidewall of the first gate electrode 80 and forming an asymmetrical inner spacer 86 in the recessed region of the first gate electrode 80. The lateral recessing involves an etching process that is selective in removing the first gate electrode material from which the first gate electrode 80 is formed. The asymmetrical inner spacer 86 can consist of one of the dielectric spacer materials mentioned above for the first gate spacers 22. In some embodiments of the present application, the dielectric spacer material from which the asymmetrical inner spacer 86 is formed is identical in composition to the dielectric spacer material from which the first inner spacer 24 is formed.In other embodiments of the present application, the dielectric spacer material from which the asymmetric inner spacer 86 is formed differs in composition from the dielectric spacer material from which the first inner spacer 24 is formed. The asymmetric inner spacer 86 has a surface that directly contacts a bottommost first inner spacer 24, and the asymmetric inner spacer 86 has at least one outermost side wall that is vertically aligned with the outermost side wall of each first inner spacer 24. As in . Fig. As shown in Figure 22A, the first gate electrode 80 of the middle first FET has one side wall that directly touches a side wall of the dielectric column 28, and another side wall that directly touches a side wall of the asymmetric inner spacer 86.

[0093] With reference to Fig. 23A, Fig. 23B and Fig. 23C is the exemplary semiconductor structure used in Fig. 22A, Fig. 22B or Fig. Figure 22C illustrates the formation of backside contact structures. The backside contact structures include at least one backside first source / drain gate structure 88; a backside first gate electrode contact structure (not shown) may also be formed. The backside first source / drain gate structure 88 is formed in each of the aforementioned backside contact openings 84.

[0094] The backside contact structures are formed using a metallization process (deposition and planarization). The backside contact structures, which include the backside first source / drain gate structure 88, consist of one of the contact conductor materials mentioned above to provide the frontside contact structures V0 and M1. The planarization process used in forming the backside contact structures removes a horizontal surface of the first outer dielectric material lining 44. This removal of the first outer dielectric material lining 44 physically exposes the first inner core dielectric material 46 of the first gate cut structure and the first deep via structure 48.

[0095] With reference to Fig. 24A, Fig. 24B and Fig. 24C is the exemplary semiconductor structure used in Fig. 23A, Fig. 23B or Fig.Figure 23C illustrates the formation of a backside ILD layer 92, which contains embedded backside VDD and VSS current structures, and a backside BEOL structure 94. The backside metal connector 90 is also formed. The backside ILD layer 92 consists of one of the dielectric materials mentioned above for the first frontside ILD layer 38. The backside ILD layer 92 can be formed using one of the deposition processes mentioned above for forming the first frontside ILD layer 38. The backside VDD and VSS current structures are formed using a metallization process (deposition and planarization). The backside VDD and VSS current structures consist of one of the contact conductor materials mentioned above for providing the frontside contact structures V0 and M1.

[0096] The backside metal connector 90 consists of one of the contact conductor materials mentioned above for providing the frontside contact structures V0 and M1. The backside metal connector 90 can be formed by removing a section of the dielectric column 28 that separates one of the backside source / drain contact structures 88 from the frontside / backside deep via structure (combination of the first deep via structure 48 and the second deep via structure 72), and then filling the gap created by removing a section of the dielectric column 28 with one of the contact conductor materials mentioned above. The filling process can involve deposition and planarization.The rear source / drain contact structure 88 is now connected to the front / rear deep via structure (combination of the first deep via structure 48 and the second deep via structure 72) by means of the rear metal connector 90.

[0097] The backside BEOL structure 94 is formed in contact with the backside ILD layer 92, which contains the embedded backside VDD and VSS current structures. The backside BEOL structure 94 may include one or more interleaving dielectric material layers (including one of the dielectric materials mentioned above for the first frontside ILD layer 38) containing backside metal wires (the metal wires may be made of any electrically conductive metal or metal alloy) embedded therein.

[0098] Although the present application has been shown and described in particular with regard to preferred embodiments thereof, the person skilled in the art will understand that the foregoing and other changes to shapes and details can be made without departing from the spirit and scope of the present application. It is therefore intended that the present application is not limited to the exact shapes and details described and illustrated, but falls within the scope of the accompanying claims.

Claims

[1] Semiconductor device comprising: a first field-effect transistor (FET) with a first gate structure and a pair of first source / drain regions; a second FET stacked on top of the first FET, featuring a second gate structure and a pair of second source / drain regions; a dielectric column located beneath the first FET and directly touching one of the first source / drain regions of the pair of first source / drain regions; and a dielectric backside gate cap located next to the dielectric column, wherein the dielectric backside gate cap directly touches a surface of a first gate electrode of the first gate structure. [2] Semiconductor device according to claim 1, wherein the dielectric column further comprises a side wall with a first section directly contacting a side wall of the first gate electrode and a second section directly contacting a side wall of the rear gate dielectric cap. [3] Semiconductor device according to claim 1, wherein the dielectric column has a height greater than the height of the rear gate dielectric cap. [4] Semiconductor device according to claim 1, further comprising a rear-side source / drain contact structure that contacts the other first source / drain region of the pair of first source / drain regions. [5] Semiconductor device according to claim 4, further comprising an asymmetrical internal spacer that separates the rear source / drain contact structure from the first gate electrode. [6] Semiconductor device according to claim 4, further comprising a back-end-of-the-line (BEOL) structure located below the first FET and connected to the back-end source / drain contact structure by a back-end VSS current source. [7] Semiconductor device according to claim 4, further comprising a common front-side source / drain contact structure that contacts the first source / drain region of the pair of first source / drain regions located on the dielectric column and one of the second source / drain regions of the pair of second source / drain regions. [8] Semiconductor device according to claim 7, wherein the common front-side source / drain contact structure is connected to a front-side back-end-of-the-line (BEOL) structure by a metal via and a metal conductor. [9] Semiconductor device according to claim 8, further comprising a front-side source / drain contact structure which contacts the other second source / drain region of the pair of second source / drain regions and is connected to the front-side BEOL structure by a metal via and at least one metal conductor. [10] Semiconductor device according to claim 8, further comprising a common front-side first / second gate electrode contact structure which contacts both the first gate electrode of the first gate structure and a second gate electrode of the second gate electrode and is connected to the front-side BEOL structure by yet another metal via and yet another metal conductor. [11] Semiconductor device according to claim 1, wherein the second gate structure comprises a second gate electrode and wherein the second gate electrode consists of a work-off metal that differs in composition from the first gate electrode. [12] Semiconductor device according to claim 1, wherein the first gate structure is wound around a section of at least one first semiconductor channel material nanolayer of a first nanolayer stack and the second gate structure is wound around a section of at least one second semiconductor channel material nanolayer of a second nanolayer stack. [13] Semiconductor device according to claim 1, wherein the first FET is spaced apart from the second FET by a bonding dielectric layer. [14] Semiconductor device according to claim 1, further comprising a first gate cut structure located next to the first FET and a second gate cut structure located next to the second FET. [15] Semiconductor device according to claim 14, wherein the first gate cut structure comprises a first outer dielectric material lining enclosing a first inner core dielectric material, and wherein the second gate cut structure comprises a second outer dielectric material lining enclosing a second inner core dielectric material. [16] Semiconductor device according to claim 14, wherein the first gate structure and the second gate structure are spaced apart by a bonding dielectric layer. [17] Semiconductor device according to claim 1, further comprising a front-side / back-side deep through-hole plating structure comprising a first end electrically connected to one of the second source / drain regions of the pair of source / drain regions by a front-side second gate-source / drain contact structure, and a second end electrically connected to a back-side BEOL structure by a VDD current source. [18] Semiconductor device according to claim 17, wherein the front / back via structure comprises an upper via section enclosed in a second outer dielectric material lining, a lower section enclosed in a first outer dielectric material lining, and a middle section enclosed in a bonding dielectric layer located between the first FET and the second FET. [19] Semiconductor device according to claim 1, wherein the first FET and the second FET are located in a first active region and wherein at least one other second FET, stacked above at least one other first FET, is located in a second active region spaced apart from the first active region, wherein a source / drain region of the at least one other first FET is electrically connected to a front-side BEOL structure by a combination of a back-side source / drain contact structure, a back-side metal connector, a front-side / back-side via structure, a metal via and a metal conductor. [20] Semiconductor device according to claim 19, wherein the backside metal connector directly contacts a side wall of a lower section of the front / backside via structure and a side wall of the backside source / drain contact structure. [21] Method for forming a stacked field-effect transistor (FET) device, the method comprising: Forming at least one first precursor gate structure comprising a first gate dielectric layer located on a surface of at least one first semiconductor channel material and a first gate placeholder structure on the first gate dielectric layer, wherein the at least one first precursor gate structure includes a pair of first source / drain regions and wherein a dielectric column is located under one of the first source / drain regions of the pair of first source / drain regions and a sacrificial placeholder structure is located under the other first source / drain region of the pair of first source / drain regions; Forming at least one second gate structure over the at least one first precursor gate structure, wherein the at least one second gate structure comprises a second gate dielectric layer located on a surface of at least one second semiconductor channel material, a second gate electrode located on the second gate dielectric layer, and a pair of second source / drain regions; forming at least front-side contact structures and a front-side BEOL structure on the second gate structure; Replacing the first gate placeholder structure from a rear side of the device with a first gate electrode, wherein the replacement transforms the at least one first precursor gate structure into at least one first gate structure; Replacing the victim placeholder structure with a backside source / drain contact structure; and Formation of at least VSS power supplies and VDD power supplies and a rear-side BEOL structure. [22] Method according to claim 21, further comprising forming at least one first gate cut structure in the first gate placeholder structure, wherein the at least one first gate cut structure comprises a first outer dielectric material lining enclosing a first inner core dielectric material. [23] Method according to claim 22, further comprising replacing the first inner core dielectric material of at least one of the first gate section structures with a conductor contact material to form a first deep via structure. [24] Method according to claim 23, further comprising forming at least one second gate section structure in the second gate electrode, wherein the at least one second gate section structure comprises a second outer dielectric material lining that encloses a second inner core dielectric material. [25] The method of claim 24, further comprising replacing the second inner core dielectric material of at least one of the second gate section structures with a conductor contact material to form a second deep via structure, wherein the second deep via structure directly connects the first deep via structure and the first and the second deep via structure together provide a front / back deep via structure.

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