COORDINATING A CHANGE IN THE PERFORMANCE STATE OF A SYSTEM BASE CHIP WITH A CHANGE IN THE PERFORMANCE STATE OF A PHY-TRANSCEIVER IMPLEMENTED BY THE SYSTEM BASE CHIP

Abstract

A method includes: providing a system base chip that supports at least two power states: a sleep state and a wake state; monitoring for power state information via a hardware interface and a communication interface, wherein the hardware interface enables communication between a physical layer (PHY) transceiver implemented on the system base chip and a PHY controller implemented on a microcontroller, and wherein the communication interface enables communication between the system base chip and the microcontroller; and coordinating a change in the power state of the system base chip at least partially based on receiving power state information via the hardware interface and the communication interface.

Description

CROSS-REFERENCE TO RELATED REGISTRATION

[0001] This application claims the benefit under 35 USC §119(e) of the preliminary US patent application serial number 63 / 512,229, filed on July 6, 2023, the disclosure of which is hereby incorporated herein by reference in its entirety. AREA

[0002] Examples generally refer to system-based chips and system-based chips that implement physical layer (PHY) devices. BACKGROUND

[0003] A system base chip (SBC) is an integrated circuit (IC) that combines several functions required for the operation of electronic systems. ICs and SBCs are used in a variety of operating contexts. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] To make it easy to identify the discussion of a specific element or action, the principal number(s) in a reference sign refer to the figure number in which that element is first introduced. Fig. Figure 1 is a block diagram of a system that implements, among other things, a 10SPE PHY, according to one or more examples. Fig. Figure 2 is a block diagram that represents a system base chip section according to one or more examples. Fig. Figure 3 is a state diagram representing transitions between wake and sleep states managed by an FSM of an SBC, according to one or more examples. Fig. Figure 4 is a state diagram that represents stepwise performance state changes from wake to sleep and from sleep to wake managed by the FSM of an SBC, according to one or more examples. Fig. Figure 5 illustrates an exemplary process for changing a performance state of a system base chip implementing a PHY transceiver of a PHY with split-PHY architecture, according to one or more examples. Fig. Figure 6 is a flowchart that represents a process for coordinating a change in the power state of an SBC implementing a PHY transceiver with a change in the power state of the PHY transceiver according to one or more examples. Fig. Figure 7 illustrates an exemplary process for changing a performance state of a system base chip, a PHY transceiver implemented by the system base chip, or both, according to one or more examples. Fig. Figure 8 is a block diagram of a switching logic that can be used in some examples to implement various functions, operations, actions, processes, or procedures disclosed herein. FORM(S) OF EXECUTION OF THE INVENTION

[0005] The following detailed description refers to the accompanying drawings, which form part of this document and illustrate specific examples of embodiments in which the present disclosure can be put into practice. These examples are described in sufficient detail to enable those skilled in the art to implement the present disclosure in practice. However, other examples may also be used, and structural, material, and procedural modifications may be made without altering the scope of protection of the disclosure.

[0006] The illustrations shown herein are not intended to be actual views of any particular process, system, structure, or device, but are merely idealized representations used to describe the examples in this disclosure. The drawings shown herein are not necessarily to scale. Similar structures or components in the various drawings may retain the same or similar numbering for the convenience of the reader; however, the similarity in numbering does not imply that the structures or components are necessarily identical in size, composition, configuration, or any other characteristic.

[0007] The following description may include examples to enable those skilled in the art to put the disclosed examples into practice. The use of the terms "exemplary", "as an example", and "for instance" means that the accompanying description is explanatory, and although the scope of protection of the disclosure is intended to include the examples and their legal equivalents, the use of these terms is not intended to limit the scope of protection of any example or of this disclosure to the specified components, steps, features, functions, or the like.

[0008] It is readily apparent that the components of the examples described here in general terms and illustrated in the drawing can be arranged and designed in a multitude of different configurations. Therefore, the following description of various examples is not intended to limit the scope of protection of this disclosure, but is merely representative of various examples. While the different aspects of the examples may be depicted in drawings, these drawings are not necessarily drawn to scale unless expressly stated otherwise.

[0009] Furthermore, the specific implementations shown and described are only examples and should not be interpreted as the only way to implement the present disclosure unless otherwise stated herein. Elements, circuits, and functions may be shown in block diagram form to avoid obscuring the present disclosure with unnecessary details. Conversely, the specific implementations shown and described are only examples and should not be interpreted as the only way to implement the present disclosure unless otherwise stated herein. Additionally, block definitions and the distribution of logic between different blocks are examples of a specific implementation. It is readily apparent to those skilled in the art that the present disclosure can be implemented in practice through numerous other distribution solutions.Details concerning timing considerations and the like have been largely omitted, insofar as such details are not necessary for a complete understanding of the present disclosure and are within the capabilities of those skilled in the art.

[0010] It is evident to those skilled in the art that information and signals can be represented using a variety of different technologies and techniques. Some drawings may illustrate signals as a single signal for the sake of clarity in representation and description. It is also evident to those skilled in the art that the signal can represent a bus of signals, where the bus can have a variety of bit widths, and the present disclosure can be implemented with any number of data signals, including a single data signal.

[0011] The various illustrative logic blocks, modules, and circuits described in connection with the examples disclosed herein may be implemented or carried out using a general-purpose processor, a special-purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein.A general-purpose processor (which may herein also be referred to as a host processor or simply a host) may be a microprocessor, but alternatively it may be any conventional processor, control unit, microcontroller, or state machine. A processor may also be implemented as a combination of data processing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. A general-purpose computer including a processor is considered a special-purpose computer, while the general-purpose computer executes computational instructions (e.g., software code) relating to examples of the present disclosure.

[0012] The examples can be described as a process represented as a program flowchart, flow diagram, structure diagram, or block diagram. Although a flowchart can describe steps of operation as a sequential process, many of these operations can be performed in a different order, in parallel, or substantially simultaneously. Furthermore, the order of the steps can be changed. A process can correspond, without limitation, to a method, thread, function, procedure, subroutine, or subprogram. Moreover, the methods disclosed herein can be implemented in hardware, software, or both. When implemented in software, the functions can be stored or transmitted as one or more instructions or as code on computer-readable media.Computer-readable media include both computer storage media and communication media, including all media that support the transfer of a computer program from one location to another.

[0013] Any reference to an element herein using a label such as "first," "second," etc., does not restrict the set or order of such elements unless such restriction is expressly stated. Rather, these labels herein may be used as a convenient method for distinguishing between two or more elements or instances of an element. Thus, a reference to a first and a second element does not mean that only two elements may be inserted there, or that the first element must in any way precede the second element. Furthermore, unless otherwise stated, a set of elements may comprise one or more elements.

[0014] In the sense used herein, the term "essentially" means, with respect to a given parameter, property, or condition, and includes, to an extent understandable to a person skilled in the art, that the given parameter, property, or condition is fulfilled with a small degree of variance, such as within acceptable manufacturing tolerances. For example, depending on the specific parameter, property, or condition that is essentially fulfilled, the parameter, property, or condition may be fulfilled to at least 90%, at least 95%, or even at least 99%.

[0015] As used herein, relational terms such as “above”, “below”, “on”, “underlying”, “above”, “below” are used without restriction for the sake of clarity and expediency in understanding the revelation and the accompanying drawings, and are not associated with or dependent on any particular preference, orientation or order, unless the context clearly indicates otherwise.

[0016] In this description, the term "coupled" and derivatives thereof may be used to indicate that two elements work together or interact with each other. When an element is described as "coupled" to another element, the elements may be in direct physical or electrical contact, or intermediate elements or layers may be present. Conversely, when an element is described as "directly coupled" to another element, no intermediate elements or layers are present. The term "connected" may be used interchangeably with the term "coupled" in this description and has the same meaning unless explicitly stated otherwise or the context would indicate otherwise to a person skilled in the art.

[0017] As used herein, the terms “activate”, “deactivate” and derivatives thereof, when used in relation to a pen, mean to activate or deactivate a signal associated with the pen (e.g., a signal specifically assigned to the pen, or a signal to which the pen is specifically assigned, without limitation).

[0018] A system base chip (SBC) is an integrated circuit (IC) that combines several functions for the operation of an electronic system. An SBC typically integrates various different functions onto a single chip.Examples of such functions include: power management functions such as voltage regulators, circuit breakers, or protection switching logic, without limitation, for managing the power supply to the system; communication interfaces such as CAN (Controller Area Network), LIN (Local Interconnect Network), SPI (Serial Peripheral Interface), or I2C (Inter-Integrated Circuit); embedded systems, such as state machines or microprocessors, that control and coordinate tasks; analog functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), temperature sensors, and other signal conditioning switching logic; and diagnostic and safety functions, such as monitoring and reporting voltage levels, temperature, or fault conditions, without limitation.

[0019] Single-board computers (SBCs) are found in a variety of operating contexts, including automotive and industrial applications. A non-restrictive example of an automotive application for SBCs is in 10SPE networks, i.e., 10 Mbps Single Pair Ethernet networks, also known as "10BASE-T1S networks." 10SPE is a network technology specified in IEEE 802.3, clauses 147 and 148. 10SPE is designed to provide collision-free, deterministic transmission in a multidrop network.

[0020] In some cases, a transceiver (xcvr) and a controller of a 10SPE physical layer device (PHY) may reside on different dies, as a non-restrictive example, so that the respective dies can undergo different processing conditions. Such an architecture is referred to herein as a "split-PHY" architecture. In the split-PHY architecture, the digital blocks of a PHY controller that are susceptible to damage during high-voltage, high-temperature processes (high-voltage, high-temperature processes are also referred to herein as "high-voltage temperature processes") may reside on a first die that does not undergo high-voltage temperature processes. Analog and digital blocks of a PHY transceiver that are not susceptible to damage during high-voltage temperature processes, or that require such high-voltage temperature processes, may reside on a second die that does undergo such processes.

[0021] The 10BASE-T1S transceiver interface standard, currently under specification development by Technology Committee 14 of the OPEN Alliance (hereinafter referred to as the “TC14 Standard”), defines a 3-pin hardware interface for communication between a PHY transceiver and a PHY controller.

[0022] In a PHY with a split-PHY architecture, the 10SPE controller functions are implemented in a microcontroller (MCU), and the 10SPE transceiver functions are implemented in an SBC. In addition to 10SPE transceiver functions, the SBC can implement non-transceiver functions, i.e., electronic system functions such as power management, watchdog circuitry, monitors, sensors, and general-purpose input / output (GPIO), without restriction. Thus, in 10SPE, the responsibilities of an SBC can, without limitation, include communication transceiver, low-voltage power, observability / control of a high-voltage domain, and functional safety mechanisms for the MCU to achieve a safe state.

[0023] Furthermore, TC14 describes the low-power (sleep-wake) behavior of the PHY transceiver for partial networking. Partial networking refers to a feature that enables selective power management and communication capabilities within a network. Partial networking allows certain network nodes to or devices, to enter a low-power or sleep state while maintaining basic communication functionality. In Ethernet networks, partial networking can be used to optimize power consumption (e.g., to reduce it without restriction), particularly in automotive applications. or industrial applications. Enabling selected devices to enter a low-power or sleep state can reduce overall power consumption, extend battery life, or improve energy efficiency, without limitation.

[0024] An SBC can implement a 10SPE PHY transceiver and can also manage other functions such as power supply and watchdog for the MCU, the PHY controller, and other devices (such as sensors, without limitation). The drivers (e.g., firmware, configurable state machines, logic circuits, or hardware, without limitation) that implement a PHY transceiver and instructions are typically separate (e.g., different data paths, without limitation) and asynchronous from the drivers that implement other SBC functions.

[0025] In the case of power state management (e.g., of the PHY transceiver and the MCU, without limitation), a lack of coordination can lead to inefficiencies, increased power consumption, and operational deviations such as unintended wake-ups or errors in correctly entering low-power states.

[0026] Accordingly, managing coordinated power states and / or coordinated power state transitions in split-PHY architectures, where the PHY transceiver and the PHY controller are implemented separately on different components (e.g., on an SBC and an MCU, without limitation), is a challenge.

[0027] One or more examples generally refer to an SBC that is able to coordinate changes in the performance state of the SBC with changes in the performance state of a PHY transceiver implemented by the SBC.

[0028] In one or more examples, the SBC implements at least part of the hardware interface between the PHY transceiver and the PHY controller (e.g., the 3-pin hardware interface, without limitation) and implements the PHY transceiver itself. Thus, the SBC is generally aware of power state information (e.g., power management commands and status information, without limitation) transmitted via the hardware interface. As a non-restrictive example, while wake-up is handled exclusively by the PHY transceiver, information about the wake-up source status is transmitted via the hardware interface. Therefore, the SBC is generally aware of the PHY transceiver's power state and any changes in that power state.Furthermore, the power provision for an MCU and the PHY controller implemented by the MCU is managed at least partially via information and commands that are transmitted between the SBC and the MCU via a communication interface (e.g. an I2C bus, without limitation).

[0029] In one or more examples, the SBC executes a power management command only if matching power management commands are received via the hardware interface (e.g., a TC14-compliant three-pin hardware interface that enables communication between the PHY controller and the PHY transceiver, without restriction) and the I2C bus. This ensures that the SBC and the PHY transceiver change the power state concurrently. For example, the SBC essentially instructs changes in power states to the drivers that control the SBC's power functions and to the drivers that implement the PHY transceiver at the same time. In some examples, the SBC may include a logic circuit (e.g., a finite state machine (FSM), without restriction) that manages changes in the power state of the SBC and the transceiver in stages.

[0030] Accordingly, if a power management command is a sleep command, the power at the SBC will not be turned off until the power state management logic determines that both the PHY transceiver and the PHY controller are (or will be) in a sleep state. Thus, a change in the power state of the SBC is at least partially dependent on the power states or scheduled power states of the PHY transceiver and the PHY controller.

[0031] Fig. Figure 1 is a block diagram of a system 100 that implements, among other things, a 10SPE PHY, according to one or more examples.

[0032] System 100 comprises an MCU 102 and an SBC 108. The MCU 102 includes a PHY controller 104 and an I2C bus controller 106. The SBC 108 includes a multi-stage, low-power input and output FSM 110 and a PHY transceiver 112. The PHY controller 104 and the PHY transceiver 112 form a 10SPE PHY. The PHY controller 104 and the PHY transceiver 112 communicate via the hardware interface 114, which includes connections for transmitting signals assigned to transmit signaling (TX connection), energy sensing signaling (ED connection), and receive signaling (RX connection). The SBC and the MCU communicate via an I2C bus and command, control and management links (the command, control and management links are represented by links INTn and RSTn, which specifically indicate an action required by the MCU, but are not intended to restrict this disclosure in any way).

[0033] The PHY controller 104 is responsible for managing the digital aspects of 10BASE-T1S PHY communication. It handles tasks such as encoding, decoding, and managing the link layer protocols. The I2C bus controller 106 manages communication over the I2C bus and facilitates the exchange of commands, control signals, and data between the MCU and the SBC. In the specific example described by Fig. As shown in Figure 1, the logic that manages communication between command, control and management links (e.g. INTn and RSTn, without limitation) is represented by the same block that represents the I2C bus controller 106, but may be a different logical partition.

[0034] The SBC 108 implements or manages functions of the PHY transceiver 112, functions of the MCU 102, functions of sensors (sensors not shown, but considered optional), and its own internal functions (SBC functions). Vuc is a supply voltage provided to the MCU by the SBC. Vsen is the supply voltage provided to one or more sensors, if any. Vsup is the supply voltage provided to the SBC and can be used to generate Vuc and Vsen, either directly or as a regulated version of Vsup. GPIO is a general-purpose input / output connection. Transmit / receive connections, common-mode choke (CMC), and connectors are physical circuits that connect the SBC 108 to a physical transmission medium, such as a twisted pair, without limitation. WAKEIN is an input connection used exclusively for receiving power management signals (e.g.,wake state or sleep state, without restriction) is used from an external source (e.g., external to System 100, without restriction).

[0035] In one or more examples, the SBC 108 coordinates power states and power state changes of two or more of: SBC 108, MCU 102, PHY controller 104, and PHY transceiver 112. The SBC 108 includes a logic circuit, here the FSM 110, to manage changes in the SBC's power state incrementally (e.g., to prevent abrupt changes that could lead to system instability or increased power consumption, without limitation), as described below.

[0036] The FSM 110 receives power state information (e.g., commands or status information, without limitation) via both the hardware interface 114 and the I2C bus. It uses this power state information to ensure that changes in the power state of the SBC 108 are synchronized with changes in the power state of the PHY transceiver 112. The FSM 110 acts as control logic, dictating all power state changes of the SBC 108 and PHY transceiver 112. Based on its state and the received inputs, the FSM 110 issues commands to the drivers 116 (which include SBC drivers and drivers implementing the PHY transceiver 112). The drivers 116 then execute the detailed commands issued by the FSM 110. For example, the SBC 108 driver 116 configures the hardware settings, manages power control, and ensures that the system components follow the instructions from the FSM 110 precisely.

[0037] During the period between the time when power state information indicates that the SBC 108 should change its power state and power state information indicating that the PHY transceiver 112 should change its power state, the SBC 108 or the PHY transceiver 112, as the case may be, can handle events occurring during this period, such as wake-up events, without restriction.

[0038] In some examples, the SBC 108 can include at least one regulated voltage source, and the sleep state of the SBC represents that the at least one regulated voltage source is OFF, and the wake state of the SBC 108 represents that the at least one regulated voltage source is ON.

[0039] Fig. Figure 2 is a block diagram representing a System Base Chip Section 200 according to one or more examples. System Base Chip Section 200 is a non-restrictive example of a section of the SBC 108. Fig. 1.

[0040] The system base chip section 200 includes a logic circuit 202, an SBC driver 204 and a PHY transceiver driver 206.

[0041] The logic circuit 202 monitors a hardware interface (e.g., the hardware interface 114 of Fig. 1, without restriction) and a communication interface (e.g., communication interface I2C bus of Fig. 1, without restriction) on power state information and receives power state information via hardware interface 208 and power state information via communication interface 210.

[0042] Power state information received via hardware interface 208 can include, as non-restrictive examples, commands regarding a power state of the PHY transceiver 112 from the PHY controller 104 to the PHY transceiver 112, and other information indicating the power state or changes in the power state of the PHY transceiver 112. For example, a sleep command can be transmitted from the PHY controller 104 to the PHY transceiver 112 via hardware interface 114, and power state information received via hardware interface 208 can include the sleep command.

[0043] Power state information received via communication interface 210 may, as non-restrictive examples, include an instruction (command) to the SBC, which includes the system base chip section 200, to enter a low-power state or a sleep state.

[0044] The SBC driver 204 (a "first driver") implements functions of the system base chip, including, without limitation, the execution of instructions 212 from the logic circuit 202 (or FSM), such as adjusting hardware settings, handling communications over specific links, and managing power control, without limitation. The PHY transceiver driver 206 (a "second driver") implements functions of the PHY transceiver, including, without limitation, the execution of instructions 214 from the logic circuit 202.

[0045] The timing of instructions 212 and 214, which include power state information and specific instructions for changing power states or intermediate states, can occur essentially at the same time. Here, "essentially at the same time," when discussing the provision of power state information or instructions more generally, means within a time window that ensures a suitably synchronized state change, typically on the order of microseconds, to maintain system stability and power efficiency.

[0046] Fig. Figure 3 is a state diagram representing transitions between wake and sleep states managed by an FSM 110 of the SBC 108, according to one or more examples.

[0047] The waking state (WAIT_SLEEP) is an initial active state in which the system is fully powered and ready for operation. In this state, both the PHY transceiver and the MCU are awake and handle regular communication and processing tasks. While awake, the FSM 110 monitors for sleep commands either from the hardware interface (PHY transceiver) or the I2C bus (MCU).

[0048] Upon receiving a sleep command, the FSM 110 will initiate the transition to sleep mode (WAIT_SLEEP to SLEEP) if both the sleep command from the receive signal (RX) and the sleep command from the I2C bus are received (this condition is in Fig. 3 represented as the expression SLEEP_CMD_RX && SLEEP_CMD_I2C). The transition from wake to sleep involves several intermediate stages (transitions through various intermediate states between WAIT_SLEEP and SLEEP) to ensure a controlled reduction in power consumption and prevent abrupt changes that could cause instability, as discussed below. In this specific example, the FSM 110 waits for a low-dropout regulator (LDO) to turn off (WAIT_LDO_OFF) and waits for a general wait time (period) to elapse before completing the transition (these conditions are defined in Fig. 3 as represented by the expression WAIT_LDO_OFF && WAIT_SLEEP). Waiting for the LDO to turn off and waiting for a general wait time to expire are optional, and conditions in addition to or in deviation from these two conditions do not exceed the scope of protection of this disclosure.

[0049] In sleep mode (SLEEP), power consumption is minimized, and the SBC 108 and System 100 in general are ready to wake up in response to a wake-up event. When a wake-up event occurs (e.g., receiving a wake-up command, without restriction), the FSM 110 reverses the staged process to transition the system to waking mode (WAIT_SLEEP). The FSM 110 will initiate the transition to waking mode (SLEEP to WAIT_SLEEP) when either the wake-up command is received from the receive signal (RX) or the wake-up command is received from the I2C bus (this condition is specified in Fig. 3 as the expression WAKE_CMD_RX || WAKE_CMD_I2C). In this specific example, the FSM 110 waits for the LDO to turn on (WAIT_LDO_ON) and waits for a general wait time to elapse before the transition to the wake state is completed (these conditions are in Fig. 3 (represented as the expression WAIT_LDO_ON && WAIT_WAKE). Waiting for the LDO to turn on and waiting for a general wait time to expire are optional, and conditions in addition to or beyond these two do not exceed the scope of protection of this disclosure.

[0050] Fig. Figure 4 is a state diagram that represents stepwise performance state changes from wake to sleep state and from sleep to wake state managed by the FSM 100 of the SBC 108, according to one or more examples.

[0051] The stepwise change of power state from wake to sleep includes the following states (states are indicated by circles): WAIT_SLEEP (i.e., awake), XCR_CTL, ISO_CTRL, LDO_CTL, WAIT_LDO_OFF, ACT_DET_CTL, and WAIT_WAKE (i.e., sleeping). Transitions between states are represented by arrows pointing from one state to the next. Conditions or events that trigger specific transitions are identified next to the arrows.

[0052] In the Transceiver Control state (XCR_CTL), the FSM configures the PHY transceiver 112 with control settings to prepare for low-power mode. In the Isolation Control state (ISO_CTL), the FSM 110 isolates certain circuits to reduce power consumption during the transition from wake to sleep states and integrates isolated circuits back into the system's power domain during sleep to wake state transitions. In the Low-Dropout Regulator Control state (LDO_CTL), the FSM 110 adjusts the power regulation settings to reduce current consumption. In the Waiting for LDO Off state (WAIT_LDO_OFF), the FSM 110 waits for confirmation that the LDO has successfully reduced or turned off its output. In the active detection control state (ACT_DET_CTL), the FSM 110 ensures that all necessary monitoring for wake-up or sleep events remains functional and reactivates the detection circuits as needed.In low-power sleep mode (WAIT_WAKE), the FSM 110 waits for a wake-up event. In the waiting state for LDO to turn on mode (WAIT_LDO_ON), ​​the FSM waits for the LDO to stabilize and provide the required voltage levels for normal operation.

[0053] The gradual transition from sleep to wakefulness includes the following states in this sequence: WAIT_SLEEP, XCR_CTL, ISO_CTL, LDO_CTL, WAIT_LDO_OFF, ACT_DET_CTL and WAIT_WAKE.

[0054] The gradual transition from sleep to wakefulness includes the following transitions in the sequence: WAIT_WAKE, ACT_DET_CTL, WAIT_LDO_ON, ISO_CTRL, CVR_CTRL, WAIT_SLEEP.

[0055] These sequences ensure that performance state transitions are smooth and coordinated, preventing sudden changes that could lead to instability or increased power consumption. The FSM 110 manages these stepwise transitions and ensures that each intermediate state is successfully completed before moving on to the next.

[0056] Fig. Figure 5 illustrates an exemplary process 500 for changing a performance state of a system base chip implementing a PHY transceiver of a PHY with a split-PHY architecture, according to one or more examples. Although the exemplary process 500 represents a specific sequence of operations, the sequence can be modified without infringing upon the scope of protection of this disclosure. For example, some of the illustrated operations can be performed in parallel or in a different sequence that does not substantially affect the function of the process 500. In other examples, different components of an exemplary device or system implementing the process 500 can perform functions essentially at the same time or in a specific sequence.Some or all of the operations of Process 500 may, as non-restrictive examples, be performed by System 100 or System Base Chip Section 200.

[0057] According to one or more examples, process 500 in operation 502 may include the provision of a system base chip that supports at least two power states: a sleep state and a wake state.

[0058] According to one or more examples, process 500 at operation 504 may include monitoring for power state information via a hardware interface and via a communication interface, wherein the hardware interface enables communication between a physical layer (PHY) transceiver implemented on the system base chip and a PHY controller implemented on a microcontroller, and wherein the communication interface enables communication between the system base chip and the microcontroller.

[0059] According to one or more examples, process 500 in operation 506 may involve coordinating a change in the power state of the system base chip, at least partially, based on receiving power state information via the hardware interface and the communication interface.

[0060] Fig. Figure 6 is a flowchart illustrating a Process 600 for coordinating a change in the power state of an SBC implementing a PHY transceiver with a change in the power state of the PHY transceiver, as shown in one or more examples. While the exemplary Process 600 represents a specific sequence of operations, the sequence can be modified without infringing upon the scope of protection of this disclosure. For example, some of the illustrated operations can be performed in parallel or in a different sequence that does not substantially affect the function of Process 600. In other examples, different components of an exemplary device or system implementing Process 600 can perform functions essentially simultaneously or in a specific sequence.Some or all of the operations of Process 600 may, as non-restrictive examples, be performed by System 100 or System Base Chip Section 200.

[0061] According to one or more examples, the procedure in Operation 602 includes receiving an initial power management command, wherein the initial power management command is received via the hardware interface.

[0062] According to one or more examples, the procedure in Operation 604 includes decoding the first power management command from signals received via the hardware interface.

[0063] According to one or more examples, the procedure in operation 606 includes receiving a second service management order, the second service management order being received via the communication interface.

[0064] According to one or more examples, the procedure in Operation 608 includes decoding the second power management command from signals received via the communication interface.

[0065] According to one or more examples, the procedure in Operation 610 includes coordinating the change in the power state of the system base chip at least partially based on the receipt of both the first power management instruction and the second power management instruction.

[0066] Fig. Figure 7 illustrates an exemplary process 700 for changing a performance state of a system base chip, a PHY transceiver implemented by the system base chip, or both, according to one or more examples. Although the exemplary process 700 represents a specific sequence of operations, the sequence can be modified without infringing upon the scope of protection of this disclosure. For example, some of the illustrated operations can be performed in parallel or in a different sequence that does not substantially affect the function of the process 700. In other examples, different components of an exemplary device or system implementing the process 700 can perform functions essentially at the same time or in a specific sequence.Some or all of the operations of Process 700 may, as non-restrictive examples, be performed by System 100 or System Base Chip Section 200.

[0067] According to one or more examples, process 700 in operation 702 may involve the stepwise management of a change in the performance state of the system base chip from a first state to a second state through several intermediate states.

[0068] According to one or more examples, process 700 in operation 704 may include that one of the first state or the second state is a waking state and the other of the first state or the second state is a sleeping state.

[0069] According to one or more examples, process 700 at operation 706 may include the multiple intermediate states comprising a transceiver control state, an isolation control state, a low-dropout regulator (LDO) control state, a waiting-to-turn-off LDO state, and an active capture control state.

[0070] It is understood by experts that functional elements of the examples disclosed herein (e.g. functions, operations, actions, processes and / or procedures) can be implemented in any suitable hardware, software, firmware or combinations thereof. Fig. Section 8 illustrates non-restrictive examples of implementations of functional elements disclosed herein. In some examples, some or all sections of the functional elements disclosed herein can be performed by hardware capable of executing the functional elements.

[0071] Fig.Figure 8 is a block diagram of a switching logic 800, which can be used in some examples to implement various functions, operations, actions, processes, or procedures disclosed herein. The switching logic 800 includes one or more processors 802 (hereafter sometimes referred to as "processors 802") operatively coupled to one or more data storage devices 804 (hereafter sometimes referred to as "storage 804"). The storage 804 includes machine-executable code 806 stored thereon, and the processors 802 include the logic circuit 808. The machine-executable code 806 includes information describing functional elements that can be implemented (e.g., performed) by the logic circuit 808. The logic circuit 808 is adapted to implement (e.g., perform) the functional elements described by the machine-executable code 806.The switching logic 800 should be regarded as special hardware configured to execute the functional elements described by machine-executable code 806. In some examples, the processors 802 can execute the functional elements described by machine-executable code 806 sequentially, concurrently (e.g., on one or more different hardware platforms), or in one or more parallel process streams.

[0072] When the machine-executable code 806 is implemented by the logic circuit 808 of the processors 802, it modifies the processors 802 to perform operations of examples disclosed herein. As a non-limiting example, the machine-executable code 806 can modify the processors 802 to perform some or all of the operations of one or more of the processes 500, 600, or 700; or processes implementing state diagram 300 or state diagram 400.

[0073] As a non-restrictive example, the machine-executable code 806 can also adapt the processors 802 to perform some or all of the features, functions, or operations disclosed herein for one or more of the following: System 100, System Base Chip Section 200, State Diagram 300, or State Diagram 400. More specifically, features, functions, or operations disclosed herein for coordinating changes in the power state.

[0074] The processors 802 may include a general-purpose processor, a special-purpose processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, another programmable device, or any combination thereof designed to perform the functions disclosed herein. A general-purpose computer, including a processor, is considered a special-purpose computer while the general-purpose computer executes functional elements corresponding to the machine-executable code 806 (e.g., software code, firmware code, hardware descriptions) that refers to examples in the present disclosure.It should be noted that a general-purpose processor (which may also be referred to herein as a host processor or simply as the host) can be a microprocessor, but alternatively, the 802 processors can include any conventional processor, controller, microcontroller, or state machine. The 802 processors can also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a multitude of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0075] In some examples, the 804 storage includes volatile data storage (e.g., random access memory (RAM)), non-volatile data storage (e.g., flash memory, a hard disk drive, a solid-state drive, an erasable programmable read-only memory (EPROM), without limitation). In some examples, the 802 processors and the 804 storage can be implemented in a single device (e.g., in a semiconductor device product, in a system-on-a-chip (SoC), without limitation). In some examples, the 802 processors and the 804 storage can be implemented in separate devices.

[0076] In some examples, the machine-executable code 806 may include computer-readable instructions (e.g., software code, firmware code). As a non-restrictive example, the computer-readable instructions may be stored by the memory 804, directly called by the processors 802, and executed by the processors 802 using at least the logic circuit 808. Also as a non-restrictive example, the computer-readable instructions may be stored on the memory 804, transferred to a storage device (not shown) for execution, and executed by the processors 802 using at least the logic circuit 808. Accordingly, in some examples, the logic circuit 808 includes an electrically configurable logic circuit 808.

[0077] In some examples, the machine-executable code 806 can describe hardware (e.g., switching logic) that is to be implemented in the logic circuit 808 to execute the functional elements. This hardware can be described at a number of abstraction levels, from concrete transistor layouts to highly abstract description languages. At a high abstraction level, a hardware description language (HDL), such as an IEEE standard hardware description language, can be used. Non-restrictive examples include VERILOG®, SYSTEMVERILOG™, or a hardware description language with VLSI (Very Large Scale Integration) (VHDL).

[0078] HDL descriptions can be converted at will into descriptions at any of numerous other levels of abstraction. As a non-restrictive example, a highly abstract description can be converted into a logic-level description, such as a register-transfer language (RTL), a gate-level (GL), a layout-level, or a mask-level description. As a non-restrictive example, microoperations performed by hardware logic circuits (e.g.,The operation of any gate, flip-flop, or register (without limitation) of the 808 logic circuit is described in an RTL and then converted into a GL description by a synthesis tool. The GL description can be converted by a placement and routing tool into a layout-level description corresponding to a physical layout of an integrated circuit, a programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. Accordingly, in some examples, the 806 machine-executable code may include an HDL, an RTL, a GL description, a mask-level description, another hardware description, or any combination thereof.

[0079] In examples where the machine-executable code 806 includes a hardware description (at any level of abstraction), a system (not shown, but including the storage 804) implements the hardware description provided by the machine-executable code 806. As a non-restrictive example, the processors 802 can include a programmable logic device (such as an FPGA or a PLC), and the logic circuit 808 can be electrically controlled to implement a circuit corresponding to the hardware description within the logic circuit 808. Also as a non-restrictive example, the logic circuit 808 can include hard-wired logic manufactured by a manufacturing system (not shown, but including the storage 804) according to the hardware description of the machine-executable code 806.

[0080] Regardless of whether the machine-executable code 806 includes computer-readable instructions or a hardware description, the logic circuit 808 is adapted to perform the functional elements described by the machine-executable code 806 when the functional elements of the machine-executable code 806 are implemented. It should be noted that, although a hardware description may not directly describe functional elements, a hardware description indirectly describes functional elements that can perform the hardware elements described by the hardware description.

[0081] As used in this disclosure, the terms “module” or “component” may refer to specific hardware implementations configured to perform the actions of the module or component and / or software objects or routines that can be stored on and / or executed by general-purpose hardware (e.g., computer-readable media, processing devices, without limitation) of the computing system. In some examples, the various components, modules, engines, and services described in this disclosure may be implemented as objects or processes that run on the computing system (e.g., as separate threads).Although some of the systems and methods described in the present disclosure are generally described as being implemented in software (stored on and / or executed by universal hardware), specific hardware implementations or a combination of software and specific hardware implementations are also possible and are considered.

[0082] As used in the present revelation, the term “combination” in relation to a multitude of elements can include a combination of all the elements or any of several different subcombinations of some of the elements. For example, the phrase “A, B, C, D or combinations thereof” can refer to any one of A, B, C or D; the combination of each of A, B, C and D; and any subcombination of A, B, C or D, such as A, B and C; A, B and D; A, C and D; B, C and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0083] Terms used in this disclosure, and in particular in the accompanying claims (e.g., the main parts of the accompanying claims, without limitation), are generally to be understood as "open" terms (e.g., the term "including" should be interpreted as "including, without limitation," the term "having" should be interpreted as "having at least"; the term "includes" should be interpreted as "includes, without limitation"). As used herein, the term "each" means "some or a whole." As used herein, the term "all" means a "whole."

[0084] Furthermore, if a specific number is intended in an introductory claim statement, this intention will be expressly stated in the claim, and in the absence of such a statement, no such intention exists. For example, the following appended claims may contain the use of the introductory phrases "at least one" and "one or more" to introduce claim statements. However, the use of such phrases should not be interpreted to imply that introducing a claim statement with the indefinite articles "one" or "a" limits a particular claim containing such an introduced claim statement to examples that contain only one such statement, even if the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "one" or "a" (e.g.,“A” and / or “an” should be interpreted as meaning “at least one” or “one or more”, without restriction); the same applies to the use of certain articles used to introduce claims.

[0085] Even if a specific number of an introduced claim statement is explicitly stated, the person skilled in the art will additionally recognize that such a statement should be interpreted as meaning at least the stated number (e.g., the mere statement of "two statements" without any other modifiers means at least two statements, or two or more statements without limitation). Furthermore, in cases where a convention is used analogously to "at least one of A, B, and C, without being limited thereto" or "one or more of A, B, and C, without being limited thereto," such a construction should generally include A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together, without being limited thereto.

[0086] Furthermore, any disjunctive word or phrase representing two or more alternative terms, whether in the description, claims, or drawings, should be understood as including either term, either term, or both terms. For example, the phrase "A or B" should be understood to include the possibilities of "A" or "B" or "A and B".

[0087] Other non-restrictive examples include: Example 1: A method comprising: providing a system base chip supporting at least two power states: a sleep state and a wake state; monitoring for power state information via a hardware interface and a communication interface, wherein the hardware interface enables communication between a physical layer (PHY) transceiver implemented on the system base chip and a PHY controller implemented on a microcontroller, and wherein the communication interface enables communication between the system base chip and the microcontroller; and coordinating a change in the power state of the system base chip at least partially based on receiving power state information via the hardware interface and the communication interface. Example 2: The procedure according to Example 1, wherein monitoring for performance status information includes monitoring for: Performance management commands and status information about performance states. Example 3: The procedure according to Examples 1 and 2, wherein coordinating the change in the power state of the system base chip includes: coordinating the change in the power state of the system base chip with a change in the power state of the PHY transceiver. Example 4: The method according to Examples 1 to 3, wherein coordinating the change in the power state of the system base chip with the change in the power state of the PHY transceiver, to provide essentially at the same time: first power state information to one or more drivers managing the power state of the system base chip; and second power state information to one or more drivers managing the power state of the PHY transceiver. Example 5: The method according to Examples 1 to 4, comprising: receiving a first power management instruction, wherein the first power management instruction is received via the hardware interface; receiving a second power management instruction, wherein the second power management instruction is received via the communication interface; and coordinating the change of the power state of the system base chip at least partially based on the receipt of both the first power management instruction and the second power management instruction. Example 6: The procedure according to Examples 1 to 5, comprising: decoding the first power management command from signals received via the hardware interface; and decoding the second power management command from signals received via the communication interface. Example 7: The procedure according to Examples 1 to 6, wherein the performance state of the system base chip does not change in response to only one of the first power management instructions or the second power management instruction. Example 8: The procedure according to Examples 1 to 7, wherein both the first service management order and the second service management order each include: a wake-up order or a sleep order. Example 9: The procedure according to Examples 1 to 8, wherein the communication interface is separate and different from the hardware interface. Example 10: The procedure according to Examples 1 to 9, wherein the PHY transceiver and the PHY controller together form a 10SPE-PHY with a split-PHY architecture. Example 11: The procedure according to Examples 1 to 10, comprising: Stepwise management of a change in the performance state of the system base chip from a first state to a second state through several intermediate states, one of which is a wake state and the other of which is a sleep state. Example 12: The procedure according to Examples 1 to 11, wherein the several intermediate states include: a transceiver control state, an isolation control state, a low-dropout regulator (LDO) control state, a waiting-for-LDO-off state, and an active sensing control state. Example 13: The method according to Examples 1 to 12, wherein the hardware interface for communication between the PHY transceiver and a PHY controller is integrated into the microcontroller. Example 14: A device comprising: a first driver for implementing functions of a PHY transceiver on a system base chip; a second driver for implementing functions of the system base chip, wherein the second driver is different from the first driver; and a logic circuit for coordinating a change in the power state of the system base chip with a change in the power state of the PHY transceiver via instructions issued to the first driver and the second driver. Example 15: The setup according to Example 14, wherein the system base chip supports at least two power states: a sleep state and a wake state. Example 16: The setup according to Examples 14 and 15, wherein the logic circuit serves to: monitor for power state information via a hardware interface and via a communication interface, wherein the hardware interface enables communication between the PHY transceiver implemented on the system base chip and a PHY controller implemented on a microcontroller, and wherein the communication interface enables communication between the system base chip and the microcontroller; and coordinate the change in the power state of the system base chip with the change in the power state of the PHY transceiver at least partially based on the reception of power state information via both the hardware interface and the communication interface. Example 17: The setup according to Examples 14 to 16, where the monitored performance state information includes: performance management commands and status information about performance states. Example 18: The setup according to Examples 14 to 17, wherein the logic circuit comprises: a finite state machine (FSM) for initiating a change in the power state of the system base chip at least partially based on power state information received via the hardware interface and the communication interface, and specifying a coordinated change in power state for the PHY transceiver. Example 19: The setup according to Examples 14 to 18, wherein the logic circuit comprises: a finite state machine (FSM) for stepwise managing a change in the power state of the system base chip from a first state to a second state through several intermediate states, one of which is a wake state and the other of which is a sleep state. Example 20: A system comprises: a microcontroller; and a system base chip supporting at least two power states: a sleep state and a wake state, wherein the system base chip serves to: monitor for power state information via a hardware interface and via a communication interface, wherein the hardware interface enables communication between a PHY transceiver implemented on the system base chip and a PHY controller implemented on the microcontroller, and wherein the communication interface enables communication between the system base chip and the microcontroller; and coordinate a change in the power state of the system base chip at least partially based on receiving power state information via both the hardware interface and the communication interface.

[0088] Although the present disclosure has been described herein with respect to certain illustrated examples, those skilled in the art will recognize and understand that the present invention is not limited to these. Rather, many additions, omissions, and modifications can be made to the illustrated and described examples without altering the scope of protection of the invention as claimed below together with its legal equivalents. Furthermore, features of one example can be combined with features of another example and still remain within the scope of protection of the invention as envisaged by the inventor. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 512,229

[0001]

Claims

[1] Procedure, encompassing: Providing a system base chip that supports at least two power states: a sleep state and a wake state; Monitoring for performance state information via a hardware interface and via a communication interface, wherein the hardware interface enables communication between a physical layer (PHY) transceiver implemented on the system base chip and a PHY controller implemented on a microcontroller, and wherein the communication interface enables communication between the system base chip and the microcontroller; and Coordinating a change in the performance state of the system base chip, at least partially based on receiving performance state information via the hardware interface and the communication interface. [2] The method of claim 1, wherein monitoring for performance state information includes monitoring for: Performance management commands and status information about performance states. [3] Method according to claim 1, wherein coordinating the change in the performance state of the system base chip comprises: Coordinate the change in the power state of the system base chip with a change in the power state of the PHY transceiver. [4] The method of claim 3, wherein the method comprises coordinating the change in the power state of the system base chip with the change in the power state of the PHY transceiver, to provide substantially at the same time: initial power state information to one or more drivers that manage the power state of the system base chip; and second power state information to one or more drivers that manage the power state of the PHY transceiver. [5] The method of claim 1, comprising: Receiving an initial power management command, wherein the initial power management command is received via the hardware interface; Receiving a second power management command, wherein the second power management command is received via the communication interface; and Coordinate the change in the power state of the system base chip, at least partially, based on the receipt of both the first power management instruction and the second power management instruction. [6] The method of claim 5, comprising: Decoding the first power management command from signals received via the hardware interface; and Decoding the second power management command from signals received via the communication interface. [7] Method according to claim 5, wherein the performance state of the system base chip does not change in response to only one of the first power management command or the second power management command. [8] Method according to claim 5, wherein both the first performance management command and the second performance management command each comprise: a wake-up command or a sleep command. [9] Method according to claim 1, wherein the communication interface is separate and distinct from the hardware interface. [10] Method according to claim 1, wherein the PHY transceiver and the PHY controller together form a 10SPE-PHY with a split-PHY architecture. [11] The method of claim 1, comprising: Stepwise management of a change in the performance state of the system base chip from a first state to a second state through several intermediate states, where one of the first state or the second state is a waking state and the other of the first state or the second state is a sleeping state. [12] The method of claim 11, wherein the multiple intermediate states comprise: a transceiver control state, an isolation control state, a low-dropout regulator (LDO) control state, a waiting-for-LDO-off state, and an active acquisition control state. [13] Method according to claim 1, wherein the hardware interface for communication between the PHY transceiver and a PHY controller is integrated into the microcontroller. [14] Institution, comprehensive: a first driver for implementing functions of a PHY transceiver on a system-based chip; a second driver for implementing functions of the system base chip, wherein the second driver differs from the first driver; and A logic circuit for coordinating a change in the power state of the system base chip with a change in the power state at the PHY transceiver via instructions issued to the first driver and the second driver. [15] Device according to claim 14, wherein the system base chip supports at least two performance states: a sleep state and a wake state. [16] Device according to claim 14, wherein the logic circuit serves to: Monitoring for performance state information via a hardware interface and via a communication interface, wherein the hardware interface enables communication between the PHY transceiver implemented on the system base chip and a PHY controller implemented on a microcontroller, and wherein the communication interface enables communication between the system base chip and the microcontroller; and Coordinating the change in the power state of the system base chip with the change in the power state of the PHY transceiver, at least partially based on receiving power state information via both the hardware interface and the communication interface. [17] Device according to claim 16, wherein the monitored performance state information includes: performance management commands and status information about performance states. [18] Device according to claim 16, wherein the logic circuit comprises: a finite state machine (FSM) for initiating a change in the power state of the system base chip at least partially based on power state information received via the hardware interface and the communication interface, and specifying a coordinated change in power state for the PHY transceiver. [19] Device according to claim 16, wherein the logic circuit comprises: a finite state machine (FSM) for stepwise managing a change in the performance state of the system base chip from a first state to a second state through several intermediate states, where one of the first state or the second state is a waking state and the other of the first state or the second state is a sleeping state. [20] System that includes: a microcontroller; and a system base chip that supports at least two power states: a sleep state and a wake state, with the system base chip serving to: Monitoring for performance state information via a hardware interface and via a communication interface, wherein the hardware interface enables communication between a PHY transceiver implemented on the system base chip and a PHY controller implemented on the microcontroller, and wherein the communication interface enables communication between the system base chip and the microcontroller; and Coordinating a change in the performance state of the system base chip, at least partially based on receiving performance state information via both the hardware interface and the communication interface.

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