SEMICONDUCTOR COMPONENT

Abstract

A semiconductor device comprises a chip having a main surface, a drift region of a first conductivity type formed on a surface layer section of the main surface, a gate structure of a trench electrode type formed on the main surface such that it is placed in the drift region, and a trough region of a second conductivity type formed along a bottom wall of the gate structure in a region below the gate structure in the drift region, wherein the trough region comprises a plurality of first trough regions, each of which is a first trough region having a first bottom section with a first depth, and which are formed at a first distance from each other in a depth direction of the gate structure, and wherein the adjacent first trough regions face each other in the depth direction of the gate structure over a section of the drift region.

Description

Related registration The present application corresponds to Japanese patent application No. 2023-178289, which was filed with the Japanese Patent Office on October 16, 2023, and the entire disclosure of the application is incorporated herein by reference. Technical field The present disclosure relates to a semiconductor device. State of the art Document 1 discloses a semiconductor device comprising a semiconductor substrate, a semiconductor region, a body region, a gate groove, a gate insulating film, a gate electrode, and a p-type diffusion region. The semiconductor region is located on the upper surface of the semiconductor substrate. The body region is located closer to the upper surface of the semiconductor substrate than to the semiconductor region. The gate trench is formed in the upper surface of the semiconductor substrate and extends through the body region. The gate insulating film covers the wall surface of the gate trench. The gate electrode is embedded in the gate trench by the gate insulating film. The p-type diffusion region is formed along the bottom wall of the gate trench in the semiconductor region. State of the art documents Patent literature Publication 1: US 2010 / 0 224 932 A [Overview] A preferred embodiment of the present disclosure provides a semiconductor device that is able to reduce resistance while suppressing a decrease in dielectric strength. The preferred embodiment of the present disclosure provides a semiconductor device comprising a chip with a main surface, a drift region of a first conductivity type formed on a surface layer section of the main surface, a trench-electrode-type gate structure formed on the main surface such that it is located in the drift region, and a trough region of a second conductivity type formed along a bottom wall of the gate structure in a region below the gate structure in the drift region. The trough region comprises a plurality of first trough regions, each of which is a first trough region having a first bottom section of a first depth and which are formed at a first distance from one another in a depth direction of the gate structure.The first adjacent trough regions face each other in the depth direction of the gate structure over a section of the drift region. Brief description of the drawings [Fig. 1] Fig. 1 is a top view showing a semiconductor device according to a first preferred embodiment of the present disclosure. [Fig. 2] Fig. 2 is a cross-sectional view taken along line II-II in Fig. 1. [Fig. 3] Fig. 3 is a top view showing a layout example of a chip. [Fig. 4] Fig. 4 is an enlarged view of a section enclosed by a dash-dot line IV in Fig. 3. [Fig. 5] Fig. 5 is a cross-sectional view taken along line VV in Fig. 4. [Fig. 6] Fig. 6 is a cross-sectional view taken along line VI-VI in Fig. 4. [Fig. 7] Fig. 7 is a cross-sectional view taken along line VII-VII in Fig. 4. [Fig. 8] Fig.Fig. 8 is an enlarged view of a section enclosed by a dash-dot line VIII in Fig. 5. [Fig. 9] Fig. 9 is an enlarged view of a section enclosed by a dash-dot line IX in Fig. 6. [Fig. 10] Fig. 10 is a cross-sectional view of a semiconductor device according to a reference example corresponding to Fig. 6. [Fig. 11] Fig. 11 is a cross-sectional view of a semiconductor device according to a reference example corresponding to Fig. 7. [Fig. 12] Fig. 12 is a top view showing a layout example of a chip according to a second preferred embodiment of the present disclosure, corresponding to Fig. 4. [Fig. 13] Fig. 13 is a cross-sectional view taken along line XIII-XIII in Fig. 12. [Fig. 14] Fig. 14 is a cross-sectional view taken along line XIV-XIV in Fig. 12 was taken. [Fig. 15] Fig. 15 is a cross-sectional view taken along line XV-XV in Fig.[Fig. 12] Fig. 16 is a cross-sectional view taken along line XVI-XVI in Fig. 12. [Fig. 17] Fig. 17 is an enlarged view of a section enclosed by a dash-dot line XVII in Fig. 15. [Fig. 18] Fig. 18 is a cross-sectional view of a semiconductor device according to a first modification example corresponding to Fig. 16. [Fig. 19] Fig. 19 is a cross-sectional view of a semiconductor device according to a second modification example corresponding to Fig. 9. [Fig. 20] Fig. 20 is a cross-sectional view of a semiconductor device according to a third modification example corresponding to Fig. 5. [Fig. 21] Fig. 21 is a cross-sectional view of the semiconductor device according to the third modification example corresponding to Fig. 6. [Fig. 22] Fig. Figure 22 is a cross-sectional view of a semiconductor device according to a fourth modification example. [Fig. 23]Fig. 23 is a cross-sectional view of the semiconductor device according to the fourth modification example. [Fig. 24] Fig. 24 is a cross-sectional view of a semiconductor device according to a fifth modification example. [Fig. 25] Fig. 25 is a cross-sectional view of the semiconductor device according to the fifth modification example. [Fig. 26] Fig. 26 is a cross-sectional view of a semiconductor device according to a sixth modification example, which corresponds to Fig. 5. [Fig. 27] Fig. 27 is a cross-sectional view of the semiconductor device according to the sixth modification example, which corresponds to Fig. 6. [Detailed description] Specific configurations are described in detail below with reference to the accompanying drawings. All accompanying drawings are schematic views and are not shown strictly to scale and do not correspond to one another with respect to relative position, scale reduction, ratio, angles, etc. The same reference numeral is assigned to a component that corresponds to every component in the accompanying drawings, and a repeated description of that component is omitted or simplified. A description of a component that has not yet been omitted or simplified is applied to a corresponding component whose description has been omitted or simplified. When the term "material" is used in this description, it includes a numerical error (configuration error) that falls within the range of ±10% based on a numerical value (configuration) that is a target value for comparison, in addition to a numerical value (configuration) that is equal to the numerical target value (configuration). Although the terms "first," "second," "third," etc., are used below, these terms are characters assigned to the name of each component to clarify the order of explanation and are not assigned to limit the name of each component. Although the conductivity type of a semiconductor (defect) is shown below using "p-type" or "n-type," the "n-type" can be referred to as the "first conductivity type" and the "p-type" as the "second conductivity type." The "p-type" is a conductivity type resulting from a trivalent element, and the "n-type" is a conductivity type resulting from a quinquevalent element. The trivalent element is at least one of boron, aluminum, gallium, and indium. The quinquevalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. Fig. 1 is a top view showing a semiconductor device 1 according to a first preferred embodiment of the present disclosure. Fig. 2 is a cross-sectional view taken along line II-II in Fig. 1. Fig. 3 is a top view showing a layout example of a chip 2. Referring to Fig. 1, Fig. 2 to Fig. 3, the semiconductor device 1 is a semiconductor switching device with an insulated-gate transistor structure Tr as an example of a device structure. The transistor structure Tr has a vertical configuration. The semiconductor device 1 is a SiC semiconductor device with the chip 2, which comprises a SiC monocrystal. The chip 2 can be referred to as the "SiC chip" or the "semiconductor chip". In this preferred embodiment, the chip 2 consists of a hexagonal SiC monocrystal and is formed in a right-angled parallelepiped shape. The hexagonal SiC monocrystal has a variety of polytypes, including 2H (hexagonal) SiC monocrystal, 4H SiC monocrystal, 6H SiC monocrystal, etc. Although an example is shown in this preferred embodiment in which the chip 2 consists of a 4H SiC monocrystal, the chip 2 can be composed of a different polytype. Chip 2 has a first principal surface (main surface) 3 on one side, a second principal surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first principal surface 3 and the second principal surface 4. The first principal surface 3 and the second principal surface 4 are each formed in a quadrilateral shape in a top view from a vertical direction Z (hereinafter referred to simply as the "top view"). The vertical direction Z is also a thickness direction of Chip 2 or a normal direction of the first principal surface 3 (second principal surface 4). The first principal surface 3 and the second principal surface 4 can each be formed in a square or a rectangular shape in the top view. Preferably, the first principal surface 3 and the second principal surface 4 are each formed by a c-plane of a SiC monocrystal. In this case, the first principal surface 3 is preferably formed by a silicon plane ((0001) plane) of the SiC monocrystal, and the second principal surface 4 is formed by a carbon plane ((000-1) plane) of the SiC monocrystal. The first face 5A and the second face 5B extend in a first direction X along the first main face 3 and face a second direction Y, which intersects the first direction X along the first main face 3. Specifically, the second direction Y intersects the first direction X perpendicularly. The third face 5C and the fourth face 5D extend in the second direction Y and face the first direction X. In this preferred embodiment, the first direction X is an m-axial direction ([1-100] direction) of the SiC monocrystal, and the second direction Y is an a-axial direction ([11-20] direction) of the SiC monocrystal. Of course, the first direction X can be the a-axial direction of the SiC monocrystal, and the second direction Y can be the m-axial direction of the SiC monocrystal. Hereinafter, a direction extending along the first principal surface 3 is sometimes expressed as the "horizontal direction," and a surface along the first principal surface 3 is sometimes expressed as the "horizontal surface." The horizontal direction is also an XY-planar surface (horizontal surface) formed by the first direction X and the second direction Y, intersecting the vertical direction Z perpendicularly. Chip 2 (first principal surface 3 and second principal surface 4) has an off angle inclined in a predetermined off direction by a predetermined angle with respect to the c-plane of the SiC monocrystal. The c-axis ((0001)-axis) of the SiC monocrystal is inclined by exactly the off angle in the off direction from a vertical line. Additionally, the c-plane of the SiC monocrystal is inclined by exactly the off angle with respect to the horizontal surface. Preferably, the off-direction is the a-axial direction (second direction Y) of the SiC monocrystal. The off-angle can be greater than 0° and not more than 10°. The off-angle can have a value that falls within at least one range below more than 0° and not more than 1°, not less than 1° and not more than 2.5°, not less than 2.5° and not more than 5°, not less than 5° and not more than 7.5°, and not less than 7.5° and not more than 10°. Preferably, the off-angle is equal to or less than 5°. Particularly preferably, the off-angle is not less than 2° and not more than 4.5°. Typically, the off-angle is set in the range of 4° ± 0.1°. This description does not preclude a configuration in which the off-angle is 0° (the first principal surface 3 is a just surface with respect to the c-plane). The semiconductor device 1 comprises an n-type first semiconductor region 6, which is formed on a surface layer section of the second main area 4 of the chip 2. A drain potential, which is a first potential (high potential), is applied to the first semiconductor region 6. The first semiconductor region 6 can be referred to as a "semiconductor layer," a "first semiconductor layer," a "drain region," etc. The first semiconductor region 6 can have an n-type impurity concentration of not less than 1 × 10¹⁴ cm⁻³ and not more than 1 × 10²¹ cm⁻³. The first semiconductor region 6 is formed in a layer shape extending along the second main surface 4 and is exposed from the second main surface 4 of the chip 2 and from the first to fourth side surfaces 5A to 5D of the chip 2. In this preferred embodiment, the first semiconductor region 6 consists of, or is composed of, an n-type semiconductor layer. Specifically, the first semiconductor region 6 consists of, or is composed of, a substrate (SiC substrate) comprising a SiC monocrystal (semiconductor monocrystal) and forms the second main surface 4 of the chip 2 and the first to fourth side surfaces 5A to 5D of the chip 2. The first semiconductor region 6 has the off-direction and off-angle mentioned above. The first semiconductor region 6 can have a thickness of not less than 10 µm and not more than 500 µm. The thickness of the first semiconductor region 6 can be a value that falls within at least one of the following ranges: not less than 10 µm and not more than 50 µm, not less than 50 µm and not more than 100 µm, not less than 100 µm and not more than 150 µm, not less than 150 µm and not more than 200 µm, not less than 200 µm and not more than 300 µm, not less than 300 µm and not more than 400 µm, and not less than 400 µm and not more than 500 µm. The semiconductor device 1 comprises an n-type second semiconductor region (drift region) 7, which is formed on a surface layer section of the first main area 3 of the chip 2. The second semiconductor region 7 can be referred to as a "semiconductor layer", a "second semiconductor layer", a "drift region", etc. The second semiconductor region 7 has an n-type impurity concentration that is lower than the n-type impurity concentration of the first semiconductor region 6. The n-type impurity concentration of the second semiconductor region 7 cannot be less than 1 × 10¹⁴ cm⁻³ and cannot be more than 1 × 10¹⁸ cm⁻³. The second semiconductor region 7 is formed in a layer shape that extends along the first main surface 3 and is electrically connected to the first semiconductor region 6. The second semiconductor region 7 is exposed from the second main surface 4 of the chip 2 and from the first to fourth side surfaces 5A to 5D of the chip 2. In this preferred embodiment, the second semiconductor region 7 consists of, or is composed of, an n-type semiconductor layer. In detail, the second semiconductor region 7 consists of, or is composed of, an epitaxial layer (SiC epitaxial layer) comprising a SiC monocrystal (semiconductor monocrystal) and forms the first main face 3 of the chip 2 and the first to fourth side faces 5A to 5D of the chip 2. The second semiconductor region 7 (epitaxial layer) has the off-direction and off-angle mentioned above. Preferably, the second semiconductor region 7 has a smaller thickness than the first semiconductor region 6. The thickness of the second semiconductor region 7 can be greater than the thickness of the first semiconductor region 6. The thickness of the second semiconductor region 7 cannot be less than 5 µm and cannot be more than 50 µm. The semiconductor device 1 comprises a first surface section 8, a second surface section 9, and first to fourth interconnect surface sections 10A to 10D, which are formed on the first main surface 3. The first surface section 8, the second surface section 9, and the first to fourth interconnect surface sections 10A to 10D define a mesa 11 in the first main surface 3. The first surface section 8, the second surface section 9, and the first to fourth interconnect surface sections 10A to 10D (mesa 11) can each be considered a component of the chip 2 (first main surface 3). The first surface section 8 can be referred to as the “active surface”, the second surface section 9 as the “outer surface”, the first to fourth connecting surface sections 10A to 10D as the “connecting surfaces” and the mesa 11 as the “active mesa”. The first surface section 8 is formed at intervals inwards from the peripheral edges of the first main surface 3 (from the first to fourth side surfaces 5A to 5D). The first surface section 8 has a flat surface extending in the horizontal direction and is formed by the c-plane (Si-plane). In this preferred embodiment, the first surface section 8 is formed in a quadrilateral shape with four sides parallel to the first to fourth side surfaces 5A to 5D in the top view. Preferably, the flat area or surface area of ​​the first surface section 8 is not less than 50% and not more than 90% of the flat area of ​​the first main surface 3. The second surface section 9 is located on the side of the peripheral edge section of the first main surface 3 with respect to the first surface section 8 and is recessed in the thickness direction of the chip 2 (towards the second main surface 4) from a height position of the first surface section 8. The second surface section 9 extends in a band shape along the first surface section 8 in the top view and is formed in an annular shape (in detail, a quadrilateral ring shape) that surrounds the first surface section 8. The second surface section 9 is continuous with the first to fourth side surfaces 5A to 5D. The second surface section 9 is essentially parallel to the first surface section 8 and has a flat surface extending in the horizontal direction. In this preferred embodiment, the second surface section 9 is formed by the c-plane (Si plane). The second surface section 9 is located within the second semiconductor region 7 at a distance from the first semiconductor region 6. The second surface section 9 is recessed to a depth less than the thickness of the second semiconductor region 7, thus exposing the second semiconductor region 7. The second surface section 9 has a depth of not less than 0.1 µm and not more than 3 µm. The depth of the second surface section 9 can be a value that falls within at least one range below 0.1 µm and not more than 0.5 µm, not less than 0.5 µm and not more than 1 µm, not less than 1 µm and not more than 1.5 µm, not less than 1.5 µm and not more than 2 µm, not less than 2 µm and not more than 2.5 µm, and not less than 2.5 µm and not more than 3 µm. Preferably, the depth of the second surface section 9 is not less than 1.5 µm and not more than 2.5 µm. The first to fourth connecting surface sections 10A to 10D extend in the vertical direction Z and are connected to the first surface section 8 and the second surface section 9. The first connecting surface section 10A is located on the side of the first side face 5A, the second connecting surface section 10B is located on the side of the second side face 5B, the third connecting surface section 10C is located on the side of the third side face 5C, and the fourth connecting surface section 10D is located on the side of the fourth side face 5D. The first connecting surface section 10A and the second connecting surface section 10B extend in the first direction X and face the second direction Y. The third connecting surface section 10C and the fourth connecting surface section 10D extend in the second direction Y and face the first direction X. The first to fourth connecting surface sections 10A to 10D can extend substantially perpendicularly between the first surface section 8 and the second surface section 9 and can delimit the mesa 11 with a quadrilateral prism shape. The first to fourth connecting surface sections 10A to 10D can be inclined obliquely downwards from the first surface section 8 to the second surface section 9 and can delimit the mesa 11 with a truncated pyramid shape. The first to fourth connecting surface sections 10A to 10D can be inclined at an angle of more than 90° and not more than 135° with respect to the first surface section 8. In this way, the mesa 11 is delineated in a protruding form in the second semiconductor region 7 in the first main area 3. The mesa 11 is formed only in the second semiconductor region 7 and not in the first semiconductor region 6. The semiconductor device 1 comprises an active region 12, which is defined within the chip 2. The active region 12 comprises a component structure (transistor structure Tr) and is a region in which an output current (drain current) is generated. The active region 12 is defined in an inner section of the chip 2. Specifically, the active region 12 is defined in the first surface section 8. The semiconductor device 1 comprises an outer edge region 13, which is defined outside the active region 12 in the chip 2. The outer edge region 13 is a region that does not include any device structure (transistor structure Tr). The outer edge region 13 is defined in a peripheral edge section of the chip 2. In detail, the outer edge region 13 is defined in the second surface section 9. The outer edge region 13 is defined in a region between a peripheral edge of the first surface section 8 and a peripheral edge of the second surface section 9 in the top view. The following shows an arrangement in the active region 12. The semiconductor device 1 comprises a plurality of trench-type gate structures 15 (trench-electrode type) formed on the first main surface 3 (first surface section 8). The gate structure 15 can be referred to as a "trench-gate structure", a "trench structure", etc. A gate potential is applied to the plurality of gate structures 15 as a control potential. Referring to Figures 2 and 3, the plurality of gate structures 15 are formed on the first surface section 8 at intervals inwards from the peripheral edges of the first surface section 8 (first to fourth connecting surface sections 10A to 10D). The plurality of gate structures 15 are arranged at intervals from each other in the first direction X in the top view and are each formed in a band shape extending in the second direction Y. The plurality of gate structures 15 are arranged in a strip shape extending in the second direction Y (depth direction) in the top view. The plurality of gate structures 15 can be arranged at intervals of not less than 0.25 µm and not more than 3 µm from each other. The multitude of gate structures 15 are located in the second semiconductor region 7. These gate structures 15 are spaced apart from a bottom section of the second semiconductor region 7 in the direction of the first main surface 3 and extend across a portion of the second semiconductor region 7 towards the first semiconductor region 6. The multitude of gate structures 15 are oriented essentially perpendicular to the first main surface 3 (first surface section 8). Fig. 4 is an enlarged view of a section enclosed by a dash-dot line IV in Fig. 3. Fig. 5 is a cross-sectional view taken along line VV in Fig. 4. Fig. 6 is a cross-sectional view taken along line VI-VI in Fig. 4. Fig. 7 is a cross-sectional view taken along line VII-VII in Fig. 4. Fig. 8 is an enlarged view of a section enclosed by a dash-dot line VIII in Fig. 5. Fig. 9 is an enlarged view of a section enclosed by a dash-dot line IX in Fig. 6. Referring to Fig. 4, Fig. 5 to Fig. 6, Fig. 8, and Fig. 9, in addition to Fig. 2 and Fig. 3, an arrangement of the plurality of gate structures 15 is described continuously. In a cross-sectional view, each of the plurality of gate structures 15 has a first side wall 15a on one side (side of the third side surface 5C) in the first direction X, a second side wall 15b on the other side (side of the fourth side surface 5D) in the first direction X and a bottom wall 15c that connects the first side wall 15a and the second side wall 15b, as shown in Fig. 8 and Fig. 9. The first sidewall 15a and the second sidewall 15b are each formed by an a-plane ((11-20) plane) of the SiC monocrystal. Alternatively, the first sidewall 15a and the second sidewall 15b can each be formed by an m-plane ((1-100) plane) of the SiC monocrystal in accordance with the depth direction (second direction Y) of the gate structure 15. The first sidewall 15a and the second sidewall 15b are substantially perpendicular to the first principal surface 3. The angle of inclination (absolute value) of the first sidewall 15a (second sidewall 15b) based on the vertical line must be no less than 85° and no more than 95°. Preferably, the angle of inclination of the first sidewall 15a (second sidewall 15b) is no less than 87° and no more than 93°. The bottom wall 15c is formed by a c-plane (Si-plane) of the SiC monocrystal.Preferably, the bottom wall 15c extends essentially flat along the horizontal direction. Of course, the bottom wall 15c can be curved in a circular arc shape in the direction of the second main surface 4. The gate structure 15 can have a width of not less than 0.1 µm and not more than 1.5 µm. The width of the gate structure 15 can fall within at least one range below 0.1 µm and not more than 0.25 µm, below 0.25 µm and not more than 0.5 µm, below 0.5 µm and not more than 0.75 µm, below 0.75 µm and not more than 1 µm, below 1 µm and not more than 1.25 µm, and below 1.25 µm and not more than 1.5 µm. Preferably, the width of the gate structure 15 is not less than 0.25 µm and not more than 0.75 µm. The gate structure 15 can have a depth of not less than 0.1 µm and not more than 3 µm. The depth of the gate structure 15 can fall within at least one range below 0.1 µm and not more than 0.5 µm, 0.5 µm and not more than 1 µm, 1 µm and not more than 1.5 µm, 1.5 µm and not more than 2 µm, 2 µm and not more than 2.5 µm, and 2.5 µm and not more than 3 µm. Preferably, the depth of the gate structure 15 is not less than 0.5 µm and not more than 1.5 µm. Preferably, the depth of the gate structure 15 is essentially equal to the depth of the second surface section 9. Each of the multiple gate structures 15 comprises a trench 16, an insulating film 17, and an embedded electrode 18. The trench 16 is formed in the first main surface 3 (first surface section 8) and delineates a wall surface of the gate structure 15 (first side wall 15a, second side wall 15b, and bottom wall 15c). The trench 16 extends along the second direction Y. The depth direction of the trench 16 is the second direction Y. The depth direction of the gate structure 15 coincides with the depth direction of the trench 16 and is also the second direction Y. The insulating film 17 can comprise at least one silicon oxide film, one silicon nitride film, and one silicon oxynitride film. In this preferred embodiment, the insulating film 17 has a single-layer structure consisting of a silicon oxide film. Particularly preferably, the insulating film 17 comprises a silicon oxide film consisting of an oxide of the chip 2. The insulating film 17 covers a wall surface of the trench 16 in a film form. The insulating film 17 comprises a first film section, a second film section, and a third film section. The first film section covers the first side wall 15a in a film form. The second film section covers the second side wall 15b in a film form. The third film section covers the bottom wall 15c in a film form and is continuous with the first and second film sections. The second film section has a thickness that is substantially equal to the thickness of the first film section. The third film section has a thickness that is greater than both the thickness of the first film section and the thickness of the second film section. Of course, the thickness of the third film section can be substantially equal to the thickness of the first film section and the thickness of the second film section.The insulating film 17 can have a thickness of not less than 10 nm and not more than 150 nm. The embedded electrode 18 can comprise either one or both p-type and n-type polysilicon. The embedded electrode 18 is embedded in the trench 16 via the insulating film 17. The embedded electrode 18 has an electrode surface exposed by the trench 16. The electrode surface is positioned on the side of the bottom wall 15c with respect to a height position of the first main surface 3. The electrode surface has a depression that tapers towards the bottom wall 15c in an inner section. Preferably, a bottom section of the depression is positioned on the side of the first main surface 3 with respect to a depth position of a middle section of the trench 16. Referring to Figures 5 and 6, the semiconductor device 1 comprises a plurality of p-type body regions 20 formed on the surface layer section of the first main surface 3 (first surface section 8). A source potential, a second potential (low potential) distinct from the first potential (high potential), is applied to the plurality of body regions 20. The body region 20 can be referred to as a "channel region," a "base region," etc. The plurality of body regions 20 can exhibit a p-type impurity concentration of not less than 1 × 10¹⁷ cm⁻³ and not more than 1 × 10¹⁹ cm⁻³. The multitude of body regions 20 are each formed in regions along the multitude of gate structures 15. In detail, each of the multitude of body regions 20 is formed in a region between the multitude of gate structures 15, and each extends in a band shape along the multitude of gate structures 15. With reference to Figs. 6 and 9, a configuration of the individual body region 20 is described below. In this preferred embodiment, the body region 20 is formed in a layered form extending in the first direction X in a cross-sectional view and is connected to one or both (in this preferred embodiment, both) of the mutually adjacent plurality of gate structures 15. The body region 20 faces the embedded electrodes 18 of the plurality of gate structures 15 across the insulating films 17 of the plurality of gate structures 15. Body region 20 is formed at a distance of one depth position of the second surface section 9 in a region on the side of the first surface section 8. Body region 20 is formed at a distance of one depth position of the bottom wall 15c of the gate structure 15 in the direction of the first main surface 3. Body region 20 has a bottom section that is located on the side of the bottom wall 15c (see Fig. 9) of the gate structure 15 with respect to one depth position of a middle section of the gate structure 15. The bottom section of body region 20 is located in a region between the bottom wall 15c of gate structure 15 and the middle section of gate structure 15. The distance between the bottom section of body region 20 and the bottom wall 15c of gate structure 15 is less than the thickness (depth) Tb of body region 20 (see Fig. 9). The bottom section of body region 20 is located on the side of the bottom wall 15c of gate structure 15 with respect to the bottom section of the recess of the embedded electrode 18. Alternatively, the bottom section of body region 20 could be located on the side of the first main surface 3 with respect to the depth position of the middle section of gate structure 15. The body region 20 can have a thickness of not less than 0.1 µm and not more than 1 µm. The thickness Tb of the body region 20 (see Fig. 9) can be a value that falls within at least one range below 0.1 µm and not more than 0.2 µm, 0.2 µm and not more than 0.4 µm, 0.4 µm and not more than 0.6 µm, 0.6 µm and not more than 0.8 µm, and 0.8 µm and not more than 1 µm. Preferably, the thickness Tb of the body region 20 (see Fig. 9) is not less than 0.3 µm and not more than 0.7 µm. Referring to Fig. 4, Fig. 6 and Fig. 9, the semiconductor device 1 comprises a plurality of n-type source regions 21 formed in a region on the side of the first main surface 3 with respect to the plurality of body regions 20. The plurality of source regions 21 have an n-type impurity concentration that is higher than the n-type impurity concentration of the second semiconductor region 7. The n-type impurity concentration of the plurality of source regions 21 cannot be less than 1 × 10¹⁸ cm⁻³ and cannot be more than 1 × 10²⁹ cm⁻³. The multitude of source regions 21 are each formed in regions along the multitude of gate structures 15 in the surface layer sections of the multitude of body regions 20. In detail, each of the multitude of source regions 21 is formed in a region between the multitude of gate structures 15, and each extends in a band shape along the multitude of gate structures 15. Referring to Figures 6 and 9, a configuration of the individual source region 21 is described below. The source region 21 is formed at a distance from the bottom section of the body region 20 in the direction of the first main surface 3. In this preferred embodiment, the source region 21 is formed in a layered form that extends in the first direction X in the cross-sectional view and is connected to one or both (in this preferred embodiment, both) of the mutually adjacent plurality of gate structures 15. The source region 21 faces the embedded electrodes 18 of the plurality of gate structures 15 across the insulating films 17 of the plurality of gate structures 15. The source region 21 has a bottom section located on the side of the bottom wall 15c (see Fig. 9) of the trench 16 with respect to a height position of the electrode surface of the embedded electrode 18, and a surface layer section located on the side of the first main surface 3 with respect to the height position of the electrode surface of the embedded electrode 18. The source region 21 has a section (bottom section) facing the embedded electrode 18 across the insulating film 17 and a section (surface layer section) not facing the embedded electrode 18 across the insulating film 17. The bottom section of source region 21 can be positioned on the side of the first main surface 3 with respect to the depth position of the bottom section of the recess of the embedded electrode 18. Naturally, the bottom section of source region 21 can also be positioned on the side of body region 20 with respect to the depth position of the bottom section of the recess. The semiconductor device 1 comprises a plurality of p-type well regions 22 formed in the chip 2 (second semiconductor region 7). The plurality of well regions 22 have a p-type impurity concentration that is higher than the p-type impurity concentration of the body region 20. Of course, the p-type impurity concentration of the plurality of well regions 22 can be equal to or less than the p-type impurity concentration of the body region 20. The p-type impurity concentration of the plurality of well regions 22 cannot be less than 1 × 10¹⁶ cm⁻³ and cannot be more than 1 × 10²⁰ cm⁻³. The plurality of well regions 22 can be referred to as a "field relaxation layer". The plurality of well regions 22 are each formed at a distance from one another in the first direction X in regions along the bottom walls 15c of the plurality of gate structures 15 in the chip 2 (second semiconductor region 7). In this preferred embodiment, the plurality of well regions 22 are each formed in a one-to-one correspondence with the plurality of gate structures 15. The multitude of trough regions 22 are each formed in a band shape that extends along a corresponding gate structure 15 in the top view and are oriented towards a corresponding embedded electrode 18 across a corresponding insulating film 17. Naturally, the multitude of trough regions 22 can be configured in a more-to-one correspondence with respect to the individual gate structure 15. In this case, the multitude of trough regions 22 are spaced apart from each other in the second direction Y. Referring to Fig. 5, Fig. 6, etc., a configuration of the individual well region 22 is described below. The well region 22 is wider than the gate structure 15 in the top view. The well region 22 is formed in a column shape that extends in the thickness direction (vertical direction Z) of the second semiconductor region 7 in the cross-sectional view. The trough region 22 can have a depth that intersects a central section between the bottom section of the second semiconductor region 7 and the bottom wall 15c of the gate structure 15. The trough region 22 can be located at a distance from the central section between the bottom section of the second semiconductor region 7 and the bottom wall 15c of the gate structure 15 in the direction of the first main surface 3. The well region 22 is located at a distance from the bottom section of the second semiconductor region 7 in the direction of the first surface section 8 and faces the first semiconductor region 6 across a section of the second semiconductor region 7. Naturally, the well region 22 can intersect the bottom section of the second semiconductor region 7 and can have a bottom section located within the first semiconductor region 6. The well region 22 forms a pn junction with the second semiconductor region 7. The basin region 22 has a thickness (depth) greater than the thickness (depth) Tb of the body region 20 (see Fig. 9) in this preferred embodiment. The thickness of the basin region 22 is a thickness in the vertical direction Z of the basin region 22 based on the bottom wall 15c of the gate structure 15. In this preferred embodiment, the thickness of the basin region 22 is greater than the depth of the gate structure 15. Of course, the thickness of the basin region 22 can be less than the depth of the gate structure 15. In this case, the thickness of the basin region 22 can be less than the thickness Tb of the body region 20 (see Fig. 9). The basin region 22 has an upper end section along a corner section of the bottom wall 15c of the gate structure 15. The basin region 22 has a first extension section 22a on the side of the first side wall 15a and a second extension section 22b on the side of the second side wall 15b (see Fig. 9) in the upper end section. The first extension section 22a extends from a region directly below the gate structure 15 to a lower end section of the first side wall 15a. The first extension section 22a is located at a distance from the bottom section of the body region 20 in the direction of the bottom wall 15c of the gate structure 15. In this preferred embodiment, the first extension section 22a faces the embedded electrode 18 in a horizontal direction across the insulating film 17. Naturally, the first extension section 22a can be formed on the side of the bottom wall 15c of the trench 16 with respect to a depth position of a lower end section of the embedded electrode 18 and can only face the insulating film 17 (third film section) in a horizontal direction. The first extension section 22a is formed in a tapered shape towards the first main surface 3 (bottom section side of the body region 20) in the cross-sectional view. The second extension section 22b extends from the region directly below the gate structure 15 to a lower end section of the second side wall 15b and faces the first extension section 22a across the gate structure 15. The second extension section 22b is formed at a distance from the bottom section of the body region 20 in the direction of the bottom wall 15c of the gate structure 15. In this preferred embodiment, the second extension section 22b faces the embedded electrode 18 in a horizontal direction across the insulating film 17. Naturally, the second extension section 22b can be formed on the side of the bottom wall 15c of the trench 16 with respect to the depth position of the lower end section of the embedded electrode 18 and can only face the insulating film 17 (third film section) in a horizontal direction. The second extension section 22b is formed in a tapered shape towards the first main surface 3 (bottom section side of the body region 20) in the cross-sectional view. The well region 22 has one or a plurality of (in this preferred embodiment, a plurality of) first bulging sections 22c (see Fig. 8). The well region 22 with four first bulging sections 22c is shown in Fig. 8 as an example. The number of first bulging sections 22c is adjusted accordingly by adapting process conditions. The plurality of first bulging sections 22c are each formed by a section in which the width in the horizontal direction (first direction X) of the well region 22 gradually increases or decreases in the thickness direction, and are formed in a multi-stage manner from the bottom wall 15c of the gate structure 15 towards the bottom section of the second semiconductor region 7. The multitude of first bulging sections 22c extend from the region directly below the gate structure 15 to both sides of the gate structure 15 in an arc shape (circular arc shape). If the basin region 22 has the single first bulging section 22c, the single first bulging section 22c can be configured such that it projects to both sides of the gate structure 15 in an arc shape (circular arc shape) in a central section of the basin region 22. The semiconductor device 1 comprises a plurality of p-type high-concentration well regions 23, each formed within a plurality of well regions 22. The plurality of high-concentration well regions 23 are regions in which the p-type impurity concentration of the well region 22 has been increased and have a p-type impurity concentration that is higher than that of the well region 22. In this preferred embodiment, the high-concentration well region 23 is considered a section of the well region 22. The p-type impurity concentration of the plurality of high-concentration well regions 23 cannot be less than 1 × 10¹⁸ cm⁻³ and cannot be more than 1 × 10²⁰ cm⁻³.The multitude of high-concentration basin regions 23 can be referred to as “high-concentration field relaxation layers”. The multitude of high-concentration basin regions 23 are each formed in a one-to-one correspondence with the multitude of basin regions 22. The multitude of high-concentration basin regions 23 are each formed in a region along the bottom wall 15c of a corresponding gate structure 15. The multitude of high-concentration basin regions 23 are each formed in a band shape that extends along a corresponding gate structure 15 (basin region 22) in plan view and are oriented towards a corresponding embedded electrode 18 across a corresponding insulating film 17. Referring to Fig. 5, Fig. 6, etc., a configuration of the individual high-concentration basin region 23 is described below. The high-concentration basin region 23 is formed at a distance from the bottom section of the basin region 22 in the direction of the bottom wall 15c of the gate structure 15. Preferably, the high-concentration basin region 23 has a bottom section 23a (see Fig. 8 and Fig. 9) which is positioned on the side of the bottom wall 15c of the gate structure 15 with respect to a depth position of the middle section of the basin region 22. The bottom section 23a of the high-concentration basin region 23 is a concentration transition section in which the p-conducting defect concentration gradually decreases towards the bottom section side of basin region 22. Naturally, the bottom section 23a of the high-concentration basin region 23 can be located on the bottom section side of basin region 22 with respect to the depth position of the middle section of basin region 22. The high-concentration basin region 23 is configured such that it is narrower in width than the basin region 22. In this preferred embodiment, the high-concentration basin region 23 is configured such that it is narrower in width than the gate structure 15. Of course, the high-concentration basin region 23 can be wider than the gate structure 15 and can bulge laterally from both sides of the gate structure 15. The high-concentration basin region 23 has a thickness (depth) Tн that is less than the depth of the gate structure 15 (see Fig. 8 and Fig. 9). The thickness Tн of the high-concentration basin region 23 is the thickness in the vertical direction Z of the high-concentration basin region 23 based on, or extending from, the bottom wall 15c of the gate structure 15. The thickness of the high-concentration basin region 23 is less than the thickness of the body region 20. Of course, the thickness of the high-concentration basin region 23 can be greater than the thickness of the body region 20 and can be greater than the depth of the gate structure 15. The semiconductor device 1 comprises a plurality of n-type high-concentration regions 24, each located in regions below the plurality of body regions 20 in the chip 2 (second semiconductor region 7). The plurality of high-concentration regions 24 are regions where the n-type impurity concentration of the second semiconductor region 7 has been increased and has an n-type impurity concentration that is higher than the n-type impurity concentration of the second semiconductor region 7. Each plurality of high-concentration regions 24 can be considered a high-concentration section of the second semiconductor region 7. The n-conducting impurity concentration of the plurality of high-concentration regions 24 cannot be less than 1 × 10¹⁶ cm⁻³ and cannot be more than 1 × 10¹⁹ cm⁻³. For example, the n-conducting impurity concentration of the plurality of high-concentration regions 24 can be compared with the n-conducting impurity concentration on the bottom-side of the second semiconductor region 7 accordingly. The multitude of high-concentration regions 24 are each formed in regions along the multitude of gate structures 15 in the regions below the multitude of body regions 20. In detail, each of the multitude of high-concentration regions 24 is formed within a thickness range between the bottom wall 15c of the multitude of gate structures 15 and the bottom section of the multitude of body regions 20 in a region between the multitude of gate structures 15. Each of the multitude of high-concentration regions 24 extends in a band shape along the multitude of gate structures 15 in the top view. Referring to Figures 5 and 6, a configuration of the individual high-concentration region 24 is described below. In this preferred embodiment, the high-concentration region 24 is formed in a layered form extending in the first direction X in the cross-sectional view and is connected to one or both (in this preferred embodiment, both) of the mutually adjacent plurality of gate structures 15. The high-concentration region 24 faces the embedded electrodes 18 of the plurality of gate structures 15 across the insulating films 17 of the plurality of gate structures 15. The high-concentration region 24 faces the source region 21 across a section of the body region 20 in the thickness direction. In this preferred embodiment, the high-concentration region 24 faces the source region 21 in a one-to-one correspondence in the thickness direction. The high-concentration region 24 is located at a distance from the bottom section of the second semiconductor region 7 in the direction of the first main surface 3 and faces the first semiconductor region 6 across a section of the second semiconductor region 7. The multitude of high concentration regions 24 may have an n-conducting impurity concentration that is essentially the same, or may have n-conducting impurity concentrations that differ from each other. The semiconductor device 1 comprises a plurality of medium-concentration n-type regions (drift regions) 25, each located in regions below the plurality of high-concentration regions 24 in the chip 2 (second semiconductor region 7). The plurality of medium-concentration regions 25 are regions where the n-type impurity concentration of the second semiconductor region 7 has been increased and have an n-type impurity concentration that is higher than the n-type impurity concentration of the second semiconductor region 7 and lower than the n-type impurity concentration of the high-concentration region 24. The plurality of medium-concentration regions 25 can be considered high-concentration sections of the second semiconductor region 7. The n-conducting impurity concentration of the plurality of medium-concentration regions 25 cannot be less than 1 × 10¹⁵ cm⁻³ and cannot be more than 1 × 10¹⁷ cm⁻³. For example, the n-conducting impurity concentration of the plurality of medium-concentration regions 25 can be compared with the n-conducting impurity concentration on the bottom-side of the second semiconductor region 7. The medium-concentration region 25 can be referred to as the "medium-concentration drift region". The plurality of medium-concentration regions 25 are each formed within a thickness range between the bottom section of the second semiconductor region 7 and the bottom section of the high-concentration regions 24 in a region between the plurality of gate structures 15. Each of the plurality of medium-concentration regions 25 has a section that is inserted in a region between the plurality of trough regions 22. In this preferred embodiment, each of the plurality of medium-concentration regions 25 has a section that is inserted in the region of the plurality of gate structures 15. Each of the plurality of medium concentration regions 25 extends in a band shape along the plurality of gate structures 15 in the top view. In this preferred embodiment, the plurality of medium concentration regions 25 are connected to one or both (in this preferred embodiment, both) of the trough regions 22 with respect to the two mutually adjacent trough regions 22. Referring to Fig. 5 and Fig. 6, a configuration of the individual region with average concentration 25 is described below. The region with average concentration 25 is formed at a distance from the bottom section of the second semiconductor region 7 in the direction of the first main surface 3 and faces the first semiconductor region 6 across a section of the second semiconductor region 7. The region with medium concentration 25 has an upper end section that is positioned at an upper level relative to the depth of the bottom wall 15c of the gate structure 15. The upper end section of the region with medium concentration 25 is located in a region between the multiple gate structures 15 and faces the gate structure 15 across the upper end section (first extension section 22a and second extension section 22b) of the basin region 22. The upper end section of the region with medium concentration 25 may have a section that is connected to the gate structure 15. The medium concentration region 25 has a bottom section located at a lower position relative to the depth of the bottom wall 15c of the gate structure 15. Specifically, the bottom section of the medium concentration region 25 is positioned at a distance from the bottom section of the basin region 22 in the direction of the first main surface 3. Preferably, the bottom section of the medium concentration region 25 is located closer to the bottom section of the basin region 22 than to the bottom section of the high concentration basin region 23. The semiconductor device 1 comprises a plurality of channel regions 26 (see Fig. 9), each formed between the plurality of source regions 21 and the plurality of high-concentration regions 24 in the plurality of body regions 20. The inversion and non-inversion of the plurality of channel regions 26 are controlled by the gate structure 15. The plurality of channel regions 26 form current paths that connect the plurality of source regions 21 and the plurality of high-concentration regions 24 along the sidewalls (first sidewall 15a and second sidewall 15b) of the plurality of gate structures 15 in the plurality of body regions 20. Referring to Fig. 4, Fig. 5, and Fig. 8, the semiconductor device 1 comprises a plurality of p-type first contact regions 27, each located in regions along the plurality of gate structures 15 in the surface layer section of the first main surface 3 (first surface section 8). The plurality of first contact regions 27 have a p-type impurity concentration that is higher than the p-type impurity concentration of the plurality of body regions 20. The p-type impurity concentration of the plurality of first contact regions 27 is higher than the p-type impurity concentration of the plurality of well regions 22. The p-type impurity concentration of the plurality of first contact regions 27 cannot be less than 1 × 10¹⁷ cm⁻³ and cannot be more than 1 × 10¹⁹ cm⁻³. The multitude of first contact regions 27 are each formed in a region between the multitude of gate structures 15. The multitude of first contact regions 27 are each formed on both sides of the multitude of gate structures 15. The multitude of first contact regions 27 are arranged at a distance in the second direction Y along the multitude of gate structures 15 and are each formed in a band shape extending in the second direction Y. The multitude of first contact regions 27 overlap at the multitude of body regions 20 and increase the p-conducting defect concentration of the multitude of body regions 20. With respect to each of the first contact regions 27 located on either side of the individual gate structure 15, the other first contact region 27 faces the first contact region 27 across the gate structure 15. The multitude of first contact regions 27 are arranged in a matrix-like pattern in the top view. With respect to the second direction Y, the length and spacing of the plurality of first contact regions 27 are adjusted according to the required channel area. The channel area corresponds to the total area of ​​the plurality of source regions 21. The length in the second direction Y of the first contact region 27 can be greater than the width in the first direction X of the gate structure 15. Conversely, the length of the first contact region 27 can be less than the width of the gate structure 15. The length-to-width ratio of the first contact region 27 to the gate structure 15 must be at least 0.5 and at most 10. The spacing ratio of the first contact region 27 to its length must be at least 1 and at most 50. Referring to Figures 5 and 8, a configuration of the individual first contact region 27 is described below. The first contact region 27 is formed in a layered form that extends horizontally along the first main surface 3 and is connected to one or both (in this preferred embodiment, both) of the mutually adjacent plurality of gate structures 15. The first contact region 27 faces the embedded electrodes 18 of the plurality of gate structures 15 across the insulating films 17 of the plurality of gate structures 15. The first contact region 27 has a thickness greater than that of the source region 21 and has a bottom section that is positioned closer to the bottom section of the second semiconductor region 7 than to the bottom section of the source region 21. The bottom section of the first contact region 27 is located on the bottom section side of the body region 20 with respect to the depth position of the bottom section of the recess of the embedded electrode 18. In this preferred embodiment, the first contact region 27 has a thickness greater than the thickness Tв of the body region 20 (see Fig. 9) and has a bottom section that is located closer to the bottom section of the second semiconductor region 7 than to the bottom section of the body region 20. The bottom section of the first contact region 27 is a concentration transition region in which the p-type impurity concentration gradually decreases towards the bottom section side of the second semiconductor region 7. The base section of the first contact region 27 can be located closer to the first main surface 3 than to the depth position of the bottom wall 15c of the gate structure 15 (see Fig. 8). In this case, the first contact region 27 can have a thickness less than the thickness of the body region 20 and can have a base section located closer to the side of the first main surface 3 than to the base section of the body region 20. The first contact region 27 can face the high-concentration region 24 across a section of the body region 20. The bottom section of the first contact region 27 is positioned closer to the bottom section of the second semiconductor region 7 than to the depth position of the bottom wall 15c of the gate structure 15 (see Fig. 8) in this preferred embodiment. In this preferred embodiment, the first contact region 27 overlaps with part or all of the high-concentration region 24 in the cross-sectional view. The first contact region 27 replaces the n-type impurity concentration of part or all of the high-concentration region 24 with the p-type impurity concentration. Therefore, the p-type impurity concentration of the bottom section of the first contact region 27 is reduced relative to the n-type impurity concentration of the high-concentration region 24. The first contact region 27 has a bottom section that intersects the bottom section of the high-concentration region 24 and is located in the medium-concentration region 25 in this preferred embodiment. Therefore, the first contact region 27 also replaces the n-conducting impurity concentration of a portion of the medium-concentration region 25 with the p-conducting impurity concentration. Preferably, the bottom section of the first contact region 27 is located closer to the first main surface 3 than to the depth position of the middle section of the trough region 22. The bottom section of the first contact region 27 overlaps with the upper end section of the well region 22 in a region that is closer to the bottom section of the second semiconductor region 7 than the depth position of the bottom wall 15c of the gate structure 15. Thus, the first contact region 27 electrically connects the well region 22 to the body region 20. Referring to Fig. 8, the first contact region 27 has a high-concentration section 27a on the side of the first main surface 3 and a low-concentration section 27b on the bottom section side of the second semiconductor region 7 in this preferred embodiment. The high-concentration section 27a is located closer to the first main surface 3 than at least the depth position of the bottom wall 15c of the gate structure 15 and forms a main body section of the first contact region 27. The high-concentration section 27a extends in a layered form in the horizontal direction along the first main surface 3. The low-concentration section 27b is located on the bottom side of the second semiconductor region 7 with respect to the high-concentration section 27a and forms the bottom of the first contact region 27. The low-concentration section 27b is also a region where the p-type impurity concentration is reduced by the n-type impurity concentration of the high-concentration region 24. The low-concentration section 27b has a smaller thickness than the high-concentration section 27a and extends in a layered form in the horizontal direction along the high-concentration section 27a. The low-concentration section 27b intersects the depth position of the bottom wall 15c of the gate structure 15 in the thickness direction. The low-concentration section 27b has a portion that is located closer to the first principal surface 3 than the depth position of the bottom wall 15c of the gate structure 15, and a portion that is located closer to the bottom portion of the second semiconductor region 7 than the depth position of the bottom wall 15c of the gate structure 15. The low-concentration section 27b overlaps with the upper end portions of the plurality of well regions 22 and is electrically connected to the plurality of well regions 22. Referring to Fig. 7, the gate structure 15 comprises a first section 15P, enclosed between the first contact regions 27 in the first direction X in the plan view, and a second section 15Q, enclosed between the source regions 21 in the first direction X in the plan view. The first section 15P and the second section 15Q are arranged alternately in the second direction Y. The first section 15P and the adjacent second section 15Q are continuous with each other. In the first section 15P of the gate structure 15, no channel region is formed on the side wall of the gate structure 15 (first side wall 15a and second side wall 15b), as shown in Fig. 8. On the other hand, in the second section 15Q of the gate structure 15, the channel region 26 is formed on the side wall of the gate structure 15 (first side wall 15a and second side wall 15b), as shown in Fig. 9. The first section 15P of the gate structure 15 is a section in which the channel region 26 is not formed, and the second section 15Q of the gate structure 15 is a section in which the channel region 26 is formed. Referring to Figures 7 and 8, a first lower region (lower non-channel region) 61 is formed below the first section 15P of the gate structure 15 (section in which the channel region 26 is not formed) in the region with medium concentration 25 and in the second semiconductor region 7. A second contact region 28 is formed in the first lower region 61 in this preferred embodiment. The well region 22 is formed in the first lower region 61. Referring to Fig. 7 and Fig. 9, a second lower region (lower channel region) 62 is formed below the second section 15Q of the gate structure 15 (section in which the channel region 26 is formed) in the region with medium concentration 25 and in the second semiconductor region 7. The second contact region 28 is not formed in the second lower region 62 in this preferred embodiment. The depth of the well region 22 of the second lower region 62 is less than the depth of the well region 22 of the first lower region 61. Referring to Figs. 7, 8 to 9, the basin region 22 comprises a first basin region 51 and a second basin region 53, which differ in the depth position of the bottom section. The first basin region 51 and the second basin region 53 are formed alternately in the second direction Y. The first basin region 51 and the adjacent second basin region 53 are continuous with each other in the second direction Y. The first well region 51 has a first bottom section 52. The first bottom section 52 is located in the second semiconductor region 7 and extends through the medium concentration region 25. The first bottom section 52 is located at a lower position relative to bottom section 23a of the high concentration well region 23. The first bottom section 52 is located at a lower position relative to bottom section 28d of the second contact region 28. The first bottom section 52 has a first depth D1 (see Fig. 8). The first depth D1 is the depth of the first bottom section 52 of the first trough region 51 based on or extending from the bottom wall 15c of the gate structure 15. The first depth D1 (see Fig. 8) is greater than the thickness Tв of the body region 20 (see Fig. 9) (D1 > Tв). Referring to Figures 7 and 8, the first trough region 51 is formed in the first lower region 61 below the second section 15Q of the gate structure 15. Specifically, the first trough region 51 extends across the entire area in the second direction Y within the first lower region 61. In this preferred embodiment, the second trough region 53 is not formed in the first lower region 61. Referring to Fig. 7, the first trough region 51 is formed at a distance W1 from the adjacent first trough region 51. The first distance W1 can be equal to the length in the second direction Y of the first contact region 27. The first distance W1 can be greater than the width in the first direction X of the gate structure 15. Naturally, the first distance W1 can be less than the length of the first contact region 27 and the width of the gate structure 15. The length ratio of the first distance W1 to the width in the first direction X of the gate structure 15 cannot be less than 0.5 and cannot be more than 10. Referring to Fig. 8, the first basin region 51 has one or a plurality of (in this preferred embodiment, a plurality of) first bulging sections 22c. In the example of Fig. 8, the first basin region 51 does not include either the first extension section 22a (see Fig. 9) or the second extension section 22b (see Fig. 9). Of course, the first basin region 51 can include both the first extension section 22a and the second extension section 22b. Referring to Fig. 7 and Fig. 9, the second basin region 53 has a second bottom section 54. The second basin region 53 has a second depth D2 (see Fig. 9). The second bottom section 54 is located in the medium concentration region 25. The second bottom section 54 is positioned lower than the bottom section 23a of the high concentration basin region 23. The second depth D2 (see Fig. 9) is less than the thickness Tb of the body region 20 (see Fig. 9) (D2 < Tb). Of course, the second depth D2 can be equal to or greater than the thickness Tb of the body region 20 (D2 ≥ Tb). The second soil section 54 of the second basin region 53 is located on the side of the first main surface 3 with respect to soil section 28d of the second contact region 28. The second soil section 54 of the second basin region 53 is located on the side of the first main surface 3 with respect to the depth position of the middle section of the region with medium concentration 25. Of course, the second soil section 54 of the second basin region 53 can also be located on the side of the second main surface 4 with respect to the depth position of the middle section of the region with medium concentration 25. The second floor section 54 of the second basin region 53 is located closer to the second main surface 4 than to floor section 23a of the high-concentration basin region 23. Floor section 23a of the high-concentration basin region 23 is located closer to the floor wall 15c of the gate structure 15 than to the second floor section 54 of the second basin region 53. A second distance W2 in the thickness direction between the second floor section 54 of the second basin region 53 and floor section 23a of the high-concentration basin region 23 is less than the thickness Tн of the high-concentration basin region 23. Of course, the second distance W2 can be equal to or greater than the thickness Tн of the high-concentration basin region 23. Referring to Fig. 7 and Fig. 9, the second trough region 53 is formed in the second lower region 62 below the second section 15Q of the gate structure 15. Specifically, the second trough region 53 extends across the entire area in the second direction Y within the second lower region 62. The first trough region 51 is not formed in the second lower region 62. Referring to Fig. 7, the medium concentration region 25 and the second semiconductor region 7 comprise an enclosed section (part) 7a, which is enclosed between the adjacent first well regions 51 in the second direction Y. The adjacent first well regions 51 in the second direction Y face each other across the enclosed section 7a in the second direction Y. The plurality of enclosed sections 7a are spaced apart from each other in the second direction Y. The length in the second direction Y of the enclosed section 7a corresponds to the first distance W1 between the adjacent first well regions 51. The enclosed section 7a has a flat top surface. The semiconductor device 1 comprises a plurality of p-type second contact regions 28, each formed in regions along the bottom walls 15c of the plurality of gate structures 15 in the chip 2. The plurality of second contact regions 28 have a p-type impurity concentration that is higher than the p-type impurity concentration of the plurality of body regions 20. The p-type impurity concentration of the plurality of second contact regions 28 is higher than the p-type impurity concentration of the plurality of well regions 22. In this preferred embodiment, the second contact region 28 is contained in the first well region 51 and is not contained in the second well region 53. The p-type impurity concentration of the plurality of second contact regions 28 cannot be less than 1 × 10¹⁸ cm⁻³ and cannot be more than 1 × 10²⁰ cm⁻³. Preferably, the p-type impurity concentration of the plurality of second contact regions 28 is substantially equal to the p-type impurity concentration of the plurality of first contact regions 27. The plurality of second contact regions 28 are each formed in a more-to-one correspondence relationship with respect to the bottom wall 15c of the plurality of gate structures 15. The plurality of second contact regions 28 are each inserted in a region between the adjacent first contact regions 27 in the first direction X in the plan view. The plurality of second contact regions 28 are placed on the same straight line as the plurality of first contact regions 27 in the first direction X. The plurality of second contact regions 28 are each formed in a band shape extending along a corresponding gate structure 15 in the top view and facing the embedded electrode 18 across the insulating film 17. With respect to the second direction Y, the length of the plurality of second contact regions 28 is essentially equal to the length of the plurality of first contact regions 27. With respect to the second direction Y, the spacing between the plurality of second contact regions 28 is essentially equal to the spacing between the plurality of first contact regions 27. Referring to Figs. 5 and 8, a configuration of the individual second contact region 28 is described below. The second contact region 28 is formed in a corresponding basin region 22 (first basin region 51). The high-concentration basin region 23 overlaps with the second contact region 28, and the latter is electrically connected to the high-concentration basin region 23 in basin region 22. The second contact region 28 is formed at an inward distance from the peripheral edge section of basin region 22. The second contact region 28 has the bottom section 28d. Referring to Fig. 8, the second contact region 28 is formed at a distance from the bottom section of the well region 22 in the direction of the bottom wall 15c of the gate structure 15 and faces the bottom section of the second semiconductor region 7 across a section of the well region 22. Each second contact region 28 is formed in a column shape that extends in the thickness direction (in the vertical direction Z) of the second semiconductor region 7 in the cross-sectional view. The second contact region 28 has a bottom section which, in this preferred embodiment, is positioned closer to the bottom section of the basin region 22 than to the thickness position of the middle section of the basin region 22. Of course, the bottom section of the second contact region 28 can also be positioned closer to the bottom wall 15c of the gate structure 15 than to the thickness position of the middle section of the basin region 22. The second contact region 28 has an upper end section along the corner section of the bottom wall 15c of the gate structure 15. The second contact region 28 is electrically connected in its upper end section to the plurality of first contact regions 27. The second contact region 28 electrically connects the trough region 22 and the high-concentration trough region 23 to the body region 20 through the plurality of first contact regions 27. The second contact region 28 has a first extension section 28a on the side of the first side wall 15a and a second extension section 28b on the side of the second side wall 15b. The first extension section 28a extends from the region directly below the gate structure 15 to the lower end section of the first side wall 15a. The first extension section 28a faces the embedded electrode 18 across the insulating film 17 in the horizontal direction. The first extension section 28a is connected to the first contact region 27 in a region along the first side wall 15a. Specifically, the first extension section 28a is connected to both the high-concentration section 27a and the low-concentration section 27b of the first contact region 27. The second extension section 28b extends from the region directly below the gate structure 15 to the lower end section of the second side wall 15b and faces the first extension section 28a across the gate structure 15. The second extension section 28b faces the embedded electrode 18 across the insulating film 17 in the horizontal direction. The second extension section 28b is connected to the first contact region 27 in a region along the second side wall 15b. Specifically, the second extension section 28b is connected to both the high-concentration section 27a and the low-concentration section 27b of the first contact region 27. The second contact region 28 has one or a plurality of (in this preferred embodiment, a plurality of) second bulging sections 28c. Figure 8 shows the second contact region 28 with two second bulging sections 28c as an example. The number of second bulging sections 28c is adjusted accordingly by adapting process conditions. The plurality of second bulging sections 28c are each formed by a section in which the width in the horizontal direction (first direction X) of the second contact region 28 gradually increases or decreases in the thickness direction, and are formed in a multi-stage manner from the bottom wall 15c of the gate structure 15 towards the bottom section of the second semiconductor region 7. Referring to Fig. 2, the semiconductor device 1 comprises a main surface insulating film 30 covering the first main surface 3. The main surface insulating film 30 selectively covers the first surface section 8, the second surface section 9, and the first to fourth interconnect surface sections 10A to 10D. The main surface insulating film 30 is bonded to the insulating films 17 of the plurality of gate structures 15 in the first surface section 8 and exposes the embedded electrodes 18 of the plurality of gate structures 15. The main surface insulating film 30 can comprise at least one silicon oxide film, one silicon nitride film, and one silicon oxynitride film. In this preferred embodiment, the main surface insulating film 30 has a single-layer structure consisting of a silicon oxide film. Particularly preferably, the main surface insulating film 30 comprises a silicon oxide film consisting of the oxide of the chip 2. Referring to Fig. 2, the semiconductor device 1 comprises an insulating interlayer film 31 covering the main surface insulating film 30. The interlayer film 31 can be referred to as an “insulating film”, an “interlayer insulating film”, an “intermediate insulating film”, etc. The interlayer film 31 selectively covers the first surface section 8, the second surface section 9, and the first to fourth interconnect surface sections 10A to 10D across the main surface insulating film 30. The interlayer film 31 covers the plurality of gate structures 15 in the first surface section 8. In this preferred embodiment, the interlayer film 31 extends continuously through the peripheral edge region of the second surface region 9 to the first to fourth side surfaces 5A to 5D. Naturally, the interlayer film 31 can be formed at an inward distance from the peripheral edge of the second surface region 9 and can expose the second semiconductor region 7 from the peripheral edge region of the second surface region 9. The interlayer film 31 can comprise at least one silicon oxide film, one silicon nitride film, and one silicon oxynitride film. Preferably, the interlayer film 31 comprises a silicon oxide film. The interlayer film 31 can have a thickness of not less than 0.5 µm and not more than 3 µm. The thickness of the interlayer film 31 can be a value that falls within at least one of the following ranges: not less than 0.5 µm and not more than 1 µm, not less than 1 µm and not more than 1.5 µm, not less than 1.5 µm and not more than 2 µm, not less than 2 µm and not more than 2.5 µm, and not less than 2.5 µm and not more than 3 µm. Referring to Fig. 5 et seq., the semiconductor device 1 comprises a plurality of source openings 32 formed in the interlayer film 31. The plurality of source openings 32 are each formed in a region between the plurality of gate structures 15 and expose the plurality of source regions 21 and the plurality of first contact regions 27. The plurality of source openings 32 extend in a band shape in the second direction Y along the plurality of gate structures 15. Preferably, each of the plurality of source openings 32 has an opening end that is curved in a circular arc shape. The plurality of source openings 32 can be arranged at a distance from one another in the second direction Y in a region between the adjacent gate structures 15. In this case, the plurality of source openings 32 can be configured in a square shape, a rectangular shape (ribbon shape), a circular shape, etc., in the top view. Referring to Fig. 3, the semiconductor device 1 comprises a plurality of gate openings 33 formed in the interlayer film 31. In this preferred embodiment, each of the plurality of gate openings 33 selectively exposes both end sections of a corresponding gate structure 15. In detail, each of the plurality of gate openings 33 selectively exposes both end sections of the embedded electrode 18 of a corresponding gate structure 15. Preferably, each of the plurality of gate openings 33 has an opening end that is curved in a circular arc shape in the same way as the source opening 32. The plurality of gate openings 33 can be configured in a square shape, a rectangular shape (ribbon shape), a circular shape, etc., in a top view. Referring to Fig. 1, Fig. 2, Fig. 5, etc., the semiconductor device 1 comprises a source electrode 35 arranged on the first main surface 3. The source electrode 35 is a terminal electrode to which a source potential is applied externally. The source electrode 35 is arranged on a section of the interlayer film 31 that covers the first surface section 8. In this preferred embodiment, the source electrode 35 has a first pad section 35a, a second pad section 35b, and a third pad section 35c. The first pad section 35a has a comparatively large planar surface and forms a main body of the source electrode 35. In this preferred embodiment, the first pad section 35a is formed in a polygonal shape (in this preferred embodiment, a quadrilateral shape) with four sides parallel to the peripheral edges of the chip 2 in the top view and is displaced towards the side of the fourth side surface 5D with respect to a central section of the first surface section 8. The second pad section 35b has a smaller surface area than the surface area of ​​the first pad section 35a and extends in a band shape (quadrilateral shape) from one end section (end section on the side of the first face 5A) in the second direction Y of the first pad section 35a towards the third face 5C. The third pad section 35c has a smaller surface area than the surface area of ​​the first pad section 35a and extends in a band shape (quadrilateral shape) from the other end section (end section on the side of the second face 5B) in the second direction Y of the first pad section 35a towards the third face 5C and faces the second pad section 35b in the second direction Y. The flat surface area of ​​the third pad section 35c can be substantially equal to the flat surface area of ​​the second pad section 35b. Of course, the flat surface area of ​​the third pad section 35c can be larger than the flat surface area of ​​the second pad section 35b, and it can be smaller than the flat surface area of ​​the second pad section 35b. One or both of the second pad section 35b and the third pad section 35c can be used as connection sections for current monitoring. The source electrode 35 can have only one of the second pad section 35b and one of the third pad section 35c. Naturally, the source electrode 35 can consist only of the first pad section 35a and have neither the second pad section 35b nor the third pad section 35c. The source electrode 35 enters the plurality of source openings 32 of the interlayer film 31 from above and is connected to the first principal surface 3 (first surface section 8) in the plurality of source openings 32. The source electrode 35 is electrically connected to the plurality of source regions 21 and to the plurality of first contact regions 27 in the plurality of source openings 32. Referring to Fig. 5, etc., the source electrode 35 in this preferred embodiment has a laminated structure comprising a lower electrode film 36 and a main electrode film 37, which are laminated to the side of the chip 2 in that order. The lower electrode film 36 in this preferred embodiment has a laminated structure comprising a first electrode film 38 and a second electrode film 39. The first electrode film 38 comprises a Ti film, and the second electrode film 39 comprises a TiN film in this preferred embodiment. It is not necessary for the lower electrode film 36 to have a laminated structure, and it may have a single-layer structure consisting of one of the first electrode films 38 (Ti film) and the second electrode film 39 (TiN film). The first electrode film 38 has a lesser thickness than the thickness of the intermediate film 31.The thickness of the first electrode film 38 cannot be less than 10 nm and cannot be more than 100 nm. The second electrode film 39 has a smaller thickness than the thickness of the intermediate film 31. Preferably, the thickness of the second electrode film 39 is greater than the thickness of the first electrode film 38. The thickness of the second electrode film 39 cannot be less than 50 nm and cannot be more than 200 nm. The first electrode film 38 collectively covers a region of the interlayer film 31 in which the plurality of source openings 32 are formed, and enters the plurality of source openings 32 of the interlayer film 31 from above. The first electrode film 38 has a section that covers an insulating main surface of the interlayer film 31, a section that covers the wall surfaces of the plurality of source openings 32, and a section that covers the first main surface 3 in the plurality of source openings 32. The first electrode film 38 covers the first main surface 3 (first surface section 8) in the source opening 32 and is mechanically and electrically connected to the plurality of source regions 21 and to the plurality of first contact regions 27 on the first main surface 3. The second electrode film 39 directly covers the first electrode film 38. The second electrode film 39 collectively covers, in a film-like form, the region of the interlayer film 31 in which the plurality of source openings 32 are formed across the first electrode film 38, and enters the plurality of source openings 32 of the interlayer film 31 from above. The second electrode film 39 has a section that, in a film-like form, covers the insulating main surface of the interlayer film 31 across the first electrode film 38, a section that, in a film-like form, covers the wall surfaces of the plurality of source openings 32 across the first electrode film 38, and a section that, in a film-like form, covers the first main surface 3 across the first electrode film 38 in the plurality of source openings 32.The second electrode film 39 covers the first main surface 3 (first surface section 8) over the first electrode film 38 in the source opening 32 in a film form and is electrically connected to the plurality of source regions 21 and to the plurality of first contact regions 27 through the first electrode film 38. The main electrode film 37 comprises a conductive material that differs from the lower electrode film 36 (first electrode film 38 and second electrode film 39). The main electrode film 37 can comprise at least one Al film, one Al alloy film, one Cu film, and one Cu alloy film. The Al alloy film can comprise at least one AlSi alloy film, one AlCu alloy film, and one AlSiCu alloy film. The main electrode film 37 has a greater thickness than the thickness (total thickness) of the lower electrode film 36. Preferably, the thickness of the main electrode film 37 is greater than the thickness of the intermediate film 31. The thickness of the main electrode film 37 cannot be less than 0.5 µm and cannot be more than 5 µm. The main electrode film 37 directly covers the lower electrode film 36 (second electrode film 39). The main electrode film 37 fills the plurality of source openings 32 and collectively covers, in a film form, the region of the intermediate film 31 in which the plurality of source openings 32 are formed. The main electrode film 37 has a section that covers the insulating main surface of the intermediate film 31 across the lower electrode film 36, a section that covers the wall surfaces of the plurality of source openings 32 across the lower electrode film 36, and a section that covers the first main surface 3 across the lower electrode film 36.The main electrode film 37 covers the first main surface 3 (first surface section 8) over the lower electrode film 36 in the source opening 32 and is electrically connected to the plurality of source regions 21 and to the plurality of first contact regions 27 through the lower electrode film 36. Referring to Fig. 1 and Fig. 2, the semiconductor device 1 comprises a gate electrode 40 arranged on the first main surface 3. The gate electrode 40 is a terminal electrode to which a gate potential is applied externally. The gate electrode 40 comprises the lower electrode film 36 and the main electrode film 37, which are laminated in that order from the side of the chip 2 in the same manner as the source electrode 35, although not shown. The gate electrode 40 is arranged at a distance from the source electrode 35 on a section of the interlayer film 31 that covers the first surface section 8. The gate electrode 40 is located in a region on the side of the third face 5C with respect to the first pad section 35a and faces the first pad section 35a in the first direction X in this preferred embodiment. Additionally, the gate electrode 40 is inserted in a region between the second pad section 35b and the third pad section 35c and faces both the second pad section 35b and the third pad section 35c in the second direction Y. The gate electrode 40 is formed in a polygonal shape (in this preferred embodiment, a quadrilateral shape) with four sides parallel to the peripheral edges of the chip 2 in the top view. The gate electrode 40 has a smaller planar area than the planar area of ​​the source electrode 35. The gate electrode 40 has a smaller planar area than the planar area of ​​the first pad section 35a. The gate electrode 40 may have a smaller planar area than the planar area of ​​the second pad section 35b (third pad section 35c). The gate electrode 40 is partially oriented towards the plurality of gate structures 15 across the interlayer film 31. Specifically, the gate electrode 40 is positioned at an inward distance from both end sections of the plurality of gate structures 15 and is oriented towards an inner section (in this preferred embodiment, a central section) of the plurality of gate structures 15 across the interlayer film 31. In this preferred embodiment, the gate electrode 40 has no direct electrical connection point with respect to the plurality of gate structures 15. Of course, the gate electrode 40 can be electrically connected to the plurality of gate structures 15 through the plurality of gate openings 33. Referring to Fig. 1, the semiconductor device 1 comprises a gate wiring 41 extending from the gate electrode 40 to the first main surface 3. The gate wiring 41 transmits the gate potential applied to the gate electrode 40 to other regions. The gate wiring 41 comprises the lower electrode film 36 and the main electrode film 37, which are laminated from the side of the chip 2 in that order in the same manner as the source electrode 35 (gate electrode 40), although not shown. Referring to Fig. 1, the gate wiring 41 extends from the gate electrode 40 onto a section of the interlayer film 31 covering the first surface section 8. The gate wiring 41 is arranged in a ribbon form to a region between the peripheral edge of the first surface section 8 and the source electrode 35. The gate wiring 41 has a section extending in a ribbon form in the first direction X and a section extending in a ribbon form in the second direction Y in the top view. The gate wiring 41 is arranged in a ribbon form with ends having four sides parallel to the peripheral edges of the first main surface 3 and surrounds the source electrode 35 in this preferred embodiment.The gate wiring 41 enters the plurality of gate openings 33 of the interlayer film 31 from above and is mechanically and electrically connected to the end section (both end sections) of the plurality of gate structures 15 in the plurality of gate openings 33. Thus, the gate potential applied to the gate electrode 40 is applied to the plurality of gate structures 15 via the gate wiring 41. Referring to Fig. 2, Fig. 5, etc., the semiconductor device 1 comprises a drain electrode 42 covering the second main surface 4. The drain electrode 42 is a terminal electrode to which a drain potential is applied externally. The drain electrode 42 is electrically connected to the first semiconductor region 6. The drain electrode 42 can cover the entire area of ​​the second main surface 4 such that it extends through the peripheral edges of the second main surface 4 (first to fourth side faces 5A to 5D). The drain electrode 42 can also partially cover the second main surface 4, exposing the peripheral edge section of the second main surface 4. The breakdown voltage applicable between the source electrode 35 and the drain electrode 42 (between the first main surface 3 and the second main surface 4) must be no less than 500 V and no more than 3000 V. The breakdown voltage can fall within at least one of the following ranges: no less than 500 V and no more than 1000 V, no less than 1000 V and no more than 1500 V, no less than 1500 V and no more than 2000 V, no less than 2000 V and no more than 2500 V, and no less than 2500 V and no more than 3000 V. Therefore, according to the preferred embodiment of this disclosure, the semiconductor device 1 comprises the chip 2, the n-type second semiconductor region 7, the trench-type gate structure 15, and the p-type well region 22. The chip 2 has the first main surface 3. The second semiconductor region 7 is formed on the surface layer portion of the first main surface 3. The gate structure 15 is formed on the first main surface 3 and is located in the second semiconductor region 7. The well region 22 is formed in the region (first lower region 61 and second lower region 62) below the gate structure 15 in the second semiconductor region 7. The well region 22 is formed along the second direction Y. If the entire area of ​​the trough region 22 has the same first depth D1 (see Fig. 11) in the same way as a semiconductor device 101 according to a reference example shown in Fig. 10 and Fig. 11, there is concern that the current path of the JFET will be pressed and that the resistance (on-resistance or JFET resistance) will increase. On the other hand, in this preferred embodiment, the basin region 22 comprises the plurality of first basin regions 51, each having a first bottom section 52 with a first depth D1. The plurality of first basin regions 51 are arranged at a distance W1 from each other in the second direction Y. The adjacent first basin regions 51 face each other in the second direction Y across the enclosed section 7a, as shown in Fig. 7. The first trough region 51 is formed in the region (first lower region 61) below the gate structure 15. An increase in current density near the bottom wall 15c of the gate structure 15 is suppressed by the first trough region 51. This allows the electric field to be relaxed with respect to the bottom wall 15c of the gate structure 15, thereby suppressing a decrease in dielectric strength due to the concentration of the electric field. Additionally, the enclosed section 7a, which is part of both the medium concentration region 25 and the second semiconductor region 7, is inserted between the adjacent first well regions 51. This enclosed section 7a acts as a current path. Therefore, it is possible to adequately ensure the current path in the region (first lower region 61) below the gate structure 15. This allows for a reduction in the on-resistance and the JFET resistance. Therefore, it is possible to reduce the resistance while suppressing a decrease in dielectric strength. In other words, the semiconductor device 1 is provided, which is capable of improving the electrical properties. Preferably, the chip comprises 2 SiC components. With this configuration, the semiconductor device 1 is provided as a SiC semiconductor device capable of improving electrical properties. The trough region 22 can comprise the first trough region 51 and the second trough region 53, which differ in depth within the bottom section in the region (first lower region 61 and second lower region 62) below the gate structure 15. The first trough region 51 and the second trough region 53 can be continuous with each other. In this configuration, the first trough region 51 and the second trough region 53 are each formed in the regions (first lower region 61 and second lower region 62) below the gate structure 15. An increase in current density near the bottom wall 15c of the gate structure 15 is suppressed by both the first trough region 51 and the second trough region 53. This allows the electric field to relax with respect to the bottom wall 15c of the gate structure 15, thereby suppressing a decrease in dielectric strength due to the concentration of the electric field.Therefore, it is possible to reduce the resistance (one-resistor or JFET resistor) while further suppressing a decrease in dielectric strength. The second trough region 53 can have a second depth D2, which is less than the first depth D1. With this configuration, it is possible to relax an electric field with respect to the bottom wall 15c of the gate structure 15, which further suppresses a decrease in dielectric strength due to the concentration of the electric field. The ratio (D2 / D1) of the second depth D2 of the second bottom section 54 of the second basin region 53 with respect to the first depth D1 of the first bottom section 52 of the first basin region 51 can be less than 0.5. With this configuration, the second depth D2 of the second bottom section 54 of the second basin region 53 is sufficiently small, and therefore it is possible to largely secure a thickness Tu (see Fig. 7) of the enclosed section 7a formed below the second basin region 53. This makes it possible to secure the current path even more adequately. The first bottom section 52 of the first basin region 51 can have a first depth D1 that is greater than the thickness Tb of the body region 20. The second basin region 53 can have a second depth D2 that is less than the thickness Tb of the body region 20. With this configuration, the second depth D2 of the second bottom section 54 of the second basin region 53 is sufficiently small, and therefore it is possible to largely secure the thickness Tu (see Fig. 7) of the enclosed section 7a formed below the second basin region 53. This allows for even more adequate securing of the current path. The first bottom section 52 of the first well region 51 can penetrate the region of medium concentration 25 and can be located in the second semiconductor region 7. The second well region 53 can have the second bottom section 54, which is located in the region of medium concentration 25. With this configuration, the second depth D2 of the second bottom section 54 of the second well region 53 is sufficiently small, and therefore it is possible to largely secure the thickness Tu (see Fig. 7) of the enclosed section 7a formed below the second well region 53. This allows for even more adequate security of the current path. Additionally, in this preferred embodiment, the enclosed section 7a, which is enclosed between the adjacent first well regions 51, is formed in the second lower region 62 below the second section (section in which the channel region 26 is formed) 15Q of the gate structure 15. The enclosed section 7a, which is part of the drift region (the region with medium concentration 25 and the second semiconductor region 7), is inserted, and therefore it is possible to secure the current path extensively in the second lower region 62, which is a lower channel region. Additionally, in this preferred embodiment, the enclosed section 7a is not formed in the first lower region 61 below the first section (region where the channel region 26 is not formed) 15P of the gate structure 15. The amount of electric current flowing to the first lower region 61, which is a lower non-channel region, is smaller than that flowing to the second lower region 62, which is a lower channel region. Therefore, no large resistance (one-point or JFET resistance) is generated, even if the width of the current path in the first lower region 61, which is a lower non-channel region, narrows. The first trough region 51 is formed in the first lower region 61, which is a lower non-channel region, and therefore it is possible to suppress an increase in current density near the bottom wall 15c of the gate structure 15.This makes it possible to relax an electric field with respect to the bottom wall 15c of the gate structure 15, effectively suppressing a decrease in dielectric strength due to the concentration of the electric field. Fig. 12 is a top view showing a layout example of a chip 2 according to a second preferred embodiment of the present disclosure, corresponding to Fig. 4. Fig. 13 is a cross-sectional view taken along line XIII-XIII in Fig. 12. Fig. 14 is a cross-sectional view taken along line XIV-XIV in Fig. 12. Fig. 15 is a cross-sectional view taken along line XV-XV in Fig. 12. Fig. 16 is a cross-sectional view taken along line XVI-XVI in Fig. 12. Fig. 17 is an enlarged view of a section enclosed by a dash-dot line XVII in Fig. 15. In Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16 to Fig. 17, the same reference numeral is assigned to the same component as each component previously described herein, and a description of the component is omitted. A semiconductor device 201 according to the second preferred embodiment of the present disclosure differs from the semiconductor device 1 in that the first well region 51 is formed in the second lower region 62, together with the first lower region 61. In the semiconductor device 201, the first well region 51 comprises a region formed in the second lower region 62. In detail, the first well region 51 has a first region 251 formed in the second lower region 62 (see Fig. 15, Fig. 16 to Fig. 17). The first region 251 comes into contact with the enclosed section 7a from one side in the second direction Y. Referring to Figs. 15, 16 to 17, the first region 251 has a third bottom section 252. The third bottom section 252 has a third depth D3 (see Fig. 17). The third depth D3 is the depth of the third bottom section 252 of the first region 251 based on, or extending from, the bottom wall 15c of the gate structure 15. The third depth D3 is greater than the thickness Tb of the body region 20 (D3 > Tb) (see Fig. 9). In this preferred embodiment, the third depth D3 is equal to the first depth D1 (see Fig. 8). Of course, the third depth D3 can differ in depth from the first depth D1. In other words, in the semiconductor device 201, the enclosed section 7a is not formed in the entire area of ​​the second lower region 62, but in a part of the second lower region 62. Referring to Fig. 17, the first region 251 has one or a plurality of (in this preferred embodiment, a plurality of) first bulging sections 22c. In this preferred embodiment, the first region 251 does not include either the first extension section 22a (see Fig. 9) or the second extension section 22b (see Fig. 9). Of course, the first region 251 can include both the first extension section 22a and the second extension section 22b. The semiconductor device 201 according to the second preferred embodiment of the present disclosure achieves the same operational effect which is equivalent to the operational effect described in relation to the first preferred embodiment. Additionally, the enclosed section 7a is not formed in the entire area of ​​the second lower region 62, but only in a portion of it. Therefore, it is possible to adjust the first distance W1 between the adjacent first trough regions 51 (see Fig. 16). The length in the second direction Y of the enclosed section 7a corresponds to the first distance W1 between the adjacent first trough regions 51 (see Fig. 16) as described above. It is possible to adjust the saturation current at the switch-on time (channel formation time) to an optimal value by adjusting the first distance W1 (see Fig. 16). Referring to Figs. 18, 19, 20, 21, 22, 23, 24, 25, 26 to 27, semiconductor devices 301A, 301B, 301C, 301D, 301E, and 301F are described below according to the first to sixth modification examples. In Figs. 18, 19, 20, 21, 22, 23, 24, 25, 26 to 27, the same reference numeral is assigned to the same component as each component previously described herein, and a description of the component is omitted. Fig. 18 is a cross-sectional view of the semiconductor device 301A according to the first modification example, which corresponds to Fig. 16. Referring to Fig. 18, the semiconductor device 301A according to the first modification example differs from the semiconductor device 201 in that the first well region 51 in the second lower region 62 includes a second region 351, together with the first region 251. The second region 351 comes into contact with the enclosed section 7a from the other side in the second direction Y. The second region 351 has the same configuration as the first region 251. The enclosed section 7a is not formed in the entire area of ​​the second lower region 62, but only in part of it. Therefore, it is possible to adjust the first distance W1 between the adjacent first well regions 51 in the same way as the semiconductor device 201 according to the second preferred embodiment. The length in the second direction Y of the enclosed section 7a corresponds to the first distance W1 (see Fig. 18) between the adjacent first well regions 51 as described above. It is possible to adjust the saturation current at the turn-on time (channel formation time) to an optimal value by adjusting the first distance W1 (see Fig. 18). Fig. 19 is a cross-sectional view of the semiconductor device 301B according to the second modification example, which corresponds to Fig. 9. Referring to Fig. 19, in the semiconductor device 301B according to the second modification example, the second bottom section 54 of the second well region 53 is placed at a height equal to that of the bottom section 23a of the high-concentration well region 23. The second depth D2 of the second bottom section 54 of the second well region 53 is the same as the thickness Tн of the high-concentration well region 23. In other words, the high-concentration well region 23 is in contact with the medium-concentration region 25 (semiconductor region) in the vertical direction Z. Fig. 20 is a cross-sectional view of the semiconductor device 301C according to the third modification example, which corresponds to Fig. 5. Fig. 21 is a cross-sectional view of the semiconductor device 301C according to the third modification example, which corresponds to Fig. 6. The semiconductor device 301C according to the third modification example differs from the semiconductor device 1 in that the high-concentration region 24 has been excluded or omitted. The region in which the high-concentration region 24 is formed in the semiconductor device 1 has been replaced in the semiconductor device 301C by the medium-concentration region 25. In this case, the plurality of channel regions 26 (see Fig. 9) are formed between the plurality of source regions 21 and the plurality of medium-concentration regions 25 in the plurality of body regions 20.The multitude of channel regions 26 form current paths that connect the multitude of source regions 21 and the multitude of medium concentration regions 25 along the side walls (first side wall 15a and second side wall 15b) of the multitude of gate structures 15 in the multitude of body regions 20, respectively. Fig. 22 is a cross-sectional view of the semiconductor device 301D according to the fourth modification example. Fig. 23 is a cross-sectional view of the semiconductor device 301D according to the fourth modification example. Figs. 22 and 23 are cross-sectional views obtained by cutting the semiconductor device 301D at different positions in the second direction Y. In the fourth modification example, the source region 21 is selectively formed on the side of the first sidewall 15a at a distance from the second sidewall 15b of that gate structure 15 on one side in the first direction X in a region (mesa section) enclosed between the adjacent gate structures 15. On the other hand, the first contact region 27 is adjacent to the source region 21 in the latitude direction (first direction X) of the region (mesa section) enclosed between the adjacent gate structures 15 and is selectively formed on the side of the second sidewall 15b. The source region 21 and the first contact region 27 are formed in a strip shape extending in the second direction Y. A third contact region 71 is selectively formed on one side of the region (mesa section) enclosed between the adjacent gate structures 15. The third contact region 71 extends in the vertical direction Z along the first side wall 15a and connects the first contact region 27 and the high-concentration basin region 23. The trough region 22, which functions as a field relaxation layer, comprises the first trough region 51 (see Fig. 22), which is formed below the high-concentration trough region 23. The trough region 22 comprises the second trough region 53 (see Fig. 23), which is formed below the high-concentration trough region 23. The first trough region 51 (see Fig. 22) and the second trough region 53 (see Fig. 23) are formed alternately in the second direction Y. Fig. 24 is a cross-sectional view of the semiconductor device 301E according to the fifth modification example. Fig. 25 is a cross-sectional view of the semiconductor device 301E according to the fifth modification example. Figs. 24 and 25 are cross-sectional views obtained by cutting the semiconductor device 301E at different positions in the second direction Y. In the fifth modification example, the source region 21 is formed on both sides of the gate structure 15 in the region (mesa section) enclosed between the adjacent gate structures 15, specifically on one side of the gate structure 15 that is one side in the first direction X, and on the other side of the gate structure 15 that is the other side in the first direction X. In this modification example, a pair of ribbon-shaped source regions 21 extends in a strip shape in the second direction Y in the region (mesa section) enclosed between the adjacent gate structures 15. Additionally, the first contact region 27 is formed between the pair of source regions 21 in a central section in the first direction X of the region (mesa section) enclosed between the adjacent gate structures 15. The first contact region 27 is enclosed between the pair of source regions 21 in the first direction X. The first contact region 27 penetrates the source region 21 in the vertical direction Z and is connected to the body region 20. The first contact region 27 extends in a band shape in the second direction Y in the region (mesa section) enclosed between the adjacent gate structures 15.The first contact region 27 and the pair of source regions 21, between which the first contact region 27 is enclosed on both sides, are formed in a strip shape that extends in the second direction Y in the region (mesa section) enclosed between the adjacent gate structures 15. The trough region 22, which functions as a field relaxation layer, comprises the first trough region 51 (see Fig. 24), which is formed below the high-concentration trough region 23. The trough region 22 comprises the second trough region 53 (see Fig. 25), which is formed below the high-concentration trough region 23. The first trough region 51 (see Fig. 24) and the second trough region 53 (see Fig. 25) are formed alternately in the second direction Y. Fig. 26 is a cross-sectional view of the semiconductor device 301F according to the sixth modification example, which corresponds to Fig. 5. Fig. 27 is a cross-sectional view of the semiconductor device 301F according to the sixth modification example, which corresponds to Fig. 6. In the sixth modification example, the basin region 22 and the high-concentration basin region 23 are configured such that they are positioned closer to the other side in the first direction X from an end section on one side of the gate structure 15. More precisely, the high-concentration basin region 23 is selectively configured on the other side in the first direction X with respect to the gate structure 15, or offset from it. In this modification example, the high-concentration basin region 23 extends downwards from a section of the body region 20 in the vertical direction Z, specifically in the region (mesa section) enclosed between the adjacent gate structures 15, and extends horizontally along the first main surface 3, overlapping with the bottom wall 15c of the gate structure 15. The high-concentration basin region 23 forms at least part of the second side wall 15b of the gate structure 15 and at least part of the bottom wall 15c of the gate structure 15 and is in contact with the insulating film 17. The high-concentration basin region 23 has an substantially L-shaped exposed surface, which is exposed as the lower part of the second side wall 15b and as the bottom wall 15c. The trough region 22, which functions as a field relaxation layer, comprises the first trough region 51 (see Fig. 26), which is formed below the high-concentration trough region 23. The trough region 22 comprises the second trough region 53 (see Fig. 27), which is formed below the high-concentration trough region 23. The first trough region 51 (see Fig. 26) and the second trough region 53 (see Fig. 27) are formed alternately in the second direction Y. The first conductivity type can be a p-type, and the second conductivity type can be an n-type, although in each of the aforementioned preferred embodiments (including the modification examples) an example has been described in which the first conductivity type is an n-type and the second conductivity type is a p-type. A specific configuration in this case can be obtained by replacing the n-conducting region with the p-conducting region and the p-conducting region with the n-conducting region in the preceding description and in the accompanying drawings. Chip 2, which comprises the SiC monocrystal, has been used in each of the aforementioned preferred embodiments (including the modification examples). However, chip 2 can also comprise a wide-bandgap semiconductor monocrystal other than the SiC monocrystal. A wide-bandgap semiconductor is one with a bandgap larger than that of silicon. For example, chip 2 can comprise gallium nitride, gallium oxide, diamond, etc. Of course, chip 2 can also comprise a silicon monocrystal. Similarly, the first semiconductor region 6 can comprise a wide-bandgap semiconductor monocrystal other than the SiC monocrystal. The first semiconductor region 6 can comprise gallium nitride, gallium oxide, diamond, etc. Naturally, the first semiconductor region 6 can also comprise a silicon monocrystal. Similarly, the second semiconductor region 7 can comprise a wide-bandgap semiconductor monocrystal other than the SiC monocrystal. The second semiconductor region 7 can comprise gallium nitride, gallium oxide, diamond, etc. Naturally, the second semiconductor region 7 can also comprise a silicon monocrystal. A p-type collector region can be formed on the surface layer section of the second main area 4 of the chip 2 in any of the aforementioned preferred embodiments (including the modification examples). In this case, the chip 2 can have a single-layer structure consisting of an n-type semiconductor substrate. In this case, the transistor structure Tr comprises an IGBT (Insulated Gate Bipolar Transistor) structure instead of a MISFET structure. A specific configuration in this case can be obtained by replacing the source of the MISFET structure with an emitter of the IGBT structure and by replacing the drain of the MISFET structure with a collector of the IGBT structure as described above. Characteristic examples taken from this description and the drawings are shown below. The alphanumeric characters etc. in parentheses below represent the corresponding components etc. in the embodiments described above, but are not intended to limit the scope of each clause or annex to those embodiments. The "semiconductor device" as defined in the following clauses may, where appropriate, be replaced by "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "MISFET device," "IGBT device," etc. [Annex 1-1] A semiconductor device (1, 201, 301A, 301B, 301C, 301D, 301E, 301F) comprising: a chip (2) having a main surface; a drift region (7) of a first conductivity type formed on a surface layer section of the main surface (3); a gate structure (15) of the trench electrode type formed on the main surface (3) such that it is placed in the drift region (7); and a trough region (22) of a second conductivity type, which is formed along a bottom wall (15c) of the gate structure (15) in a region below the gate structure (15) in the drift region (7), wherein the trough region (22) comprises a plurality of first trough regions (51), each of which is a first trough region (51) having a first bottom section (52) with a first depth (D1), and which are separated at a first distance (W1) from each other in the depth direction (Y) respectively.are formed in a deep region of the gate structure (15), and wherein the first trough regions (51) adjacent to each other are oriented towards each other in the depth direction (Y) or in the deep region of the gate structure (15) over a section (7a) of the drift region (7, 25). With this configuration, the trough region (22) comprises the plurality of first trough regions (51) that are formed at a first distance (W1) from each other in the depth direction (Y) of the gate structure (15) in the region below the gate structure (15). The adjacent first trough regions (51) face each other in the depth direction (Y) of the gate structure (15) across the section (7a) of the drift region (7, 25). The first trough region (51) is located in the region below the gate structure (15). An increase in current density near the bottom wall (15c) of the gate structure (15) is suppressed by the first trough region (51). This allows the electric field to relax with respect to the bottom wall (15c) of the gate structure (15), thereby suppressing a decrease in withstand voltage due to the concentration of the electric field. Section (7a) of the drift region (7, 25) is located between the adjacent first trough regions (51). This section (7a) functions as a current path. Therefore, it is possible to adequately ensure the current path in the region below the gate structure (15). This allows for a reduction in resistance (on-resistor or JFET resistance). Therefore, it is possible to reduce resistance while suppressing a decrease in dielectric strength. In other words, a semiconductor device (1, 201, 301A, 301B, 301C, 301D, 301E, 301F) can be provided that is capable of improving electrical properties. [Appendix 1-2] The semiconductor device (1, 201, 301A, 301B, 301C, 301D, 301E, 301F) according to Annex 1-1, wherein the chip (2) comprises SiC. [Appendix 1-3] The semiconductor device (1, 201, 301A, 301B, 301C, 301D, 301E, 301F) according to Annex 1-1 or Annex 1-2, wherein the first spacing (W1) is greater than the first depth (D1) of the first well region (51). [Appendix 1-4] The semiconductor device (1, 201, 301A, 301B, 301C, 301D, 301E, 301F) according to any one of Annexes 1-1 to 1-3, wherein the well region (22) further comprises a second well region (53) which is configured to be continuous with the first well region (51) between the adjacent first well regions (51) and which has a second bottom section (54) with a second depth (D2) which is less than the first depth (D1). With this configuration, the basin region (22) comprises the first basin region (51) and the second basin region (53), which differ in depth within the soil section in the region below the gate structure (15). The first basin region (51) and the second basin region (53) are continuous with each other or merge seamlessly. The first well region (51) and the second well region (53) are located in the region below the gate structure (15). An increase in current density near the bottom wall (15c) of the gate structure (15) is suppressed by both the first well region (51) and the second well region (53). This allows the electric field to relax with respect to the bottom wall (15c) of the gate structure (15), thereby suppressing a decrease in dielectric strength due to the concentration of the electric field. Therefore, it is possible to reduce the resistance (on-resistance or JFET resistance) while further suppressing a decrease in dielectric strength. [Appendix 1-5] The semiconductor device (1, 201, 301A, 301B, 301C, 301D, 301E, 301F) according to Annex 1-4, wherein a ratio (D2 / D1) of the second depth (D2) in relation to the first depth (D1) is less than 0.5. [Annex 1-6] The semiconductor device (1, 201, 301A, 301B, 301C, 301D, 301E, 301F) according to Annex 1-4 or Annex 1-5, further comprising a body region (20) formed on the side of the main surface (3) in relation to the drift region (7, 25) in the surface layer section of the main surface (3) and through which the gate structure (15) penetrates, wherein the first depth (D1) is greater than a thickness (TB) of the body region (20), and the second depth (D2) is less than the thickness (TB) of the body region (20). [Appendix 1-7] The semiconductor device (1, 201, 301A, 301B, 301C, 301D, 301E, 301F) according to Annex 1-6, wherein the body region (20) extends in the depth direction (Y) of the gate structure (15) along a side wall (15a, 15b) of the gate structure (15), and wherein the body region (20) is connected to the well region (22). [Appendix 1-8] The semiconductor device (1, 201, 301A, 301C, 301D, 301E, 301F) according to one of Annexes 1-4 to 1-7, further comprising a high-concentration well region (23) of the second conductivity type, which is formed in the well region (22) at a distance from the first bottom section (52) of the first well region (51) towards the bottom wall (15c) of the gate structure (15) and which has a defect concentration that is higher than that of the well region (22), wherein the second bottom section (54) of the second well region (53) is placed in the drift region (7, 25), and wherein the high-concentration well region (23) has a bottom section (23a) that is placed closer to the bottom wall (15c) of the gate structure (15) than to the second bottom section (54) of the second well region (53). [Appendix 1-9] The semiconductor device (201, 301A, 301B, 301C, 301D, 301E, 301F) according to one of Annexes 1-4 to 1-8, further comprising a high-concentration well region (23) of a second conductivity type, which is formed in the well region (22) at a distance from the first bottom section (52) of the first well region (51) in the direction of the bottom wall (15c) of the gate structure (15) and which has a defect concentration that is higher than the defect concentration of the well region (22), wherein the high-concentration well region (23) has a bottom section (23a) which is placed at a height equal to the height of the second bottom section (54) of the second well region (53). [Appendix 1-10] The semiconductor device (1, 201, 301A, 301B, 301C) according to one of Annexes 1-1 to 1-9, further comprising a channel region (26) of a second conductivity type formed along the side wall (15a, 15b) of the gate structure (15), wherein an enclosed section or sandwich section (7a) enclosed between the adjacent first trough regions (51) of the drift region (7, 25) is formed in a lower channel region (62) below a section (15Q) of the gate structure (15) in which the channel region (26) is formed. With this configuration, the enclosed section (7a), which is enclosed between the adjacent first trough regions (51), is formed in the lower channel region (62) below the section (15Q) of the gate structure (15) in which the channel region (26) is formed. The enclosed section (7a), which is part of the drift region (7), is inserted, and therefore it is possible to secure the current path widely in the lower channel region (62). [Appendix 1-11] The semiconductor device (1, 301B, 301C) according to Annex 1-10, wherein the first trough region (51) is not formed in the lower channel region (62). [Appendix 1-12] The semiconductor device (201, 301A) according to Annex 1-10, wherein the first trough region (51) comprises a region formed in the lower channel region (62). [Appendix 1-13] The semiconductor device (201, 301A) according to Annex 1-12, wherein the first trough region (51) has a first region (251) which comes into contact with the enclosed section (7a) from one side in the depth direction (Y) of the gate structure (15) in the lower channel region (62). [Appendix 1-14] The semiconductor device (301A) according to Annex 1-13, wherein the first trough region (51) further comprises a second region (351) which comes into contact with the enclosed section (7a) from the other side in the depth direction (Y) of the gate structure (15) in the first lower region (61) or in the lower channel region (62). [Appendix 1-15] The semiconductor device (1, 201, 301A, 301B, 301C) according to any one of Annexes 1-10 to 1-14, wherein the first trough region (51) is formed in a lower non-channel region (61) below a region (15P) of the gate structure (15) in which the channel region (26) is not formed, and wherein the enclosed section (7a) is not formed in the lower non-channel region (61). With this configuration, the enclosed section (7a) is not formed in the lower non-channel region (61) below the region (15P) of the gate structures (15), where the channel region (26) is not formed. The amount of electric current flowing to the lower non-channel region (61) is smaller than that flowing to the lower channel region (62). Therefore, no large resistance (one-point or JFET resistance) is generated, even if the width of the current path in the lower non-channel region (61) narrows. The first trough region (51) is formed in the lower non-channel region (61), and therefore it is possible to suppress an increase in current density near the bottom wall (15c) of the gate structure (15). This allows the electric field to be relaxed with respect to the bottom wall (15c) of the gate structure (15), effectively suppressing a decrease in dielectric strength due to the concentration of the electric field. [Appendix 1-16] The semiconductor device (1, 201, 301A, 301B, 301C) according to Annex 1-15, wherein in the lower non-channel region (61) the first trough region (51) is formed in an entire area in the depth direction (Y) of the gate structure. [Appendix 1-17] Semiconductor device (301D), in particular according to any one of Annexes 1-1 to 1-9, comprising: a chip (2) having a main surface; a drift region (7) of a first conductivity type formed on a surface layer section of the main surface (3); a gate structure (15) of a trench electrode type formed on the main surface (3) such that it is placed in the drift region (7);and a trough region (22) of a second conductivity type, which is formed along a bottom wall (15c) of the gate structure (15) in a region below the gate structure (15) in the drift region (7), wherein the gate structure (15) is formed in a strip shape, and wherein in a region sandwiched between the adjacent gate structures (15), a source region (21) is selectively formed, namely on one side of a side wall (15a) on one side of the gate structure (15) on the other side at a distance from a side wall (15b) on the other side of the gate structure (15) on one side, or between a side wall (15a) of a gate structure (15) and a side wall (15b) of an adjacent gate structure (15). [Appendix 1-18] Semiconductor device (301E), in particular according to any one of Annexes 1-1 to 1-9, comprising: a chip (2) having a main surface; a drift region (7) of a first conductivity type formed on a surface layer section of the main surface (3); a gate structure (15) of a trench electrode type formed on the main surface (3) such that it is placed in the drift region (7);and a trough region (22) of a second conductivity type, which is formed along a bottom wall (15c) of the gate structure (15) in a region below the gate structure (15) in the drift region (7), wherein the gate structure (15) is formed in a strip shape, and wherein a source region (21) is formed in a region sandwiched between the adjacent gate structures (15), namely on both sides of a side wall (15b) on the other side of the gate structure (15) on one side and a side wall (15a) on one side of the gate structure (15) on the other side, or on both sides of a side wall (15b) of a gate structure (15) on one side and a side wall (15a) of another gate structure (15) on the other side. Reference symbol list 1 Semiconductor device 2 Chip 3 First major face (main face) 4 Second major face 5A First side face 5B Second side face 5C Third side face 5D Fourth side face 6 First semiconductor region 7 Second semiconductor region (drift region) 7a Enclosed section (section) 8 First surface section 9 Second surface section 10A First interconnect surface section 10B Second interconnect surface section 10C Third interconnect surface section 10D Fourth interconnect surface section 11 Mesa 12 Active region 13 Outer edge region 15 Gate structure 15a First side wall (side wall) 15b Second side wall (side wall) 15c Bottom wall 15P First section (section without channel region) 15Q Second section (section with channel region) 16 Trench 17 Insulating film 18 Embedded electrode 20 Body region 21 Source region 22 Basin region 22a First extension section 22b Second extension section 22c FirstBulging section 23 High-concentration trough region 23a Bottom section 24 High-concentration region 25 Medium-concentration region (drift region) 26 Channel region 27 First contact region 27a High-concentration section 27b Low-concentration section 28 Second contact region 28a First extension section 28b Second extension section 28c Second bulging section 28d Bottom section 30 Main surface insulating film 31 Intermediate layer film 32 Source opening 33 Gate opening 35 Source electrode 35a First pad section 35b Second pad section 35c Third pad section 36 Lower electrode film 37 Main electrode film 38 First electrode film 39 Second electrode film 40 Gate electrode 41 Gate wiring 42 Drain electrode 51 First trough region 52 First bottom section 53 Second trough region 54 Second bottom section 61 First lower region (lower non-channel region) 62 Second lower region (lower channel region) 101 Semiconductor device 201 Semiconductor device 251First Region 252 Third Bottom Section 301A Semiconductor Device 301B Semiconductor Device 301C Semiconductor Device 301D Semiconductor Device 301E Semiconductor Device 301F Semiconductor Device 351 Second Region D1 First Depth D2 Second Depth D3 Third Depth TB Thickness TH Thickness Tu Thickness Tr Transistor Structure W1 First Spacing W2 Second Spacing X First Direction Y Second Direction Z Vertical Direction QUOTES INCLUDED IN THE DESCRIPTION This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature JP 2023-178289

[0001] US 2010 / 0 224 932 A

[0005]

Claims

Semiconductor device comprising: a chip (2) having a main surface (3); a drift region (7) of a first conductivity type formed on a surface layer section of the main surface (3); a gate structure (15) of the trench electrode type formed on the main surface (3) such that it is placed in the drift region (7);and a trough region (22) of a second conductivity type, which is formed along a bottom wall (15c) of the gate structure (15) in a region below the gate structure (15) in the drift region (7), wherein the trough region (22) comprises a plurality of first trough regions (51), each of which is a first trough region (51) having a first bottom section (52) with a first depth (D1), and which are formed at a first distance (W1) from each other in a depth direction (Y) of the gate structure (15), and wherein the adjacent first trough regions (51) face each other in the depth direction of the gate structure (15) across a section (7a) of the drift region (7, 25). Semiconductor device according to claim 1, wherein the chip (2) comprises SiC. Semiconductor device according to claim 1 or claim 2, wherein the first distance (W1) is greater than the first depth (D1) of the first trough region (51). Semiconductor device according to any one of claims 1 to 3, wherein the well region (22) further comprises a second well region (53) which is configured to be continuous with the plurality of first well regions (51) between the plurality of first well regions (51) and which has a second bottom section (54) with a second depth (D2) which is less than the first depth (D1). Semiconductor device according to claim 4, wherein a ratio (D2 / D1) of the second depth (D2) in relation to the first depth (D1) is less than 0.

5. Semiconductor device according to claim 4 or claim 5, further comprising a body region (20) which is formed on the side of the main surface (3) in relation to the drift region (7, 25) in the surface layer section of the main surface (3) and through which the gate structure (15) penetrates, wherein the first depth (D1) is greater than a thickness (TB) of the body region (20), and wherein the second depth (D2) is less than the thickness (TB) of the body region (20). Semiconductor device according to claim 6, wherein the body region (20) extends in the depth direction of the gate structure (15) along a side wall (15a, 15b) of the gate structure (15), and wherein the body region (20) is connected to the well region (22). Semiconductor device according to any one of claims 4 to 7, further comprising a high-concentration well region (23) of the second conductivity type, which is formed in the well region (22) at a distance from the first bottom section (52) of the first well region (51) in the direction of the bottom wall (15c) of the gate structure (15) and which has a defect concentration that is higher than that of the well region (22), wherein the second bottom section (54) of the second well region (53) is placed in the drift region (7, 25), and wherein the high-concentration well region (23) has a bottom section (23a) that is placed closer to the bottom wall (15c) of the gate structure (15) than to the second bottom section (54) of the second well region (53). Semiconductor device according to any one of claims 4 to 8, further comprising a high-concentration well region (23) of the second conductivity type, which is formed in the well region (22) at a distance from the first bottom section (52) of the first well region (51) in the direction of the bottom wall (15c) of the gate structure (15) and which has a defect concentration that is higher than the defect concentration of the well region (22), wherein the second bottom section (54) of the second well region (53) is placed at a height that is equal to the height of a bottom section (23a) of the high-concentration well region (23). Semiconductor device according to any one of claims 1 to 9, further comprising a channel region (26) of the second conductivity type formed along the side wall (15a, 15b) of the gate structure (15), wherein a sandwich-like enclosed section (7a) enclosed between the mutually adjacent first trough regions (51) of the drift region (7, 25) is formed in a lower channel region (62) below a section (15Q) of the gate structure (15) in which the channel region (26) is formed. Semiconductor device according to claim 10, wherein the first trough region (51) is not formed in the lower channel region (62). Semiconductor device according to claim 10, wherein the first trough region (51) comprises a region formed in the lower channel region (62). Semiconductor device according to claim 12, wherein the first trough region (51) has a first region (251) which comes into contact with the enclosed section (7a) from one side in the depth direction of the gate structure (15) in the lower channel region (62). Semiconductor device according to claim 13, wherein the first trough region (51) further comprises a second region (351) which comes into contact with the enclosed section (7a) from the other side in the depth direction (Y) of the gate structure (15) in the lower channel region (62). Semiconductor device according to any one of claims 10 to 14, wherein the first trough region (51) is formed in a lower non-channel region (61) below a region (15P) of the gate structure (15) in which the channel region (26) is not formed, and wherein the enclosed section (7a) is not formed in the lower non-channel region (61). Semiconductor device according to claim 15, wherein in the lower non-channel region (61) the first trough region (51) is formed in an entire area in the depth direction (Y) of the gate structure.

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