Housing architectures with vertically stacked dies and voltage converters
DE112024005202T5Undetermined Publication Date: 2026-10-08INTEL CORP
Patent Information
- Application Number
- DE112024005202
- Authority / Receiving Office
- DE · DE
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-11-08
- Filing Date
- 2024-11-08
- Publication Date
- 2026-10-08
Abstract
Embodiments of a microelectronic assembly can include a first IC die with a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, wherein the first IC die comprises a substrate and a metallization stack with an interface parallel to the first and second surfaces, the substrate comprising a voltage converter circuit (VC) and a computing circuit; and a second IC die with a fourth surface, wherein the third surface of the first IC die is electrically coupled to the fourth surface of the second IC die by an interconnect.
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Citation Information
Patent Citations
US18541311B1