Optoelectronic semiconductor chip

Abstract

An optoelectronic semiconductor chip (1) is specified comprising a semiconductor body (2), which comprises a semiconductor layer sequence and an active region suitable for generating radiation, and a radiation-transmissive and electrically conductive contact layer (6), which is arranged on the semiconductor body and is electrically conductively connected to the active region, wherein the contact layer extends over a barrier layer (5) of the semiconductor layer sequence and over a connection layer (4) of the semiconductor layer sequence and the contact layer is electrically conductively connected to the active region via a connection region (7) of the connection layer. A method for producing a contact structure for an optoelectronic semiconductor chip suitable for generating radiation is furthermore specified.

Description

[0001] Optoelectronic semiconductor chip

[0002] The present invention relates to an optoelectronic semiconductor chip.

[0003] An object of the present invention is to provide a radiation-emitting semiconductor chip with high output coupling efficiency that can be manufactured in a simplified manner. In particular, a surface-emitting semiconductor chip is to be provided that emits the majority of the total radiation power coupled out of the chip via a top surface of the chip. Furthermore, a simplified method for manufacturing a contact structure for an optoelectronic semiconductor chip suitable for radiation generation with high output coupling efficiency is to be provided.

[0004] In this context, the term "top side" preferably refers to a side of the semiconductor chip facing away from a mounting side for mounting the chip on an external connecting conductor.

[0005] This problem is solved by a semiconductor chip having the features of claim 1 and a method according to claim 26. Advantageous embodiments and further developments of the invention are the subject of the dependent claims.

[0006] An optoelectronic semiconductor chip according to the invention comprises a semiconductor body that includes a sequence of semiconductor layers and an active region suitable for generating radiation. The semiconductor chip comprises a radiolucent and electrically conductive contact layer arranged on the semiconductor body and electrically connected to the active area. This contact layer extends across a barrier layer and a connection layer of the semiconductor layer sequence. The contact layer is electrically connected to the active area via a connection area of ​​the connection layer.

[0007] Compared to a strongly absorbing contact layer, such as a thick metal layer, the radiation-transmitting contact layer exhibits a higher transmission coefficient, preferably a higher transmission, for radiation generated in the active region. Consequently, the radiation power that can be extracted from the semiconductor chip and transmitted through the contact layer is increased.

[0008] Furthermore, the radiolucent and electrically conductive contact layer can be used more easily for current expansion compared to a metallic contact layer. Current can be homogeneously distributed across the contact layer along a lateral main direction of extension of the semiconductor body and particularly uniformly impressed into the semiconductor body, since it is not necessary to provide openings for radiation transmission in the contact layer. The contact layer can, in particular, be designed as a gapless, i.e., uninterrupted and continuous, layer.

[0009] While charge carriers can be injected towards the active area via the connection area of ​​the connection layer, the barrier layer is preferably such that designed such that charge carrier injection via the contact layer to the active area via the barrier layer is reduced compared to charge carrier injection via the connection layer.

[0010] The contact layer preferably borders the barrier layer in a barrier region and / or the connection region in the connection region. In particular, the barrier layer and the connection region can delimit the semiconductor body on the side facing the contact layer. The barrier region is preferably formed by the direct contact area of ​​the contact layer with the barrier layer. The connection region is preferably formed by the direct contact area of ​​the contact layer with the connection region.

[0011] In the semiconductor chip according to the invention, current can thus be injected into the semiconductor body in certain areas via the connection area, while charge carrier injection via the barrier area is greatly reduced compared to injection via the connection area.

[0012] By means of a contact structure comprising the contact layer, the connection layer, and the barrier layer, targeted, localized charge carrier injection into the semiconductor body can be achieved in predefined areas. These areas can be defined solely by the barrier region of the barrier layer and the connection region of the connection layer, which expediently exhibit different electrical contact properties with respect to the contact layer. Additional measures for defining a connection region, such as a layer arranged between the semiconductor body and the contact layer, are not required. Electrical contact with the semiconductor body can be advantageously avoided if the electrically insulating layer, e.g., a silicon nitride layer, which is not part of the semiconductor body, is partially open.

[0013] It should be noted that even a contact structure with a contact layer that forms both a barrier region and a connection region to a semiconductor body constitutes an independent invention.

[0014] In a preferred embodiment, the barrier layer and the connection layer are configured such that the barrier for charge carrier injection via the contact layer through the barrier layer into the semiconductor body is greater than the barrier for charge carrier injection via the contact layer through the connection layer into the semiconductor body. In particular, the barrier layer and the connection layer are advantageously configured with respect to a contact layer made of a predetermined material or material composition.

[0015] For example, the electrical contact resistance of the contact layer to the termination layer is lower than the electrical contact resistance of the contact layer to the barrier layer. Charge carrier injection into the semiconductor body via the barrier layer can thus be reduced particularly efficiently, while charge carrier injection via the termination layer is simultaneously increased accordingly.

[0016] In another preferred embodiment, the connection layer and the barrier layer are different, In particular, they are implemented as separate layers within the semiconductor layer sequence. Different electrical contact properties between the connection layer and the barrier layer can thus be achieved more easily. The connection layer and the barrier layer can have different compositions. Preferably, the connection layer and the barrier layer contain different semiconductor materials, in particular different III-V semiconductor materials, or are based on different materials. Most preferably, the connection layer and the barrier layer contain semiconductor materials from different materials.

[0017] Semiconductor material systems, in particular different III-V semiconductor material systems, or are based on different material systems.

[0018] III-V compound semiconductor materials, such as nitride compound semiconductors, phosphide compound semiconductors or arsenide compound semiconductors, are particularly suitable for forming a semiconductor layer sequence for the semiconductor body of an efficient semiconductor chip, especially for forming an active region with high quantum efficiency.

[0019] Are the connection layer and the barrier layer based on different of the previously mentioned III-V-

[0020] Semiconductor material systems, the connection layer is preferably based on a phosphide compound semiconductor material and the barrier layer on an arsenide compound semiconductor material, or vice versa. Semiconductor layers based on materials made from these ■ Material systems can be based on a common The growing substrate and, in particular, the plants are grown on top of each other.

[0021] In case of doubt, "based on nitride compound semiconductor material" means that at least part of the semiconductor layer sequence comprises a nitride / V compound semiconductor material, preferably Al. n Ga m Initiative- n - m N, where O ≤ n ≤ l, 0 < m < 1 and n+m < 1, in particular with m≠O and / or n≠O. This material need not necessarily have a mathematically exact composition according to the formula above. Rather, it can contain one or more dopants as well as additional components that exhibit the characteristic physical properties of Al. n Ga m Ini_ n - m The N-materials do not change substantially. For the sake of simplicity, however, the formula above only includes the essential components of the crystal lattice (Al, Ga, In, N), even though these may be partially replaced by small amounts of other substances.

[0022] Accordingly, in the present case, “based on phosphide compound semiconductor material” means, in case of doubt, that at least part of the semiconductor layer sequence comprises a phosphide / V compound semiconductor material, preferably

[0023] Al n Ga 1n In 1-11 - Jn P, where O ≤ n ≤ l, O ≤ m ≤ l and n+m < 1, in particular with m≠O and / or n≠O. This material need not necessarily have a mathematically exact composition according to the formula above. Rather, it can contain one or more dopants as well as additional components that exhibit the characteristic physical properties of Al. n Ga m Initiative- n - m The P-materials do not change in any essential way. For the sake of simplicity, however, the formula above only includes the essential components of the crystal lattice (Al, Ga, In, P) , even if these may be partially replaced by small amounts of other substances.

[0024] Similarly, in the present case, "based on arsenide compound semiconductor material" means, in case of doubt, that at least part of the semiconductor layer sequence comprises an arsenide / V compound semiconductor material, preferably

[0025] Al n Ga 1n In1. n - m As, where O ≤ n ≤ l, O ≤ m ≤ l and n+m < 1, in particular with m≠O and / or n≠O. This material also does not necessarily have to have a mathematically exact composition according to the formula above and may contain one or more dopants as well as additional components that impart the characteristic physical properties of Al. n Ga m Initiative- n-m The properties of As materials do not change significantly. However, for the sake of simplicity, the formula above only includes the essential components of the crystal lattice (Al, Ga, In, As), even though some of these may be replaced by small amounts of other substances.

[0026] Nitride compound semiconductor material is particularly suitable for an active region for generating ultraviolet to blue radiation, phosphide compound semiconductor material particularly suitable for an active region for generating yellow to red radiation, and arsenide compound semiconductor material particularly suitable for generating infrared radiation. Preferably, the semiconductor chip is configured to generate visible light.

[0027] The connection layer is based, for example, on an arsenide compound semiconductor material, and the barrier layer on a phosphide compound semiconductor material. These compound semiconductor materials can be simplified into a They are monolithically integrated into a common semiconductor layer sequence.

[0028] The connection layer and the barrier layer can be designed not only through different compositions, but also alternatively or additionally through other measures to achieve different electrical contact properties relative to the contact layer. In particular, the connection layer and the barrier layer can be based on the same material system or even have the same material composition. Suitable measures for achieving different contact properties are explained in more detail below.

[0029] In a further preferred embodiment, the connection layer is arranged between the active area and the barrier layer, particularly between the barrier area and the active area. Advantageously, the barrier layer has a recess that preferably penetrates the entire layer. The contact layer can extend through the recess. Electrical and, in particular, direct contact between the contact layer and the connection layer can be established through the recess. The connection area can define the boundaries of the recess in the barrier layer.

[0030] In a further preferred embodiment, the barrier layer is arranged between the active area and the connection layer, in particular between the connection area and the active area. Advantageously, the connection layer has a recess through which the contact layer extends. The formation of a barrier region between the contact layer and the The barrier layer is thus made easier. The barrier area can limit the recess of the connecting layer.

[0031] The respective non-recessed layer - the connection or barrier layer - can be designed as a continuous, i.e. recess-free, layer.

[0032] Furthermore, the barrier layer can be arranged between the contact layer and the connection layer, or the connection layer can be arranged between the contact layer and the barrier layer.

[0033] In a further preferred embodiment, the contact layer is designed as a recess-free layer. The contact layer can be fully adjacent to the semiconductor body. Preferably, the contact layer is fully adjacent to the barrier layer and the terminal layer.

[0034] In a further preferred embodiment, the connection layer and the barrier layer are monolithically integrated into the semiconductor layer sequence. The semiconductor layer sequence, comprising the active region, the connection layer, and the barrier layer, can therefore be fabricated in a single, continuous process. For example, the semiconductor layer sequence, including the connection layer and the barrier layer, can be grown epitaxially on a growth substrate. The connection layer and the barrier layer can thus be grown epitaxially.

[0035] The connection layer and the barrier layer can still be adjacent to each other. The contact layer is preferably applied to the prefabricated semiconductor body. For this purpose, a process different from the manufacturing process of the semiconductor layer sequence is particularly preferred. A deposition process is especially suitable for applying the contact layer.

[0036] In a further preferred embodiment, the barrier layer and the connection layer have different conductor types (n-type and p-type, respectively). Layers with different conductor types can differ considerably with respect to their electrical contact properties with the contact layer, thus simplifying the formation of the barrier layer and the connection layer.

[0037] For example, the barrier layer and a semiconductor layer of the semiconductor layer sequence located on the side of the active region facing away from the barrier layer can have the same conduction type, e.g. n-type.

[0038] In such a configuration with different conductor types, the barrier layer is preferably arranged on the side of the connection layer facing the contact layer. Otherwise, charge carriers injected via the connection layer would potentially have to overcome a pn junction formed by the barrier layer in the semiconductor body to reach the active region. Such a barrier for charge carriers in the semiconductor body between the connection layer and the active region can be avoided by arranging the barrier layer on the side of the connection layer facing away from the active region. In another preferred embodiment, the connection layer is doped and the barrier layer is undoped. Different contact properties between the connection layer and the barrier layer and the contact layer can also be achieved in this way. Here, the 'The connection layer can be arranged between the contact layer and the barrier layer, or the barrier layer can be arranged between the connection layer and the contact layer. Since undoped layers generally have a comparatively low conductivity, arranging the barrier layer between the contact layer and the connection layer is particularly advantageous due to improved conduction of charge carriers within the semiconductor body to the active region. However, since a relatively thin layer with a comparatively low contribution to the electrical resistance of the semiconductor body can suffice to form a barrier, the latter arrangement is not strictly necessary.

[0039] In a further preferred embodiment, the connection layer and the barrier layer have the same conductor type. The dopant concentration in the connection layer is preferably higher, particularly in the connection area, than the dopant concentration in the barrier layer. This also allows the contact resistance of the contact layer to the barrier layer to be adjusted relative to the contact resistance of the connection layer. ' can be increased. Since the dopant concentration can have a significantly greater influence on the electrical contact formation of the contact layer to the semiconductor body than on the electrical resistance in the volume of the semiconductor body, both the contact layer between the barrier layer and the Both the contact layer and the barrier layer can be arranged between the connection layer and the contact layer. However, arranging the barrier layer between the connection layer and the contact layer is particularly advantageous in this case as well.

[0040] In a further preferred embodiment, the dopant concentration of the connection layer is 5*10 15 l / (cm 3 ) or more. A dopant concentration of 1 * 10 16 l / (cm 3 ) and especially of 1 * 10 17 l / (cm 3 A concentration of µg or more has proven particularly advantageous for the connection layer. This is especially beneficial with regard to the formation of an ohmic contact between the contact layer and the connection layer, as the formation of an ohmic, low-barrier contact can be achieved more easily with higher dopant concentrations.

[0041] In another preferred embodiment, the connection layer is designed to be p-conducting.

[0042] In a further preferred embodiment ' The connection layer and the barrier layer are free from modifications that affect the conductivity or contact properties of the layers with the contact layer. In particular, these layers are preferably modification-free, apart from the doping or intrinsic design of the respective layer and / or different layer compositions. The layers can therefore already be manufactured with the respective contact properties, e.g., grown. Subsequent measures, such as oxidation or implantation, e.g., proton implantation, to define regions with high conductivity are not required. Barriers for the charge carrier injection can be advantageously omitted.

[0043] The layers – connecting and / or barrier layer – can each exhibit a conductivity that is essentially constant in the lateral direction along their entire lateral course.

[0044] In another preferred embodiment, the semiconductor body is designed as a thin-film semiconductor body.

[0045] For the purposes of this application, a thin-film semiconductor body can be considered to be a semiconductor body in which the fabrication substrate on which the semiconductor layer sequence of the semiconductor body is produced is thinned, partially removed from the semiconductor layer sequence, or completely removed from the semiconductor layer sequence. The fabrication substrate can be formed by means of a substrate on which the semiconductor layer sequence is deposited. For example, the fabrication substrate can be formed by the growth substrate on which the semiconductor layer sequence is epitaxially grown.

[0046] In a preferred embodiment, the semiconductor chip comprises a substrate on which the semiconductor layer sequence is arranged, and the contact layer is arranged between the semiconductor layer sequence and the substrate. The substrate is preferably different from the manufacturing substrate of the semiconductor layer sequence. The substrate can mechanically stabilize the semiconductor layer sequence. It is particularly advantageous to use such a substrate when the semiconductor chip is formed with a thin-film semiconductor body, since in a thin-film In semiconductor bodies, the stabilizing effect of the manufacturing substrate is at least reduced or completely eliminated.

[0047] Since the support for the thin-film semiconductor body is different from the manufacturing substrate, it can be chosen relatively freely without having to possess the properties required for the fabrication of the semiconductor layer sequence, e.g., regarding the crystal structure, such as the lattice constant. For example, the support can be optimized with respect to thermal or electrical conductivity. This can increase the efficiency of the semiconductor chip.

[0048] The contact structure with the connection layer, the barrier layer and the contact layer can in particular be designed as a buried contact structure, via which the semiconductor body can be electrically contacted on the carrier side.

[0049] The semiconductor layer sequence for the thin-film semiconductor body is preferably arranged on the support before the thinning, partial, or complete removal of the substrate, so that the support mechanically stabilizes the semiconductor layer sequence. This reduces the risk of damage to the semiconductor layer sequence due to insufficient mechanical stabilization during substrate processing.

[0050] The carrier is particularly preferably placed on the side facing away from the manufacturing substrate.

[0051] Semiconductor layer sequence arranged. Furthermore, an intermediate carrier can also be arranged in this way, and the carrier After removing the substrate, the layers are deposited on the side of the semiconductor layer sequence facing away from the intermediate support, i.e., the side on which the substrate was located. The intermediate support can then be removed.

[0052] In a further preferred embodiment, a mirror layer is arranged on the side of the contact layer facing away from the active area. Preferably, the mirror layer is electrically conductive, and particularly preferably, the mirror layer is electrically connected to the contact layer.

[0053] The reflective layer is advantageously designed to reflect the radiation generated in the active region. By means of the reflective layer, radiation passing through the transparent contact layer and striking the reflective layer can be reflected back into the semiconductor body. This increases the radiation power coupled out of the semiconductor chip via the side of the semiconductor body facing away from the reflective layer.

[0054] The side of the semiconductor body facing away from the reflective layer preferably forms the top surface of the surface-emitting semiconductor chip. The reflective layer is preferably arranged on the side of the semiconductor body facing a mounting surface for mounting the semiconductor chip onto an external conductor.

[0055] Furthermore, the mirror layer is preferably designed as a recess-free layer. Furthermore, the mirror layer preferentially borders the contact layer. The mirror layer can border the contact layer across its entire surface.

[0056] By means of an electrically conductive mirror layer and the contact layer, a reflective contact structure with a region-specific electrical connection to the semiconductor body can be formed in a particularly simple way.

[0057] In a preferred embodiment, the mirror layer contains a metal. A metal-containing mirror layer is characterized by an advantageously low dependence of the reflectivity on the angle of incidence of the radiation on the mirror layer. This is particularly true at comparatively large angles to the ■ The surface normal of the mirror layer can thus reliably reflect this incident radiation.

[0058] Preferably, the mirror layer is metallic or contains an alloy that includes at least one metal. Suitable metals are, for example, Au, Al, or Ag; suitable alloys that preferably contain at least one of the aforementioned metals are, for example, AuGe or AuZn. A metal-containing mirror layer can be applied to the thin-film semiconductor body, for example, by vapor deposition.

[0059] Furthermore, direct contact between the semiconductor body and the mirror layer can be avoided by means of a continuous contact layer arranged between the mirror layer and the semiconductor body. Areas of lower reflectivity can be formed in such a contact area between the mirror layer and the semiconductor body. This is because an alloy containing a metallic material from the mirror layer can form in the contact area. This alloy can have a lower reflectivity than the remaining area of ​​the mirror layer. This can be avoided within the scope of the invention.

[0060] A thin-film semiconductor chip, i.e., a semiconductor chip with a thin-film semiconductor body and substrate, may further be characterized by at least one of the following features:

[0061] - On a main surface of a radiation-generating epitaxial layer sequence facing the support, a reflective layer is applied or formed which reflects at least part of the electromagnetic radiation generated in the epitaxial layer sequence back into this ' • ;

[0062] - the epitaxial layer sequence has a thickness in the range of 20 μm or less, particularly in the range of 10 μm; and / or

[0063] - the epitaxial layer sequence contains at least one semiconductor layer with at least one surface that has a mixing structure which ideally leads to an approximately ergodic distribution of light in the epitaxial layer sequence, i.e. it exhibits a scattering behavior that is as ergodic and stochastic as possible.

[0064] A basic principle of a thin-film LED chip is described, for example, in I. Schnitzer et al. , Appl. Phys. Lett. 63 (16), October 18, 1993, 2174 - 2176, the disclosure content of which is hereby incorporated by reference. To attach the semiconductor body to the substrate for a thin-film semiconductor chip, a bonding layer can be arranged and / or formed between the contact layer and the substrate. The mirror layer is preferably arranged between the bonding layer and the contact layer.

[0065] In a further preferred embodiment, the barrier region covers an electrode of the semiconductor chip located on the side of the semiconductor body facing away from the barrier region. The electrode can, in particular, be designed as an electrode metallization. Furthermore, the electrode can be provided for wire bonding. Such electrodes are generally absorbent with respect to the radiation generated in the active region. Since charge carriers are not injected into the semiconductor body via the barrier region, or only to a significantly reduced extent, only a comparatively low radiant power is generated in the area of ​​the active region covered laterally by the electrode. In this way, the radiant power absorbable by the electrode can be reduced, as the radiant power generated below the electrode is reduced due to the arrangement of the barrier region.The efficiency of the semiconductor chip, in particular the radiation power that can be extracted from the chip, is consequently increased.

[0066] In a further preferred embodiment, the barrier region is arranged in an edge region of the semiconductor chip, in particular an edge region of the semiconductor body. In the edge region of the active area, which the barrier region preferably covers in this case, the proportion of non-radiatively recombining charge carriers is often particularly high. The quantum efficiency of the The capacity of semiconductor chips can be increased by such an arrangement of the barrier area.

[0067] In a further preferred embodiment, the semiconductor chip has a plurality of barrier regions, wherein one of these barrier regions covers the electrode of the semiconductor chip located on the side of the semiconductor body facing away from the barrier region, and another barrier region is located in the edge region of the chip. These barrier regions can be configured as a continuous region or as separate regions. In the first case, unlike the second case, any two points of the barrier region can be connected to each other without leaving the barrier region.

[0068] In a further preferred embodiment, the semiconductor chip comprises a plurality of connection areas. These connection areas can be configured as a contiguous region or as separate regions. The plurality of connection areas allows radiation generation to be concentrated on zones of the active region that are particularly favorable for radiation extraction from the semiconductor chip. Suitable zones in this respect are, for example, those not covered by the electrode or an electrode structure on the side of the semiconductor body facing away from the contact layer.

[0069] In a further preferred embodiment, the contact layer contains a transparent and electrically conductive oxide (TCO), in particular a metal oxide, for example a zinc oxide such as ZnO, an indium tin oxide (ITO), or a tin oxide such as SnO2. Conductive oxides are characterized by high radiation transmittance combined with high conductivity, particularly in the lateral direction. ZnO or ITO are particularly suitable for forming electrical contacts with p-type semiconductor materials. SnO₂ is particularly suitable for forming contacts with n-type semiconductor materials.

[0070] A TCO-containing contact layer can be doped, which can increase its conductivity. Suitable materials for this purpose include aluminum for ZnO or steel for SnO2.

[0071] Furthermore, radiolucent and electrically conductive oxides can be characterized by advantageously high thermal conductivities. In contrast, the thermal conductivities of dielectric layers, e.g., made of SiN, which are used to form a contact layer with the semiconductor body, are generally lower. This reduces the thermal resistance for heat dissipation from the semiconductor body. Consequently, the risk of thermally induced damage to the semiconductor chip can be reduced.

[0072] For electrical contact with the semiconductor body, a relatively thin, radiolucent contact layer is sufficient. This contact layer can, for example, have a thickness of 200 nm or less. If the contact layer has a varying thickness along its lateral surface, the minimum thickness can be used to determine the thickness of the contact layer. Preferably, the radiation-transparent contact layer has a thickness greater than or equal to one-quarter of the wavelength of the radiation generated in the active region within the contact layer. Mathematically expressed, the thickness D of the contact layer, and in particular the minimum thickness, preferably satisfies the following relationship:

[0073] λ

[0074] D>- -+m-

[0075] 4n k 2n k

[0076] where λ is a characteristic emission wavelength, such as the peak wavelength, the dominant wavelength, or a center-of-mass wavelength of the emission spectrum of the radiation generated in the active region, n k the refractive index of the contact layer and m = 0,1,2,... is.

[0077] Furthermore, the thickness D is preferably larger than the right-hand side of the inequality, i.e., not equal to the right-hand side. This allows the overall reflectivity of the reflective contact structure, including the mirror layer and the contact layer, to be advantageously increased, taking oblique radiation incidence into account. ' One

[0078] Changing the thickness by integer multiples of changes the

[0079] 2n k

[0080] The reflective properties of the contact structure are not critical. Therefore, m=0 is preferred. This allows the contact layer to be designed in a particularly material-efficient manner.

[0081] In a further preferred embodiment, the connection layer contains GaAs or AlGaAs, preferably with a low Al content. GaAs or AlGaAs, particularly with a low Al content, e.g., of 40% or less, is suitable for the Electrical contact formation with TCO materials, especially with ZnO, is particularly suitable.

[0082] By means of a contact layer containing ZnO and a mirror layer containing Au, a particularly efficient and easy-to-manufacture semiconductor chip can be formed, especially with an active area containing a phosphide compound semiconductor material.

[0083] In a further preferred embodiment, the semiconductor chip is configured as a luminescent diode chip, for example as an LED chip for generating incoherent radiation, e.g. as an LED chip without a resonator or as an RCLED chip (Resonant Cavity Light Emitting Diode) with a resonator, or as a laser diode chip for generating coherent radiation, e.g. for an edge-emitting laser, a vertical-emitting laser with an internal resonator (VCSEL: Vertical Cavity Surface Emitting Laser) or a vertical-emitting laser with an external resonator (VECSEL: Vertical External Cavity Surface Emitting Laser).

[0084] In a method according to the invention for producing a contact structure for an optoelectronic semiconductor chip suitable for radiation generation, a sequence of semiconductor layers with a connection layer and a barrier layer is first provided, wherein the barrier layer is arranged on the connection layer.

[0085] In a first variant, the connection layer can be partially removed, exposing the barrier layer. Complementarily, in a second variant, the barrier layer can be partially removed, exposing the connection layer. For the In the first variant, a semiconductor layer sequence is advantageously provided in which the barrier layer is arranged between the connection layer and the active region of the semiconductor layer sequence. In the second variant, the connection layer is advantageously arranged between the barrier layer and the active region.

[0086] Subsequently, a radiolucent and electrically conductive contact layer is applied to the semiconductor layer sequence, wherein the contact layer is arranged both, and in particular directly, on the terminal layer and also, and in particular directly, on the barrier layer. The electrical contact resistance of the barrier layer to the contact layer is preferably greater than the electrical contact resistance of the contact layer to the terminal layer.

[0087] The contact layer can be deposited onto the semiconductor layer sequence, particularly using a vacuum process. For example, the contact layer can be deposited using a PVD (Physical Vapor Deposition) process, such as sputtering or evaporation, or a CVD (Chemical Vapor Deposition) process, such as PECVD (Plasma Enhanced Chemical Vapor Deposition).

[0088] To promote electrical contact between the contact layer and the connection layer, a temperature process, e.g. a sintering process, can be carried out after the contact layer has been applied.

[0089] The contact layer can also be applied across the entire surface of the semiconductor layer sequence. Furthermore, the contact layer can be unstructured, i.e., applied according to the The layer, e.g., a continuous layer, should not be further structured. The provision of an electrically insulating structured layer, e.g., a silicon nitride layer, may be omitted due to the formation of the ' The connection layer and the barrier layer with different electrical contact properties can be omitted from the contact layer. This eliminates the need for the insulating layer and a structuring step, such as a photolithography step, for the insulating layer.

[0090] In a preferred embodiment of the method, a reflective layer, particularly an electrically conductive one, is applied to the side of the contact layer facing away from the semiconductor layer sequence. Preferably, the reflective layer is deposited, e.g., by vapor deposition or sputtering. Furthermore, the reflective layer is preferably applied as a continuous layer, particularly covering the entire surface. The reflective layer can be applied in a vacuum process.

[0091] The layered assembly, comprising the contact layer, the connection layer, the barrier layer, and optionally the mirror layer, can subsequently be arranged on a substrate for the semiconductor chip. The contact layer is advantageously positioned between the substrate and the semiconductor layer sequence. The substrate is preferably part of the semiconductor chip for which the contact structure is intended.

[0092] A substrate on which the semiconductor layer sequence is preferably arranged during provisioning, e.g. the manufacturing substrate of the semiconductor layer sequence, can be according to The layer arrangement on the substrate can be thinned, partially removed, or completely eliminated. Advantageously, in this case, the contact layer is applied to the side of the semiconductor body facing away from the substrate.

[0093] Preferably, the method is carried out during the production of a semiconductor chip according to the invention. Features described above and below for the semiconductor chip can therefore also refer to the method for producing the contact structure or for producing a semiconductor chip with a corresponding contact structure, and vice versa.

[0094] Advantageous embodiments and further developments of the invention will result from the following description of the exemplary embodiments in conjunction with the figures.

[0095] Figure 1 shows a schematic sectional view of a first embodiment of an optoelectronic semiconductor chip according to the invention.

[0096] Figure 2 shows a schematic sectional view of another embodiment of a semiconductor chip according to the invention,

[0097] Figure 3 shows a schematic sectional view of another embodiment of an optoelectronic semiconductor chip ,

[0098] Figure 4 shows schematic top views of the upper and lower sides of a semiconductor body for a semiconductor chip according to the invention, in figures 4A and 4B respectively. Figure 5 shows, with reference to the schematic sectional views in Figures 5A to 5D, intermediate steps of a first embodiment of a method according to the invention for forming a contact structure for an optoelectronic semiconductor chip,

[0099] Figure 6 shows, based on the schematic sectional views in Figures 6A to 6D, intermediate steps of a further embodiment of a method according to the invention for forming a contact structure for an optoelectronic semiconductor chip.

[0100] Identical, similar, and similarly effective elements in the figures are provided with the same reference symbols.

[0101] Figures 1 and 2 each show a schematic sectional view of an embodiment of an optoelectronic semiconductor chip 1 according to the invention, e.g. an LED chip.

[0102] The semiconductor chip 1 comprises a semiconductor body 2, which includes a sequence of semiconductor layers with an active region 3 suitable for radiation generation. A connection layer 4 and a barrier layer 5 are integrated into the semiconductor layer sequence, which is preferably grown epitaxially, for example by means of MOVPE (Metal-Organic Vapor Phase Epitaxy), on a growth substrate (not shown).

[0103] A radiolucent and electrically conductive contact layer 6 is arranged on the semiconductor body 2, bordering the terminal layer 4 and the barrier layer 5. In the direct contact area of ​​the contact layer to the A connection area 7 is formed in the connection layer, through which the contact layer 6 is electrically connected to the active area. A barrier area 8 is formed in the direct contact area between the contact layer and the barrier layer 5.

[0104] Charge carrier injection into the semiconductor body 2 via the barrier region 8 is more difficult than charge carrier injection into the semiconductor body via the connection region 7. By means of the continuous and uninterrupted contact layer 6, a simplified, region-specific current injection into the semiconductor body can be achieved through the formation of the connection and barrier regions. A dielectric layer between the semiconductor body 2 and the contact layer 6, which is specifically designed to facilitate electrical contact between the contact layer and the semiconductor body, is therefore unnecessary.

[0105] In an advantageous embodiment, the thickness of the connection layer and / or the barrier layer is greater than 10 nm, preferably greater than or equal to 30 nm, and particularly preferably greater than or equal to 50 nm. Alternatively or additionally, the thickness of the barrier layer and / or the connection layer is advantageously less than 1000 nm, preferably less than or equal to 500 nm, and particularly preferably less than or equal to 300 nm. Such thicknesses are particularly suitable for the connection layer to form electrical contacts with the contact layer on the one hand, and for forming a barrier to the contact layer by means of the barrier layer on the other. An electrically conductive mirror layer 9 is arranged on the side of the contact layer 6 facing away from the semiconductor body 2. The mirror layer is preferably designed as a continuous, uninterrupted layer. Furthermore, the mirror layer 9 preferably borders the contact layer 6, particularly over its entire surface.

[0106] The contact layer 6 is advantageously arranged continuously between the mirror layer 9 and the semiconductor body 2. This avoids direct contact between the semiconductor material of the semiconductor body 2 and the mirror layer 9. The risk of alloy formation between the mirror layer material and the semiconductor material, which would reduce reflectivity, is thus minimized. Consequently, the mirror layer can exhibit a consistently high reflectivity across its entire lateral extent.

[0107] The semiconductor body 2 is still designed as a thin-film semiconductor body, in which the growth substrate for the semiconductor layer sequence is partially (not shown) or completely removed from the semiconductor layer sequence.

[0108] For mechanical stabilization of the thin-film semiconductor body 2, it is arranged on a support 10, which is separated from the growth substrate of the

[0109] The semiconductor layer sequence differs. Semiconductor chip 1 is therefore designed as a thin-film semiconductor chip.

[0110] To attach the thin-film semiconductor body 2 to the support 10, a space is provided between the mirror layer 9 and the support. A connection layer 11 is arranged. The connection layer 11 and / or the carrier 10 are preferably electrically conductive, so that electrical contact of the semiconductor chip 1 can be made through the carrier 10, the connection layer 11, the mirror layer 9 and the contact layer 6.

[0111] A mounting electrode 12 is arranged on the side of the mirror layer 9 facing away from the contact layer 6, in particular on the side of the support 10 facing away from the contact layer 6. The semiconductor chip 1 can be arranged on an external conductor, for example a conductor of a surface-mount device or the conductor of a printed circuit board, electrically connected to it, and in particular fixed to it, by means of the mounting electrode 12.

[0112] An electrode 14 is arranged on a top surface 13 of the semiconductor chip 1 facing away from the contact layer 6. The electrode 14 is preferably designed as a bonding electrode and is provided for electrically conductive connection with a bonding wire, via which the semiconductor chip 1 can be electrically connected to a further external conductor. The electrode 14 and the mounting electrode 12 can each be designed as a metallization.

[0113] During chip operation, charge carriers are injected into the active region 3 via electrodes 12 and 14, where they can recombine and emit radiation. Charge carriers injected into the semiconductor body 2 via electrode 14 and the contact layer 6 are indicated by corresponding arrows. By designing and arranging the connection area 7, radiation generation in the active region 3 can be concentrated in particularly suitable areas. Radiation generated in zones of the active region 3 that are vertically overlapped by the electrode 14 is more likely to be absorbed by the electrode 14. Therefore, the connection area 7 is preferably spaced laterally from the electrode 14. Advantageously, the barrier area 8 covers the electrode 14, particularly completely. To further prevent radiation generation below the electrode 14, the barrier area 8 is laterally widened in a (partial) area that overlaps with the electrode 14, relative to the lateral extent of the electrode 14. This further prevents radiation generation below the electrode 14 due to current expansion in the semiconductor body.

[0114] During operation of the semiconductor chip 1, radiation generation is concentrated on areas of the active region 3 not covered by the electrode 14 – compare the regions outlined in Figures 1 and 2, in which charge carriers injected into the semiconductor body via the electrode 14 and the connection region 7 recombine, generating radiation. These regions are advantageously spaced laterally from the electrode 14.

[0115] Radiation emanating from the active area 3 towards the contact layer 6 can pass through the radiation-transparent contact layer and strike the mirror layer 9. By means of the mirror layer 9 This radiation can be reflected back into the semiconductor body 2 and coupled out of the semiconductor chip 1 via the upper surface 13 of the semiconductor body 2 facing away from the mirror layer. This is illustrated by beam 15.

[0116] By means of the mirror layer 9, the absorption of radiation in elements arranged on the side of the mirror layer facing away from the active region 3, such as the interconnect layer 11 or the support 10, can be reduced and at the same time the radiation power emerging from the semiconductor body via the top surface 13 can be increased. • become.

[0117] In the lateral edge region of the semiconductor body, and especially in the active region 3, the risk of non-radiative recombination of charge carriers is particularly high. The barrier region 8 therefore covers the edge region of the active region, thus reducing charge carrier injection via the contact layer 6 into the semiconductor body 2 towards the edge region of the active region. The barrier layer can also delimit the semiconductor body 2, particularly laterally.

[0118] The active region 3 is arranged or formed between a first semiconductor layer 16 and a second semiconductor layer 17, which have different conductor types (n-type and p-type, respectively). Preferably, the semiconductor layers 16 and 17 are configured as cladding layers. A cladding layer can increase the confinement of charge carriers in the active region and thus the conversion efficiency of electrical power and radiative power of the semiconductor chip. If necessary, a separate connection layer can be omitted and the semiconductor layer 16 can serve as the connection layer.

[0119] Overall, the invention allows the formation of a surface-emitting thin-film semiconductor chip which, as explained above, has a simplified contact structure for area-specific current injection into the semiconductor body and a high coupling efficiency.

[0120] In a preferred embodiment, the semiconductor body, in particular the active region 3, the connection layer 4, the barrier layer 5, the first semiconductor layer 16 and / or the second semiconductor layer 17, contains a III-V semiconductor material. Using such semiconductor materials, a semiconductor chip with particularly high internal quantum efficiency can be formed. Furthermore, the semiconductor chip is preferably designed to generate visible radiation.

[0121] The contact layer 6 is preferably designed as a TCO contact layer. TCO materials are characterized not only by high radiation transmittance but also by high electrical conductivity.

[0122] A difference between the embodiment shown in Figure 1 and the embodiment shown in Figure 2 lies in the arrangement and design of the connection layer and the barrier layer. In the embodiment shown in Figure 1, the barrier layer 5 is designed as a continuous layer and is arranged between the connection layer 4 and the active area. The connection layer 4 is partially recessed so that the contact layer can pass through the connection layer 4 and form the barrier area 8 by direct contact with the barrier layer 5. In contrast, in the embodiment shown in Figure 2, the connection layer 4 is designed as a continuous layer and is arranged between the barrier layer 5 and the active area. Here, the barrier layer 5 is partially recessed to form the connection area 7 by direct contact between the contact layer and the connection layer.

[0123] In both embodiments, the electrical contact resistance of the contact layer 6 to the barrier layer 5 is intentionally increased compared to the contact resistance of the contact layer 6 to the terminal layer 4. The terminal area 7 and the barrier area 8 are connected in parallel with respect to the contact layer 6, so that, due to the increased contact resistance, significantly fewer charge carriers are injected into the semiconductor body via the barrier layer than via the terminal layer. For this purpose, the terminal layer 4 and the barrier layer 5 are preferably configured differently from each other.

[0124] Preferably, the connection layer has the same conductor type as the first semiconductor layer 16, which is arranged between the active region and the connection layer, for example p-type.

[0125] The following describes a semiconductor chip 1 whose active region is a phosphide compound semiconductor material, especially InGaAlP, contains particularly suitable designs for some elements of the semiconductor chip.

[0126] The contact layer 6 is preferably implemented as a ZnO layer. Optionally, the contact layer can be doped to increase conductivity. For example, aluminum is suitable as a ZnO dopant.

[0127] As connection layer 4 for a ZnO contact layer to the semiconductor body, a p-type, e.g. Mg-doped, (Al) GaAs layer with a dopant concentration of greater than or equal to 5*10 15 l / (cm 3 ), preferably of l*10 16 l / (cm 3 ) or more, especially preferred by l*lθ 17 l / (cm 3) or more, is particularly suitable. Since GaAs absorbs in the visible spectral range, an AlGaAs layer is especially advantageous as a connection layer for a visible radiation-generating active region. The band gap of the AlGaAs layer can be adjusted by varying the Al content, thus reducing or completely preventing radiation absorption in the connection layer. The Al content is preferably 40% or less.

[0128] An Au or AuZn mirror layer is characterized by particularly high reflectivities for radiation generated with phosphide compound semiconductor materials, especially from the yellow to the red spectral range.

[0129] Carrier 10 may contain or consist of germanium or GaAs.

[0130] Furthermore, due to the omission of a dielectric material for defining the contact structure, the ' thermal Resistance between the mirror layer and the semiconductor body is reduced. ZnO, for example, has a higher thermal conductivity (0.54 W / (core)) than silicon nitride (SiN). x : typically 0.1 W / (core) to 0.2 W / (core) ). As a result, the risk of heat-related efficiency loss or damage to the semiconductor chip can be reduced. This is particularly noticeable in a semiconductor chip where carrier 10 is omitted or where the carrier is significantly thinned.

[0131] Compared to a semiconductor chip 1 with dielectric material to define local electrical contact points, the thermal resistance of the chip can be reduced by up to 50%.

[0132] The bonding layer 11 can be designed as a solder layer, for example as an AuSn-containing layer, as an electrically conductive adhesive layer or as a layer formed by means of a wafer bonding process.

[0133] The barrier layer 5 and the connection layer 4 can consist of different materials, with the material of the contact layer 6 being electrically better connected to the material of the connection layer 4 than to that of the barrier layer 5. For example, in the case of an arsenide-based connection layer, such as an (Al)GaAs connection layer, the barrier layer can contain a phosphide compound semiconductor material, for example InAlP or InGaAlP.

[0134] Furthermore, the contact resistance of the The resistance of the contact layer 4 can be deliberately reduced compared to that of the barrier layer 5. In this case, the contact and barrier layers can have the same material composition, apart from the doping. However, a difference in contact resistance can be amplified more easily by using different material compositions.

[0135] To increase the contact resistance of the barrier layer 5 to the contact layer 6 compared to the contact resistance of the contact layer 6 to the connection layer 4, the barrier layer can be doped for a conductor type different from the connection layer, for example n-type.

[0136] Also via doping of barrier layer 5 for ■By using the same conductor types as the connection layer but with a lower dopant concentration, a predominant charge carrier injection into the semiconductor body 2 can be achieved via the connection area. Preferably, the barrier layer has a dopant concentration of less than 5 × 10 15 l / (cm 3 ) on. If necessary, the same dopant or different dopant materials can be used for the bonding and barrier layers.

[0137] As an alternative to influencing the contact resistance via the dopant concentration or the conductor type, the barrier layer can be undoped. This also allows for an increase in the contact resistance of the barrier layer to the contact layer when the terminal layer is doped. Here too, the terminal and barrier layers can be modified apart from the The doping may require the material to have the same composition. However, differences in contact resistance can be amplified by using different material compositions.

[0138] Since the charge carriers, after injection into the semiconductor body 2 in the embodiment shown in Figure 1, still have to penetrate the continuous barrier layer to reach the active region, the barrier layer 5 in the embodiment shown in Figure 1 is preferably undoped and correspondingly thin, or it is designed with the same conductivity type as the terminal layer 4, but with a lower dopant concentration. For low-resistance charge carrier transport within the semiconductor body, lower dopant concentrations are generally sufficient than for efficient, low-barrier charge carrier injection into the semiconductor body.

[0139] To optimize the reflectivity of the reflective contact structure with the contact layer and the mirror layer, the contact layer preferably has a thickness greater than λ / (4ri k ) , where λ is a characteristic emission wavelength, such as one of the wavelengths mentioned above, of the radiation generated in the active region and, in particular, of the radiation coupled out of the semiconductor chip. n k denotes the refractive index of the contact layer material. For example, the contact layer thickness is greater than 400 ran. Preferably, the contact layer has a minimum thickness of such a value.

[0140] In addition to the good electrical connection to the semiconductor body in connection area 7, this also allows for an optimized effect over a wide range of incidence angles. Reflectivity of the reflective contact structure can be achieved. However, for contact formation alone, a contact layer with a thickness of less than λ / (4n) is sufficient. k ) , e.g. of 200 nm or less, are sufficient.

[0141] In a further preferred embodiment, the active region comprises a double heterostructure or a single or multiple quantum well structure. Such structures can advantageously increase the quantum efficiency of the active region.

[0142] Within the scope of this application, the term "quantum well structure" encompasses any structure in which charge carriers undergo, or can undergo, a quantization of their energy states through confinement. In particular, the term "quantum well structure" does not specify the dimensionality of the quantization. It therefore includes, among other things, quantum wells, quantum wires, and quantum dots, and any combination thereof.

[0143] Figure 4 shows schematic top views of a semiconductor chip according to the invention, for example a chip according to Figure 1 or Figure 2. Figure 4A shows a top view of the top surface 13 of the semiconductor body 2, and Figure 4B shows a top view of the connection layer 4 and the barrier layer 5 of the semiconductor body 2.

[0144] Electrode 14 has an electrode area 140, which is designed for connection to a bond wire. Electrically conductively connected to area 140 are webs 141, which ' to expand the current. The area 140 is electrically connected to an electrode frame 142 by means of the webs 141. The electrode frame 142 is located in the edge region of the Top side 13 is arranged. In the sectional views according to Figures 1 and 2, the electrode frame or the electrode webs are not explicitly shown.

[0145] Using such an electrode structure, a lateral current spread can be achieved starting from electrode area 140.

[0146] As can be seen from Figure 4B, the shape of the barrier region 8 is preferably adapted to that of the electrode structure shown in Figure 4A. The barrier region can therefore have a basic geometry corresponding to the electrode structure.

[0147] As shown in Figure 4, the semiconductor chip 1 has a plurality of separate connection areas 7 and a continuous barrier area 8, which is shaped according to the electrode structure. The barrier area 8 accordingly has a region 80 from which webs 81 extend to connect the region 80 to a barrier frame 82. Compared to the electrode structure, the corresponding areas of the barrier area preferably have a larger lateral extent. The barrier area is preferably designed such that, despite a current expansion in the semiconductor body, radiation generation in the active area below the electrode structure is avoided.

[0148] Furthermore, the semiconductor chip may optionally comprise a plurality of separate barrier regions (not shown). This is particularly useful if recombination of charge carriers in the edge region of the semiconductor body is to be suppressed and the electrode 14 only has the electrode region 140. A first barrier region is then preferably located below the electrode region 140 and a second barrier region, spatially separated from it, is arranged in the edge region of the semiconductor body 2.

[0149] Furthermore, the connection area, especially in the case of separate barrier areas, can be designed as a continuous area (not shown).

[0150] Figure 3 shows a further embodiment of an optoelectronic semiconductor chip 1 according to the invention. The semiconductor chip 1 essentially corresponds to the embodiments shown in Figures 1 and 2. In contrast, the semiconductor body 2 has one or more recesses 20 extending from the side of the semiconductor body 2 facing the contact layer 6 towards the active region 3. The recesses 20 may, in particular, taper towards the active region 3.

[0151] Furthermore, the recesses 20 preferably penetrate the connection layer 4, the barrier layer 5 and optionally the semiconductor layer 16. The contact layer 6 extends into the recess and preferably lines it. The mirror layer 9 also preferably extends into the recess.

[0152] Between the active region 3 and the contact layer, a further barrier layer 18 is arranged, to which the contact layer 6 adjoins in a further barrier region 19. The further barrier layer is preferably p-conducting and / or has a surface that is p-conducting relative to the contact layer 6. The connecting layer has a lower dopant concentration as described above.

[0153] The recess, and in particular the mirror layer arranged within it, allows the angular distribution of radiation reflected back into the semiconductor body from the mirror layer to be more broadly scattered compared to reflection from a completely flat mirror layer, with respect to the top surface 13. The probability that radiation with an angle smaller than a critical angle of the •The total internal reflection that strikes the top surface 13 of the semiconductor body 2 and can thus couple out of the semiconductor body is increased by this. Accordingly, the proportion of radiation that continues to be totally reflected within the semiconductor body can be reduced by means of the recess 20. Overall, this increases the coupling efficiency of the semiconductor chip.

[0154] The recesses 20 can, for example, be formed by means of a microprism structure. The recesses 20 can, for example, be produced by etching.

[0155] There may be several separate exemptions provided for, or there may be one continuous exemption.

[0156] Figures 5 and 6 show, in Figures 5A to 5D and 6A to 6D respectively, an embodiment of a method according to the invention for producing a contact structure for an optoelectronic semiconductor chip suitable for radiation generation. The method for forming the contact structure is described here in connection with the production of a semiconductor chip according to the invention, wherein the method according to Figure 5 is applicable to a semiconductor chip according to Figure 1 and the method according to Figure 6 is suitable for a semiconductor chip according to Figure 2.

[0157] First, in both methods, a semiconductor layer sequence 21 is provided, comprising a connection layer 4 and a barrier layer 5, Figures 5A and 6A. Furthermore, the

[0158] The semiconductor layer sequence includes an active region 3 suitable for radiation generation.

[0159] Semiconductor layer sequence 21 is arranged on a substrate 22. The substrate 22 is preferably the growth substrate on which the semiconductor layer sequence 21, with the monolithically integrated connection layer and the monolithically integrated barrier layer, was epitaxially grown, e.g., using MOVPE. The connection layer 4 and the barrier layer 5 are preferably arranged on the side of the active region facing away from the substrate 22.

[0160] For a semiconductor layer sequence with an active region based on phosphide compound semiconductor material, GaAs, for example, is suitable as a growth substrate. The semiconductor layer sequence 21 is specifically intended for the formation of a semiconductor body for the optoelectronic semiconductor chip.

[0161] The connection layer 4 and the barrier layer 5 are designed such that they exhibit different contact resistances, preferably predetermined contact resistances, relative to a predetermined material or material composition to be applied to the prefabricated semiconductor layer sequence. The contact resistance of the contact layer to the barrier layer is where appropriately greater than the contact resistance of the connecting layer to the given contact layer.

[0162] According to Figure 5A, the barrier layer 5 is arranged between the active area 3 and the connection view, whereas according to Figure 6A, the connection layer is arranged between the active area and the barrier layer.

[0163] Subsequently, the connection layer 4 is partially removed, exposing the barrier layer 5 to form a barrier region to the contact layer (Figure 5B), or alternatively, the barrier layer 5 is partially removed, exposing the connection layer 4 to form a connection region to the contact layer (Figure 6B). For example, the following are suitable for this partial removal: . an etching process using a suitably structured mask.

[0164] In this process, specific regions of the connection layer or barrier layer are removed. In the embodiment shown in Figure 5, the regions of connection layer 4 are removed where current injection into the semiconductor body of the chip is undesirable in the finished semiconductor chip. In contrast, in the method shown in Figure 6, the regions of the connection layer where current injection is desired in the finished semiconductor chip are exposed. This structuring of the semiconductor layer sequence effectively defines the barrier region and the connection region for the semiconductor chip.

[0165] On the side of the semiconductor layer sequence 21 facing away from the substrate 22, a A contact layer 6 is applied, which borders barrier layer 5 in barrier region 8 and connection layer 4 in connection region 7. The contact layer 6 is electrically connected to the active region via connection region 7 and is transparent to radiation generated in the active region. A TCO contact layer 6, in particular a ZnO contact layer, is especially suitable for this purpose. The contact layer 6 can be deposited onto the semiconductor layer sequence 21 by sputtering or PECVD, and in particular in a vacuum process.

[0166] After applying the contact layer 6, the ■ 'The layered composite is further sintered, preferably improving the electrical contact properties of the contact layer to the connection layer 4. The layered composite with the semiconductor layer sequence and the contact layer applied to it can be sintered for, for example, five minutes or longer, e.g., seven minutes, at a temperature of 450°C. 0 C sintered.

[0167] Since the contact layer 6 is essentially electrically connected not to the barrier layer but only to the terminal layer 4, the contact layer can be applied across its entire surface of the semiconductor layer sequence. Subsequent structuring or structured application of the contact layer is unnecessary, yet local current injection can still be achieved. A structured dielectric layer between the contact layer and the barrier region is also unnecessary.

[0168] Current passage openings for local current injection into the semiconductor layer sequence can be omitted. Subsequently, a mirror layer 9 is applied to the side of the contact layer 6 facing away from the semiconductor layer sequence 21. The mirror layer is preferably metallic or made of a metal-containing alloy. The mirror layer can be deposited onto the layer assembly, particularly in a vacuum process, e.g., by vapor deposition or sputtering. For example, the mirror layer contains or consists of Au or AuZn. The mirror layer can be deposited over the entire surface of the layer assembly.

[0169] The resulting structure is shown schematically in Figures 5C and 6C. Due to the continuous contact layer 6, direct contact between the mirror layer 9 and the semiconductor material of the semiconductor layer sequence is prevented, thus avoiding alloy formation between the mirror layer and the semiconductor material, which would reduce reflectivity.

[0170] On the side of the mirror layer 9 facing away from the substrate, the layer structure is subsequently attached to a support 10 by means of a bonding layer 11. The support can, for example, contain Ge or GaAs. The bonding layer 11 is preferably electrically conductive. The bonding layer 11 can be a solder layer, an electrically conductive adhesive layer, or a layer formed by a wafer bonding process.

[0171] The substrate is then removed, at least partially (not shown) or completely, from the semiconductor layer sequence 21, for example by means of Etching or a laser deposition process. Preferably, at least an area of ​​the upper surface 13 of the semiconductor layer sequence 21 facing away from the contact layer 6 is exposed, onto which an electrode 14 can subsequently be applied, in particular deposited. Preferably, however, the substrate 22 is completely removed. The height of the chip can thus be reduced.

[0172] On the side of contact layer 6 facing away from the semiconductor layer sequence 21, in particular the

[0173] On the side of the substrate 10 facing away from the semiconductor layer sequence 21, a mounting electrode 12, e.g., a metallization, is applied at a suitable time for mounting the semiconductor chip onto an external electrical conductor. The semiconductor chip 1 produced by the respective method, with a semiconductor body formed by the semiconductor layer sequence 21, is shown schematically in Figures 5D and 6D.

[0174] The process can, of course, also be used for the simultaneous production of multiple semiconductor chips in a wafer array, whereby the chips can be manufactured particularly easily and cost-effectively with a contact structure for local current injection. The contact layer can be deposited across the entire wafer, with electrical connection made via connection areas defined in the semiconductor layer sequence.

[0175] This patent application claims priority over German patent applications DE 10 2006 019725.9 of April 27, 2006 and DE 10 2006 034847.8 of July 27, 2006, the entirety of which The disclosure content is hereby explicitly included in the present application by reference.

[0176] The invention is not limited by the description based on the exemplary embodiments. Rather, the invention encompasses every new feature as well as every combination of features, which in particular includes every combination of features in the patent claims, even if this feature or combination itself is not explicitly specified in the patent claims or exemplary embodiments.

Claims

Patent claims 1. Optoelectronic semiconductor chip (1) comprising a semiconductor body (2) comprising a sequence of semiconductor layers and an active region (3) suitable for generating radiation, and a radiolucent and electrically conductive contact layer (6) arranged on the semiconductor body and electrically connected to the active region, wherein the contact layer extends over a barrier layer (5) of the semiconductor layer sequence and over a connection layer (4) of the semiconductor layer sequence and the contact layer is electrically connected to the active region via a connection area (7) of the connection layer.

2. Semiconductor chip according to claim 1, wherein the contact layer (6) is adjacent to the barrier layer (5) in a barrier region (8) and / or wherein the contact layer is adjacent to the connection layer (4) in the connection region (7).

3. Semiconductor chip according to claim 1 or 2, wherein an electrical contact resistance of the contact layer (6) to the connection layer (4) is smaller than an electrical contact resistance of the contact layer to the barrier layer (5) .

4. Semiconductor chip according to one of the preceding claims, wherein the contact layer (6) contains a radiolucent and electrically conductive oxide, in particular a metal oxide, for example a zinc oxide, a tin oxide or an indium tin oxide.

5. Semiconductor chip according to one of the preceding claims, in which a mirror layer (9) is arranged on the side of the contact layer (6) facing away from the active area (3).

6. Semiconductor chip according to claim 5, wherein the mirror layer (9) contains a metal.

7. Semiconductor chip according to claims 4 and 6, wherein the mirror layer (9) contains Au and the contact layer (6) contains ZnO.

8. Semiconductor chip according to any one of claims 1 to 7, wherein the barrier layer (5) and the connection layer (4) have different conductor types.

9. Semiconductor chip according to claim 8, wherein a semiconductor layer of the semiconductor layer sequence arranged on the side of the active area (3) facing away from the barrier layer (5) and the barrier layer have the same conductor types.

10. Semiconductor chip according to one of claims 1 to 7, wherein the connection layer (4) is doped and the barrier layer (5) is undoped.

11. Semiconductor chip according to any one of claims 1 to 7, wherein the connection layer (4) and the barrier layer (5) have the same conductor type, wherein the dopant concentration of the connection layer is greater than the dopant concentration of the barrier layer.

12. Semiconductor chip according to one of the preceding claims, wherein the connection layer (4) is p-conducting.

13. Semiconductor chip according to one of claims 1 to 12, wherein the connection layer (4) is arranged between the active area (3) and the barrier layer (5).

14. Semiconductor chip according to one of the preceding claims, wherein the barrier layer (5) has a recess through which the contact layer (6) extends.

15. Semiconductor chip according to one of claims 1 to 12 or 14, wherein the barrier layer (5) is arranged between the active area (3) and the connection layer (4).

16. Semiconductor chip according to one of the preceding claims, wherein the connection layer (4) has a recess through which the contact layer (6) extends.

17. Semiconductor chip according to one of the preceding claims, wherein the contact layer (6) is designed as a recess-free layer.

18. Semiconductor chip according to one of the preceding claims, wherein the connection layer (4) and the barrier layer (5) are monolithically integrated in the semiconductor body (2).

19. Semiconductor chip according to one of the preceding claims, wherein the semiconductor body (2) is designed as a thin-film semiconductor body.

20. Semiconductor chip according to claim 19, wherein the semiconductor chip comprises a support (10) on which the semiconductor layer sequence is arranged, and the contact layer (6) is arranged between the semiconductor layer sequence and the support.

21. Semiconductor chip according to claim 20, . wherein the support (10) is different from a growth substrate (22) of the semiconductor layer sequence.

22. Semiconductor chip according to one of claims 2 to 21, wherein the barrier region (8) covers an electrode (14) of the semiconductor chip arranged on the side of the semiconductor body facing away from the barrier region.

23. Semiconductor chip according to one of claims 2 to 21, wherein the barrier region (8) is arranged in an edge region of the semiconductor chip.

24. Semiconductor chip according to claims 22 and 23, comprising a plurality of barrier regions (80, 81, 82), wherein one of these barrier regions (80) covers the electrode (14) of the semiconductor chip located on the side of the semiconductor body facing away from the barrier region, and another barrier region (82) is located in the edge region of the semiconductor chip.

25. Semiconductor chip according to claim 24, wherein the barrier regions (80, 81, 82) are interconnected.

26. Method for manufacturing a contact structure for an optoelectronic semiconductor chip suitable for radiation generation, comprising the following steps: - Providing a semiconductor layer sequence (21) with a terminal layer (4) and a barrier layer (5) , wherein the barrier layer is arranged on the terminal layer; - .Partial removal of the connection layer of the semiconductor layer sequence, exposing the barrier layer, or partial removal of the barrier layer of the semiconductor layer sequence, exposing the connection layer; - Applying a radiolucent and electrically conductive contact layer (6) to the Semiconductor layer sequence, wherein the contact layer is arranged both directly on the connection layer and directly on the barrier layer.

27. Method according to claim 26, wherein the contact layer (6) is on the ■ . A sequence of semiconductor layers is deposited.

28. Method according to claim 26 or 27, wherein a sintering process is carried out after the application of the contact layer (6).

29. Method according to one of claims 26 to 28, wherein a mirror layer (9) is applied to the side of the contact layer (6) facing away from the connecting layer (4).

30. Method according to any one of claims 26 to 29, wherein the method is carried out in the manufacture of a semiconductor chip (1) according to any one of claims 1 to 25.