STACKABLE III-V SEMICONDUCTOR ELEMENT

Description

[0001] The invention relates to a stack-shaped III-V semiconductor device.

[0002] High-blocking Schottky diodes and IGBTs based on silicon or SiC are known from Josef Lutz et al, Semiconductor Power Devices, Springer Verlag, 2011, ISBN 978-3-642-11124-2.

[0003] From "GaAs Power Devices" by German Ashkinazi, ISBN 965-7094-19-4, high-voltage-resistant semiconductor diodes p +< - n - n +< as well as Schottky diodes, high-voltage-resistant pnip transistors based on GaAs are known.

[0004] Further semiconductor devices are from US 2006 / 0281263 A1; US ​​2016 / 315140 A1; US ​​2013 / 075783 A1; WO 2016 / 204098 A1; US ​​2018 / 047725 A1; from Tom Simon et al: "Gallium arsenide semiconductor parameters extracted from pin diode measurements and simulations", IET POWER ELECTRONICS, Vol. 9, No. 4, March 30, 2016, pp. 689-697; from G. Ashkinazi et al: "PROCESS AND DEVICE CHARACTERIZATION OF HIGH VOLTAGE GALLIUM ARSENIDE PIN LAYERS GROWN BY AN IMPROVED LIQUID PHASE EPITAXY METHOD", January 1, 1993, pp. 1749-1755; known as US 2014 / 048845 A1; US ​​2001 / 030331 A1; US ​​2002 / 100934 A1 and US 2001 / 026984 A1.

[0005] In particular, US patent 2006 / 0281263 A1 discloses an IGBT, which can be made of GaAs, with a p+< substrate, an n-doped intermediate layer, an n-< drift layer, a p-doped region, an n+< doped region, and three terminal contact layers. The intermediate layer includes defects that affect the lifetime of the minority charge carriers.

[0006] Against this background, the object of the invention is to provide a device that further develops the state of the art.

[0007] The problem is solved by a stacked III-V semiconductor device with the features of claim 1. Advantageous embodiments of the invention are the subject of dependent claims.

[0008] Preferably, the concentration of defects in the n-layer is less than 10 17< N / cm 3<, most preferably less than 5 x 10 16< N / cm 3< .

[0009] Preferably, most or all of the aforementioned semiconductor layers can be produced using liquid phase epitaxy (LPE) or MOVPE equipment.

[0010] Contrary to the previous belief that GaAs is only suitable for fast components or solar cells with blocking voltages in the low-voltage range, i.e., below 10 volts, it has surprisingly been shown that thick n-< layers, i.e., layers above 30 µm or preferably above 60 µm, can be deposited easily and cost-effectively using the aforementioned epitaxial systems with good crystal quality.

[0011] This surprisingly makes it possible to manufacture high-blocking semiconductor devices from GaAs. In this context, high-blocking devices are defined as semiconductor devices with a blocking voltage above 100 V.

[0012] Preferably, the connection contacts consist of metallically conductive semiconductor layers or metal layers, or a combination of both. The connection contacts establish a low-resistance electrical contact with the immediately adjacent doped semiconductor layers.

[0013] Furthermore, it is understood that the connection contacts are preferably interconnected by means of bond wires or soldered connections with contact fingers, the so-called pins. The connection contacts are preferably arranged on a top or bottom surface of the stack formed from the semiconductor areas or semiconductor layers.

[0014] Surprisingly, it was shown that, contrary to previous efforts, defects in epitaxy due to the formation of recombination centers must be avoided in any case in order to achieve the best possible crystal quality, but leakage currents can be reduced by the targeted incorporation of recombination centers in the n-< layer.

[0015] By incorporating recombination centers, the diffusion length of the charge carriers can be significantly reduced, so that the charge carriers are much less likely to enter the space charge region and be separated according to their polarity.

[0016] Furthermore, it was surprisingly shown that in forward operation of the component, i.e., the space charge region is flooded with charge carriers, the current flow is only negligibly reduced.

[0017] In other words, a reduction in leakage current by a factor of 10 to 100, which is typical for high-blocking components such as diodes or IGBTs. The leakage current, depending on the reverse voltage and temperature, ranges between a few pA and mA, and is negligible in forward operation with currents in the range above a few hundred mA to a few tens of A.

[0018] It should also be noted that the defect layer is preferably not formed within the space charge region. Preferably, the thickness of the n-< layer is such that the defect layer is spaced away from the space charge region.

[0019] Furthermore, leakage currents increase sharply with temperature, reaching several tens of milliamps. Due to this exponential increase with rising temperature, low leakage currents are particularly advantageous when used in hot environments up to 300°C. This is achieved by the defect layer according to the invention. By incorporating the defect layer, leakage currents can be reduced by more than an order of magnitude compared to semiconductor devices without a defect layer.

[0020] Furthermore, the manufacturing process becomes significantly more robust, i.e., insensitive to high background doping.

[0021] Another advantage is that, with the III-V semiconductor components according to the invention, low leakage currents at blocking voltages in a range of 200V - 3300 V can be produced in a simple manner, especially in the case of diodes or IGBTs, with lower on-resistances and lower capacitances per area than conventional high-blocking diodes made of Si or SiC.

[0022] This makes switching frequencies from 30 kHz to 0.5 GHz and current densities from 0.5 A / mm² to 5 A / mm² achievable. Furthermore, the III-V semiconductor diode according to the invention can be manufactured more cost-effectively than comparable high-blocking diodes made of SiC.

[0023] Semiconductor diodes according to this non-inventive embodiment can preferably be used as freewheeling diodes.

[0024] It should be noted that the III-V semiconductor diodes according to this embodiment exhibit low on-resistances in the range of 1 mΩ to 200 mΩ. The capacitances per unit area are in the range of 2 pF to 100 pF and are significantly lower than those of comparable SiC diodes.

[0025] Another advantage is that the charge carriers in GaAs semiconductor structures have a lower effective mass compared to silicon. Higher temperatures can also be achieved at the pn junctions compared to silicon without damaging the devices. This allows for higher switching frequencies and lower losses with GaAs semiconductor structures that have high blocking voltages compared to similar silicon semiconductor structures. Furthermore, thanks to their high temperature resistance of up to 300°C, the III-V semiconductor devices according to the invention can also be used in hot environments, i.e., in a range up to 180°C.

[0026] Another advantage is that III-V semiconductor diodes can be manufactured much more cost-effectively than comparable high-blocking diodes made of SiC.

[0027] In one embodiment, the surface of the p+< substrate is metallized in order to electrically connect the components, in particular the semiconductor diode.

[0028] Not according to the invention, the cathode of the semiconductor diode is metallurgically bonded to a substrate designed as a heat sink after metallization. In other words, the anode is formed on the surface of the diode on the p+ layer.

[0029] According to an unclaimed alternative embodiment, the p +< region and the n +< region are formed in a layered form, and the layered n +< region and the layered p +< region are each bonded to the n -< layer, wherein the layered n +< region has a layer thickness of 50 - 675 µm and the layered p +< region has a layer thickness greater than 2 µm.

[0030] In an unclaimed further development, the n-< region comprises a defect layer with a layer thickness between 0.5 µm and 50 µm, wherein the defect layer has a defect concentration in a range between 1•10 13< N / cm 3< and 5•10 16< N / cm 3<.

[0031] Preferably, the defect layer has a distance to an interface.

[0032] The term interface here refers to the transition between two differently doped layers or regions, in particular the transition between the n-< layer and the intermediate layer, or the transition between the n-< layer and the p+< region, or the transition between the n-< layer and the n+< region. Preferably, the distance is at most half the thickness of the n-< layer.

[0033] It is understood that the defect layer can be created in various ways, for example by implantation or incorporation of foreign atoms, and that charge carrier recombination is achieved within the defect layer. Preferably, the defects or recombination centers are created by incorporating chromium.

[0034] According to another alternative embodiment, the p+< region and the n+< region are formed in a layered form, wherein the layered n+< region is bonded to the n-< layer and a doped intermediate layer with a layer thickness of 1-50 µm and a dopant concentration of 10 12< -10 17< cm³< is arranged between the n-< layer and the p+< layer and the intermediate layer is bonded to the n-< layer and to the p+< layer.

[0035] It is understood that the intermediate layer has at least one different dopant concentration compared to the layers bonded together.

[0036] Preferably, the intermediate layer is p-doped and most preferably comprises zinc or silicon. The dopant concentration of the p-doped intermediate layer is most preferably lower than the dopant concentration of the p+< region, particularly by a factor of 2 to a factor of 5 orders of magnitude.

[0037] Alternatively, the intermediate layer is n-doped and preferably comprises silicon and / or tin, wherein the dopant concentration of the n-doped intermediate layer is particularly preferably up to a factor of 100 smaller than the dopant concentration of the n-< region.

[0038] One advantage is that the III-V semiconductor diode designed according to this unclaimed embodiment allows for the simple production of reverse voltages in the range of 200 V to 3300 V with lower on-resistances and lower capacitances per unit area than conventional high-blocking diodes made of Si or SiC. This enables switching frequencies from 30 kHz to 0.5 GHz and current densities from 0.5 A / mm² to 5 A / mm². In particular, the III-V semiconductor diodes according to the invention can be used as freewheeling diodes.

[0039] It should be noted that the III-V semiconductor diodes according to this embodiment also exhibit low on-resistances in the range between 1 mΩ and 200 mΩ. The capacitances per unit area are in the range between 2 pF and 100 pF.

[0040] It should also be noted that the defect layer should ideally not be located within the space charge region. Preferably, the thickness of the p-layer is such that the defect layer is spaced away from the space charge region.

[0041] According to the invention, the p +< region and the n +< region are formed in a layered form, the layered n +< region and the layered p +< region are bonded to the n -< layer, and the dopant concentration increases within the n -< layer from the surface of the n -< layer adjacent to the p +< region to the surface of the n -< layer adjacent to the n +< region by a factor of between 1.5 and 2.5.

[0042] Preferably, the dopant concentration of the n-layer 14 changes in a step-like manner, i.e., the dopant concentration exhibits a profile parallel to the layer thickness of the n-layer 14 with at least one step or even several steps. Alternatively, the profile exhibits a gradient, i.e., a continuous increase.

[0043] According to an initial alternative development, the layered p +< region is formed as a substrate with a layer thickness of 50-500 µm and the layered n +< region has a layer thickness of less than 30 µm.

[0044] According to a second alternative further development, the layered n +< -region is formed as a substrate with a layer thickness of 50-400 µm and the layered p +< -region has a layer thickness greater than 2 µm.

[0045] According to a further development, the p+< region and the n+< region are formed in a layered form, a p-doped intermediate layer with a layer thickness of 1-50 µm and a dopant concentration of 1012< -1017< N / cm3< is arranged between the n-< layer and the p+< region, the layered n+< region and the intermediate layer are each metallurgically bonded to the n-< layer and the layered p+< region is metallurgically bonded to the intermediate layer, and the stacked III-V semiconductor device has a first defect layer with a layer thickness between 0.5 µm and 40 µm, wherein the defect layer is arranged within the p-doped intermediate layer and has a defect concentration in a range between 1•1013< N / cm3< and 5•1016< N / cm3<.

[0046] The statements made above apply to the intermediate layer and the defect layer of this embodiment.

[0047] In another embodiment, the stacked layer structure consisting of the p+< substrate, the n- layer and the n+< layer has a semiconductor bond formed between the n-< layer and the p+< substrate.

[0048] It is noted that the term semiconductor bond is used synonymously with the term wafer bond.

[0049] In one embodiment, the layer structure consisting of a p +< substrate forms a first sub-stack and the layer structure consisting of the n +< layer and the n -< layer forms a second sub-stack.

[0050] In a further development, the stacked layer structure includes an intermediate layer positioned between the p+< substrate and the n-< layer. The first substack comprises this intermediate layer. The semiconductor bond is located between the intermediate layer and the n-< layer.

[0051] In a further education course, the first sub-stack and the second sub-stack are each monolithically formed.

[0052] In another embodiment, the first substack is formed by creating an intermediate layer from a p+< substrate using epitaxy. Preferably, the intermediate layer, formed as a p-< layer, has a doping concentration of less than 1013 N / cm-3, i.e., the intermediate layer is intrinsically doped, or a doping concentration between 1013 N / cm-3 and 1013 N / cm-3. In one embodiment, the p+< substrate is thinned to a thickness between 200 µm and 500 µm by a grinding process before or after bonding.

[0053] In another embodiment, the second stack is formed by connecting the n-< substrate to the second stack, i.e., the n+< layer, via a wafer bonding process, starting from an n-< substrate. In one embodiment, the n+< layer is configured as an n+< substrate.

[0054] In a further process step, the n-< substrate is thinned to the desired thickness.

[0055] Preferably, the thickness of the n-substrate is in the range of 50 µm to 250 µm. Preferably, the doping concentration of the n-substrate is in the range of 1013 N / cm-3 to 1015 N / cm-3. An advantage of wafer bonding is that thick n-substrate layers can be readily produced. This eliminates the need for a lengthy deposition process during epitaxy. Wafer bonding also reduces the number of stacking defects.

[0056] In an alternative embodiment, the n-substrate has a doping concentration greater than 1010 N / cm-3 and less than 1013 N / cm-3. Since the doping concentration is extremely low, the n-substrate can also be considered an intrinsic layer.

[0057] In a further development step, the n-< substrate is directly bonded to the first stack using a semiconductor bonding process. Subsequently, the n-< substrate is thinned to the desired thickness of the n-< layer. After thinning the n-< substrate or the n-< layer, the n+< layer is created by epitaxy or high-dose implantation with a doping concentration in the range between 10<18 N / cm-3 and less than 5 × 10<19 N / cm-3.

[0058] It is understood that the thinning of the n-< substrate is preferably carried out by means of a CMP step, i.e. by means of chemical mechanical polishing.

[0059] In another further development, the stack-shaped semiconductor device has a first terminal contact layer, a second terminal contact layer and a p-< layer, wherein the p-< layer has a dopant concentration between 10 12< and 10 16< N / cm 3< and a layer thickness between 10 nm and 10µm and comprises a GaAs compound or consists of a GaAs compound or comprises or consists of further III-V compounds.

[0060] The n +< region is layered with a layer thickness between 50µm and 400µm, and the underside of the n -< layer is bonded to the top side of the layered n +< region.

[0061] The p-< layer is metallurgically bonded to the top surface of the n-< layer, the p+< region consists of at least two spaced-apart sub-regions, each sub-region of the p+< region having a dopant concentration of 5 • 10 18< -5 • 10 20< N / cm³<, is formed as a rib running parallel to a top surface of the p-< layer not according to the invention and extends from the top surface of the p-< layer into the n-< layer.

[0062] Preferably, the ribs not according to the invention are formed along certain crystallographic directions, i.e., the ribs preferably run along a given crystallographic direction.

[0063] The first contact layer is materially bonded to the underside of the n +< -area.

[0064] The second terminal contact layer is materially bonded and electrically conductively connected to a part of the top surface of the p -< layer, wherein the second terminal contact layer is materially bonded and electrically conductively connected to the entire top surface or a part of the top surface of each sub-area of ​​the p +< region.

[0065] The second terminal contact layer comprises a metal or metallic compound, or consists of a metal or metallic compound and forms a Schottky contact.

[0066] It should be noted that the second contact layer is called the anode and the first contact layer the cathode. The first contact layer forms an ohmic contact, while the second contact layer forms a metal-semiconductor junction. It is understood that further layers can be formed on top of the contact layers, for example, to bond the Schottky diode.

[0067] One advantage is that the Schottky contact, which is not according to the invention, can be completely shielded from the penetration of the high electric field by means of the very thin, low-doped p-layer as a third semiconductor layer and the p+< regions, which are formed at the edges and preferably below the second contact termination layer. For this purpose, the ribs are relatively close together, so that only relatively narrow n-< layer regions remain between adjacent ribs.

[0068] This allows reverse voltages of the Schottky diode not according to the invention to be readily achieved in a range between 200 V and 600 V, and even above 600 V. Combined with the significantly lower effective mass of GaAs compared to silicon, fast switching times can be achieved. The Schottky diode according to the invention is therefore particularly suitable as a freewheeling diode in the field of power electronics, preferably in switched-mode power supplies and inverters.

[0069] Preferably, the second terminal contact layer is rectangular, rectangular with rounded corner edges, or circular and preferably covers more than 30%, most preferably more than 50%, of the area of ​​the semiconductor layer on the top side of the semiconductor stack.

[0070] Preferably, a further semiconductor layer configured as an n-layer is arranged on the p-< layer, wherein the further n-< layer has a dopant concentration between 1012 N / cm3 and 1016 N / cm3 and a layer thickness between 0.005 µm and 10 µm and comprises or consists of a GaAs compound. The further n-< layer then forms a top surface of the stack, wherein the p+< regions extend from a top surface of the further n-< layer through the further n-< layer and the p+< layer down to the underlying n-< layer.

[0071] According to the invention, the III-V semiconductor device comprises at least one p-region, a dielectric layer preferably consisting of one or more deposited layers (oxide, nitride), and at least three terminal contact layers, wherein the p+< region is formed as a layered substrate with a layer thickness of preferably 50–500 µm, the p-region borders the n-< layer, has a dopant concentration of 1014–1018 cm3, and comprises or consists of a GaAs compound, the at least one p-region forms a first pn junction with the n-< layer, and the n+< region forms a second pn junction with the at least one p-region. The dielectric layer covers at least the first pn junction and the second pn junction and is metallurgically bonded to the n-< layer, the p-region, and the n+< region.A doped intermediate layer with a thickness of 1–50 µm and a dopant concentration of 1012–1017 cm3 is arranged between the layered p+ region and the n- region, wherein the intermediate layer is metallurgically bonded to at least the layered p+ region. The first terminal contact layer is electrically conductively connected to the underside of the layered p+ region, the second terminal contact layer is formed as a field plate on the dielectric layer, and the third terminal contact layer is electrically conductively connected to the at least one p-region and the at least one n+ region. It should be noted that the second terminal contact layer is referred to as the gate. The first terminal contact layer is typically referred to as the collector or anode, while the third terminal contact layer is referred to as the emitter or cathode.

[0072] It is understood that the interlayer of the IGBT semiconductor structure has a dopant concentration that differs at least slightly from that of the adjacent layers. The preceding statements regarding the interlayer in a semiconductor diode, in particular the embodiments and advantages, also apply accordingly to the interlayer in an IGBT semiconductor structure.

[0073] Preferably, the overall height of the IGBT semiconductor structure is at most 150-500 µm and / or the edge length or diameter of the IGBT semiconductor structure is between 1 mm and 15 mm. Particularly preferably, the p-region and / or the n-region on the top surface of the IGBT semiconductor structure are circular or straight, with semicircles arranged at the end face of the structures.

[0074] According to further training, the dielectric layer comprises a deposited oxide and has a layer thickness of 10nm to 1µm.

[0075] One advantage is that the III-IV IGBT semiconductor structure can be manufactured more cost-effectively than comparable semiconductor structures made of SiC. Due to its longer minority carrier lifetime, the GaAs IGBT has a higher current-carrying capacity compared to similar SiC devices.

[0076] Another advantage of the III-V IGBT semiconductor structure according to the invention is its high temperature resistance of up to 300°C. In other words, the III-V semiconductor diodes can also be used in hot environments.

[0077] According to another embodiment, the p +< region comprises zinc and / or the n +< region comprises chromium and / or silicon and / or palladium and / or tin and / or the n -< layer comprises silicon and / or palladium and / or tin.

[0078] Studies have shown that different blocking voltages, especially for semiconductor diodes, can be achieved with certain combinations of a p-<- intermediate layer and an n-<- layer.

[0079] In a first variant, the p-< layer comprises a thickness between 10 µm and 25 µm for a blocking voltage of approximately 900 V, and the n-< layer has a thickness between 40 µm and 90 µm.

[0080] In a second variant, the: for a blocking voltage of approximately 1200 V, the p-<- intermediate layer has a thickness between 25 µm and 35 µm, and the n-<- layer has a thickness between 40 µm and 70 µm.

[0081] In a third variant, the p-< layer comprises a thickness between 35 µm and 50 µm for a blocking voltage of approximately 1500 V, and the n-< layer comprises a thickness between 70 µm and 150 µm and 70 µm.

[0082] The diodes in the first to third variants can also be called punch diodes.

[0083] In a fourth variant, the p-<- intermediate layer has a thickness between 10 µm and 25 µm, and the n-<- layer has a thickness between 60 µm and 110 µm.

[0084] In a fifth variant, the p-<- intermediate layer has a thickness between 25 µm and 35 µm, and the n-<- layer has a thickness between 70 µm and 140 µm.

[0085] In a sixth variant, the p-<- intermediate layer has a thickness between 35 µm and 50 µm, and the n-<- layer has a thickness between 80 µm and 200 µm.

[0086] The diodes in the fourth to sixth variants can also be referred to as n "non-reach-through" diodes.

[0087] The invention is explained in more detail below with reference to the drawings. Similar parts are labelled with identical designations. The illustrated embodiments are highly schematic; that is, the distances and the lateral and vertical extents are not to scale and, unless otherwise indicated, do not exhibit any derivable geometric relationships to one another. The drawings show: Figure 1 shows a view of a non-inventive embodiment of a stacked III-V semiconductor device, Figure 2 shows a top view of the stacked III-V semiconductor device of the non-inventive embodiment of the Figure 1Figure 3 shows a view of a non-inventive embodiment of a stacked III-V semiconductor diode, Figure 4 shows a view of a non-inventive embodiment of a stacked III-V semiconductor diode, Figure 5 shows a view of a non-inventive embodiment of a stacked III-V semiconductor diode, Figure 6 shows a view of a non-inventive embodiment of a stacked III-V semiconductor diode, Figure 7 shows a view of a non-inventive embodiment of a Schottky diode, Figure 8 shows a view of a non-inventive alternative embodiment of a Schottky diode, Figure 9 shows a view of an inventive embodiment of an IGBT semiconductor structure, Figure 10 shows a top view of the IGBT semiconductor structure of the Figure 9 Figure 11 shows a view of another embodiment of an IGBT semiconductor structure according to the invention.

[0088] The illustration of Figure 1Figure 1 shows a side view of a non-inventive embodiment of a stacked III-V semiconductor device 10. The illustration of the Figure 2 A top view of the III-V semiconductor device 10. The device 10 is configured as a diode with a stack of three semiconductor layers and two contact layers, each of the semiconductor layers comprising or consisting of a GaAs compound.

[0089] The first semiconductor layer is a p+< region 12, formed as a substrate, with a layer thickness D1 and is heavily p-doped with a dopant concentration of 5 × 10¹⁸ < - 5 × 10²⁰ < N / cm³. The second semiconductor layer is a first n-< layer 14 with a layer thickness D2. The third semiconductor layer is a heavily n-doped, layered n+< region 16 with a dopant concentration of at least 10¹⁹ < N / cm³. The three semiconductor layers are monolithically grown on top of each other in the aforementioned order, such that a bottom surface of the n-< layer 14 is metallurgically bonded to a top surface of the p+< substrate, and a bottom surface of the n+< layer is metallurgically bonded to the n-< layer 14.

[0090] The n-< layer 14 is weakly n-doped with a dopant concentration between 1012 N / cm3 and 1017 N / cm3, with the dopant concentration increasing by a factor of 1.5 to 2.5 in one direction from the bottom of the n-< layer 14 to the top of the n-< layer 14. Furthermore, the n-< layer 14 comprises chromium (Cr) with a concentration of at least 1014 N / cm3 or at least 1015 N / cm3.

[0091] A first contact layer 40 is materially bonded and electrically conductive to the underside of the p+< substrate 12, i.e., the underside of the stack, and a second contact layer 42 is materially bonded and electrically conductive to the top side of the n+< layer, i.e., the top side of the stack, wherein the two contact layers 40 and 42, according to the illustrated embodiment, only partially cover the respective surface of the semiconductor layer.

[0092] Alternatively, the n +< layer is formed as a substrate on which the 14 and a layered p +< region are epitaxially generated, such that the bottom of the n +< layer forms the bottom of the stack and the top of the stack is the top of the p +< layer (not shown).

[0093] In the illustration of the Figure 3 Another embodiment of a non-inventive III-V semiconductor device is shown as a diode. The following only highlights the differences compared to the illustration of the Figure 1 explained.

[0094] The n +< -region 14 is formed as a substrate on which the n -< -layer 14 and a layered p +< -region have grown.

[0095] The n-< layer 14 is low-n doped and has a constant dopant concentration across the entire layer. Within the n-< layer 14, a defect layer 22 is arranged with a defect concentration in the range between 1 × 1013 N / cm3 and 5 × 1016 N / cm3 and a layer thickness D4 of 0.5 µm and 50 µm, wherein the defect layer 22 has a first distance A1 to an interface between the n-< layer 14 and the p+< region 12, i.e., to the top surface of the n-< layer 14.

[0096] In the illustration of the Figure 4 is one of the representations of Figure 3Alternative non-inventive embodiments are shown, wherein the sequence of the semiconductor layers is inverted, such that the p+< region 12 is formed as a layered substrate, followed by the n-< layer 14 containing the defect layer 22 and the n+< layer 16. The first distance A1 accordingly indicates the distance of the defect layer 22 to the underside of the n-< layer 14.

[0097] In the illustration of the Figure 5 Another alternative embodiment of a non-inventive III-V semiconductor device is shown as a diode. The following only highlights the differences compared to the illustration of the Figure 1 explained.

[0098] The III-V semiconductor device 10 has the n+< region 12 as a substrate, followed by the n-< layer 14 with a constant dopant concentration over the entire layer, an intermediate layer 24 with a layer thickness D5, and the p+< layer 12. The intermediate layer 24 is p- or n-doped with a dopant concentration of 1012 - 1017 cm3.

[0099] In the illustration of the Figure 6 is one of the representations of Figure 5 An alternative embodiment not according to the invention is shown, wherein the sequence of the semiconductor layers is inverted, so that the p +< -region 12 is formed as a substrate and is followed by the intermediate layer 24, the n -< -layer 14 and the n +< -layer in the aforementioned sequence.

[0100] In the illustration of the Figure 7Figure 10 shows a further alternative embodiment of a non-inventive III-V semiconductor device. Only the differences from the preceding figures will be explained below.

[0101] The III-V semiconductor device 10 is configured as a Schottky diode, comprising the n+< region forming the substrate, followed by the monolithically grown, layered n-< region 14 on the substrate, and a p-< layer 26 with a layer thickness D6 grown on the n-< region 14. The p+< region 12 has two spaced-apart sub-regions, the sub-regions extending from a top surface of the p-< layer 26 to a depth D1 through the entire p-< layer 26 into the n-< layer 14.

[0102] In the illustrated embodiment, the first terminal contact layer 40 covers the entire underside of the n +< substrate, while the second terminal contact layer 42 covers only a part of the top side of the p -< layer 26 and a part of the top side of each p +< sub-area, so that one edge of the second terminal contact layer 42 is located within the top side of a p +< sub-area.

[0103] In the illustration of the Figure 8 is one of the representations of Figure 7 An alternative embodiment of a Schottky diode not according to the invention is shown, wherein the p +< -region consists of six spaced-apart sub-regions and the second contact layer 42 partially covers a top surface of the first sub-region and a top surface of the sixth sub-region and completely covers the top surfaces of the intermediate sub-regions.

[0104] In the illustrations of Figures 9 and 10Figure 10 shows an embodiment of a III-V semiconductor device according to the invention in a side view and a top view. Only the differences from the preceding figures are explained below.

[0105] The III-V semiconductor device 10 is configured as a stacked IGBT semiconductor structure with a so-called non-punch-through design, wherein the p+< region is configured as the substrate, followed by a weakly n- or p-doped intermediate layer 24 and an n-< layer 14, the p region 28 extending from the top of the stack to a depth D7 into the n-< layer 14. A further portion of the top of the stack is formed by the n+< region 16, the n+< region extending from the top of the stack to a depth D8 into the p region 28, the depth D7 of the p region 28 being greater than the depth D8 of the n+< region 16.

[0106] Thus, two pn junctions are formed adjacent to the top surface of the semiconductor stack, namely a first pn junction 32 between the p-region 28 and the n-< layer 14 and a second pn junction 34 between the n+< region 16 and the p-region 28. A dielectric layer 30 with a layer thickness D9 covers at least the first pn junction 32 and the second pn junction 34 and is metallurgically bonded to the top surface of the semiconductor stack, in particular to the n+< region 16, the p-region 28 and the n-< layer 14.

[0107] The first terminal contact layer 40 is formed as a metal layer, which is metallurgically bonded and electrically conductive to a bottom surface of the stack, i.e., to the bottom surface of the p+< region. The second terminal contact 42 is formed as a field plate on a surface of the dielectric layer 30 facing away from the semiconductor structure. A third terminal contact 44 is also formed as a metal layer, which is metallurgically bonded and electrically conductive to a portion of the top surface of the stack formed by the p region 28 and the n+< region 16.

[0108] The illustration of Figure 10 The depicted top surface of the semiconductor structure without contact layers has a rectangular contour, with the p-region 28 and the n +< -region 16 being circular.

[0109] In the illustration of the Figure 11Another alternative embodiment of an IGBT semiconductor structure according to the invention is shown. The following only highlights the differences compared to the illustrations of the Figure 9 explained. The semiconductor structure 10 is designed as a so-called trench IGBT.

[0110] The p-region 28 and the n +< -region 16 are each formed as layers on the n -< -layer 14 and the p-region 28 respectively, wherein the semiconductor structure has a trench 46, the so-called trench, extending from the top through the layered n +< -region 16 and the layered p-region 28 into the n -< -layer 14.

[0111] The first pn junction 32 and the second pn junction 34 are perpendicular to a side face 48 of the trench 46. The side face 48 and a bottom 50 of the trench 46 are covered with the dielectric layer 30. The second terminal contact 42, designed as a field plate, extends accordingly onto the dielectric layer 30. The third terminal contact layer 44 is arranged on a side face 52 of the semiconductor structure opposite the side face 48 of the trench 46 and is electrically connected to the layered n+< region 16 and the layered p region 28. Preferably, the side faces run along crystallographic directions of the III-V semiconductor material.

Claims

1. Stacked monolithic III-V semiconductor module (10) constructed as an IGBT structure comprising a stack, which is formed from III-V semiconductor layers, with an upper side and a lower side, - a layer-shaped p+ region (12), which is constructed as a substrate, with an upper side, a lower side and an electrically effective dopant concentration of 5•1018 - 5•1020 N / cm3, wherein the lower side of the p+ substrate forms the lower side of the stack, followed by a weakly n-doped or p-doped intermediate layer (24) and a n- layer (14), wherein the intermediate layer has a layer thickness between 1 µm and 50 µm and a dopant concentration of 1012 N / cm3 - 1017 N / cm3 and is connected by material couple at least with the p+ region, and wherein the n- layer (14) has a lower side, an upper side, a dopant concentration of 1012 - 1017 N / cm3 and a layer thickness (D2) of 10 - 300 µm, - at least one p region (28), - an n+ region (16) with an upper side, a lower side and a dopant concentration of at least 1019 N / cm3, - a dielectric layer (30) and at least three terminal contact layers (40, 42, 44), wherein the p region (28) has a dopant concentration of 1014 N / cm3 - 1018 N / cm3 and adjoins the n-layer (14) and the n+ region (16), wherein the at least one p region (28) forms together with the the n- layer (14) a first pn transition (34), and the n+ region (16) forms together with the at least one p region (28) a second pn transition (34), and the dielectric layer (30) covers at least the first pn transition (32) and the second pn transition (34) and is connected by material couple with the n- layer (14), the p region (28) and the n+ region (16), and the first terminal contact layer (40) is electrically conductively connected with the lower side of the layer-shaped p+ region (12), and the second terminal contact layer (42) is formed as a field plate on the dielectric layer (30) and serves as gate of the IGBT structure, and the third terminal contact layer (44) is electrically conductively connected with the at least one p region (28) and the at least one n+ region (16), and the layers and the regions each comprise a GaAs compound or consist of a GaAs compound, and the n- layer (14) comprises defects with a concentration of at least 1014 N / cm3, and the dopant concentration increases in a direction from the lower side of the n- layer (14) to the upper side of the n- layer (14) by a factor of 1.5 to 2.5.

2. Stacked monolithic III-V semiconductor module (10), which is constructed as an IGBT structure, according to claim 1, characterised in that the p region (28) formed on the n- layer (14) and the n+ region (16) formed on the p region are each formed as layers and the stack formed from the III-V semiconductor layers has a trench (46) extending from the upper side through the layer-shaped n+ region (16) and the layer-shaped p region (28) into the n- layer (14).

3. Stacked monolithic III-V semiconductor module (10), which is constructed as an IGBT structure, according to claim 2, characterised in that the side surface (48) as well as a base (50) of the trench (46) are covered by the dielectric layer (30), the second terminal contact (42) formed as a field plate extends on the dielectric layer (30) and the third terminal contact layer (44) is arranged at a side surface (52), which is opposite the side surface (48) of the trench (46), of the semiconductor structure, wherein the first pn transition (32) and the second pn transition (34) extend perpendicularly to a side surface (48) of the trench (46).

4. Stacked III-V semiconductor module (10) according to any one of claims 1 to 3, characterised in that the p+ region (12) has a layer thickness (D1) of 50 - 500 µm.

5. Stacked III-V semiconductor module (10) according to claim 2, characterised in that the layer-shaped n+ region (16) has a layer thickness (D3) smaller than 30 µm.

6. Stacked III-V semiconductor module (10) according to any one of claims 1 to 5, characterised in that the p+ region (12) comprises zinc.

7. Stacked III-V semiconductor module (10) according to any one of claims 1 to 6, characterised in that the n+ region (16) comprises chromium and / or silicon and / or palladium and / or tin.

8. Stacked III-V semiconductor module (10) according to any one of claims 1 to 7, characterised in that the n- layer (14) comprises silicon and / or palladium and / or tin.

9. Stacked III-V semiconductor module (10) according to any one of claims 1 to 8, characterised in that the n- layer (14) comprises chromium with a concentration in a range between 1•1013 N / cm3 and 5•1016 N / cm3.

10. Stacked III-V semiconductor module (10) according to any one of claims 1 to 9, characterised in that the n- layer (14) comprises defects with a concentration of at least 1015 N / cm3.