PROCESSING OF PROCESS DATA

Description

1. Field of the invention

[0001] The invention relates in general to the processing of data and in particular to the processing of local bus data at a data bus participant of a local bus. 2. State of the art

[0002] Data bus participants are mostly used in automation systems.

[0003] Automation systems are used primarily for controlling industrial plants, buildings, and means of transport. Controlling an automation system typically requires several sensors and actuators. These monitor and control the process performed by the system. The various sensors and actuators of an automation system are often also referred to as automation devices.

[0004] These automation devices can either be connected directly to the controller of the automation system, or they can first be connected to input and output modules, often also called I / O modules. These can then, in turn, be connected directly to the controller. The automation devices can either be integrated directly into the I / O modules or connected to them via cables or wirelessly.

[0005] The control of an automation system is typically achieved using one or more programmable logic controllers (PLCs). PLCs can be arranged hierarchically or decentrally within the system. PLCs come in different performance classes, allowing them to perform various control and regulation tasks depending on their processing and memory capacity. In its simplest form, a PLC has inputs, outputs, an operating system (firmware), and an interface through which a user program can be loaded. The user program defines how the outputs should be switched based on the inputs. The inputs and outputs can be connected to automation devices and / or I / O modules, and the logic defined in the user program allows the PLC to monitor and control the processes performed by the automation system.The process is monitored by sensors and controlled by actuators. The controller, also known as the central controller or central unit, takes over the control of at least one automation device or I / O module connected to it.

[0006] However, directly connecting the automation devices to the at least one controller, or the I / O modules to the at least one controller, via parallel wiring—that is, running a separate line from each automation device or I / O module to the higher-level controller—is very complex. The cabling effort increases significantly with parallel wiring, especially as the level of automation in an automation system increases. This results in considerable effort during the planning, installation, commissioning, and maintenance phases.

[0007] Therefore, bus systems are predominantly used in modern automation technology to connect automation devices or I / O modules to the controller. These participants in a bus system are also called bus participants. Because data is exchanged on the bus system, bus participants are also frequently referred to as data bus participants. To further simplify the connection of individual automation devices or I / O modules to the bus system, groups of automation devices or I / O modules are often first interconnected using a specialized local bus to form a local bus system. Subsequently, at least one participant in this local bus is connected to the bus system that is connected to the controller.The local bus system may differ from the bus system used to establish the connection with the controller.

[0008] The device connected to the controller's bus system within a group of local bus participants is often referred to as the local bus master. Alternatively, it is also called the head station of the local bus system. This local bus master may contain additional logic, circuitry, or functionalities compared to other local bus participants, which are necessary for connecting to the controller's bus system. The local bus master itself may also contain a PLC. Furthermore, this device may have logic and circuitry for conversion between the two bus systems. The local bus master can therefore also be configured as a gateway or bus converter, ensuring the conversion of data in the format of one bus system to the format of the local bus system and vice versa. Usually, but not always, the local bus master is specialized in connecting the local bus to the higher-level bus.

[0009] The local buses used are usually tailored to the specific operational requirements of the automation devices or I / O modules, or take into account their specific hardware design. The groups of automation devices or I / O modules within the local bus system typically form a subgroup of the automation system, responsible for executing a specific task within the process being carried out by the automation system. The data exchanged on the buses for the process is also frequently referred to as local bus data or process data, because this data contains information for regulating or controlling the process being executed by the automation system. This data can include, among other things, measurement data, control data, status data, and / or other information. Depending on the bus protocol used, other data can be prepended to this information ( English header) or appended ( EnglishThis other data can contain information about the data itself, or information about internal communication on the local bus. A wide variety of different information is known to be included, which can be prepended to or appended to the data depending on the bus protocol used.

[0010] A ring bus is a specialized form of local bus, as described, for example, in US 5,472,347A. In a ring bus, data bus participants, such as automation devices or I / O modules, are each connected to their directly adjacent data bus participants, and data is forwarded sequentially from one data bus participant to the next. The data transmitted on the local bus can also be referred to as local bus data. Thus, data is not sent to all data bus participants simultaneously, but rather sequentially, with each data bus participant receiving data from its upstream data bus participant and forwarding data to its downstream data bus participant. Between receiving the data and forwarding it, the data bus participant can process the received data.When the data reaches the last data bus participant in the sequence, it is routed back from that participant to the first participant in the sequence. This return routing can either go through all data bus participants or bypass them using a bypass line. The ring bus therefore has a downward and an upward flow of data. Data in a ring bus is usually transmitted in the form of data packets that pass through all data bus participants.

[0011] In a ring bus, the data packet is passed from one data bus participant to the next. At any given time, each data bus participant receives only a portion of the data packet from the upstream data bus participant. Once the data contained in this portion has been processed by the data bus participant, it is forwarded to the downstream data bus participant, and simultaneously, a new portion of the data packet is received from the upstream data bus participant. In this way, all parts of the data packet sequentially pass through all data bus participants.

[0012] Each data bus participant has a different processing time, meaning a different time between the acquisition of process data and the availability of a processing result. In the aforementioned state of the art, this differing processing time is accommodated by each data bus participant having adaptive runtime delays. This means the process data is temporarily stored in the data bus participant until it has completed its processing before the data is forwarded to the next data bus participant.

[0013] Further state of the art is disclosed in US 2013 / 177026 A1 and US 2013 / 173868 A1.

[0014] The object of the present invention is to provide a data bus participant and a corresponding method that improves the processing of process data. 3. Summary of the invention

[0015] This task is solved with a data bus participant and a method according to the independent claims. Advantageous embodiments are described in the dependent claims.

[0016] A data bus participant is used to control or monitor a process, in particular by outputting control signals, e.g., to actuators, and / or by receiving measurement signals, e.g., from sensors. The data bus participant converts the control signals and / or measurement signals into process data for the local bus, or vice versa. Data bus participants can also be referred to as local bus participants.

[0017] The data bus participant according to the invention for processing data can be connected to a local bus – i.e., adapted to be connected to the local bus – in particular a ring bus. In a local bus with data bus participants, data is transmitted in the form of data packets. The data packets can also be referred to as telegrams. A data packet has, for example, a header, a payload, and advantageously a checksum. A data packet is advantageously a communication data packet or a process data packet.

[0018] A communication data packet does not contain process data. Advantageously, a communication data packet contains data, in particular for programming and / or controlling and / or monitoring and / or identifying at least one data bus participant. Advantageously, the communication data packet has an address that is assigned to at least one data bus participant. Preferably, the data bus participant is configured to evaluate the address.

[0019] A process data packet contains process data that is sent and / or received by the data bus participants on the local bus. Advantageously, the process data packet does not contain an address for transmitting the process data to or from a data bus participant on the local bus. Within the process data packet, the process data is arranged, for example, in such a way that data bus participants can identify the process data belonging to their respective data bus participant based on the position of the process data within the packet, such as one or more bits within an assigned contiguous data block (1 byte). Advantageously, the process data packet has an identifier (IDE) that is assigned to the type of data packet, i.e., the process data packet, and is identifiable by the data bus participant. The process data can also be referred to as local bus data.

[0020] The data bus participant according to the invention has an input interface for receiving initial local bus data and an output interface for sending subsequent local bus data. The input interface can, for example, be connected to the local bus – i.e., adapted to be connected to the local bus – and the data bus participant can receive initial local bus data from an upstream data bus participant via the input interface. The output interface can, for example, be connected to the local bus – i.e., adapted to be connected to the local bus – and the data bus participant can send subsequent local bus data to a downstream data bus participant via the output interface. In this case, the data bus participants themselves form the local bus, and further elements, e.g., a termination element, may also be provided.The upstream data bus participant can be a data bus participant that physically precedes the receiving data bus participant, either directly or indirectly, on the local bus, or it can be the local bus master, which, for example, represents the first data bus participant on the local bus. The downstream data bus participant can be a data bus participant that physically follows the sending data bus participant, either directly or indirectly, on the local bus. The reception and transmission of the first and second local bus data can occur with a specific, preferably constant, bus clock. This bus clock therefore specifies the clock frequency at which communication between the data bus participants takes place. For example, a portion of the local bus data is received and transmitted per clock cycle. This portion of the local bus data can, for example, be received or sent bit by bit, and a specific number of bits can be received and sent with each clock cycle.For example, one bit or eight bits (one byte) can be received and sent per clock cycle. However, several clock cycles can elapse between receiving and sending, and sending and receiving always occur in integer intervals. In particular, the data bus participant must have time between receiving the first local bus data and sending the second local bus data to process the first data in order to generate the second data.

[0021] For processing data, in particular the first local bus data, the data bus participant according to the invention can have a processing component adapted for clock-controlled processing of the first local bus data and / or data stored in a memory and for outputting at least one control signal that controls a logic unit. The stored data can be stored in a memory, which can serve as a means for holding the data. The storage means can be part of the data bus participant, or alternatively, it can be external to the data bus participant or an add-on module. The data bus participant only needs access to the storage means.

[0022] The logic unit is adapted to modify at least a portion or a specific amount of the first local bus data based on the control signal from the processing component that generates the second local bus data. This modification can involve bitwise altering the first local bus data currently present at the data bus participant. Alternatively, the modification triggered by the control signal can consist of leaving the first local bus data unchanged. In this case, the first local bus data passes through the data bus participant unchanged because, for example, the first local bus data is not directed at the data bus participant itself—that is, it is not designed to trigger control or regulation at that data bus participant, but rather is directed at another data bus participant. In this case, the processing component can generate a control signal that instructs the logic unit not to modify the first local bus data.In this case, the first local bus data corresponds to the second local bus data. If a change occurs, the control signal from the processing component directs the logic unit to modify the first local bus data, or at least a part or set of it, so that the first local bus data differs from the second. The part of the logic unit adapted for data modification is preferably not clock-controlled.

[0023] In one embodiment of the invention, the second local bus data present at the output interface is instantaneous compared to the output of the first local bus data from the input interface to the logic unit—apart from the inherent delay of the logic unit's components. During an initial period, when the processing component generates a control signal that instructs the logic unit's components to make changes, these changes may initially be unstable. However, to ensure deterministic runtime behavior of the data bus participant and stable changes through the control signal in every case, while preventing premature transmission of the second local bus data via the output interface, the logic unit is adapted to clock-controlled delay of the transmission of the second local bus data via the output interface.A time interval caused by the clock-controlled delay ensures that the instability of the changes has ceased.

[0024] The clock-controlled delay is advantageously a constant delay. This means that each data bus participant, or rather its logic unit, delays the transmission of the second local bus data by a constant time or a specific number of clock cycles of the processing component, or by a constant number of bus cycles of the local bus. For this purpose, the logic unit can, for example, have a number of delay elements corresponding to the number of delayed clock cycles / bus cycles. That is, for each clock cycle or for each constant time by which the transmission of the second local bus data is to be delayed, there is advantageously exactly one delay element. Alternatively, a counter can also be used. For example, a signal can be output from the input interface to the logic unit, which, for instance, confirms the validity of the first local bus data.This signal is delayed by a specific constant time or a specific constant number of clock cycles / bus cycles by a number of delay elements before it is passed from the logic unit to the output interface. The output interface is advantageously configured to only forward the second local bus data to the downstream data bus participant upon receipt of this signal, which indicates the validity of the first local bus data. The validity of the first local bus data depends on a hardware check, such as a hardware counter. This means that a validity signal is delayed, but not the data itself. This has the advantage that the delay elements can be designed very simply, because they do not need to hold the data, but only a validity signal, which can be a single bit. The delay elements can therefore be implemented using simple components.The number of delay elements can correspond to the number of operating cycles / bus cycles to be delayed. The number of delay elements is chosen based on the time required by the processing component to perform processing and output a corresponding control signal to the logic unit. The output interface is therefore configured to send the second local bus data only upon receipt of the validity signal. In other words, the output interface waits to send the second local bus data until a delayed validity signal is received.

[0025] The data bus participant according to the invention achieves deterministic runtime behavior for the data bus participants and the entire local bus. This means that the time required to process the process data on the local bus is known to the local bus master and the controller and depends only on the number of data bus participants involved. This has the advantage that the runtime of the local bus can be predicted during installation. In other words, the runtime is a multiple of the processing time of a single data bus participant. In non-deterministic systems, the runtime is the sum of the different processing times of the various data bus participants.

[0026] In a preferred embodiment of the data bus participant according to the invention, the logic unit is arranged between the input interface and the output interface. The logic unit establishes the connection between the input interface and the output interface. Preferably, the logic unit is connected to both the input and output interfaces. This ensures that no other units cause a non-deterministic delay in processing.

[0027] In a further preferred embodiment of the data bus participant according to the invention, the operating clock of the processing component is based on the clock frequency of a bus clock of the local bus. For example, the operating clock can be a multiple of the bus clock or even equal to the bus clock. The operating clock of the processing component indicates the clock frequency at which the processing component operates and can process data. The bus clock indicates the clock frequency at which the output interfaces send secondary local bus data. This clock frequency can be specified by the local bus master, which sends data to the downstream data bus participant of the local bus. It is also conceivable that a data bus participant has a certain number of delay elements and that the data bus participant is configured before or upon insertion into the local bus such that it uses only a specific number of these delay elements.This specific number can be adjusted so that all data bus participants in the local bus use the same number of delay elements.

[0028] In a further preferred embodiment of the data bus participant according to the invention, the logic unit comprises at least one delay element which has a clock input for delaying its stored value. The delay element can, for example, be a bistable flip-flop that can assume two stable states. With the aid of the clock input, the bistable flip-flop can be configured to release the control inputs only at certain times, i.e., to allow a change in the stored or delayed validity signal only at specific times. Considering a clock signal also enables synchronization of the bistable flip-flop with the processing component.

[0029] According to the invention, the logic unit comprises non-clocked logic elements or logic blocks. Advantageously, these logic elements have a very short signal propagation delay. The modification of the first local bus data by the logic unit is based on the control signal of the processing component. This signal is not instantaneous because the processing component requires a certain amount of time to process, for example, the first local bus data. "Processing" in this case means that the processing component must execute a specific set of instructions for the currently available first local bus data. This set of instructions can be stored in the data bus participant in the form of a list. Based on these instructions, the processing component is able to generate a control signal that instructs the logic unit to make a corresponding modification to the first local bus data.The processing component can access an instruction set containing, for example, the instructions "SKIP", "MOVE", "NEGATION", "INCREMENT", "AND", and "OR", or a combination thereof. The instructions to be executed are stored in instruction lists within the data bus participant or in a memory accessible to the data bus participant. However, the processing of the instructions and the generation of the control signal are clocked and take a certain amount of time. Therefore, it can be said that the logic elements of the logic unit for modifying the initial local bus data are not clocked, but their behavior can be controlled by a clock-dependent control signal. This control signal can cause either a change to the initial local bus data or no change at all.When the control signal triggers a change, the first local bus data at the logic unit's input differs at least partially from the second local bus data at the logic unit's output. If the control signal signals that no change should be made, the first local bus data at the logic unit's input corresponds to the second local bus data at the logic unit's output.

[0030] In a further preferred embodiment of the data bus participant according to the invention, the input interface is adapted for serial-to-parallel conversion and / or for decoding the first local bus data, and the output interface is adapted for parallel-to-serial conversion and / or for encoding the second local bus data. That is, the data on the local bus is transmitted in serial form and optionally in coded form. The input interface converts the serial data into parallel data streams and decodes them, if necessary, for processing by the processing component or for modification by the logic unit, before the second local bus data is subsequently converted back to serial by the output interface and optionally encoded before being sent to the downstream data bus participant.The input interface can, for example, be adapted for the parallel output of the first local bus data in the form of a symbol with a fixed number of bits, such as 8 bits, or 1 byte. Due to the serial-to-parallel conversion, a constant number of data bits are available at the logic unit; these can be modified or provided unchanged at the logic unit's output with virtually no delay – apart from the inherent delay of the logic unit's components.

[0031] In a further preferred embodiment of the data bus participant according to the invention, the logic unit also has a bypass connection between the input interface and the output interface for forwarding first local bus data as second local bus data. This local bus data can, for example, contain control data that cannot or should not be modified by the logic unit. This local bus data via the bypass connection preferably does not contain any process data.

[0032] The aforementioned task is also solved by a method for processing data in a data bus participant that can be connected to a local bus, in particular a ring bus. That is, the data bus participant must be adapted to be connected to the local bus.The method involves receiving initial local bus data at an input interface connectable to the local bus – i.e., an input interface adapted to be connected to the local bus – clock-controlled processing of the initial local bus data and / or data stored in memory by a processing component, output of a control signal by the processing component, modification of at least part or a quantity of the initial local bus data based on the control signal to generate second local bus data to be sent by a logic unit, clock-controlled delay of the sending of the second local bus data through an output interface connectable to the local bus – i.e., an output interface adapted to be connected to the local bus – by the logic unit, and sending of the second local bus data through the output interface after the delay.The modification of the initial local bus data by the logic unit can, for example, be performed at a bit-granular level. The processing component can access an instruction set containing, for example, the instructions "SKIP", "MOVE", "NEGATION", "AND", "OR", and "INCREMENT", or a combination thereof, where the instructions to be executed are stored in instruction lists within the data bus participant or in a memory to which the data bus participant has access. 4. Brief description of the drawings

[0033] The invention is explained in more detail below with reference to exemplary embodiments and the accompanying drawings. Further details, features, and advantages of the subject matter of the invention will become apparent from the described exemplary embodiments. The drawings show: Fig. 1 a schematic block diagram of an exemplary automation system with a programmable logic controller and an exemplary ring bus; Fig. 2 a schematic representation of a data packet containing local bus data sent by a local bus master; Fig. 3 a schematic representation of an exemplary embodiment of a data bus participant with a processing unit for processing the data in Figure 2 shown data package; and Fig. 4 a schematic block diagram of an exemplary embodiment of a logic unit of the in Figure 3 shown data bus participant. 5. Description of preferred embodiments

[0034] Figure 1Figure 1 shows a schematic block diagram of an automation system. It will be understood by those skilled in the art that the automation system shown is only an example and that all elements, modules, components, participants, and units belonging to the automation system may be configured differently but can nevertheless fulfill the basic functionalities described here.

[0035] The in Figure 1The automation system shown has a higher-level control unit 1, which can be implemented, for example, with a programmable logic controller (PLC). Such a PLC 1 is fundamentally used to control and regulate the process executed by the automation system. Nowadays, however, PLCs 1 in automation systems also perform more advanced functions, such as visualization, alarm generation, and recording of all process-related data, and as such, the PLC 1 acts as a human-machine interface. PLCs 1 are available in different performance classes, offering varying resources (computing capacity, storage capacity, number and type of inputs and outputs, and interfaces) that enable the PLC 1 to control and regulate the automation system's process. A PLC 1 typically has a modular design and consists of individual components, each fulfilling a different task.A PLC (Programmable Logic Controller) typically consists of a central processing unit (with one or more main processors and memory modules) and several modules with inputs and outputs. Such modular PLCs can be easily expanded by adding modules. The specific modules required depend on the complexity of the process and the overall design of the automation system. In modern automation systems, the PLC is usually no longer an independent system, but rather connected to the internet or intranet via interfaces (not shown here). This means the PLC is part of a network from which it can receive information, instructions, programming, and so on.For example, PLC 1 can receive information about materials supplied to the process via a connection to a computer located on the intranet or internet. This allows for optimal process control, for instance, by knowing the quantity or properties of these materials. It is also conceivable that PLC 1 can be controlled by a user via access from the intranet or internet. For example, a user can access PLC 1 using a computer, also called a master computer, and check, modify, or correct its user programming. Accordingly, access to PLC 1 is possible from one or more remote control centers or monitoring stations. The master computers may, if necessary, have visualization capabilities to display process sequences.

[0036] To control the automation system's processes, PLC 1 is connected to automation devices. To minimize wiring effort, bus systems are used for these connections. In the Figure 1 In the illustrated embodiment, the PLC 1 is connected to a local bus master 3 of a subordinate local bus system via a higher-level bus 2, which in this embodiment can be a fieldbus. However, not only a local bus master 3 of a local bus, as in this embodiment, can be connected to the higher-level bus 2, but also any other devices – not shown here – that are configured for communication with the PLC 1.

[0037] In the embodiment shown here, the higher-level bus 2 is connected to the local bus master 3. For this purpose, the local bus master 3 has a first interface 4 designed to connect to the higher-level bus 2. The interface 4 can, for example, have a socket, and the higher-level bus 2 can have a plug that can be received by the socket. The plug and socket can, for example, be modular plugs and sockets, meaning that each wire of the higher-level bus 2 is electrically or optically connected to a connection in the modular socket. However, those skilled in the art are also aware of other ways in which an interface 4 can be designed so that the local bus master 3 can be electrically or optically connected to the higher-level bus 2.Experts are familiar with screw, twist, click, or plug connections, which can be used to establish an electrical or optical connection. In most cases, a male connector is inserted into a female counterpart. This insertion usually not only establishes the electrical or optical connection but also ensures that the two parts are mechanically coupled and can only be separated by applying a certain force. However, it is also conceivable that the higher-level bus 2 is hardwired to interface 4.

[0038] In the embodiment shown here, the local bus master 3 has a second interface for connecting it to the local bus. Data bus participants 7a, 7b, ..., 7n are connected to or form the local bus. Advantageously, the local bus is configured such that a data packet sent by the local bus master 3 is transmitted through all data bus participants 7a, 7b, ..., 7n connected to the local bus and back to the local bus master 3. Each data bus participant 7a, 7b, ..., 7n receives only a portion of the data packet from the preceding data bus participant 7a, 7b, ..., 7n. After a period of time in which the data contained in this part can be processed by the data bus participant 7a, 7b, ..., 7n, the part is forwarded to the downstream data bus participant 7a, 7b, ..., 7n and at the same time a new part of the data packet is received by the upstream data bus participant 7a, 7b, ..., 7n.In this way, all parts of the data packet sequentially pass through all data bus participants 7a, 7b, ..., 7n. The local bus is advantageously configured in a ring-shaped structure. Such local buses can also be referred to as ring buses 6. Alternatively, the local bus can also be configured in a branch or star topology, or as a combination or hybrid of the aforementioned configurations. The sending and receiving of the data packets is accomplished via the second interface of the local bus master 3. In the embodiment shown here, the second interface is divided into a first part 5a and a second part 5b. The first part 5a of the second interface establishes the downward connection in the ring bus 6, and the second part 5b of the second interface establishes the upward connection in the ring bus 6.

[0039] The Ringbus 6, whose data transmission direction is indicated by arrows in the Figure 1The embodiment shown in the example shown here comprises data bus participants 7a, 7b, ..., 7n. In this embodiment, each of these data bus participants 7a, 7b, ..., 7n has an interface 8 for receiving data from an upstream or preceding data bus participant 7a, 7b, ..., 7n. In the case of data bus participant 7a, it receives data from the upstream local bus master 3 via interface 8. The data on the local bus 6 can also be referred to as local bus data. Furthermore, in this embodiment, each of the data bus participants 7a, 7b, ..., 7n has an interface 9 for forwarding data to a downstream or subsequent data bus participant 7a, 7b, ..., 7n. In the case of data bus participant 7a, it sends data to the downstream data bus participant 7b via interface 9.Interfaces 8 and 9 are used to propagate data downwards along the ring bus 6, i.e., away from the local bus master 3. Furthermore, in this embodiment, data bus participants 7a, 7b, ..., 7n also have interfaces 10 and 11 for propagating data upwards along the ring bus 6, i.e., towards the local bus master 3. In the case of data bus participant 7a, interface 10 is designed to receive data from the downstream data bus participant 7b, and interface 11 is designed to forward data to the upstream data bus participant, here the local bus master 3. Therefore, interfaces 9 and 11 can also be described as transmitter interfaces, whereas interfaces 8 and 10 are receiver interfaces.

[0040] In the embodiment shown here, the connections between the interfaces and the PLC 1 or the data bus participants 7a, 7b, ..., 7n are implemented using cables or circuit boards for direct or indirect contact via electrical contacts. Alternatively, the individual connections can be made wirelessly, with the interfaces providing the necessary conversions to the radio standards used.

[0041] Even though the local bus master 3 and the individual data bus participants 7a, 7b, ..., 7n are shown spaced apart from each other in the embodiment shown here, i.e., the local bus master 3 is arranged decentrally from the data bus participants 7a, 7b, ..., 7n, it is known to those skilled in the art that the data bus participants 7a, 7b, ..., 7n and the local bus master 3 – which also represents a data bus participant of the ring bus 6 – can also be directly connected to each other. For example, contacts of one data bus participant can engage corresponding receptacles or receiving contacts of a directly adjacent data bus participant to establish an electrical connection between the data bus participants so that data can be sent in the downward and upward directions. For example, the data bus participants 7a, 7b, ..., 7n can have receptacles on the side facing away from the master and contacts on the side facing the master. If the data bus participants 7a, 7b, ...If the data bus participants 7a, 7b, ..., 7n are arranged in a corresponding sequence, the contacts of each data bus participant 7a, 7b, ..., 7n engage with the corresponding contacts of the other data bus participant 7a, 7b, ..., 7n, thus establishing an electrical connection. The local bus master 3 then has corresponding contacts on its side that engage with the corresponding contacts of the first data bus participant 7a, thereby establishing an electrical connection between interfaces 5a and 8 or interfaces 5b and 11. However, other methods are also known to those skilled in the art, such as push contacts or knife-and-fork contacts, for establishing an electrical or optical connection between two directly adjacent data bus participants 7a, 7b, ..., 7n.

[0042] If the data bus participants 7a, 7b, ..., 7n and the local bus master 3 are to be directly connected, they can also have mechanical mounts or fasteners with which the individual data bus participants 7a, 7b, ..., 7n and the local bus master 3 can be connected to each other. For example, a data bus participant 7a, 7b, ..., 7n can have a projection on one side and an undercut on the other. If the data bus participants 7a, 7b, ..., 7n are then connected in series, one projection engages with an undercut of the other data bus participant 7a, 7b, ..., 7n, thus creating a mechanical connection. For easy connection of the data bus participants 7a, 7b, ..., 7n, they can also be arranged on a common mount, for example, a DIN rail. The data bus participants 7a, 7b, ..., 7n have corresponding fastening means. Alternatively or additionally, the data bus participants 7a, 7b, ..., 7n can also have, for example, detachably connectable fastening means with which the data bus participants 7a, 7b, ..., 7n can be attached either to the DIN rail or to another mounting.

[0043] The detachable fastening device can be interchangeable, and a suitable fastening device for the desired mounting can be connected to the data bus participants 7a, 7b, ..., 7n, so that these can be attached to the desired mounting.

[0044] Furthermore, the data bus participants 7a, 7b, ..., 7n in the Figure 1 The illustrated embodiment also includes a processing unit 12, which consists, for example, of a processing component and a logic unit, which are arranged in Figure 3are shown in more detail. Processing unit 12 can also be referred to as the overall circuit of the data bus participant. That is, processing unit 12 receives data via inputs 8 and 10 and outputs data on outputs 9 and 11. Furthermore, processing unit 12 can receive data from inputs and outputs 13 and 14 receive or output. Furthermore, processing unit 12 has access to a memory – not shown here – of data bus participant 7a, 7b, ..., 7n in which, for example, data, process data, or instruction lists are stored.

[0045] The processing unit 12 can be configured to process received data and output data. Data to be processed can be received either from an upstream data bus participant or from inputs 13 of data bus participant 7a, 7b, ..., 7n. The inputs 13 of data bus participant 7a, 7b, ..., 7n can be connected to sensors 15 that send, for example, measurement data, status data, etc. Processed data can be output either to a downstream data bus participant or to outputs 14 of data bus participant 7a, 7b, ..., 7n. The outputs 14 of data bus participant 7a, 7b, ..., 7n can be connected to actuators 16 that, for example, perform a specific action using the data addressed to them. If data processing is also required in the upstream direction, data can also be received from a downstream data bus participant 7a, 7b, ..., 7n are received and processed data is sent to an upstream data bus participant 7a, 7b, ..., 7n.

[0046] For the sake of simplicity, in the embodiment shown here, the data bus participants 7a, 7b, ..., 7n are shown with only one input 13 and one output 14, and only data bus participant 7b is connected to sensor 15 and actuator 16.

[0047] However, it is known to those skilled in the art that the data bus participants 7a, 7b, ..., 7n can have a multitude of inputs and outputs 13 and 14, and can be connected to a multitude of different sensors 15 and actuators 16. The characteristic feature of the sensors 15 is that they receive data or signals and send them to the data bus participants 7a, 7b, ..., 7n, whereas actuators 16 receive data or signals from the data bus participants 7a, 7b, ..., 7n and perform an action based on this data or these signals.

[0048] Alternatively, interfaces 8, 9, 10, and 11 can be integrated into a module unit, and data bus participants 7a, 7b, ..., 7n can be plugged into this module unit. The module units can also be referred to as the basic elements of the ring bus 6. The ring bus infrastructure is built using the module units, and the data bus participants 7a, 7b, ..., 7n are interchangeable, so that the ring bus 6 can be configured with any number of data bus participants 7a, 7b, ..., 7n. The module units also ensure that even if a data bus participant 7a, 7b, ..., 7n is removed, communication between the remaining data bus participants 7a, 7b, ..., 7n is not interrupted, because communication continues via the remaining module units.

[0049] The data bus participants 7a, 7b, ..., 7n shown in this embodiment are also frequently referred to as I / O modules due to their inputs and outputs 13, 14, which can be connected to sensors 15 and actuators 16, respectively. Although the data bus participants 7a, 7b, ..., 7n are shown spatially separated from the sensors 15 and actuators 16 in this embodiment, the sensors 15 and actuators 16 can also be integrated into the I / O module.

[0050] The ring bus 6 shown in the embodiment presented here is based on cycle frame communication. A cycle frame can be defined, for example, as a recurring (cyclic), preferably equidistant, time interval in which data can be transmitted on the ring bus 6. The cycle frame has, for example, at least one start identifier (SOC) and a time range for data transmission. Several start identifiers (SOCs) of successive cycle frames are advantageously equidistant from each other in time. The aforementioned time range is provided for the transmission of data, which can be transmitted within the cycle frame in the form of data packets. The start identifier (SOC) and the data packets are transmitted via the ring bus 6 and pass through all data bus participants 7a, 7b, ..., 7n. Advantageously, the cycle frame is initiated by the local bus master 3 in the ring bus 6.The startup identifier (SOC) can be transferred separately, i.e., as an independent symbol, or advantageously contained in a startup data package (SOC package).

[0051] Within the time frame of the cycle, no, one, or several data packets are transmitted. Advantageously, idle data is inserted into a cycle frame, particularly adjacent to at least one data packet. Advantageously, the transmission of the data packets and / or the idle data results in a continuous signal on the ring bus 6. This signal enables the data bus participants 7a, 7b, ..., 7n to synchronize to it. Advantageously, the cycle frame also includes a trailer. The trailer has a variable length and follows the data transmission time frame, preferably until the next start identifier (SOC) of the next cycle frame. Advantageously, the trailer contains idle data.

[0052] Each data packet is sent downwards by the local bus master 3 to the first data bus participant 7a of the ring bus 6. This participant receives the first part of the data packet via interface 8. Such a part of the data packet is subsequently referred to as a piece or unit. Data bus participant 7a then processes the part and forwards it to the next data bus participant 7b via interface 9. Preferably, the first data bus participant 7a simultaneously receives a second part of the data packet, and so on. The size of the data packet parts, i.e., the packet's segmentation, depends on the storage capacity of data bus participants 7a, 7b, ..., 7n. For example, a fixed number of bits, such as 8 bits of the data packet, can be available for processing simultaneously at data bus participants 7a, 7b, ..., 7n.

[0053] The data packet accordingly passes through the data bus participants 7a, 7b, ..., 7n unit by unit, in chunks, or parts by part, for example, in segments or symbols of 8 bits. The part of the data packet that has been processed by the last data bus participant, in this embodiment data bus participant 7n, then travels upwards through the ring bus 6, so that the parts, starting from the last data bus participant 7n, are sent back upwards towards the local bus master 3 through all data bus participants 7a, 7b, ..., 7n. For this purpose, the last data bus participant 7n either has a switchable bridge that connects interface 9 with interface 10, or a switchable bridge – not shown here – is connected to the last data bus participant 7n, which performs the function of routing the parts of the data packet from interface 9 to interface 10.Alternatively, interface 10 of data bus participant 7n can also be connected directly to interface 5b of local bus master 3 using a bypass line - not shown here.

[0054] In the upward direction, the units of the data packet(s), as in the embodiment shown here, can be looped back to the local bus master 3 by the individual data bus participants 7a, 7b, ..., 7n without further processing. However, it is also conceivable that the units of the data packet are processed again in the upward direction, so that the data packet can be processed twice: once in the downward direction to the last data bus participant 7n and once in the upward direction to the local bus master 3. For example, processing in the upward direction can be carried out by signal refresh and / or phase shifting.

[0055] When processing data packets downwards, i.e., away from local bus master 3, or upwards, i.e., towards local bus master 3, processing is accomplished using instruction lists. These instruction lists contain sets of instructions that can be executed by the processing unit 12 of the data bus participants 7a, 7b, ..., 7n. The instruction lists themselves can be sent to the individual data bus participants 7a, 7b, ..., 7n by local bus master 3 during an initialization phase, or, advantageously, sent to the data bus participants 7a, 7b, ..., 7n during ongoing communication, so that programming of the data bus participants 7a, 7b, ..., 7n takes place without interrupting communication.

[0056] Which instruction lists the data bus participants 7a, 7b, ..., 7n should use can be communicated to them by means of an instruction list index. This instruction list index informs the data bus participant which stored instruction list should be used. An instruction list index is thus assigned to an instruction list, or vice versa, so that the instruction list to be used can be identified with the help of the instruction list index. For this purpose, the instruction list index preferably has a value that is assigned to an instruction list; for example, the value points to a specific instruction list or to its memory location. The value itself can also be the memory address where the instruction list is stored or where at least the first instruction of the instruction list is stored.Alternatively or additionally, the value can also point to a memory area where the corresponding instruction list is stored. In the aforementioned cases, one can also speak of a direct mapping. The value of the instruction list index can, for example, also be used as input for a conversion table (. EnglishA lookup table (LUT) is a lookup table. The value of the instruction list index is the input value of the LUT. The output value of the LUT can be the memory address of the first instruction in the corresponding instruction list or otherwise identify the LUT. The LUT can be implemented in software or hardware, for example, as logic, and specifies a unique mapping from an input value to an output value, where the output value indicates the instruction list to be used. The specific mapping between the LUT index and the instruction list depends on the LUT. Using a LUT can also be described as an indirect mapping.In both direct and indirect assignment, the instruction list to be used by the data bus participant can be uniquely identified, i.e., located, via the instruction list index. The instruction list index can be inserted into the data packet before the local bus data to be processed, so that the data bus participants 7a, 7b, ..., 7n can use the corresponding instruction list according to the order of the local bus data in the data packet. The instruction lists contain instructions that are adapted to the order of the local bus data in the data packet. The instruction lists can, for example, contain a "SKIP" instruction for local bus data not addressed to data bus participant 7a, 7b, ..., 7n, thus instructing data bus participant 7a, 7b, ..., 7n to skip the corresponding part of the data packet, whereas the instruction list for local bus data addressed to data bus participant 7a, 7b, ..., 7n are directed at corresponding instructions for processing the local bus data. The processing of the local bus data can thus be decoupled from the actual position of the local bus data in the data packet, since the data bus participants are adapted to the order of the local bus data in the data packet using the instruction lists. The processing of local bus data by processing unit 12 is in . Figure 3 shown in more detail.

[0057] First, however, in Figure 2 A schematic representation of a data packet 17 used by a local bus master 3, containing local bus data P1, P2, and P3, is shown. The local bus data P1, P2, and P3 are, for example, process data. The data packet 17 shown consists of a general header, an information section, and a checksum section.

[0058] The header contains a field 18, which contains a unique, one-time-occurring bit pattern IDE, also known as a codeword or packet identifier. The number and structure of unique bit patterns or codewords depend on the encoding used on the ring bus 6. Alternatively or additionally, special bit patterns or codewords can be defined in the bus protocol used. The only important thing is that the data bus participants 7a, 7b, ..., 7n can uniquely identify the type of data packet 17 from the bit pattern or codeword of field 18. The codeword of field 18 is forwarded directly, for example, via a bypass connection. In the embodiment shown here, the data bus participants 7a, 7b, ..., 7n knowledge that if a field 18 is received with a bit pattern IDE, it is a data packet 17 carrying process data P1, P2, P3.

[0059] The header can also contain further information, such as whether data packet 17 is moving downwards or upwards. For example, the last data bus participant 7n can write information into the header indicating that data packet 17 has already passed through this data bus participant 7n and been sent back towards local bus master 3. Furthermore, the header can also contain information about the length of data packet 17, so that data bus participants 7a, 7b, ..., 7n can check the integrity of data packet 17 or know how many parts of data packet 17 are still to be received by data bus participants 7a, 7b, ..., 7n before a new data packet 17 is sent. However, those skilled in the art are also aware of other fields that can be written into the header of a data packet 17, which are used for control or error detection by data bus participants 7a, 7b, ..., 7n can be used.

[0060] The information portion of data packet 17 can first contain an instruction list index field 19, ILI, which specifies which instruction list the data bus participants 7a, 7b, ..., 7n should use. For example, during normal operation of the ring bus 6, it may be intended that all data bus participants 7a, 7b, ..., 7n use their first instruction list, whereas in the event of an error, the second instruction list should be used. The instruction list index can directly point to the memory location of the instruction list stored in the data bus participant 7a, 7b, ..., 7n, or the instruction list index can contain a value that allows the data bus participant 7a, 7b, ..., 7n to locate the corresponding instruction list, for example, via a conversion table. The information portion also contains the actual process data P1, P2, and P3. These process data P1, P2, P3 are shown with different patterns in the embodiment shown here.

[0061] In the embodiment shown here, data packet 17 is divided into symbols of 8 bits each. Data packet 17 is received and processed in this segmentation by data bus participants 7a, 7b, ..., 7n. That is, first, the local bus master 3 sends the symbol or field IDE 18 to the first data bus participant 7a. After a predetermined time, the local bus master 3 sends another symbol of the header of data packet 17 to data bus participant 7a, which in turn simultaneously sends the symbol or field IDE 18 to data bus participant 7b. This predetermined time between sending and receiving the symbols of the data packet can also be referred to as the clocking of the local bus, i.e., the bus clock. Sending and receiving can occur on each clock cycle or can take place over several clock cycles.

[0062] Furthermore, data packet 17 contains a field 20 in its information section, which can be configured as a counter and which can be incremented or decremented by each data bus participant 7a, 7b, ..., 7n through which this part of data packet 17 has already been routed. The counter value of field 20 can be used by the local bus master 3 to check whether data packet 17 has passed through all data bus participants 7a, 7b, ..., 7n.

[0063] The in Figure 2 The data packet 17 shown has a unique bit pattern 18 and ends with a checksum. However, those skilled in the art are aware that a cycle frame can contain multiple data packets, which are organizationally contained within a single cycle frame. Data packets themselves can be identified by unique prefixed bit patterns.

[0064] In the embodiment shown here, the data bus participants 7a, 7b, ..., 7n are configured to evaluate such that when a data packet with the bit pattern IDE 18 is received, this data packet carries process data P1, P2, P3, ..., PN. The processing of local bus data using the example of process data P1, P2, P3 is described in Figure 3 shown in more detail.

[0065] Figure 3 shows a schematic representation of an exemplary embodiment of a data bus participant 7a of the in Figure 1 The ring bus 6 shown is used for processing a [unclear] in [unclear] Figure 2 The data package shown, 17, contains the process data P1, P2, P3 as local bus data.

[0066] In the embodiment shown here, the data bus participant 7a has an input interface 8 which symbolically transmits the data packet 17 downwards - as shown in Figure 2As shown, the device receiving this data packet can also be referred to as a local bus data packet or local bus data. In the case of data bus participant 7a, it receives the local bus data from the upstream local bus master 3 via input interface 8. In the embodiment described here, the local bus data is received serially at input interface 8. This means that the local bus data is received sequentially, specifically bit by bit. In the embodiment described here, the local bus data is received serially. Figure 3 In the illustrated embodiment, further components can be arranged in the input interface 8. For example, a decoder – not shown here – capable of decoding an encoded input signal can also be integrated at or within the input interface 8. Furthermore, in Figure 3It has been shown that at least one serial-to-parallel converter is integrated into the input interface 8, which converts the serially received part of the data packet 17 into a parallel data stream 24. For example, the serial-to-parallel converter can convert the symbols of the data packet 17 into an 8-bit parallel data stream 24. This parallel data stream 24 is then fed to the processing unit 12 and can accordingly also be referred to as the parallel input data stream 24.

[0067] Furthermore, the input interface 8 can output a validity signal 23, which indicates that the data was received without errors. The validity signal 23 is also supplied to the processing unit 12 and, in particular, to the processing component 21a.

[0068] In the embodiment shown here, the processing unit 12 comprises a processing component 21a and a logic unit 21b. The parallel data stream 24 generated by the serial-to-parallel converter is fed to the processing component 21a and the logic unit 21b. The processing component 21a is configured to evaluate the instruction lists 19 received prior to the process data P1, P2, P3 and to control which instruction list, and thus which instructions, must be executed for the subsequent process data P1, P2, P3. Using these instructions and the fed parallel data stream 25, the processing component 21a is configured to generate a control signal 26. This control signal 26 controls the logic unit 21b to modify or manipulate the incoming parallel data stream 24.The logic unit 21b, which can also be referred to as the manipulation unit, is configured to generate a modified parallel data stream 27 based on the control signal 26. This modified parallel data stream 27 is fed to the output interface 9 and can accordingly also be referred to as the parallel output data stream 27. The parallel data stream 24 corresponds to the first local bus data at the input interface 8 at any given time; for example, at time τ = 1, this parallel data stream 24 corresponds to the 8 bits of the first process data P1. Thus, at time τ = 1, the parallel data stream 24 represents the 8 bits of the first local bus data P1. Almost without delay, the logic unit also provides the parallel data stream 27 at time τ = 1, i.e., the second local bus data P1' at the output interface 9.Since no change to the first local bus data P1 has yet occurred at this time, the parallel data streams 24 and 27 still correspond. However, after the logic unit 21b receives the control signal 26 from the processing component 21a, the first local bus data P1 is changed to the second local bus data P1', so that at time τ = 1' the first local bus data P1 no longer corresponds to the second local bus data P1', at least under the assumption that the control signal 26 controls a change to the first local bus data P1. The same applies to τ = 2 / 2' with the process data P2 and τ = 3 / 3' with the process data P3. This means that even if the first local bus data is always referred to as P1, P2, P3 in the following, or the second local bus data as P1', P2', P3' in the following, the person skilled in the art is aware that the individual process data P1, P1', P2, P2', P3, P3' are each always associated with a specific time τ = 1 / 1', τ = 2 / 2', τ = 3 / 3', etc.This is because, at any given time, a data bus participant 7a, 7b, ..., 7n only has access to and can process a portion of data packet 17. Therefore, the following description must always be considered in conjunction with the temporal component.

[0069] Since logic unit 21b consists of logic elements (not shown here), there is virtually no delay in the signal flow between the input and output of logic unit 21b. This means that when the first local bus data P1, P2, P3 are present at the input of logic unit 21b, they are output as the second local bus data P1', P2', P3' at logic unit 21b almost without delay. In this case, the first local bus data P1, P2, P3 (still) correspond to the second local bus data P1', P2', P3' because logic unit 21b has not yet made any changes to the first local bus data P1, P2, P3. Only through a control signal 26 generated by processing component 21a, which is fed to logic unit 21b, is a change made to the first local bus data P1, P2, P3.The processing component 21a is configured to perform a predetermined processing operation on the process data P1, P2, P3 based on instructions in its instruction list, the corresponding list being selected in data packet 17 using ILI 19. However, the processing component 21a requires time to generate the control signal 26 and execute the instructions in the instruction list. The logic unit 21b, on the other hand, can provide the parallel data stream 24 as a parallel data stream 27 at the output interface 9 almost without delay. To prevent the output interface 9 from prematurely converting the parallel data stream 27 into a serial signal via the parallel-to-serial converter located at the output interface 9 and sending this to the downstream data bus participant 7b, the output interface 9 is configured to transmit only after receiving a validation signal 23 from the logic unit 21b.

[0070] Output interface 9 can also include an encoder to encode the serial data stream according to system requirements. The validity signal 23' at the input of output interface 9 is based on the validity signal 23 output from input interface 8 to logic unit 21b. To allow processing component 21a sufficient time to generate control signal 26 and for logic unit 21b to use the control signal to change the first local bus data P1, P2, P3 into the second local bus data P1', P2', P3', logic unit 21b delays the validity signal 23 from input interface 8. For this purpose, logic unit 21b includes a number of delay elements 22a, 22b that delay the validity signal 23 by a certain constant time until it is present at output interface 9 as the delayed validity signal 23'. The length of the delay depends on the number of delay elements 22a, 22b.In the embodiment shown here, the two delay elements 22a, 22b correspond to a delay of two operating cycles of the processing component 21a. The processing component 21a thus has two operating cycles to generate the control signal and to control the logic unit 21a accordingly to change the process data P1, P2, P3 before the delayed validity signal 23' is forwarded to the output interface 9 and the second local bus data P1', P2', P3' is sent to the next data bus participant 7b. Although only two delay elements 22a, 22b are shown here, it is known to those skilled in the art that any number of delay elements 22a, 22b can be used. To ensure deterministic behavior of the ring bus 6, it is only important that the data bus participants 7a, 7b, ..., 7n each have a constant delay, i.e. a constant number of delay elements 22a, 22b.For example, it is preferred if all data bus participants 7a, 7b, ..., 7n have the same number of delay elements 22a, 22b.

[0071] In the embodiment shown here, the local bus data P1, P2, P3 is only processed in the downward direction, i.e., between interfaces 8 and 9. No further processing takes place in the upward direction, i.e., between interfaces 10 and 11. This is indicated by the fact that interfaces 10 and 11 are directly connected. However, those skilled in the art are aware that processing of the local bus data P1, P2, P3, or the already processed local bus data P1', P2', P3', can also take place in the upward direction, corresponding to the downward direction. For this purpose, the data bus participant 7a can have another unit corresponding to processing unit 12, or processing unit 12 itself can be used.

[0072] In the embodiment shown here, it is also shown that all local bus data P1, P2, and P3 are processed by the data bus participant 7a, as indicated by their modified pattern. However, it is well known to those skilled in the art that the processing component 21a can also contain instructions that instruct the logic unit 21b not to make any changes. In this case, the first local bus data P1, P2, P3 correspond to the second local bus data P1', P2', and P3'. Nevertheless, the validity signal 23 is delayed for a specific time by the delay elements 22a and 22b before it is sent to the output interface 9. The output interface 9 then sends the unprocessed local bus data P1, P2, P3 to the downstream data bus participant 7b.

[0073] A detailed view of logic unit 21b for changing the local bus data P1, P2, P3 is in Figure 4 depicted. Figure 4Figure 1 shows, by way of example, various logic elements of the logic unit 21b through which the parallel input data stream 24 is passed in order to generate a parallel output data stream 27. In the exemplary embodiment of the Figure 4The input data stream 24 and the output data stream 27 each have a width of 8 bits. The various logic elements of the logic unit 21b are configured to receive a control signal 26 from the processing component 21a and to make changes to the parallel input data stream 24 according to their logic function. In the embodiment shown here, the control signal 26 has four individual control signal components 26', 26", 26‴, 26ʺʺ, which are generated by the processing component 21a to control the four logic elements of the logic unit 21b, shown here only as examples. The control signal 26"" controls a multiplexer, which, on a logic one, outputs the first local bus data 24 as the second local bus data 27 via the bypass line 28. Conversely, on a logic zero, the second local bus data is generated by the upstream logic.The control signal 26‴ controls another multiplexer and an adder for incrementing the first local bus data 24. If the control signal 26‴ is logic zero, the output values ​​of OR gates are output as the second local bus data. The control signal 26" is inputted to the inputs of the OR gates. The inverted control signal 26' is inputted to the inputs of the AND gates. The OR and AND gates implement the erase and set functions. In the representation of the... Figure 4 Eight OR gates and eight AND gates are provided, although for the sake of simplicity, only one OR gate and one AND gate are shown. However, those skilled in the art are aware that logic elements other than those shown here may be present and that these may be controlled by only one or more control signals.

[0074] If the input data stream 24 does not contain process data P1, P2, P3, but instead, for example, control data intended only for the processing component 21a, which does not require any modification, then the logic unit 21b also has a bypass line 28, which allows the local bus data to be routed around the logic elements. For example, a packet identifier (e.g., IDE) is passed through as control data via the bypass line.

[0075] Furthermore, in the embodiment shown here, the logic unit 21b has two delay elements 22a and 22b that delay the validity signal 23 by a specific time until this delayed validity signal 23' is forwarded to the output interface 9. The delay elements 22a and 22b can, for example, be state-controlled flip-flops and be able to store one bit for the duration of one clock cycle. As already described above, this one clock cycle corresponds, preferably, to a working clock cycle from the processing component 21a, which can be a multiple of the clock cycle of the ring bus 6 or even equal to it. Only when the delayed validity signal 23' is received at the output interface 9 does this interface send the second local bus data P1', P2', P3', modified by the logic elements of the logic unit 21b, to the next data bus participant 7b in the ring bus 6.

[0076] The components of the device according to the invention, described in the exemplary embodiment as separate units, modules, or interfaces, can be implemented as separate hardware, but are preferably integrated on the same semiconductor chip. Preferably, their function is implemented by hardware consisting of logic gates. For example, the units, modules, or interfaces can be implemented on an FPGA / ASIC. Reference symbol list

[0077] 1 Programmable Logic Controller (PLC) 2 Higher-level bus 3 Local bus master 4 First interface 5a, b Second interface 6 Ring bus 7a, b, n Data bus participant 8 Input interface 9 Output interface 10 Downward data input interface 11 Downward data output interface 12 Processing unit 13, 14 Inputs / Outputs 15 Sensor 16 Actuator 17 Data packet with process data 18 IDE code word 19 Instruction list index P1, P2, P3 First local bus data, process data P1', P2', P3' Second local bus data, processed process data 20 Counter value 21a Processing component 21b Logic elements 22a, 22b Delay element 23, 23' Validation signal 24 Parallel input data stream, first local bus data 25 Data to be processed 26, 26', 26", 26‴, 26"" Control signal 27 Parallel output data stream, second local bus data 28 Bypass line

Claims

1. A logic unit (21b) adapted to change a quantity of first local bus data (P1, P2, P3) received by an input interface (8) based on a control signal (26) for generating second local bus data (P1', P2', P3') to be transmitted; wherein the logic unit (21b) comprises non-clock-controlled logic elements controlled by the control signal (26) for changing the first local bus data (P1, P2, P3); and wherein the logic unit (21b) is further adapted to clock-controlled delay the transmission of the second local bus data (P1', P2', P3') by an output interface (9).

2. The logic unit (21b) according to claim 1, wherein a parallel input data stream (24) is passed through the logic unit (21b) to generate a parallel output data stream (27).

3. The logic unit (21b) according to any one of the preceding claims, further comprising: at least one delay element (22a, 22b) having a clock input for temporal clock-controlled delaying the transmission of the second local bus data (P1', P2', P3').

4. The logic unit (21b) according to claim 3, wherein the at least one delay element (22a, 22b) is a state-controlled flip-flop.

5. The logic unit (21b) according to any one of the preceding claims, wherein the logic unit (21b) is adapted to: set a number of bits in the first local bus data (P1, P2, P3), or delete a number of bits from the first local bus data (P1, P2, P3), or increment a number of bits in the first local bus data (P1, P2, P3), or buffer an overflow bit from the first local bus data (P1, P2, P3), or a combination thereof for generating the second local bus data (P1', P2', P3').

6. The logic unit (21b) according to any one of the preceding claims, wherein the logic unit (21b) is adapted to output a validity signal (23') to the output interface (9), wherein the validity signal (23') is clock-controlled delayed by the logic unit (21b).

7. The logic unit (21b) according to any one of the preceding claims, further comprising: an in particular controllable bypass connection (28) between input interface (8) and output interface (9) for forwarding local bus data.

8. The logic unit (21b) according to claim 7, wherein the local bus data forwarded by the bypass connection (28) is not changed by the logic unit (21b).

9. The logic unit (21b) according to claim 8, wherein the local bus data forwarded by the bypass connection (28) does not contain any process data, or wherein a packet identifier is looped through as control data via the bypass connection (28).

10. The logic unit (21b) according to any one of the preceding claims, further comprising: a multiplexer controlled by a fourth control signal component (26ʺʺ) of the control signal (26) and outputting at a logic one the first local bus data (P1, P2, P3) via a bypass line (28) as second local bus data (P1', P2', P3') and at a logic zero the second local bus data (P1', P2', P3') is formed by a logic upstream of the multiplexer.

11. The logic unit (21b) according to any one of the preceding claims, further comprising: an adder for incrementing the first local bus data (P1, P2, P3) and a multiplexer both controlled by a third control signal component (26‴) of the control signal (26).

12. A method for processing data in a logic unit (21b), the method comprising: receiving first local bus data (P1, P2, P3) at an input interface (8); changing a quantity of the received first local bus data (P1, P2, P3) based on a control signal (26) for generating second local bus data (P1', P2', P3') to be transmitted; and clock-controlled delaying the transmission of the second local bus data (P1', P2', P3') by an output interface (9).