MULTI-PROCESSOR AND MULTI-INTERFACE DATA PROCESSING DEVICE

Description

[0001] The invention relates to a data processing device with multiple processor units and multiple interface units, in particular a data processing device for use in avionics.

[0002] Avionics typically refers to all the electrical and electronic equipment used on board an aircraft. Following the development of modern microelectronics, the integration of ever more functionality into smaller, more powerful, and more efficient avionics computer systems is progressing rapidly. A key characteristic of avionics computer systems is that they generally have to undergo lengthy and complex certification processes. Only with successful certification can the corresponding components be used in aviation, for example, in aircraft or avionics equipment. This means that modifications to the components can only be implemented very slowly and cautiously.

[0003] In typical avionics computer systems, processors are usually provided on which individual applications can run. These processors are connected to interfaces, which in turn can be connected to other devices, such as measuring instruments or sensors.

[0004] Due to the aforementioned complex approval processes, in practice it can happen that interfaces, particularly regarding their structure or definitions, must remain unchanged for decades. Any modification of an interface, or even a complete redefinition of one, would be extremely costly and therefore only makes sense if the benefits outweigh the significant effort.

[0005] On existing aircraft platforms, modernization programs often involve replacing several existing subsystems with single, highly integrated devices. The existing functionality can then be expanded with additional capabilities.

[0006] Fig. 1 The diagram schematically illustrates the typical development of avionics systems. The left side of the image shows a traditional composite architecture 1, which is to be further developed into a highly integrated avionics system 2 as part of the modernization process.

[0007] The traditional network architecture 1 is characterized by the presence of a large number of individual computer systems 3, each computer system 3 having one or more processors 4 and interfaces 5 connected to the processors 4. The interfaces 5 can in turn be coupled with suitable connectors 6, for example device plugs or sockets, to connect external devices.

[0008] As part of the modernization process, such complex and diverse systems are to be further integrated, as shown in the right-hand part of the image. Fig. 1 The aim is to make modern multi-core processors 7 fully usable in avionics, even for safety-critical applications.

[0009] The result is a highly parallel computer architecture on which a large number of diverse applications (software) can be executed simultaneously in multiple contexts. These applications, or contexts, share a defined set of physical resources (hardware). These physical resources typically include a large number of input and output interfaces (I / O interfaces) of the computer subsystem.

[0010] One challenge is achieving a flexible I / O architecture that allows for the integration of established (long-standing) as well as new or even future interface standards. This should be standardized as much as possible and made efficiently usable for a certified multi-core computer subsystem.

[0011] In avionics, known systems typically have a fixed assignment of physical interfaces to a single software application, a processor core, or a processor. This severely limits the scalability and flexibility of existing subsystems. If more than one interface of a specific type is to be implemented, for example, using an application-specific integrated circuit (IC), the integrated circuit and its associated functionality are assigned to a single processor core and its corresponding driver and application software context. A degree of flexibility can be achieved using I / O server software. However, this approach does not provide satisfactory solutions, particularly regarding the complex interrelationships involving additive latency, complex scheduling, multiple data copy operations, and computation time requirements.These approaches are therefore often very complex or have high latency.

[0012] Data exchange between the interfaces (I / O hardware) and the software layers typically occurs when the respective software application requests data. Following this request, data is either retrieved directly from memory allocated to the interfaces via peripheral interfaces (e.g., PCI Express) or made available in the respective memory for transmission.

[0013] Often, additional dedicated hardware is also used to organize data transport between the peripherals and main memory, thus relieving the software application (for example, with the help of a processor DMA controller).

[0014] Fig. 2 shows an abstract example of a typical known implementation of a computer system in avionics with multiple interfaces that are shared by applications (software applications) on multiple processors.

[0015] In the present example, three processors 4 are shown, on which a total of five different applications are running. For better differentiation, the processors are labeled with the reference symbols 4a, 4b, and 4c. The interfaces 5, which are described in more detail here for explanation purposes, are labeled with the reference symbols 5a and 5b.

[0016] Interfaces 5 and 5a, 5b can be coupled to external devices E not shown, for example other devices, sensors, relays, valves, electric motors, etc.

[0017] In this example, data is supplied from the external device E via interface 5a and from there transferred to processor 4a via connection 8. Specifically, the data flow occurs from interface 5a to application 2, which runs on processor 4a. Application 2 controls interface 5a and thus also the data flow.

[0018] Furthermore, application 2 shares the incoming data with application 1, which also runs on processor 4a, and with application 3, which runs on a different processor, namely processor 4b.

[0019] The resulting data flows are characterized by connections 9a (between application 2 and application 1) and 9b (between application 2 and application 3).

[0020] Each data flow is associated with latencies that can vary in length. Reading data from interface 5a by application 2 typically takes less than 1 ms. This also applies to copying data from application 2 to application 1 via connection 9a within processor 4a.

[0021] Copying from processor 4a to processor 4b, namely from application 2 to application 3, can be much more time-consuming and typically takes less than 40 ms.

[0022] Another data flow is shown in the right part of the image. Fig. 2 This diagram shows how data is to be output to an external device E via interface 5b. Interface 5b is controlled by application 4 via a connection 10. Since data from application 3 is to be output via interface 5b, application 4 on processor 4c makes interface 5b available to application 3 on the other processor 4b for sending data. For this purpose, there is a further connection 11 between application 3 and application 4.

[0023] This process therefore requires data to be copied again between two processors (here processors 4b and 4c), which can lead to latencies of < 40 ms. Writing by application 4 (software) to interface 5b typically takes < 1 ms.

[0024] The typical latencies mentioned here can arise particularly from software data transfer, copy operations, and asynchronous software scheduling between individual processors. These latencies, or rather the processes underlying them, are described in... Fig. 2 also indicated by dashed arrows.

[0025] US patent 2006 / 0123071 A1 describes a device for processing signals provided by sensors in a vehicle's powertrain.

[0026] US patent 9,137,038 B1 discloses an avionics computer system with data processing distributed across multiple processors, the processors being interconnected via a data bus.

[0027] EP 3 098 718 A1 generally describes a virtualization platform with a host processor and an acceleration processor coupled to it.

[0028] The invention is based on the objective of improving an avionics data processing device as described above, on the one hand with regard to its flexibility and on the other hand with regard to data flow speeds or a reduction in latency times.

[0029] The problem is solved according to the invention by an avionics computer system with a data processing device having the features of claim 1. Advantageous embodiments are specified in the dependent claims. The data processing device according to the invention can therefore be used particularly advantageously in avionics computer systems.

[0030] An avionics computer system is specified, comprising a data processing device, multiple processors, multiple interfaces to which external devices can be connected, and connections between the interfaces and the processors, through which data can be transported between the interfaces and the processors, wherein at least one data management device is provided in the connections for handling data flows between the interfaces and the processors.

[0031] In contrast to known data processing devices, this data processing device incorporates an additional data management unit in the connections between the interfaces and the processors, designed to handle data flows. This relieves the processors and the software applications running on them of data handling tasks, thereby increasing efficiency.

[0032] The external devices mentioned are typically equipment, sensors, motors, valves, switches, lighting elements, air conditioning components, etc., which are used, for example, in aviation and which can be connected to the interfaces. These external devices are therefore not part of the specified data processing device. Rather, the system boundary of the described data processing device is such that the connectable external devices are not included within it.

[0033] Processors are processing units that can be structured in a known manner and may, in particular, include one or more main processors or processor cores (CPU), control units, arithmetic logic units (ALU), registers, data lines (data buses), caches, and a memory management unit (MMU). The term "processor" therefore encompasses not only the processor itself, but also, of course, the memory areas connected to the processor (for example, main memory) that are necessary for the processor's operation.

[0034] The interfaces can be of various designs, particularly hardware interfaces, intended to connect devices used in aviation to one or more processors. Accordingly, they can be designed, for example, as analog or digital, parallel or serial interfaces, etc.

[0035] The interfaces can therefore include various different interface types, for example discrete interfaces (28 V / GNDopen, 12 V, 5 V, TTL, PWM), analog interfaces (current, voltage, frequency), serial interfaces, digital interfaces, etc. The interfaces can also include several traditional discrete (analog, digital), serial (ARINC-429, RS-422, etc.), bus (MIL-STD-1553, CAN, STANAG-3910, etc.) as well as modern network interfaces (Ethernet, AFDX, Fibre Channel, etc.).

[0036] The connections mentioned can exist on the one hand between processors and interfaces, and on the other hand also directly between the processors.

[0037] For example, as mentioned above in connection with Fig. 1 explained - an avionics computer system may have several processor units in which multi-core processors are operated, on which software applications run that need to access the interfaces across the board.

[0038] The data management system is therefore provided separately and in addition to the interfaces and processors. This means that the interfaces and processors do not need to be physically modified, which can simplify and accelerate the corresponding approval processes.

[0039] Managing data flows includes, in particular, carrying out the measures usually associated with them, such as managing, sorting, and forwarding incoming and outgoing data.

[0040] Depending on the complexity of the data processing device, several data management devices can also be used, each assigned to the interfaces and handling the data flows to and from the interfaces.

[0041] The interfaces can be configured to receive data from external devices that can be connected to them, and / or to send data to external devices that can be connected to them. The interfaces can thus perform the usual data reception and transmission.

[0042] At least one of the interfaces can therefore be configured to receive data from an external device that can be connected to the interface, and at least one of the interfaces can be configured to send data to an external device that can be connected to the interface.

[0043] The data management unit can be implemented as a hardware component. This means that data management is not performed by software, and therefore not using the applications running on the processors, but rather that the data management unit constitutes a separate hardware component. In particular, the data management unit can be implemented as an integrated circuit (IC).

[0044] The hardware component or integrated circuit can be designed modularly and / or logically separated from the processors and interfaces. The hardware component can thus be physically separate from the processors and interfaces and constitute its own component, meaning that the processors and interfaces do not need to be physically modified, thereby simplifying the approval process. It is also possible, for example, for the hardware component to be implemented on a system-on-a-chip (SoC), where all components are integrated on a single chip, while maintaining a logical separation between the hardware component and the other components (processors, interfaces).

[0045] The hardware component can be directly connected to at least some of the interfaces. This enables fast data exchange.

[0046] Processors can have memory areas for storing data, and the data management unit (DMU) can be configured to handle data flows to these memory areas. Specifically, physical memory areas can be defined for applications running on the processors. These memory areas are typically located in main memory, and the data stored there is accessible to the respective applications. The memory areas can also be accessed directly by the DMU without requiring the use of the applications themselves. This reduces the load on the applications and significantly lowers latency. The DMU can thus directly write data to or read data from these physical memory areas.

[0047] Using main memory (i.e., processor RAM) is particularly advantageous. For example, memory can also be physically assigned as an external device via an interface. However, it is then only accessible to the processor through this peripheral interface, which can cause significant latency. Main memory, on the other hand, is accessible quickly and with low latency from the processor, which is not the case with memory assigned to an external device.

[0048] At least one of the processor units can have one or more processor cores. Likewise, it is possible for a computer system to have at least one or more processor units.

[0049] The data processing device can be used to particular advantage in avionics computer systems.

[0050] The data management unit, in the form of an integrated circuit (hardware), handles the sorting and routing of incoming and outgoing data across multiple assigned avionics I / O interfaces of various types completely autonomously. This occurs largely without constant control overhead or data transfer by the software running in the processors.

[0051] The data received via the interfaces is made available to multiple independent software applications directly in the processor's main memory by the data management unit. Data that the software intends to transmit externally to external systems is retrieved from the processor's main memory by the data management unit. This data transfer between an interface and the processor's main memory occurs without the active involvement of any software application running on the processor.

[0052] Through appropriate memory access management (processor and operating system configuration), conflict-free and secure sharing of the data management device (the integrated circuit), the implemented interfaces, and all received and transmitted data by multiple software applications is enabled simultaneously. The software applications can be executed in parallel on one or more processor cores or on one or more multi-core processors.

[0053] Regardless of the interface type, the same generic approach can be used for robust and synchronized data exchange between the hardware (the data management unit) and the software (the applications running on the processors). This allows the use of industry-standard-compatible data structures, such as well-known systems like PCI Express or Rapid I / O. These data structures can utilize ring buffers in conjunction with a suitable synchronization model (producer, consumer, pointer) and a communication model (packet-based memory transfers, direct memory access (DMA)).

[0054] Due to the use of essentially industry-standard compatible components, the effort required for approval procedures as part of safety-critical avionics is manageable, without restricting flexibility and efficiency.

[0055] The data processing device enables a standardization of the data input and output mechanism, regardless of the interface type used. By offloading the hardware load on software applications, software execution efficiency increases. Relieving the software of input and output tasks reduces interference during software execution, thus facilitating the demonstration of determinism, which is crucial for regulatory approvals.

[0056] The data processing device represents a robust model that allows different interfaces to be used simultaneously by different applications without additive latency.

[0057] The device enables very good scalability from traditional systems with single processors to modern systems with one or more multi-core processors.

[0058] These and other advantages and features are explained below using an example and the accompanying figures. They illustrate: Fig. 1 a schematic example of the consolidation of older computer systems onto new computer architectures; Fig. 2 the basic structure of a data processing device according to the state of the art; Fig. 3 a schematic representation of a data processing device according to the invention; and Fig. 4 A detailed overview of memory management.

[0059] Fig. 3 Figure 1 shows the schematic structure of a data processing device according to the invention, which can, for example, be part of a computer system. Components that already mentioned above in connection with Fig. 2 Components that resemble or may be identical to those described in the state of the art are marked with the same reference numerals.

[0060] It is thus evident that in the data processing device according to the invention of Fig. 3 in contrast to the data processing device of Fig. 2 at least one additional data management device 20 is provided in the connection 8 between the interfaces 5 and the processors 4. In the Fig. 3 The example shown uses two data management units 20 (HW I / O Manager - Hardware). Other variants may be equipped with only one data management unit 20 or with several data management units 20.

[0061] The data management unit 20 handles the data flow between the various interface devices 5 and the applications running on the processors 4. In particular, the data management unit 20 is implemented in hardware, e.g., in the form of an integrated circuit (HW I / O Manager).

[0062] The Data Management Unit 20 handles interface management and data transport, enabling significantly lower latency times, as will be explained later. These significantly lower latencies are primarily due to the virtualization of interfaces by the Data Management Unit, the direct sharing of processor main memory (explained later), and the autonomous sorting and forwarding of incoming and outgoing data by the Data Management Unit 20.

[0063] In the Fig. 3 In the specific example shown, the data management unit 20 receives data from interface 5a, which in turn is connected to an external device E, and writes it directly into the main memory areas used by applications 1 and 2 in processor 4a. This differs from the prior art example of Fig. 2 It is therefore not necessary that - as there - an application (in Fig. 2 : Application 2) receives data and makes it available for use by another application (in Fig. 2 Application 1) does not need to copy the data. Rather, the data management facility 20 handles the provision of the data to both applications 1 and 2 simultaneously.

[0064] Furthermore, the data received via interface 5a is also written directly into the main memory area of ​​application 3, thus eliminating the need for time-consuming copying operations there as well (in Fig. 2 Copying data from application 2 to application 3 is no longer necessary.

[0065] For this purpose, fixed physical connections are defined, particularly for the data management unit 20, to the respective memory areas, which ideally remain unchanged during operation. The data management unit 20 thus "knows" exactly which data must be written to which memory areas of the processors 4.

[0066] The data flows thus take place via the connection 8 between the (receiving) interface 5a and the memory areas of applications 1 and 2 for processor 4a and the memory area of ​​application 3 on processor 4b.

[0067] The write operations performed by the data management device 20 result in extremely short latency times. These are typically below 5 µs. For comparison: the read and copy operations of the device of Fig. 2 Significantly longer latency times in the millisecond range were required. The latency times, or rather the processes underlying them, are described in... Fig. 3 also indicated by dashed arrows.

[0068] In the right part of the image of Fig. 3 This is an example of sending data from applications 3 and 4. Here, the (in Fig. 3 The data management unit 20 (shown in the right part of the image) goes directly to the storage areas of applications 3 and 4 and transfers the data read there directly to interface 5b.

[0069] The data flow thus takes place via connection 10 from application 3 in processor 4b and application 4 in processor 4c via the data management unit 20 to the (transmit) interface 5b.

[0070] Here too, the resulting latency times are very short and typically less than 10 µs.

[0071] Furthermore, the processors 4 can be interconnected in the usual way via connections 11.

[0072] The in Fig. 3 The processors shown (4) can each have one processor core (“CPU”) as well as the associated memory hierarchy and memory management. If the processors (4) are part of multi-core processors (see, for example, the multi-core processors (7) in Fig. 1 It is also possible that the processor cores (CPU) share memory management with other processor cores (CPU) that are part of the multi-core processor in question. In this context, with reference to Fig. 1 It was added that for the multi-core processors shown there as examples, 7 each have four processor cores (corresponding to "CPU" in Fig. 3 ) are shown. Of course, the multi-core processors 7 can also be structured differently.

[0073] Accordingly, in the example of Fig. 3 For example, processors 4a and 4b could be part of a first multi-core processor, and processor 4c could be part of another multi-core processor.

[0074] Fig. 4 shows in greater detail an example of another application to better explain data flows and memory accesses.

[0075] Here, the representation of the actual main processor 4 is separate from the main memory 21 assigned to the processor 4. In the representations in the Fig. 2 and 3 The respective main memory was not shown separately, but as part of the processor 4 (more accurately: processor setup, consisting of the actual processors as well as necessary additional components such as memory areas, etc.).

[0076] Processor 4 runs applications 1 and 2, each of which is allocated memory areas 22 (for application 1) and 23 (for application 2). Memory areas 22 and 23 are managed in a known manner by a memory management system 24.

[0077] The data management unit 20 (HW I / O Manager) has a suitable configuration 25 that enables it to handle the respective defined assigned interfaces 5 or 5a, 5b and the associated data flows. In particular, the data management unit 20 "knows" which data from which interface 5 must be written to which memory areas 22, 23 in main memory 21, or which data must be read from and sent from there.

[0078] In the Fig. 4 In the example shown, the received data is written via the (receiving) interface 5a by the data management unit 20 into the memory areas 22 (for application 1) and 23 (for application 2), as already shown in the previous example. Fig. 3 explained. Applications 1 and 2, in turn, have direct access to memory areas 22 and 23.

[0079] In the example shown, the data to be output is written by application 2 into memory area 23 and read from there by the data management unit 20 and routed to interface 5b.

[0080] Fig. 4 This only shows the structure of a highly simplified system. In more complex systems, it is possible, for example, for multiple processor cores ("CPU") to share common memory management and main memory (e.g., in multi-core processors). The data management unit 20 can itself be coupled with multiple multi-core processors.

Claims

1. An avionics computer system comprising a data processing apparatus, comprising - multiple processor devices (4), each having one or more processor cores on which multiple software applications can be executed in parallel, and each having a main memory (21) with memory areas (22, 23) for storing data associated with the software applications; - multiple interface devices (5) to which external devices (E) can each be connected, wherein there is an assignment of the physical interface devices (5) to the individual software applications executed on the processor cores and to the assigned memory areas (22, 23); and comprising - connections (8, 10) between the interface devices (5) and the processor devices (4), via which data can be transported between the interface devices (5) and the memory areas (22, 23) of the processor devices (4); wherein - at least one data management device (20) is provided in the connections (8, 10) between the interface devices (5) and the memory areas (22, 23) of the processor devices (4) for handling data flows between the interface devices (5) and software applications associated with the memory areas (22, 23) that run on the processor devices (4); - the data management device is configured to handle data flows to memory areas (22, 23) of the processor devices (4); - the memory areas (22, 23) are directly controllable by the data management device (20), such that the data management device can write data into or read data from physical memory areas that are firmly defined for relevant applications, wherein the data transfer between an interface device (5) and a memory area (22, 23) takes place without active involvement of the software application running on the processor device (4); - the data management device (20) is configured as a hardware component; - the hardware component is configured modularly and / or logically distinct from the processor devices (4) and the interface devices (5); - the hardware component is directly connected to at least one part of the interface devices (5).

2. The avionics computer system according to claim 1, wherein the interface devices (5) are configured to receive data from external devices (E) that can be connected to the interface devices, and / or transmit data to external devices that can be connected to the interface devices.

3. The avionics computer system according to claim 1 or 2, wherein at least one of the interface devices (5) is configured to receive data from an external device (E) that can be connected to the interface device, and at least one interface device is configured to transmit data to an external device that can be connected to the interface device.

4. The avionics computer system according to any one of the preceding claims, wherein the external device (E) are units, sensors, motors, valves, switches, lighting elements, and air conditioning components that are used in aviation and can be connected to associated interface devices (5).