COPPER-CERAMIC SUBSTRATE

Description

[0001] The invention relates to a copper-ceramic substrate having the features of the preamble of claim 1.

[0002] Copper-ceramic substrates (e.g., DCB, AMB) are used, for example, in the production of electronic power modules and consist of a ceramic substrate with copper layers applied to either one or both sides. The copper layers are prefabricated as copper foil, typically with a thickness of 0.1 mm to 1.0 mm, and bonded to the ceramic substrate using a bonding process. Such bonding processes are also known as DCB (Direct Copper Bonding) or AMB (Active Metal Brazing). However, if the ceramic substrate has higher strength, even thicker copper layers or sheets can be applied, which is generally advantageous in terms of electrical and thermal properties.

[0003] Ceramic substrates include ceramic plates made of materials such as mullite, Al 2 O 3 , Si 3 N 4 , AlN, ZTA, ATZ, TiO 2 , ZrO 2 , MgO, CaO, CaCO 3 or a mixture of at least two of these materials.

[0004] It is known that copper-ceramic substrates with a copper layer having a fine microstructure, for example with a mean grain size of a maximum of 100 µ m, at least on the free surface facing away from the ceramic substrate, there are fundamental advantages regarding suitability for optical inspection and for bonding capability in fine wire bonding for wire diameters smaller than 50 µThe properties of copper, including its etching behavior for the finest structures, grain boundary formation, electroplating suitability, and general further processing, are all important factors. Accordingly, a fine and homogeneous microstructure in the copper layer, especially on the free surface, is advantageous. Furthermore, a fine and therefore harder microstructure offers higher mechanical resistance to damage (e.g., scratches). The DCB process takes place just below the melting point of copper at temperatures above 1050°C. The soldering processes in the AMB process occur at temperatures ≥ 800°C. The thermal influence in the AMB and DCB manufacturing processes coarsens the copper, a tendency that increases with higher copper purity. Therefore, greater resistance of the copper or copper alloy to grain coarsening is required.

[0005] A higher proportion of alloying elements in the copper, i.e., copper with lower purity, is diametrically opposed to the requirements for the conductivity of the copper layer, which, according to the requirements of the end application of the copper-ceramic substrate, is in the range of at least 55 MS / m. Furthermore, the copper-ceramic substrate should be cost-effective to manufacture.

[0006] US2016 / 120017 discloses copper foils with a purity of 99.90 wt%, which may contain 180 ppm Ag or 100 ppm Ag and no oxygen. The copper foil can be laminated with a ceramic substrate.1

[0007] WO2020 / 162445 shows the bonding of a very pure copper plate with a ceramic substrate. Phosphorus counteracts the grain-refining behavior of elements that cause grain growth. Therefore, the presence of phosphorus in the copper plate is limited to 1 ppm.

[0008] Against this background, the invention is based on the objective of providing a copper-ceramic substrate which has a fine and homogeneous microstructure and high conductivity and can be manufactured cost-effectively.

[0009] According to the invention, a copper-ceramic substrate with the features of claim 1 is proposed to solve the problem. Further preferred developments can be found in the dependent claims.

[0010] A copper-ceramic substrate is therefore proposed, comprising a ceramic support and at least one copper layer bonded to a surface of the ceramic support. The copper layer contains at least 99.5% Cu (copper). Furthermore, the copper layer contains at least 50 ppm Ag (silver) and a maximum of 3000 ppm Ag, as well as 0.1–30 ppm P. The copper layer may contain additional amounts of other elements.

[0011] In advantageous embodiments, the copper-ceramic substrate has two copper layers, each of which is connected to a surface of the ceramic support.

[0012] A further advantageous embodiment is proposed wherein the copper layer has a proportion of at least 99.7% Cu (copper), for example 99.8% Cu.

[0013] The proposed proportions can achieve fine grain formation in the copper layer(s) of the copper-ceramic substrate. A fine and homogeneous microstructure develops within the copper layer. Average grain sizes of up to 100 mm can be achieved. µ m can be achieved, which can also be maintained at the high required process temperatures.

[0014] According to an advantageous embodiment, it is proposed that the copper layer have an average grain size between 40 µ m and 100 µm, preferably between 40 µ m and 80 µ m, exhibits. The average grain size can further preferably be between 40 µ m and 60 µ m, for example 50 µ The standard deviation of the average grain size can, for example, be less than 30 m. µAccordingly, the copper layers, particularly the free surface of the copper substrate or the copper layers themselves, meet high requirements for a fine and homogeneous microstructure for various applications. The copper layer is therefore particularly well-suited for optical inspection and for bonding in fine wire bonding. Furthermore, due to its fine and homogeneous microstructure, the copper layer exhibits particularly good etching behavior for the finest structures and is especially suitable for electroplating processes, particularly because of its very shallow grain boundary grooves and the associated low roughness. Homogeneous and consistent mechanical properties of the surface and microstructure help to achieve consistent properties in subsequent processing steps.A suitable further processing method could be, for example, wire bonding using ultrasonic technology, with bonding wires having diameters in the range of, for example, 10 to 100 mm. µ The components must be joined with pinpoint accuracy. Microstructural homogeneity at the contact points of the bond wires is of great importance. Furthermore, the fine grain formation can achieve increased strength of the copper layer according to the Hall-Petch relationship.

[0015] The surface of the copper layer is particularly suitable for soldering chips, especially with the ongoing miniaturization of chips, as the homogeneous and fine structure can reduce stress gradients in the area of ​​soldered chips, which increases the quality of the soldering as well as the lifespan of the solder joint compared to a coarse and inhomogeneous structure.

[0016] The proposed copper-ceramic substrate simultaneously offers high conductivity > 55 MS / m in the copper layers due to the high copper content.

[0017] A particular cost advantage arises from the fact that the copper-ceramic substrate can be produced using both Active Metal Brazing (AMB) and Direct Copper Bonding (DCB). In particular, the copper-ceramic substrate can also be produced using silver-free solders via AMB, which require higher brazing temperatures ≥1000°C. Furthermore, the copper-ceramic substrate can be produced using other thermal joining processes, such as thermal diffusion bonding. The proposed copper-ceramic substrate therefore exhibits high resistance to grain coarsening.

[0018] It is proposed that the copper layer have an indentation hardness of at least 0.7 GPa for indentation depths between 0.4 µ m to 0.6 µ m has.

[0019] It is further proposed that the copper layer have an indentation hardness of at least 0.8 GPa for indentation depths between 0.1 µ m and 0.25 µ m has.

[0020] The high surface hardness of the copper layer is particularly advantageous for low penetration depths (<1). µ The surface hardness (m), which can be determined particularly using the depth-resolved QCSM method, results in higher resistance to mechanical influences (e.g., higher scratch resistance) during downstream processing or transport to these processes. This ensures a higher surface quality. A correspondingly high surface hardness in the specified range is also advantageous for a variety of downstream processing methods.

[0021] According to a further development, it is proposed that the copper layer contain a maximum of 800 ppm Ag. This can lead to a reduction in costs, in particular.

[0022] It is stipulated that the copper layer must contain a maximum of 30 ppm phosphorus. It has been recognized that the presence of phosphorus can suppress the positive, grain-refining properties of the proposed alloy. This is particularly true for commercially traded copper, which can regularly contain higher levels of phosphorus. It has been shown that limiting the phosphorus content effectively reduces this negative impact.

[0023] Furthermore, it is stipulated that the copper layer must contain at least 0.1 ppm phosphorus. Further reducing the phosphorus content does not result in any further improvement in the properties of the copper layer.

[0024] According to a preferred embodiment, the copper layer has a maximum oxygen content of 10 ppm O₂, and preferably a maximum of 5 ppm O₂. A correspondingly low oxygen content achieves sufficient hydrogen resistance, allowing various process steps to be carried out under a hydrogen atmosphere. At the same time, a low oxygen content, particularly of a maximum of 5 ppm O₂, has a positive effect on the conductivity of the copper layer.

[0025] It is further proposed that the copper layer contain at least 0.1 ppm O₂. Further reducing the oxygen content will not result in any further improvement in the properties of the copper layer.

[0026] It is further proposed that The copper layer has a proportion of the elements Cd, Ce, Ge, V, Zn of at least 0.01 ppm to a maximum of 1 ppm each, wherein, according to a further preferred embodiment, the copper layer has a total proportion of the elements Cd, Ce, Ge, V, Zn of at least 0.1 ppm and a maximum of 5 ppm. This simplifies the achievement of high conductivity and a correspondingly fine microstructure.

[0027] It is further proposed that The copper layer has a proportion of the elements Bi, Se, Sn, and Te of at least 0.01 ppm and at most 2 ppm, wherein, according to a further preferred embodiment, the copper layer has a total proportion of the elements Bi, Se, Sn, and Te of at least 0.1 ppm and at most 8 ppm. This simplifies the achievement of high conductivity and a correspondingly fine microstructure.

[0028] It is further proposed that The copper layer has a proportion of the elements Al, Sb, Ti, Zr of at least 0.01 ppm to a maximum of 3 ppm each, wherein, according to a further preferred embodiment, the copper layer has a total proportion of the elements Al, Sb, Ti, Zr of at least 0.1 ppm and a maximum of 10 ppm. This simplifies the achievement of high conductivity and a correspondingly fine microstructure.

[0029] It is further proposed that The copper layer has a proportion of the elements As, Co, In, Mn, Pb, Si of at least 0.01 ppm to a maximum of 5 ppm each, wherein, according to a further preferred embodiment, the copper layer has a total proportion of the elements As, Co, In, Mn, Pb, Si of at least 0.1 ppm and a maximum of 20 ppm. This simplifies the achievement of high conductivity and a correspondingly fine microstructure.

[0030] It is further proposed that The copper layer contains a proportion of the elements B, Be, Cr, Fe, Mn, Ni, and S of at least 0.01 ppm and at most 10 ppm, wherein, according to a further preferred embodiment, the copper layer contains a total proportion of the elements B, Be, Cr, Fe, Mn, Ni, and S of at least 0.1 ppm and at most 50 ppm. This simplifies the achievement of high conductivity and a correspondingly fine microstructure.

[0031] It is further proposed that the copper layer contain a maximum of 50 ppm of the elements Cd, Ce, Ge, V, Zn, Bi, Se, Sn, Te, Al, Sb, Ti, Zr, As, Co, In, Mn, Pb, Si, B, Be, Cr, Fe, Mn, Ni, S, including other impurities. This simplifies the achievement of high conductivity and a correspondingly fine microstructure.

[0032] The stated proportions refer to the weight percentages.

[0033] The invention is explained below with reference to preferred embodiments and the accompanying figures. Fig. 1 a copper-ceramic substrate with one copper layer; Fig. 2 a copper-ceramic substrate with two copper layers; Fig. 3 a micrograph of a fine copper layer of a copper-ceramic substrate according to the invention after the DCB process; Fig. 4 a micrograph of a fine copper layer of a copper-ceramic substrate according to the invention after the AMB process; Fig. 5 grain size distribution of copper layers of a copper-ceramic substrate according to the invention after the DCB and AMB processes; Fig. 6 nanohardness of copper layers of a copper-ceramic substrate according to the invention after the DCB and AMB processes compared to a reference copper; and Fig. 7 micrographs showing the area fraction of crystal twins of copper layers of a copper-ceramic substrate according to the invention after the DCB and AMB processes in comparison.

[0034] Power modules are semiconductor components used in power electronics and function as semiconductor switches. They contain several power semiconductors (chips) within a package, electrically insulated from the heat sink. These chips are applied to a metallized surface of an electrically insulating plate (e.g., ceramic) by soldering or bonding to ensure both heat dissipation towards the base plate and electrical insulation. The composite of metallized layers and insulating plate is called a copper-ceramic substrate 1 and is manufactured on an industrial scale using either DCB (Direct Copper Bonding) or AMB (Active Metal Brazing) technology.

[0035] The chips are contacted by bonding with thin bonding wires. Furthermore, other modules with a wide variety of functions (e.g., sensors, resistors) can be present and integrated.

[0036] To produce a DCB substrate, ceramic supports 2 (e.g., Al₂O₃, Si₃N₄, Al₂, ZTA, ATZ) are bonded together on their top and bottom surfaces with copper layers 3, 4 in a bonding process. In preparation for this process, the copper layers 3, 4 can be surface oxidized (e.g., chemically or thermally) before being deposited onto the ceramic support 2. The bonding occurs in a high-temperature process ≥1050°C, whereby a eutectic melt forms on the surface of the copper layers 3, 4, which then bonds with the ceramic support 2. This bond, for example in the case of copper (Cu) on aluminum oxide (Al₂O₃), consists of a thin Cu-Al spinel layer.

[0037] To produce an AMB substrate, copper layers 3 and 4 are soldered onto a ceramic support 2 using a suitable hard solder. The soldering process takes place in a vacuum or a suitable protective atmosphere, e.g., hydrogen, at temperatures above 800°C. This can be a batch or continuous process. The use of silver-free solders (e.g., CuAlTiSi solders) increases the required process temperature, allowing these soldering processes to take place at temperatures up to 1050°C.

[0038] Furthermore, processes can also be used to produce the copper-ceramic substrate 1 in which the bond between copper and ceramic is created via a diffusion-based joining process (e.g., thermal diffusion bonding). The process temperatures here are also ≥1000°C.

[0039] In Figure 1Figure 1 shows a schematic representation of an embodiment of a copper-ceramic substrate 1 with a ceramic support 2 and a proposed copper layer 3. The copper layer 3 has a high copper content of at least 99.5% Cu, with a silver content of at least 50 ppm Ag and a maximum of 3000 ppm Ag.

[0040] The copper layer 3 can be connected to the ceramic support 2, for example, using the DCB process described above or the AMB process, so that it is connected to the ceramic support 2 by a material-bonded connection in the surface edge zone 5.

[0041] In the Figure 2 Figure 1 is a schematic representation of an embodiment of a copper-ceramic substrate 1 with a ceramic support 2 analogous to the embodiment of the Figure 1The figure shown depicts two proposed copper layers, 3 and 4. Copper layers 3 and 4 have a high copper content of at least 99.5% Cu, with a silver content of at least 50 ppm Ag and a maximum of 3000 ppm Ag.

[0042] The copper layers 3 and 4 can be connected to the ceramic support 2, for example, using the DCB process described above or the AMB process, so that they are connected to the ceramic support 2 by a material-bonded connection in the respective surface edge zones 5 and 6.

[0043] The copper layers 3 and 4 with the proposed proportions of Cu and Ag, in particular with the proposed O proportions of a maximum of 10 ppm O, more preferably a maximum of 5 ppm O, are highly conductive Cu materials and have a conductivity of 55 MS / m, preferably at least 57 MS / m and particularly preferably at least 58 MS / m.

[0044] The addition of silver, the limitation of the phosphorus content to a maximum of 30 ppm P, and the presence of other elements in the copper layers 3, 4 ensure that the comparatively small amounts of silver are sufficient to counteract the coarsening of the microstructure of the copper layers 3, 4 caused by the thermal influence in the AMB or DCB process, so that the copper layers 3, 4 of the copper-ceramic substrate 1 exhibit a fine and homogeneous microstructure. This is particularly suitable, for example, for etching very fine structures. Furthermore, the fine microstructure results in increased strength of the copper layers 3, 4 and thus increased resistance to mechanical damage according to the Hall-Patch relationship.

[0045] The copper semi-finished products of copper layers 3 and 4 can have a thickness of 0.1 to 1.0 mm and are placed in large dimensions onto the ceramic substrate 2 and bonded to the ceramic substrate 2 using the DCB process. Subsequently, the large-area copper-ceramic substrate 1 is cut into smaller units and further processed. Alternatively, the bonding can be carried out using the AMB process.

[0046] Such copper semi-finished products for the copper layers 3, 4 can be produced, for example, in manufacturing processes under oxygen exclusion.

[0047] Additionally, copper layers 3 and 4 may contain a minimum of 0.01 ppm and a maximum of 1 ppm of each of the elements Cd, Ce, Ge, V, and Zn, and / or a minimum of 0.01 ppm and a maximum of 2 ppm of each of the elements Bi, Se, Sn, and Te, and / or a minimum of 0.01 ppm and a maximum of 3 ppm of each of the elements Al, Sb, Ti, and Zr, and / or a minimum of 0.01 ppm and a maximum of 5 ppm of each of the elements As, Co, In, Mn, Pb, and Si, and / or a minimum of 0.01 ppm and a maximum of 10 ppm of each of the elements B, Be, Cr, Fe, Mn, Ni, and S. These additional elements may have been intentionally introduced into the microstructure by doping during the melting process immediately before casting, or they may already be present in copper layers 3 and 4 due to impurities from the production of the copper semi-finished products. In any case, the proportion of these elements, including other impurities, should preferably not exceed 50 ppm.

[0048] Furthermore, according to a further preferred embodiment, the copper layers 3, 4 can have a total proportion of the elements Cd, Ce, Ge, V, Zn of at least 0.05 ppm and a maximum of 5 ppm, a total proportion of the elements Bi, Se, Sn, Te of at least 0.1 ppm and a maximum of 8 ppm, a total proportion of the elements Al, Sb, Ti, Zr of at least 0.1 ppm and a maximum of 10 ppm, a total proportion of the elements As, Co, In, Mn, Pb, Si of at least 0.1 ppm and a maximum of 20 ppm, and a total proportion of the elements B, Be, Cr, Fe, Mn, Ni, S of at least 0.1 ppm and a maximum of 50 ppm.

[0049] The described proportions of the elements can help to achieve the proposed average grain size of the microstructure. The microstructure formation is primarily due to the grain refinement of the microstructure caused by the elements and to the reduction of secondary recrystallization during the bonding process.

[0050] In Figure 3Figure 1 shows a micrograph of one of the copper layers 3, 4 of the copper-ceramic substrate 1, which was produced using a DCB process. In this embodiment, the microstructure of the copper layers 3, 4 is characterized by a mean grain size of 56.5 mm. µ m with a standard deviation of 28.5 µ m and is therefore below the requirements of 100 µ Average grain size. Grain sizes were determined according to the line section method (DIN EN ISO 2624).

[0051] In Figure 4 Figure 1 shows a micrograph of one of the copper layers 3, 4 of the copper-ceramic substrate 1, which was produced using an AMB process. In this embodiment, the microstructure of the copper layers 3, 4 is characterized by a mean grain size of 78. µ m with a standard deviation of 34.6 µ m and is therefore below the requirements of 100 µAverage grain size. Grain sizes were determined according to the line section method (DIN EN ISO 2624).

[0052] The particle size distribution of the two embodiments according to the Figures 3 and 4 is in the Figure 5 shown. Both the DCB process and the AMB process result in a monomodal grain size distribution in the copper layer 3, 4.

[0053] In Figure 6 are indentation hardnesses in GPa over a normal shift in µA nanohardness test using the depth-resolved QCSM method was performed on a copper layer 3, 4 produced according to the DCB process (black circles), the AMB process (white circles), and a reference copper layer (black squares). The nanohardness tests were carried out with several load levels, with a maximum test force of 100 mN. A Berkovich indenter was used. The indentation hardness is plotted accordingly as a function of the indentation depth. The surfaces of the copper layers 3, 4 of the copper-ceramic substrates 1 according to the invention show a higher indentation hardness across all indentation depths up to 3.5 m for both manufacturing methods. µm as the reference copper. It has been shown that the proposed alloy achieves a significantly improved indentation hardness for shallow indentation depths or near-surface regions of the copper layers 3, 4. This increases, among other things, the resistance to scratches and is advantageous for resistance to mechanical influences during further processing. These properties of high indentation hardness for near-surface regions of less than, for example, 2 µ m, for example 1 µ m or, for example, 0.5 µ m is also advantageous for applying the finest bond wires using the ultrasonic welding process.

[0054] Furthermore, the microstructures of the copper layers 3, 4 of the copper-ceramic substrate 1 according to the invention, produced by both the DCB process and the AMB process, are characterized by increased twinning. Twins can be identified in the micrograph as strips corresponding to the central region of a grain folded into the twinning position. The microstructure can vary depending on the chosen manufacturing method, for example, DCB ( Figure 7a ) or AMB ( Figure 7b ), of the copper-ceramic substrate 1 differ slightly.

[0055] Twinning is a known phenomenon in copper alloys. In the case of copper-ceramic substrate 1, enhanced twinning is observed during the thermally activated joining process. This thermal twinning occurs during the recrystallization process. It is thermally induced twinning (annealed twins). Twinning has a particularly positive effect on the hardness of the material, especially in fine-grained microstructures.

[0056] The twins are in the Figure 7 dark colored. According to the Figure 7a The microstructure of copper layer 3, 4 according to the DCB process results in a twin area fraction of 19.4%. For copper layer 3, 4 according to the AMB process, as described in the exemplary embodiment of... Figure 7bThis results in a surface area fraction of 21.6%. Although the stated surface area fractions differ only slightly from a reference copper sample, there are more smaller twins, which has a greater effect on the increase in hardness than a smaller number of larger twins.

Claims

1. Copper-ceramic substrate (1) comprising - a ceramic carrier (2) and - at least one copper layer (3, 4) bonded to a surface of the ceramic carrier (2), characterized in that - the copper layer (3, 4) has a Cu content of at least 99.5%, - the copper layer (3, 4) has an Ag content of at least 50 ppm, and - the copper layer (3, 4) has an Ag content of not more than 3000 ppm Ag, and - the copper layer (3, 4) has a P content of not more than 30 ppm, and - the copper layer (3, 4) has a P content of at least 0.1 ppm. The contents are weight fractions.

2. Copper-ceramic substrate (1) according to claim 1, characterized in that the copper layer (3, 4) has a mean grain size between 40 µm and 100 µm. The grain sizes were determined according to the linear intercept method (DIN EN ISO 2624).

3. Copper-ceramic substrate (1) according to claim 2, characterized in that the copper layer (3, 4) has a mean grain size between 40 µm and 80 µm.

4. Copper-ceramic substrate (1) according to any of the preceding claims, characterized in that the copper layer (3, 4) has a penetration hardness of at least 0.7 GPa for penetration depths between 0.4 µm and 0.6 µm.

5. Copper-ceramic substrate (1) according to any of the preceding claims, characterized in that the copper layer (3, 4) has a penetration hardness of at least 0.8 GPa for penetration depths between 0.1 µm and 0.25 µm. The nanohardness measurement was performed by means of a depth-resolved QCSM method. The nanohardness measurement were performed with a plurality of stress levels, the maximum test force being 100 mN. A Berkovich indenter was used as the indenter.

6. Copper-ceramic substrate (1) according to any of the preceding claims, characterized in that - the copper layer (3, 4) has an O content of not more than 10 ppm.

7. Copper-ceramic substrate (1) according to any of the preceding claims, characterized in that - the copper layer (3, 4) has an O content of at least 0.1 ppm.

8. Copper-ceramic substrate (1) according to any of the preceding claims, characterized in that the copper layer (3, 4) has a content of the elements Cd, Ce, Ge, V, Zn, Bi, Se, Sn, Te, Al, Sb, Ti, Zr, As, Co, In, Mn, Pb, Si, B, Be, Cr, Fe, Mn, Ni and S, including further impurities, of not more than 50 ppm.