METHOD FOR PRODUCING A NANOSCALER STRUCTURE

Description

[0001] The present invention relates to a method for producing a nanoscale channel structure. Furthermore, the present invention relates to a computer program that executes each step of the method, and to a machine-readable storage medium that stores the computer program. Finally, the invention relates to an electronic control unit configured to execute the method. State of the art

[0002] Nanoscale channels are required for microfluidic applications. For example, genome sequencers use nanochannels to guide DNA strands as close as possible to readout electrodes and decode them during this process. In gas chromatography, nanochannels are advantageous for separating gas species due to their high surface-to-volume ratio, as the separation occurs through specific wall interactions. In both cases, the precise geometry of the nanochannel is particularly important. However, conventional methods for fabricating nanoscale channel structures result in poorly reproducible channel geometries. This is because the methods either employ time-dependent etching or undercutting, or seal the already open channel by layer deposition, partially coating the channel walls. Some methods are also subject to strong geometric constraints.Rounded edges in a coating also impair the production of nanoscale channel structures.

[0003] German patent DE 20 2017 107 858 U1 relates to a device for a protein corona sensor array for the early detection of diseases. In this device, a sample can be passed through a nanochannel across a sensor array. The channels can be formed by sacrificial etching. This process uses lithographic techniques to structure a material on a substrate. This material is then covered by another material of a different chemical composition. It can be subjected to lithographic and etching processes, or other processing methods. The substrate is then exposed to a chemical agent that selectively removes the first material. Channels are formed in the second material, leaving cavities where the first material was present before the etching process. Since the geometries of the channels are determined by the lithography, they cannot be produced with good reproducibility using this method.

[0004] Patent document WO 2011 / 078650 A2 relates to a method for producing nanochannels in which a first sacrificial layer is structured to form a block with sidewalls, and then a second thin sacrificial layer is formed on these sidewalls. The first sacrificial layer is then completely removed, and the remaining thin vertical posts are used as sacrificial structures for nanochannels to be formed in a subsequently applied cover layer. Disclosure of the invention

[0005] A method according to the invention is defined in claim 1. Further aspects of the invention are defined in independent claims 8-10.

[0006] The process for fabricating a nanoscale channel structure comprises at least eight process steps (a to h): In a first process step (step a), a sacrificial layer is deposited and structured on a substrate. The substrate can be either a bulk material or a layered substructure onto which the sacrificial layer is deposited. This sacrificial layer can also be referred to as a "gate layer." Suitable deposition methods include, in particular, low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). Suitable materials for the sacrificial layer include, in particular, silicon or silicon nitride.In this process, a first sacrificial layer of polycrystalline silicon is preferably deposited by LPCVD or ALD, and a first sacrificial layer of silicon nitride is preferably deposited by PECVD. Structuring is defined as the complete removal of the first sacrificial layer in certain areas, thus exposing the substrate. The boundaries between the structured first sacrificial layer and the areas of the substrate that have been exposed define the course of the nanoscale channel structure.

[0007] In a second process step (step b), a second sacrificial layer is deposited on the substrate and on the first sacrificial layer. The second sacrificial layer can also be referred to as a "channel layer." The thickness of the second sacrificial layer defines the height of the nanoscale channels. It is therefore preferably deposited with a thickness of less than 100 nm and particularly preferably with a thickness of less than 10 nm. The same methods are preferred for depositing the second sacrificial layer as for depositing the first sacrificial layer. Furthermore, the same materials are also preferred for depositing the second sacrificial layer as for depositing the first sacrificial layer. Particularly preferably, the first and second sacrificial layers are deposited from the same material. This allows for subsequent removal of the first and second sacrificial layers using the same method.

[0008] In a third process step (step c), an etch masking layer is deposited onto the second sacrificial layer. The etch masking layer can also be referred to as a "spacer layer." It can optionally be structured after deposition. Suitable deposition methods include, in particular, PECVD or ALD. Suitable materials for the etch masking layer are, in particular, oxides. The thickness of the etch masking layer defines the width of the nanoscale channels. It is therefore deposited with a thickness that is preferably at least 1 nm. Its maximum thickness is preferably less than 100 nm, and particularly preferably less than 20 nm. This achieves an advantageous width for the nanoscale channel structure. Furthermore, the thickness of the etch masking layer is preferably less than the thickness of the first sacrificial layer. It is particularly preferably at least three times less than the thickness of the first sacrificial layer.It is particularly advantageous if its thickness is at least 30 times less than that of the first sacrificial layer. This ensures that the mesa structure, consisting of the first and second sacrificial layers, is coated with a particularly conformal finish, free of rounded edges.

[0009] In a fourth process step (step d), the etch masking layer and the second sacrificial layer are partially removed. A suitable method for the partial removal of the etch masking layer and the second sacrificial layer is anisotropic etching, such as reactive ion etching (RIE). If, in this process step, the etch masking layer and the second sacrificial layer applied to the first sacrificial layer are etched back, then the second sacrificial layer and the etch masking layer applied to the substrate are also largely etched back. Only where the side surfaces of the first sacrificial layer are covered by the second sacrificial layer and the etch masking layer are the second sacrificial layer and the etch masking layer not completely etched back.

[0010] In a fifth process step (step e), the first sacrificial layer is removed, and a further partial removal of the second sacrificial layer is carried out. This can preferably be done using the same method as the removal of the layers in step d, particularly if the first and second sacrificial layers consist of the same material. This leaves only a remnant of the second sacrificial layer corresponding to the width of the planned nanoscale channel structure and a remnant of the etch masking layer on top of it. The etch masking layer protects the underlying second sacrificial layer to a width that corresponds to the thickness of the etch masking layer and thus to the width of the planned channel structure.

[0011] In a sixth process step (step f), a wall layer is deposited on the etch masking layer and on the substrate. This wall layer, which can also be referred to as a "confinement layer," forms the walls of the nanoscale channel structure. Preferably, it is deposited from the same material as the etch masking layer. This allows the remaining traces of the etch masking layer and the wall layer to fuse into a structure composed of the same material.

[0012] In a seventh process step (step g), access openings to the second sacrificial layer are structured. This can be done by structuring the wall layer.

[0013] In an eighth process step (step h), the remaining second sacrificial layer in the channel area is removed. This can be achieved, in particular, by isotropic etching, for example with xenon difluoride (XeF₂) or with sulfur hexafluoride (SF₆). These substances can be brought into contact with the second sacrificial layer through the access openings structured in step g.

[0014] In this way, a nanoscale channel structure is obtained, accessible through the access openings in the wall layer. Since the height of the channels is defined by the thickness of the second sacrificial layer and the width of the channels by the thickness of the etched masking layer, and since the layer thicknesses can be set with very high accuracy during deposition, the process enables highly reproducible, mass-production-ready fabrication of nanoscale channel structures.

[0015] The computer program is configured to execute each step of the process when run on a computer or electronic control unit. For this purpose, the computer or electronic control unit can control devices that perform the deposition, structuring, and removal steps of the process. The computer program enables the implementation of different embodiments of the process on a control unit of a manufacturing device for nanoscale channel structures without requiring any structural modifications. It is stored on a machine-readable storage medium.

[0016] By uploading the computer program to a conventional electronic control unit, the electronic control unit is obtained which is set up to produce a nanoscale channel structure using the method, provided it controls a suitable manufacturing device for this purpose. Brief description of the drawings

[0017] An embodiment of the invention is shown in the drawings and is explained in more detail in the following description. Figure 1 shows a cross-sectional view of a substrate on which a first sacrificial layer was deposited and structured. Figure 2 shows a cross-sectional view of the substrate according to Figure 1 , after a second sacrificial layer has been deposited on top of the substrate and the first sacrificial layer. Figure 3 shows a cross-sectional view of the substrate according to Figure 2 , after an etching masking layer was deposited on the second sacrificial layer. Figure 4 shows a cross-sectional view of the substrate according to Figure 3 , after the etching masking layer and the second sacrificial layer have been partially removed. Figure 5 shows a cross-sectional view of a substrate according to Figure 4 , after the first layer of victims was removed. Figure 6shows a cross-sectional view of the substrate according to Figure 5 , after a wall layer has been deposited on the etching masking layer and on the substrate. Figure 7 shows a cross-sectional view of the substrate according to Figure 6 after removing the second sacrificial layer. Exemplary embodiments of the invention

[0018] In one embodiment of the invention, a first sacrificial layer 2 made of polysilicon with a thickness of 150 nm is deposited on a substrate 1. It is structured such that the substrate 1 is partially exposed again. This is in Figure 1 depicted.

[0019] Subsequently, a second sacrificial layer 3, also made of polysilicon, is deposited using LPCVD such that it covers the exposed surface of the substrate 1, the surface of the first sacrificial layer 2, and the side faces of the first sacrificial layer 2 with a thickness of 5 nm. Since the first sacrificial layer 2 and the second sacrificial layer 3 are made of the same material, they fuse together, as shown in Figure 2 is shown.

[0020] As in Figure 3 As shown, an oxide layer is then deposited, for example by means of PECVD, as an etch masking layer 4, such that it covers the surface and side surfaces of the 5 nm thick second sacrificial layer 3 with a thickness of 10 nm.

[0021] Subsequently, anisotropic RIE etching is performed as a back-etching process until the substrate 1 is partially exposed again. This means that in the areas not covered by the first sacrificial layer 2, the etch masking layer 4 and the underlying second sacrificial layer 3 are completely removed. The layer structure applied to the top of the first sacrificial layer 2 is also removed from the second sacrificial layer 3 and the etch masking layer 4. The parts of the etch masking layer 4 that cover the sides of the first sacrificial layer 2 are not removed, as the anisotropic etching only proceeds from top to bottom. These remaining parts of the etch masking layer 4 can therefore protect the underlying part of the second sacrificial layer 3 from back-etching. The parts of the second sacrificial layer 3 that are located between the first sacrificial layer 2 and the etch masking layer 4 are also not removed. This is in Figure 4 depicted.

[0022] The parameters of the RIE etching process are now modified so that only the first sacrificial layer 2 and the second sacrificial layer 3 are attacked in the subsequent etching process, but no longer the etch masking layer 4. This completely removes the first sacrificial layer 2, leaving behind the remnants of the etch masking layer 4 and the remnants of the second sacrificial layer 3 protected by it, as described in Figure 5 shown, remaining on substrate 1.

[0023] A wall layer 5, for example made of an oxide, is now deposited by PECVD to a thickness of 200 nm. As in Figure 6 As shown, wall layer 5 merges with the remnants of the etch masking layer 4, since these two layers consist of the same material. This results in protrusions on wall layer 5 above the remnants of the etch masking layer 4. Figure 6The figure shows the resulting layer structure when these protrusions have already been partially smoothed by structuring, leaving only an indication on the top of the wall layer 5 where the remains of the second sacrificial layer 3 are located and where the nanoscale channels will run in the finished channel structure.

[0024] Access points to the remnants of the second sacrificial layer 3 are structured, and XeF₂ is introduced through these points until the remnants of the second sacrificial layer 3 are completely removed by isotropic etching. This leaves behind nanoscale channels 6 where the remnants of the second sacrificial layer 3 were previously located. These channels are accessible through the access points. The width of the nanoscale channels corresponds to the former thickness of the etched masking layer 4, and thus 10 nm. The height of the nanoscale channels corresponds to the former thickness of the second sacrificial layer, and thus 5 nm. The nanoscale channel structure obtained in this way can be used, for example, in a DNA sequencer or a gas sensor.

Claims

1. Method for producing a nanoscale channel structure, comprising the following steps: a) depositing and structuring a first sacrificial layer (2) on a substrate (1), b) depositing a second sacrificial layer (3) on the substrate (1) and on the first sacrificial layer (2), the thickness of the second sacrificial layer (3) defining the height of the channel structure, c) depositing an etch masking layer (4) on the second sacrificial layer (3), d) partially removing the etch masking layer (4) and the second sacrificial layer (3) in such a way that the layer structure applied on top of the first sacrificial layer (2) and composed of the second sacrificial layer (3) and the etch masking layer (4) is removed, but the parts of the etch masking layer (4) which cover the sides of the first sacrificial layer (2) and the parts of the second sacrificial layer (3) which are arranged between the first sacrificial layer (2) and the etch masking layer (4) are not removed, e) removing the first sacrificial layer (2) and further partially removing the second sacrificial layer (3) in such a way that exposed parts of the second sacrificial layer (3) are removed and the residues of the etch masking layer (4) and the residues of the second sacrificial layer (3) that are protected thereby remain on the substrate (1), f) depositing a wall layer (5) on the etch masking layer (4) and on the substrate (1), g) structuring access openings to the second sacrificial layer (3), and h) removing the remaining second sacrificial layer (3) so that a nanoscale channel structure is obtained.

2. Method according to Claim 1, characterized in that the second sacrificial layer (3) is deposited with a thickness of less than 100 nm.

3. Method according to Claim 1 or 2, characterized in that the first sacrificial layer (2) and the second sacrificial layer (3) are deposited from the same material.

4. Method according to any of Claims 1 to 3, characterized in that the etch masking layer (4) is deposited with a smaller thickness than the first sacrificial layer (2).

5. Method according to any of Claims 1 to 4, characterized in that partially removing the etch masking layer (4) and the second sacrificial layer (3) and also removing the first sacrificial layer (2) and further partially removing the second sacrificial layer (3) are effected by anisotropic etching.

6. Method according to any of Claims 1 to 5, characterized in that the wall layer (5) is deposited from the same material as the etch masking layer (4).

7. Method according to any of Claims 1 to 6, characterized in that removing the remaining second sacrificial layer (3) is effected by isotropic etching.

8. Electronic control unit configured to carry out and / or control the steps of the method for producing a nanoscale channel structure according to any of Claims 1 to 7 in a corresponding production apparatus.

9. Computer program, in particular running on a computing device and / or an electronic control unit according to Claim 8, which is configured to carry out and / or control the steps of the method according to any of Claims 1 to 7 in a corresponding production apparatus.

10. Machine-readable storage medium on which a computer program according to Claim 9 is stored.