TRANSMIT-RECEIVER DEVICE FOR A PARTICIPANT STATION OF A SERIAL BUS SYSTEM AND METHOD FOR RECEIVING DIFFERENTIAL SIGNALS IN A SERIAL BUS SYSTEM

Description

[0001] The present invention relates to a transmit-receive device for a subscriber station of a serial bus system and a method for receiving differential signals in a serial bus system, which can be used in a transmit / receive device (transceiver). State of the art

[0002] Serial bus systems are used for message or data transmission in technical systems. For example, a serial bus system can enable communication between sensors and control units in a vehicle or a technical production plant, etc.

[0003] In a CAN bus system, messages are transmitted using the CAN and / or CAN FD protocol, as described in the ISO 11898-1:2015 standard as the CAN protocol specification with CAN FD. With CAN FD, transmission on the bus alternates between a slower operating mode in a first communication phase (arbitration phase) and a faster operating mode in a second communication phase (data phase). A CAN FD bus system can achieve a data transmission rate of greater than 1 Mbit per second (1 Mbps) in the second communication phase. Most manufacturers initially implement CAN FD in vehicles with an arbitration bit rate of 500 kbit / s and a data bit rate of 2 Mbit / s.

[0004] To enable even higher data rates in the second communication phase, successor bus systems to CAN FD exist, such as CAN-SIC and CAN-XL. With CAN-SIC, according to the CiA601-4 standard, a data rate of approximately 5 to 8 Mbit / s can be achieved in the second communication phase. CAN-XL requires a data rate of > 10 Mbit / s in the second communication phase. The current standard for CAN-XL, CiA610-3, is defined by the CAN in Automation (CiA) organization.

[0005] In all the CAN-based bus systems mentioned above, a separate bus signal CAN_H and ideally a bus signal CAN_L are driven onto a bus for each transmit signal TxD. At least during the initial communication phase, one bus state is actively driven in the CAN_H and CAN_L bus signals. The other bus state is not driven and arises automatically due to a termination resistor on the bus lines or bus wires.

[0006] In a CAN bus system, transmit / receive devices, also known as CAN transceivers or CAN FD transceivers, etc., are typically used for the individual communication participants to send and receive bus signals. With CAN XL, the transmit / receive devices must be able to send the CAN_H and CAN_L bus signals in the second communication phase using a different physical layer and receive them with a different reception threshold than in the first communication phase. The physical layer corresponds to the physical layer or layer 1 of the well-known OSI (Open Systems Interconnection) model. The physical layer of a CAN XL transmit / receive device is currently defined in the CiA610-3 standard.

[0007] This allows data to be sent to the bus at a significantly higher data rate in the second communication phase than in the first. Furthermore, the bus levels of the CAN_H and CAN_L signals can differ between the first and second communication phases. For a low error rate, it is crucial that a newly connected device can detect which communication phase is currently active on the bus.

[0008] For all operational phases of communication on the bus, it must therefore be ensured that a receiving participant station of the bus system can correctly recognize and evaluate the levels of the bus signals CAN_H, CAN_L.

[0009] US 2005 / 0141565 A1 concerns one of a number of nodes in a communication system. The nodes are connected to a communication medium for the transmission of data between them. The aforementioned single node comprises a communication controller, through which the node is connected to the communication medium, and a bus monitor for controlling the communication controller's access to the communication medium.In order to provide an inexpensive yet reliable way to monitor the synchronized clock signal of a node of a communication system, and in particular to detect deviations in the synchronized clock signal, it is proposed that a synchronized clock signal be provided by the communication controller to the bus monitor, and that the bus monitor include means for monitoring the synchronized clock signal using a bus monitor-internal clock signal generated by an electronic circuit, which is less accurate than the synchronized clock signal to be monitored. Disclosure of the invention

[0010] Therefore, the object of the present invention is to provide a transceiver for a subscriber station of a serial bus system and a method for receiving differential signals in a serial bus system, which solve the aforementioned problems. In particular, the transceiver and the method should enable reliable and efficient detection of bus signals, even if the transceiver is not the sender of the message currently transmitted on the bus and the physical layer is switching between two communication phases during communication on the bus.

[0011] The problem is solved by a transceiver for a subscriber station of a serial bus system with the features of claim 1. In the bus system, differential signals are generated on a bus of the bus system in a first communication phase with a first physical layer and in a second communication phase with a second physical layer. The transceiver has a first comparator for evaluating the differential signals received from the bus with a first reception threshold in the first communication phase and for evaluating the differential signals received from the bus with a third reception threshold in the second communication phase, wherein the first comparator is configured to output a digital received signal to a communication control device of the subscriber station.a second comparator for evaluating the differential signals received from the bus with a second reception threshold in the first communication phase for the receive signal driver, and a masking block for generating a masked comparator signal, which is a temporarily masked output signal of the second comparator, and for generating an output signal from the masked comparator signal and the output signal of the first comparator for the receive signal driver.

[0012] The described transceiver is designed to enable reliable and straightforward detection of bus signals during operation of the bus system. This applies particularly to communication scenarios where the transceiver is not the sender of the message currently transmitted on the bus and the physical layer switches between two communication phases. The transceiver can reliably distinguish between the respective bus states of the individual communication phases and thus between the individual communication phases during bus communication.

[0013] The described transceiver enables compliance with the CAN XL communication requirements, which are specified in particular in the CiA610-3 standard. However, this requires a relatively inexpensive second receive comparator, even when receiving signals from the bus with a bit time of approximately 50 ns, corresponding to a bus transmission rate of approximately 20 Mbit / s. This is because the comparator does not require the very high bandwidth necessary for receiving signals with a bit time of approximately 50 ns or less.

[0014] Furthermore, the described transceiver is designed such that the signal levels of the bus signals can be converted into a digital receive signal by simultaneously evaluating two receive thresholds. The two receive thresholds used in the individual communication phases can differ for each communication phase.

[0015] This ensures that the transceiver device does not disrupt communication on the bus with its superior receiving station, which may be newly connected or reconnected after a fault. The receiving station can reliably detect whether the bus is free of data traffic using the transceiver device. Because the transceiver reliably assigns the current bus states, the newly connected receiving station will only send data to the bus once it is clear. Therefore, connecting a receiving station, for example, during initial startup or attempting to reconnect after a bus communication fault, does not disrupt communication on the bus.

[0016] As a result, the transceiver enables the use of different receive thresholds for the arbitration and data phases. This not only allows for higher bit rates in bus communication but also prevents communication errors from reducing the transmittable bit rate.

[0017] Further advantageous configurations of the transmitting and receiving device are described in the dependent claims.

[0018] The masking block can include a timing element connected to an output of the second comparator and configured to output the masked comparator signal, and a logic circuit configured to generate a signal for output to the receive signal driver from the output signal of the first comparator and the masked comparator signal.

[0019] Optionally, the logic circuit is an AND gate to form a serial logical AND operation of the output signal of the first comparator and the masked comparator signal.

[0020] The transmit / receive device may also have a driver for driving a digital receive signal to a communication control device of a subscriber station of the bus system, and a receive signal logic circuit for forwarding an output signal from a first comparator line, which includes the first comparator, and an output signal from a second comparator line, which includes the second comparator, to the driver when communication takes place in the first communication phase, and for forwarding only the output signal from the first comparator line to the driver when communication takes place in the second communication phase.

[0021] The transmit / receive device may also have a first voltage divider connected to the bus, which outputs the differential signals received from the bus to the first comparator, and a second voltage divider connected to the bus, which outputs the differential signals received from the bus to the second comparator.

[0022] The first and second voltage dividers can each have a circuit of resistors to which the first and second comparators are connected, with the first and second comparators evaluating the differential signals simultaneously.

[0023] The first voltage divider can have a switch arranged to set the first receive threshold for the first voltage divider in a first switching position and to set the third receive threshold for the first voltage divider in a second switching position, wherein the second voltage divider is configured to set the second receive threshold.

[0024] The switching unit can be arranged to add or remove a resistor to ground.

[0025] Optionally, the switching unit can be an NMOS transistor.

[0026] In a special embodiment, the transmitting / receiving device is configured to output the output signal of the second comparator to the receiving signal driver when the switch, in its first switching position, has set the first receiving threshold in the first voltage divider, and the transmitting / receiving device may also be configured not to output the output signal of the second comparator to the receiving signal driver when the switch, in its second switching position, has set the third receiving threshold in the first voltage divider.

[0027] It is conceivable that the transmit / receive device also has an operating mode setting unit for controlling the switch to change the first voltage divider between the first and third receive thresholds, depending on whether the first or second communication phase is taking place on the bus.

[0028] The transmit / receive device may also have a transmit module for sending signals to a bus of the bus system.

[0029] The previously described transmit / receive device can be part of a subscriber station for a serial bus system. The subscriber station can also include a communication control unit for managing communication within the bus system and for generating a digital transmit signal for the transmit module.

[0030] Optionally, the participant station is designed for communication in a bus system, in which at least temporarily exclusive, collision-free access of a participant station to the bus of the bus system is guaranteed.

[0031] The aforementioned problem is further solved by a method for receiving differential signals in a serial bus system with the features of claim 15. In the bus system, differential signals are generated on a bus of the bus system in a first communication phase with a first physical layer and in a second communication phase with a second physical layer. The method comprises the steps of receiving differential signals from the bus with a transceiver, evaluating the differential signals received from the bus with a first reception threshold in the first communication phase with a first comparator, and evaluating the differential signals received from the bus with a third reception threshold in the second communication phase with the first comparator.wherein the first comparator outputs a digital receive signal to a communication control unit of the receiving station in the first and second communication phases, and evaluates, with a second comparator, the differential signals received from the bus with a second receive threshold in the first communication phase for the receive signal driver, and generates, with a masking block, a masked comparator signal which is a temporarily masked output signal of the second comparator, and generates, with the masking block, an output signal from the masked comparator signal and the output signal of the first comparator for the receive signal driver.

[0032] The method offers the same advantages as previously mentioned in relation to the transmitting and receiving equipment.

[0033] Other possible implementations of the invention also include combinations of features or embodiments described previously or subsequently with regard to the exemplary embodiments, even if not explicitly mentioned. In such cases, the person skilled in the art will also add individual aspects as improvements or additions to the respective basic form of the invention. Drawings

[0034] The invention is described in more detail below with reference to the accompanying drawing and by means of exemplary embodiments. The drawing shows: Fig. 1 a simplified block diagram of a bus system according to a first embodiment; Fig. 2 a diagram illustrating the structure of a message that can be sent by a participant station of the bus system according to the first embodiment; Fig. 3 An example of the ideal timing of bus signals CAN_H, CAN_L in the bus system of Fig. 1 ; Fig. 4 the time course of a differential voltage VDIFF, which occurs on the bus of the bus system as a result of the bus signals from Fig. 4 trains; Fig. 5 a simplified block diagram of a transmit-receive device with a receiver module for a subscriber station of the bus system according to the first embodiment; Fig. 6 a circuit diagram of a receiver module according to a first embodiment; Fig. 7 the time course of a differential voltage VDIFF, which occurs on the bus of the bus system as a result of the transmit-receive device of Fig. 5 trains; Fig. 8 the temporal profile of a received signal, which the receiving module of Fig. 6 from the signal received by the bus Fig. 7 forms when a timing element of the receiver module is inactive; Fig. 9 the temporal profile of a received signal, which the receiving module of Fig. 6 from the signal received by the bus Fig. 7 forms when the timer of the receiver module is active; Fig. 10 An example of the temporal profile of a digital transmission signal, which, according to a second embodiment, is converted into bus signals CAN_H, CAN_L for a bus of the bus system of in the arbitration phase (SIC operating mode). Fig. 1 to be implemented; Fig. 11 the temporal evolution of the bus signals CAN_H, CAN_L during the transition between a recessive bus state to a dominant bus state and back to the recessive bus state, which occurs during the arbitration phase (SIC operating mode) due to the transmit signal from Fig. 10 be sent to the bus; Fig. 12 An example of the temporal profile of a digital transmission signal, which, according to the second embodiment, is converted in the data phase into bus signals CAN_H, CAN_L for the bus of the bus system of Fig. 1 to be implemented; and Fig. 13 the temporal progression of the bus signals CAN_H, CAN_L, which in the data phase are due to the transmit signal from Fig. 12 be sent to the bus.

[0035] In the figures, identical or functionally equivalent elements are provided with the same reference symbols unless otherwise specified. Description of the exemplary implementations

[0036] Fig. 1 Figure 1 shows a bus system 1, which can be, for example, at least partially a CAN bus system, a CAN FD bus system, etc. Bus system 1 can be used in a vehicle, in particular a motor vehicle, an aircraft, etc., or in a hospital, etc.

[0037] In Fig. 1 Bus system 1 has a plurality of terminal stations 10, 20, 30, each connected to a bus 40 or bus line with a first bus wire 41 and a second bus wire 42. The bus wires 41 and 42 can also be called CAN_H and CAN_L for the signals on bus 40. Messages 45, 46, 47 in the form of signals can be transmitted between the individual terminal stations 10, 20, 30 via bus 40. The terminal stations 10, 20, 30 can be, for example, control units or display devices of a motor vehicle.

[0038] As in Fig. 1 As shown, participant stations 10 and 30 each have a communication control unit 11 and a transmit / receive unit 12. The transmit / receive unit 12 has a transmit module 121 and a receive module 122.

[0039] The subscriber station 20 has a communication control unit 21 and a transmit / receive unit 22. The transmit / receive unit 22 has a transmit module 221 and a receive module 222.

[0040] The transmit / receive equipment 12 of subscriber stations 10 and 30, and the transmit / receive equipment 22 of subscriber station 20, are each directly connected to bus 40, even if this is in Fig. 1 not shown.

[0041] The communication control devices 11, 21 each serve to control communication between the respective subscriber station 10, 20, 30 via bus 40 with at least one other subscriber station of the subscriber stations 10, 20, 30 that are connected to bus 40.

[0042] The communication control units 11 create and read initial messages 45, 47, which are, for example, modified CAN messages 45, 47. These modified CAN messages 45, 47 are based, for example, on the CAN XL format. The transmit / receive unit 12 is used to send and receive messages 45, 47 from the bus 40. The transmit module 121 receives a digital transmit signal TxD created by the communication control unit 11 for one of the messages 45, 47 and converts it into signals on the bus 40. The receive module 121 receives signals transmitted on the bus 40 corresponding to messages 45 to 47 and generates a digital receive signal RxD from them. The receive module 122 sends the receive signal RxD to the communication control unit 11.

[0043] The communication control unit 21 can be implemented like a conventional CAN controller according to ISO 11898-1:2015, i.e., like a CAN FD-tolerant Classical CAN controller or a CAN FD controller. The communication control unit 21 creates and reads secondary messages 46, for example, CAN FD messages 46. The transmit / receive unit 22 is used to send and receive the messages 46 from the bus 40. The transmit module 221 receives a digital transmit signal TxD created by the communication control unit 21 and converts it into signals for a message 46 on the bus 40. The receive module 221 receives signals transmitted on the bus 40 corresponding to messages 45 to 47 and generates a digital receive signal RxD from them. Alternatively, the transmit / receive unit 22 can be implemented like a conventional CAN transceiver.

[0044] For sending messages 45 and 47 using CAN SIC or CAN XL, proven features are adopted that are responsible for the robustness and user-friendliness of CAN and CAN FD, in particular the frame structure with identifier and arbitration according to the well-known CSMA / CR method. The CSMA / CR method results in so-called recessive states on bus 40, which can be overwritten by other participating stations 10, 20, and 30 with dominant levels or dominant states on bus 40.

[0045] With the two participant stations 10, 30, the formation and then transmission of messages 45 with various CAN formats, in particular the CAN FD format or the CAN SIC format or the CAN XL format, as well as the reception of such messages 45, is possible, as described in more detail below.

[0046] Fig. 2 Figure 1 shows a frame 450 for message 45, which is in particular a CAN XL frame, as provided by the communication control unit 11 to the transmit / receive unit 12 for transmission on bus 40. In this embodiment, the communication control unit 11 creates the frame 450 as compatible with CAN FD. Alternatively, the frame 450 is compatible with CAN SIC.

[0047] According to Fig. 2 Frame 450 for CAN communication on bus 40 is divided into different communication phases 451 and 452: an arbitration phase 451 (first communication phase) and a data phase 452 (second communication phase). Following a start bit SOF, frame 450 has an arbitration field 453, a control field 454 (where the switch from arbitration phase 451 to data phase 452 occurs), a data field 455, a checksum field 456, and a frame termination field 457.

[0048] In arbitration phase 451, an identifier (ID) with, for example, bits ID28 to ID18 in the arbitration field 453 is used to negotiate bitwise between participating stations 10, 20, and 30 which station wants to send the message 45, 46 with the highest priority and therefore receives exclusive access to bus 40 of bus system 1 for sending in the subsequent data phase 452. A physical layer, similar to CAN and CAN-FD, is used in arbitration phase 451. This physical layer corresponds to the physical layer, or layer 1, of the well-known OSI model (Open Systems Interconnection model).

[0049] An important point during phase 451 is the use of the well-known CSMA / CR protocol, which allows simultaneous access to bus 40 by participant stations 10, 20, and 30 without destroying the higher-priority message 45 or 46. This makes it relatively easy to add further bus participant stations 10, 20, and 30 to bus system 1, which is very advantageous.

[0050] The CSMA / CR protocol necessitates the existence of recessive states on bus 40, which can be overridden by other participant stations 10, 20, 30 with dominant levels or states on bus 40. In the recessive state, high impedance conditions prevail at individual participant stations 10, 20, 30, which, in combination with the parasitic effects of the bus circuitry, results in longer time constants. This limits the maximum bit rate of today's CAN FD physical layer to approximately 2 megabits per second in real-world vehicle applications.

[0051] In data phase 452, in addition to a portion of the control field 454, the payload data of the CAN-XL frame 450 or message 45 from data field 455, as well as the checksum field 456, are transmitted. The checksum field 456 can contain a checksum of the data from data phase 452, including the stuff bits that the sender of message 45 inserts as an inverse bit after a predetermined number of identical bits, in particular 10 identical bits. At the end of data phase 452, the signal switches back to arbitration phase 451.

[0052] In an end field in frame termination phase 457, at least one acknowledge bit can be present. Additionally, a sequence of 11 identical bits can be present, indicating the end of the CAN XL frame 450. The at least one acknowledge bit can be used to communicate whether a receiver has detected an error in the received CAN XL frame 450 or message 45.

[0053] A sender of message 45 only begins sending bits of data phase 452 to bus 40 when the subscriber station 10, as the sender, has won the arbitration and thus has exclusive access to bus 40 of bus system 1 for sending.

[0054] Thus, in the arbitration phase 451, the participating stations 10 and 30 partially use a format known from CAN / CAN-FD according to ISO 11898-1:2015, particularly up to and including the FDF bit. However, compared to CAN or CAN FD in the data phase 452, the second communication phase, an increase in the net data transmission rate, especially to over 10 megabits per second, is possible. Furthermore, increasing the size of the payload per frame, especially to approximately 2 kilobytes or any other value, is possible.

[0055] Fig. 3 The diagram on the left shows that in arbitration phase 451, participating stations 10, 20, and 30, with a first physical layer 451_P, each send signals CAN_H and CAN_L over time t to bus 40, which have a first bit duration t_bt1. The signals CAN_H and CAN_L are serial signals and alternately have at least one dominant state 401, where VCAN_H = 3.5 V and VCAN_L = 1.5 V, or at least one recessive state 402, where VCAN_H = VCAN_L = 2.5 V. Dominant states 401 are driven in phase 451 with NRZ encoding of the transmitted signal TxD when TxD = 0 or L (LOW). Recessive states 402 are generated, or arise during NRZ encoding of the transmitted signal TxD in phase 451, if TxD = 1 or H (HIGH). After the arbitration in arbitration phase 451, one of the participating stations 10, 20, or 30 is determined as the winner.

[0056] Do participant stations 10, 20, 30 detect a signal in control field 454 from Fig. 3 For the switch from the first to the second communication phase 451, 452, the respective transmit / receive device 12 switches its physical layer 451_P at the end of the arbitration phase 451 from a first operating mode (SLOW), which can also be implemented as a SIC operating mode, to the physical layer 452_P of the data phase 452, as shown on the right in Fig. 3 shown. For this purpose, the operating modes of data phase 452 are activated as follows.

[0057] Assume that subscriber station 10 has won the arbitration. Then, at the end of the arbitration phase 451, the transmit / receive device 12 of subscriber station 10 switches its physical layer 451_P from a first operating mode (SLOW) to the physical layer 452_P for a second operating mode (FAST_TX), since subscriber station 10 is the sender of message 45 in the data phase 452. The transmitter module 121 then generates, in data phase 452 or in the second operating mode (FAST_TX), the states L0 or L1 for the signals CAN_H, CAN_L on bus 40 sequentially and thus serially, depending on a transmit signal TxD. State L0 (VCAN_H = 3.0 V, VCAN_L = 2.0 V) is driven by pulse width modulation (PWM encoding) of the transmit signal TxD for a first PWM symbol in the transmit signal TxD.The state L1 (VCAN_H = 2.0 V and VCAN_L = 3.0 V) is driven in the pulse width modulation (PWM encoding) of the transmit signal TxD for a second PWM symbol that differs from the first PWM symbol in the transmit signal TxD.

[0058] The frequency of the CAN_H and CAN_L signals can be increased in data phase 452, as shown on the right side in Fig. 3 shown in the example of Fig. 3 In this case, the bit time or bit duration t_bt2 in data phase 452 is shorter or lower than the bit time or bit duration t_bt1 in arbitration phase 451. Therefore, the net data transmission rate in data phase 452 in the example of Fig. 3 increased compared to the arbitration phase 451.

[0059] In contrast, the transmit / receive equipment 12 of subscriber station 30 switches its physical layer 451_P from the first operating mode (SLOW) to the physical layer 452_P for a third operating mode (FAST_RX) at the end of the arbitration phase 451, since subscriber station 30 is only a receiver, and not a transmitter, of the frame 450 during the data phase 452. After the end of the data phase 452, all transmit / receive equipment 12 of subscriber stations 10 and 30 switch their operating mode to the first operating mode (SLOW). Thus, all transmit / receive equipment 12 also switch their physical layer.

[0060] According to Fig. 4 In the arbitration phase 451, ideally a differential signal VDIFF = CAN_H - CAN_L is formed on bus 40 with values ​​of VDIFF = 2V for dominant states 401 and VDIFF = 0V for recessive states 402. This is shown on the left side in Fig. 4 shown. In contrast, a differential signal VDIFF = CAN_H - CAN_L with states L0, L1 is formed on bus 40 in data phase 452, as shown on the right side in Fig. 4 shown. State L0 has a value VDIFF = 1V. State L1 has a value VDIFF = -1V.

[0061] The receiver module 122 can distinguish between states 401 and 402 using any two of the reception thresholds T1, T2, and T3, which lie within the ranges TH_T1, TH_T2, and TH_T3. For this purpose, the receiver module 122 samples the signals from Fig. 3 oder Fig. 4 at time points t_A. To evaluate the sampling result, the receiver module 122 uses the receive threshold T1 of, for example, 0.7 V and the receive threshold T2 of, for example, -0.35 V during the arbitration phase 451. In contrast, during the data phase 452, the receiver module 122 only uses signals that were evaluated with the receive threshold T3. When switching between the first to third operating modes (SLOW, FAST_TX, FAST_RX), which were previously defined with respect to Fig. 3 As described below, the receiver module 122 switches the reception thresholds T2 and T3 as described below.

[0062] The receive threshold T2 is used to detect whether bus 40 is free when the new participant station 12 joins the communication on bus 40 and attempts to integrate itself. In the CAN standard, the receive threshold T2 is referred to as OOB (Out-of-Boundary). The conditions for a traffic-free CAN-XL bus are that no dominant state 401 occurs, which typically has a differential voltage VDIFF = 2V. Therefore, the receive threshold T1 of, for example, 0.7V must not be exceeded. Furthermore, no levels corresponding to state L1 may occur, which typically has a differential voltage VDIFF = 2V -1V. Therefore, the receive threshold T2 of, for example, -0.35V must not be undercut.

[0063] Each subscriber station 10, 30 switches the operating mode of the transmit / receive device 12 to the operating mode of the arbitration phase 451 when the subscriber station 12 is newly connected to the communication on bus 40.

[0064] Adding participant station 10 may be necessary for two reasons: firstly, when participant station 10 is initially started and needs to be integrated into the communication on bus 40; and secondly, when participant station 10 attempts to reintegrate into the communication on bus 40 after a bus communication error. Only when it is determined that the bus is free may participant station 10 itself send data, specifically messages 45 and 47, to bus 40 in these cases. For this to occur, a check is performed to ensure that no dominant level is present on bus 40, meaning that the receive threshold T1 is not exceeded. Additionally, a check is performed to ensure that neither L0 nor L1 levels are present on bus 40. Depending on the transceiver's transmit level, the threshold T1 can be exceeded by levels for states 401 (dom) and L0.Therefore, the threshold T2 is used, which performs a detection via states L0.

[0065] Table 1 below shows the values ​​that can be set for the individual receive thresholds on bus 40. VDIFF_min specifies the lower limit, in V, that may be set for each of the ranges TH_T1, TH_T2, TH_T3. VDIFF_typ specifies the value that is typically or usually set for each of the corresponding receive thresholds T1, T2, T3. VDIFF_max specifies the upper limit, in V, that may be set for each of the corresponding receive thresholds T1, T2, T3. Table 1: Tolerance ranges of the reception thresholds T1, T2, T3 Empfangsschwelle VDIFF_min in V VDIFF_typ in V VDIFF_max in V Toleranz in V T1 0,5 0,7 0,9 + / - 0,2 T2 -0,45 -0,35 -0,25 + / - 0,1 T3 -0,1 0,0 +0,1 + / - 0,1

[0066] Fig. 5 Figure 1 shows the basic structure of the transmit / receive unit 12 of the subscriber station 10. The transmit module 121 is shown in a very simplified manner. The transmit module 121 is directly connected to bus 40 in order to send the transmit signal TxD of the communication control unit 11 to bus 40 in order to transmit signals according to Fig. 3 to generate on bus 40.

[0067] The receiver module 122 has a driver 1221 for the digital receive signal RxD, a logic circuit 1222, and a receiver circuit 15. The receiver circuit 15 has a first receive comparator line 151, a second receive comparator line 152, a receive stage 153, and a masking block 155. The receive comparators 151 and 152 are each receive comparator lines with a low-voltage comparator. This is in relation to Fig. 6 explained in more detail.

[0068] According to Fig. 5 The receiver circuit 15 is connected between bus 40 and logic circuit 1222. The driver 1221 is connected to the output of logic circuit 1222. The driver 1221 drives or sends the digital receive signal RxD to the communication control unit 11.

[0069] In receiver circuit 15, receiver stage 153 is connected to bus 40. During operation of bus system 1, receiver stage 153 generates signals S_1 and S_2 from the CAN_H and CAN_L signals and passes these on to the first receiver comparator line 151. The first receiver comparator line 151 generates a comparator output signal C_1 from the S_1 and S_2 signals.

[0070] Furthermore, during operation of bus system 1, the receiver stage 153 generates additional signals S_3 and S_4 from the CAN_H and CAN_L signals and forwards these to the second receiver comparator line 152. The second receiver comparator line 152 generates a comparator output signal C_2 from the S_3 and S_4 signals.

[0071] The logic circuit 1222 is configured to output signal C_1 and signal C_2 to driver 1221, or only signal C_2, depending on the operating mode of the transmitter / receiver 12. The operating mode of the transmitter / receiver 12, in particular its receiver module 122, is one of the first to third operating modes (SLOW, FAST_TX, FAST_RX), as described previously. For this purpose, the logic circuit 1222 can include at least one AND gate. Alternatively, the logic circuit 1222 has other logic components to fulfill the function of the receiver module 122 described below.

[0072] The receiver stage 153, the masking block 155 and their connection to the logic circuit 1222 are described by means of Fig. 6 described in more detail.

[0073] As in Fig. 6 As shown, the receiver circuit 15 also has a bus biasing source 154, which supplies a voltage CAN_SUPPLY / 2 to the receiver stage 153. CAN_SUPPLY is usually 5 V. In this case, the bus biasing source 154 supplies a voltage of 2.5 V to the receiver stage 153.

[0074] The first receiving comparator line 151 has a first input filter 1511, a first comparator 1512 that outputs a digital output signal CA1, and a first output filter 1513 that outputs a digital output signal C_1. The second receiving comparator line 152 has a second input filter 1521, a second comparator 1522 that outputs a digital output signal CA2, and a second output filter 1523 that outputs a digital output signal C_2. The filters 1511, 1523, 1521, and 1523 each filter out interference from the signals input to the respective filter 1511, 1523, 1521, and 1523, respectively. Each of the receiving comparators 1512 and 1522 is a low-voltage comparator.

[0075] The masking block 155 is connected between the receive comparator lines 151 and 152. The masking block 155 has a timing element 1551, which outputs a digital signal CM, and a logic circuit 1552, which outputs a digital signal C1. The logic circuit 1552 can include at least one AND gate. Alternatively, the logic circuit 1552 has other logic elements to perform the function of the receive module 122 described below.

[0076] The receiver stage 153 has a first voltage divider 1531 with a first switch Sw1, a second voltage divider 1532, an operating mode setting unit 1533, and an optional second switch Sw2. The first and second voltage dividers 1531 and 1532 are each supplied with the same voltage from the bus bias source 154, in particular 2.5V for recessive state 402 ( Fig. 3 The second switch Sw2 can optionally switch off the second voltage divider 1532.

[0077] The first voltage divider 1531 and the second voltage divider 1532, for example, are each resistive voltage dividers, or resistance-to-resistance voltage dividers, each containing several resistors that form a resistor network. The first voltage divider 1531 and the second voltage divider 1532 each have a resistor connected to ground (CAN_GND) and terminal 44, respectively, even though this is shown in the diagram. Fig. 6 not shown in detail.

[0078] The first voltage divider 1531 can, for example, set the reception threshold T1 of Fig. 4 or the reception threshold T3 of Fig. 4 The outputs of the first voltage divider 1531 are connected to the inputs of the first input filter 1511. Switch Sw1, controlled by the operating mode setting unit 1533, is used to select the setting of the first voltage divider 1531. When switch Sw1 is in the appropriate position, the first voltage divider 1531 sets the receive threshold T1 of Fig. 4 one, otherwise the first voltage divider 1531 sets the reception threshold T3 of Fig. 4 one. For this purpose, switch Sw1 can be arranged, for example, to make a path to a resistor to ground (terminal 44) conductive, in order to lower the reception threshold T1 of Fig. 4 to adjust. If switch Sw1 then makes the path to the resistor to ground (terminal 44) non-conductive, the third reception threshold T3 is set. Fig. 4 set.

[0079] The outputs of the second voltage divider 1532 are connected to the inputs of the second input filter 1521. The second voltage divider 1532 can, for example, set the receive threshold T2 of Fig. 4 set.

[0080] The circuit of the resistors in the resistor networks of the voltage dividers 1531, 1532 is symmetrically constructed.

[0081] To meet the input resistance requirement Rin for CANH and CANL, voltage dividers 1531 and 1532 each have two resistance paths: one for the CANH connection and one for the CANL connection. Here, Rin_CANH and Rin_CANL are set to 25 kΩ to 50 kΩ. Typically, an input resistance Rin of 37.5 kΩ is chosen for the CANH connection (pin) for the CAN_H signal and for the CANL connection (pin) for the CAN_L signal.

[0082] The switching unit Sw1 can be a transistor, in particular an NMOS transistor. The abbreviation "NMOS" refers to an n-channel MOSFET, where "MOSFET" stands for metal-oxide field-effect transistor.

[0083] Voltage dividers 1531 and 1532 form a double divider structure. They divide the bus voltages generated by the CAN_H and CAN_L signals into values ​​that can be processed by comparator lines 151 and 152.

[0084] The dual divider structure of the receiver stage 15 allows two different reception thresholds T1, T2, and T3 to be tested independently and therefore simultaneously. Additionally, the switching unit Sw1, controlled by the operating mode setting unit 1533, allows switching between two reception thresholds T1, T2, and T3. This allows either the reception thresholds T1 and T2 to be set according to... Fig. 4 independently and simultaneously tested, or the reception thresholds T1, T3 according to Fig. 4 They can be tested independently and simultaneously. Therefore, any two of the three reception thresholds T1, T2, T3 can be switched to the third reception threshold as needed.

[0085] The operating mode setting unit 1533 thus sets the receive thresholds T1, T2, T3 according to the currently required operating mode (SLOW, FAST_TX, FAST_RX) of the transmit / receive device 12. The following applies to the example described above: Table 2: Assignment of comparator output signals and receive thresholds Signal detektierte Empfangsschwelle Phase 451 detektierte Empfangsschwelle Phase 452 CA1 T1 T3 CA2 T2 -

[0086] Specifically, in the preceding example, this means that only a single receive threshold, the receive threshold T3, is checked when the transmit / receive device 12 is itself in a FAST operating mode (FAST_TX, FAST_RX), i.e., during the data phase 452. For this purpose, the first receive comparator line 151 is used and switched to the receive threshold T3 (typically VDIFF = 0 V). During the arbitration phase 451, however, both receive comparator lines 151 and 152 are used.

[0087] The second comparator 1522 can, for example, be configured to detect signals on bus 40 in data phase 452, which have a typical bit time t_bt2 ( Fig. 3 ) of 50 ns. In this case, the states L0 / L1 are transmitted or sent in data phase 452 at a transmission rate of 20 Mbit / s. This requires a very high bandwidth for the second comparator 1522.

[0088] If the transmit / receive device 12 is currently a receiving node, meaning another subscriber station 10, 20, 30 on bus 40 is sending message 45 to bus 40, the following applies. Upon detection of an L1 state with t_bt2 = 50ns ( Fig. 3 The second comparator 1522 must acknowledge this at its output in the signal CA2 with a pulse of at least 15 ns, as specified in the CiA610-3 standard. Consequently, during a transition from a low-impedance dominant state 401 to a comparatively high-impedance recessive state 402, oscillations S1 occur in the differential voltage VDIFF on bus 40, as shown in Fig. 7 shown.

[0089] If masking block 155 is not active, the receive signal driver 1221 outputs a receive signal RxD, as shown in Fig. 8 shown. Due to the required high bandwidth of the second comparator 1522, the undershoots (oscillation S1) of Fig. 7 in the form of dominant glitches G1 at output RXD in the receive signal RxD, as in Fig. 8 shown. The glitches G1 are small disturbances that are visible at the output RXD in the received signal RxD. In the example of Fig. 8 are all sub-oscillators (oscillation S1) of Fig. 7 each is represented in the RxD signal and thus visible to the communication control unit 11.

[0090] Depending on the topology and oscillation period, unwanted glitches G1 can occur in the received signal RxD up to the sampling point t_A. These glitches G1 distort the received signal RxD, which can disrupt communication in bus system 1.

[0091] However, if masking block 155 is active, the receive signal driver 1221 outputs a receive signal RxD, as shown in Fig. 9 shown. The resulting received signal from Fig. 9 are all sub-oscillators (oscillation S1) of Fig. 7 Each is masked out and therefore not included in the RxD signal from Fig. 9 depicted and therefore not visible to the communication control unit 11.

[0092] The receiver module 122 from Fig. 6 The output signal CA2 of the second comparator 1522 is output to the masking block 155, in particular its timing element 1551.

[0093] According to one possibility, the timing element 155 causes the output of the second comparator 1522 to be masked out by default for a predetermined masking time t_22 whenever a recessive bus state is entered, in which the receive threshold T1 is undershot and detection by the first comparator 1512 occurs. This masks out the undershoots (oscillation S1) in the differential voltage VDIFF of Fig. 7 "Overlooked" by the second comparator 1522 and not signaled at the RxD, as in Fig. 9 As shown, the output of the second comparator 1522 is only reactivated after the predetermined time t_22 has elapsed. This makes the second comparator line 152 fast and capable of meeting the values ​​required by the CiA610-3 standard.

[0094] Due to the masking block 155, the second comparator 1522 does not, by default, have the high bandwidth in the first communication phase 451 or in the first operating mode (SLOW phase) to detect at least 15ns at the output from a 50ns wide bit on bus 40.

[0095] The nominal value of the predetermined masking time t_22 can, for example, be approximately 500 ns. The value for the predetermined masking time t_22 can be configured in the transmit / receive device 12. This is advantageous because the differential undershoots (oscillation S1) in the differential voltage VDIFF of Fig. 7 among other things, it also depends on the bus topology, such as the number of branch lines, star topology, etc.

[0096] Alternatively, the value for the predetermined masking time t_22 can be set automatically in the transmit / receive device 12.

[0097] According to a second possibility, the following applies: If a message 45, sent from another subscriber station 10, 20, 30 of bus system 1, exceeds the receive threshold T1 in the transmit / receive device 12, then either a dominant or an L0 bus state exists. This means that the transmit / receive device 12 has recognized that communication is taking place on bus 40. Consequently, the receive signal RxD goes to the value LW (LOW), which allows the communication control device 11 to recognize that bus 40 is occupied.

[0098] According to a third possibility, the following applies: If the receive threshold T1 is not exceeded, either a low L0 state may have been transmitted by another subscriber station 10, 20, 30 of bus system 1, which L0 state was not detected by the receive threshold T1, or bus 40 is truly recessive and therefore free. Thus, after the predetermined time t_22 has elapsed, the second comparator 1522, i.e., with the high bandwidth, is used for measurement. This allows the L1 states in the signal on bus 40 to be reliably detected by the second comparator 1522.

[0099] This means that the masking block 155, with the help of the timing element 1551 and the logic circuit 1552, can always ensure the correct recognition of the individual communication phases 451, 452 on bus 40 in receiving nodes, even when the physical layer is switched between the communication phases 451, 452 to send signals CAN_H, CAN_L to bus 40.

[0100] This enables a high data transmission rate on bus 40 and thus a very efficient operation of bus system 1.

[0101] According to a second embodiment, the transmitter module 121 generates the signals CAN_H, CAN_L for the two communication phases on bus 40, as shown by Fig. 10 bis Fig. 13 described below.

[0102] Fig. 10 Figure 1 shows an example of a portion of the digital transmit signal TxD, which the transmit module 121 receives from the communication control unit 11 during arbitration phase 451, and from which it generates the signals CAN_H and CAN_L for bus 40. Fig. 10 The transmitted signal TxD changes from a state LW (Low) to a state HI (High) and back to the state LW (Low).

[0103] Ideally, the received signal RxD is identical to the transmitted signal TxD. In such an ideal case, there is no transmission delay / latency, especially over bus 40, and no possible reception error.

[0104] As in Fig. 11 To show more precisely, the transmitter module 121 can be used for the transmission signal TxD from Fig. 10 in CAN SIC or CAN XL operating mode the signals CAN_H, CAN_L from Fig. 11 for bus lines 41, 42. Unlike Fig. 3 , is in the signals from Fig. 11 Additionally, a state 403 (sic) exists. State 403 (sic) can have a different duration, as shown by state 403_0 (sic) during the transition from state 402 (rec) to state 401 (dom) and state 403_1 (sic) during the transition from state 401 (dom) to state 402 (rec). State 403_0 (sic) is shorter in duration than state 403_1 (sic). To process signals according to Fig. 11 To generate this, the transmitter module 121 is switched to a SIC operating mode (SIC mode).

[0105] According to the CiA610-3 standard for CAN XL, the passage through the short sic state 403_0 is not required, and its existence depends on the implementation. The duration of the "long" state 403_1 (sic) is specified for both CAN-SIC and the SIC mode in CAN-XL as t_sic < 530 ns, beginning with the rising edge of the transmit signal TxD. Fig. 10 .

[0106] In the "long" state 403_1, the transmitter module 121 is designed to match the impedance between bus conductors 41 (CANH) and 42 (CANL) as closely as possible to the characteristic impedance Zw of the bus line used. Here, Zw = 100 ohms or 120 ohms. This matching prevents reflections and thus allows operation at higher bit rates. For simplicity, the following text will always refer to state 403 or state 403.

[0107] Fig. 12 shows an example of another part of the digital transmit signal TxD, which the transmit module 121 according to the second embodiment receives in the data phase 452 from the communication control unit 11 ( Fig. 1 ) receives, and generates the CAN_H and CAN_L signals for bus 40 from it. In Fig. 12 The transmitted signal TxD changes several times from state HI (High) to state LW (Low) and back to state HI (High) and so on.

[0108] As in Fig. 13 To show more precisely, the transmitter module 121 generates the transmission signal TxD from Fig. 12 The signals CAN_H and CAN_L for bus wires 41 and 42 are configured such that state L0 is established for a state LW (Low). Additionally, state L1 is established for a state HI (High).

[0109] It is possible that for the two bus states L0 and L1, at least temporarily, no dominant and recessive bus states are used, but instead a first bus state and a second bus state are used, both of which are driven. An example of such a bus system is a CAN XL bus system.

[0110] The receiver module 122 can also receive the signals according to Fig. 11 and Fig. 13 The two different communication phases are received: the SIC operating mode or arbitration phase 451 and the data phase 452. For this purpose, the receiving module 122 switches the reception thresholds T1 and T3 for the respective operating modes, as previously described in relation to the preceding embodiment.

[0111] The operating mode setting unit 1533 thus sets the receive thresholds T1, T2, T3 according to the currently required operating mode (SIC, FAST_TX, FAST_RX) of the transmit / receive device 120.

[0112] The comparator lines 151, 152 can also be combined with the masking block 155 in this way. Fig. 6 can be operated very advantageously.

[0113] All previously described configurations of the transmit / receive device 12, the transmit module 121, the receive module 122, the subscriber stations 10, 20, 30, the bus system 1, and the method implemented therein according to the first and second embodiments and their modifications can be used individually or in any possible combination. In addition, the following modifications are particularly conceivable.

[0114] The bus system 1 described above, according to the first and second embodiments, is based on the CAN protocol. However, the bus system 1 according to the first and / or second embodiment can alternatively be a different type of communication network in which the signals are transmitted as differential signals. It is advantageous, but not a necessary requirement, that the bus system 1 ensures exclusive, collision-free access to bus 40 for a participant station 10, 20, 30, at least for certain periods of time.

[0115] The bus system 1 according to the first and / or second embodiment and their modifications is, in particular, a CAN bus system, a CAN HS bus system, a CAN FD bus system, a CAN SIC bus system, or a CAN XL bus system. However, the bus system 1 can be a different communication network in which the signals are transmitted as differential signals and serially via bus 40.

[0116] Thus, the functionality of the previously described embodiments can be used, for example, in transmitting / receiving devices 12, 22 which can be operated in a CAN bus system or a CAN HS bus system or a CAN FD bus system or a CAN SIC bus system or a CAN XL bus system.

[0117] The number and arrangement of the participant stations 10, 20, 30 in the bus system 1 according to the first and second embodiments and their modifications is arbitrary. In particular, only participant stations 10 or only participant stations 30 are present in the bus systems 1 of the first or second embodiment.

Claims

1. Transmitting / receiving device (12) for a subscriber station (10; 30) of a serial bus system (1), in which differential signals (CAN_H, CAN_L) on a bus (40) of the bus system (1) are generated using a first physical layer (451_P) in a first communication phase (451) of communication on the bus (40) and are generated using a second physical layer (452_P) in a second communication phase (452) of communication on the bus (40), the transmitting / receiving device (12) comprising a first comparator (1512) for evaluating the differential signals (CAN_H, CAN_L) received from the bus (40) using a first reception threshold (T1) in the first communication phase (451) and for evaluating the differential signals (CAN_H, CAN_L) received from the bus (40) using a third reception threshold (T3) in the second communication phase (452), the first comparator (1512) being configured to output an output signal (CA1) in order to output a digital received signal (RxD) to a communication control device (11) of the subscriber station (10; 30), a second comparator (1522) for evaluating the differential signals (CAN_H, CAN_L) received from the bus (40) using a second reception threshold (T2) in the first communication phase (451) for the received signal driver (1221), and a masking block (155) for generating a masked comparator signal (Cm), which is a temporarily masked output signal (CA2) of the second comparator (1522), and for generating an output signal (C1) from the masked comparator signal (Cm) and the output signal (CA1) of the first comparator (1512) for the received signal driver (1221).

2. Transmitting / receiving device (12) according to Claim 1, the masking block (155) comprising a timer (1551) connected to an output of the second comparator (1522) and configured to output the masked comparator signal (Cm), and a logic circuit (1552) configured to generate a signal (C1) for output to the received signal driver (1221) from the output signal (CA1) of the first comparator (1512) and the masked comparator signal (Cm).

3. Transmitting / receiving device (12) according to Claim 2, the logic circuit (1552) being an AND gate to serially calculate a logic AND function for the output signal (CA1) of the first comparator (1512) and the masked comparator signal (Cm).

4. Transmitting / receiving device (12) according to one of the preceding claims, additionally having a driver (1221) for driving a digital received signal (RxD) to a communication control device (11) of a subscriber station (10; 30) of the bus system (1), and a received signal logic circuit (1222) for forwarding an output signal (C_1) from a first comparator line (151) comprising the first comparator (1512) and an output signal (C_2) from a second comparator line (152) comprising the second comparator (1522) to the driver (1221) when communication takes place in the first communication phase (451), and for forwarding only the output signal (C_1) from the first comparator line (151) to the driver (1221) when communication takes place in the second communication phase (451).

5. Transmitting / receiving device (12) according to one of the preceding claims, additionally having a first voltage divider (1531), which is connected to the bus (40) and which outputs the differential signals (CAN_H, CAN_L) received from the bus (40) to the first comparator (1512), a second voltage divider (1532), which is connected to the bus (40) and which outputs the differential signals (CAN_H, CAN_L) received from the bus (40) to the second comparator (1522).

6. Transmitting / receiving device (12) according to Claim 5, the first and second voltage dividers (1531, 1532) comprising a circuit of resistors, to which the first and second comparators (1512, 1522) are connected, and the first and second comparators (1512, 1522) evaluating the differential signals (CAN_H, CAN_L) simultaneously.

7. Transmitting / receiving device (12) according to Claim 5 or 6, the first voltage divider (1531) comprising a switch (Sw1) designed to set the first reception threshold (T1) for the first voltage divider (1532) in a first switching position and to set the third reception threshold (T3) for the first voltage divider (1532) in a second switching position, and the second voltage divider (1532) being configured to set the second reception threshold (T2).

8. Transmitting / receiving device (12) according to Claim 7, the switch (Sw1) being designed to connect or disconnect a resistor to / from earth.

9. Transmitting / receiving device (12) according to Claim 7 or 8, the switch (Sw1) being an NMOS transistor.

10. Transmitting / receiving device (12) according to one of Claims 7 to 9, the transmitting / receiving device (12) being configured to output the output signal (CA2) of the second comparator (1522) to the received signal driver (1221) when the switch (Sw1) in its first switching position has set the first reception threshold (T1) in the first voltage divider (1532), and the transmitting / receiving device (12) being configured not to output the output signal (CA2) of the second comparator (1522) to the received signal driver (1221) when the switch (Sw1) in its second switching position has set the third reception threshold (T3) in the first voltage divider (1532).

11. Transmitting / receiving device (12) according to one of Claims 7 to 10, additionally having an operating mode setting unit (1533) for controlling the switch (Sw1) to switch the first voltage divider (1531) between the first and third reception thresholds (T1, T3) on the basis of whether the first or second communication phase (451, 452) takes place on the bus (40).

12. Transmitting / receiving device (12; 22; 120) according to one of the preceding claims, additionally having a transmitting module (121) for transmitting signals to a bus (40) of the bus system (1).

13. Subscriber station (10; 20; 30) for a serial bus system (1), having a transmitting / receiving device (12; 22) according to one of the preceding claims, and a communication control device (11; 21) for controlling communication in the bus system (1) and for generating a digital transmission signal (TxD) for the transmitting module (121).

14. Subscriber station (10; 20; 30) according to Claim 11, the subscriber station (10; 20; 30) being configured for communication in a bus system (1), in which exclusive, collision-free access by a subscriber station (10, 20, 30) to the bus (40) of the bus system (1) is at least temporarily guaranteed.

15. Method for receiving differential signals in a serial bus system (1), wherein differential signals (CAN_H, CAN_L) on a bus (40) of the bus system (1) are generated using a first physical layer (451_P) in a first communication phase (451) of communication on the bus (40) and are generated using a second physical layer (452_P) in a second communication phase (452) of communication on the bus (40), the method comprising the steps of using a transmitting / receiving device (12) to receive differential signals (CAN_H, CAN_L) from the bus (40), using a first comparator (1512) to evaluate the differential signals (CAN_H, CAN_L) received from the bus (40) using a first reception threshold (T1) in the first communication phase (451), using the first comparator (1512) to evaluate the differential signals (CAN_H, CAN_L) received from the bus (40) using a third reception threshold (T3) in the second communication phase (452), the first comparator (1512) outputting a digital received signal (RxD) to a communication control device (11) of the subscriber station (10; 30) in order to output an output signal (CA1) in the first and second communication phases (451, 452), and using a second comparator (1522) to evaluate the differential signals (CAN_H, CAN_L) received from the bus (40) using a second reception threshold (T2) in the first communication phase (451) for the received signal driver (1221), and using a masking block (155) to generate a masked comparator signal (Cm), which is a temporarily masked output signal (CA2) of the second comparator (1522), and using the masking block (155) to generate an output signal (C1) from the masked comparator signal (Cm) and the output signal (CA1) of the first comparator (1512) for the received signal driver (1221).