GEL CODEWORD STRUCTURE CODING AND DECODING METHOD, DEVICE AND ASSOCIATED EQUIPMENT

Description

TECHNICAL FIELD

[0001] This application relates to the field of communication coding, and in particular, to a generalized error-locating (GEL) codeword structure encoding and decoding method, an apparatus, and a related device.BACKGROUND

[0002] With the robust growth of data center construction, corresponding data traffic increases rapidly. This has a positive effect on a communications network, especially on an optical network market, and injects new lives into an optical network device market. With the continuous growth of the data center construction, data center interconnect becomes a fastest-growing application in optical network devices, but new requirements are also imposed on the data center interconnect. Emerging requirements on metropolitan hyperscale data center interconnect include smaller sizes and lower power consumption in terms of cost-per-bit.

[0003] In an existing GEL codeword structure, a row code A and a column code B are defined in GF (q A ) and GF (q B ), where GF is short for Galois Field, and is also referred to as a finite field, GF (q A ) represents a finite field including q A elements, and GF (q B ) represents a finite field including q B elements. The row code A and the column code B meet the following constraint: q A = 2 l 1 , q B = 2 l 2 , l 1 l 2 , where l 1 and l 2 are both integers, l 1 and l 2 represent bit widths represented by using binary forms of elements in GF (2 l1< ) and GF (2 l2< ) respectively, and l 1 can be exactly divided by l 2 . Because a syndrome required by the code B for performing decoding is an error value of the code A, a bit width of the error value of the code A needs to be an integer multiple of a bit width of the syndrome of the code B. In the existing GEL codeword structure, an exact division constraint is required in a GFat which a row code and a column code are located. Consequently, codeword construction is inflexible, complexity of implementation is high, and codeword overheads are relatively high.

[0004] Igor Zhilin ET AL: "Generalized Error Locating Codes with Soft Decoding of Inner Codes", Proceedings of 21st European Wireless Conference, European Wireless 2015, 20 May 2015 (2015-05-20), pages 178-182, XP055542620, proposes to consider a generalized error-locating code (GEL-code) as a possible candidate for data transmission systems that require high code, rates along with strict requirements on wrong decoding probabiiity. The paper describes the Construction of the GEL-code and the algorithms for encoding and decoding.

[0005] GRIESSER H ET AL: "On the decoding of generalized error-locating codes", ITG-FACHBERICHTE; ISSN 0932-6022; VOL. 183, VDE-VERLAG, DE, vol. 159, 1 January 2000 (2000-01-01), TECHNICAL FIELDS pages 209-214, XP009191138, considers a class of codes, called error-locating codes, that is especially suited for high rate applications on good channels which can reduce the bit error rate. Hard-decision multi-stage decoding for this type of code is investigated and compared with a known decoding algorithm for generalized concatenated codes.

[0006] I. Y. Zhilin et al: "Generalized Error-Locating Codes and Minimization of Redundancy for Specified Input and Output Error Probabilities" JOURNAL OF COMMUNICATIONS TECHNOLOGY AND ELECTRONICS, NAUKA / INTERPERIODICA PUBLISHING, MOSCOW, RU, vol. 60, no. 6, 12 July 2015 (2015-07-12), pages 695-706, XP035511800, discloses generalized error-locating codes. An algorithm for calculation of the upper bound of the probability of erroneous decoding for known code parameters and the input error probability is given. Based on this algorithm, an algorithm for selection of the code parameters for a specified design and input and output error probabilities is constructed. The lower bound of the probability of erroneous decoding is given. Examples of the dependence of the probability of erroneous decoding on the input error probability are given and the behavior of the obtained curves is explained.

[0007] Johannes Mancher et al.: "On the Equivalence of Generalized Concatenated Codes and Generalized Error Location Codes", IEEE TRANSACTIONS ON INFORMATION THEORY, IEEE PRESS, USA, vol. 46, no. 2, 1 March 2000 (2000-03-01), XP011027591, ISSN: 0018-9448, discloses that the generator matrix of a generalized concatenated code (GCC code) of order L consists of L submatrices, where the lth submatrix is the Kronecker product of the generator matrices of the lth inner code and the lth outer code. In a similar way it is showed that the parity-check matrix of a generalized error-location code (GEL code) of order L consists of L submatrices, where the lth submatrix is the Kronecker product of the parity-check matrices of the lth inner code and the lth outer code. Then these defining matrices are used to show that for any GCC code there exists an equivalent GEL code and vice versa.

[0008] A. Fahmer et al.: "On GEL Codes for Partial Response Channels", Department of Telecommunications and Applied Information Theory, University of Ulm, investigates the performance of a class of concatenated error correcting block codes, called generalized error-locating codes, over partial response channels as they are found in digital magnetic storage systems. Generalized error- locating codes are suited for high-rate high-speed applications due to the lowcomplexity hard input decoding algorithm. The code and the decoding algorithm is constructed according to the error structure of the channel to spend the redundancy in an advantageous way. Simulation results for the (precoded) partial response channel 1 - D 2< (PR4) compare results for different sector lengths. It is also explained how a modulation constraint can be included in the system.

[0009] Igor Zhilin et al.: "High-Rate Codes for High-Reliability Data Transmission" Inst, for Information Transmission Problems Russian Academy of Science Moscow, Russia discloses to consider that a generalized error-locating code (GEL-code) as a possible candidate for data transmission systems that require high code rates along with strict requirements on wrong decoding probability. GEL codes are one of a few that allow analytical computation of code error probability bounds and have practical construction method. The paper describes the construction of the GEL-code and the algorithms for encoding and decoding. It represents the upper and lower bounds on wrong decoding probability. It gives a method for constructing such GEL code (with the minimal redundancy) that guarantees that the probability of wrong decoding will be less than required one (for a given channel error probability). Numerical results for the upper and lower bounds for the various GEL-codes and the analysis of the energy gain for the different signal-code structures are given.SUMMARY

[0010] Embodiments of the present invention are defined by the appended claims. A GEL codeword structure encoding method according to independent claim 1, a sending device according to independent claim 2, a computer program product according to independent claim 3, and a computer-readable storage medium according to independent claim 4 are provided, so as to reduce complexity of decoding, and reduce codeword overheads.

[0011] In a GEL codeword structure, in a decoding process, decoding is started from the first layer, and decoding from a second layer to a last layer is performed sequentially. Each layer needs to obtain prior information from an upper layer during decoding, and then decoding is performed according to the prior information. However, the first layer cannot obtain prior information. Therefore, decoding can be performed only according to check codes of a row code and a column code. Because of a capability of decoding the check codes of the row code and the column code, decoding at the first layer may fail. However, in this embodiment of this application, when GEL coding is performed, the SPC parity bit is added, where the SPC parity bit is used to check the error location in the codes A (that is, row codes) at the first layer during decoding. In this way, the SPC parity bit can be used as prior information of a code A in a first row, so that the code A in the first row can be decoded according to the SPC, and a success rate of decoding the code A in the first row is improved, thereby improving efficiency of an entire decoding process. In addition, in this embodiment of this application, the code A is defined in the finite field GF (2 l1< ), the code B is defined in the finite field GF (2 l2< ), and l 1 and l 2 , are positive integers. In this way, an exact division constraint does not exist between l 1 and l 2 . Therefore, in a GEL codeword structure design process, l 2 may be reduced as much as possible, that is, a bit width of a code B symbol is reduced, and complexity of decoding the code B is reduced, so that codeword overheads are reduced, and performance of the GEL code is effectively improved. This meets requirements of the system for low power consumption of products, and also improves performance of a communications transmission system.BRIEF DESCRIPTION OF DRAWINGS

[0012] FIG. 1 is a schematic diagram of a sending device according to an embodiment of this application; FIG. 2 is a schematic diagram of a GEL codeword structure encoding method according to an embodiment of this application; FIG. 3 is a schematic diagram of a GEL codeword structure according to an embodiment of this application; FIG. 4 is a schematic diagram of a GEL codeword structure encoding procedure according to an embodiment of this application; FIG. 5 is another schematic diagram of a GEL codeword structure encoding method according to an embodiment of this application; FIG. 6 is a schematic diagram of a receiving device according to an embodiment of this application; FIG. 7 is a schematic diagram of a GEL codeword structure decoding method according to an embodiment of this application; FIG. 8 is a schematic diagram of a GEL codeword structure decoding procedure according to an embodiment of this application; FIG. 9 is another schematic diagram of a sending device according to an embodiment of this application; and FIG. 10 is another schematic diagram of a receiving device according to an embodiment of this application. DESCRIPTION OF EMBODIMENTS

[0013] Embodiments of this application provide a GEL codeword structure encoding and decoding method, an apparatus, and a related device, so as to reduce complexity of implementation, improve performance of a GEL code, and improve decoding efficiency.

[0014] Forward error correction (Forward Error Correction), is a method for improving reliability of data communication, and has a function of correcting data. In a unidirectional communication channel, once an error is found, a receiving device no longer has a permission to request transmission. Therefore, when an error occurs during transmission, the receiving device can correct erroneous data by using FEC. In FEC, a GEL codeword structure is a commonly used encoding structure and decoding structure. The GEL codeword structure includes a row code and a column code, and a check code of a GEL code is obtained by performing an encoding operation on a parity bit of the column code by using the row code, thereby completing encoding of data. Before sending data, a sending device encodes data by using the GEL codeword structure. After receiving data, the receiving device decodes the data by using the GEL codeword structure, and corrects erroneous data. Before data is exchanged between the sending device and the receiving device, the sending device and the receiving device first agree on a GEL codeword structure encoding manner, or before receiving data sent by the sending device, the receiving device first obtains a GEL codeword structure encoding manner of the sending device.

[0015] FIG. 1 is a sending device 100 provided in an embodiment of this application. The sending device 100 includes a memory 101, a processor 102, and a transceiver 103. The memory 101, the processor 102, and the transceiver 103 are interconnected by using a bus 104, and the sending device 100 may further include a communications interface 105.

[0016] The processor 102, the memory 101, the transceiver 103, and the communications interface 105 may implement mutual communication connections by using the bus 104, or may implement communication by using other means such as wireless transmission.

[0017] The memory 101 may include a volatile memory (English: volatile memory), for example, a random access memory (RAM); or the memory may include a nonvolatile memory, for example, a read-only memory ROM), a flash memory, a hard disk (HDD), or a solid-state drive (SSD); or the memory 101 may include a combination of the memories of the foregoing types. When the technical solution provided in this application is implemented by using software, steps that need to be executed in the GEL codeword structure encoding method provided in FIG. 2 of this application are implemented. A computer instruction is stored in the memory 101 and is executed by the processor 102, and receiving and sending functions of the sending device 100 are implemented by the processor 102 by invoking the computer instruction in the memory 101 to control the transceiver 103.

[0018] This application further provides a GEL codeword structure encoding method. In FIG. 1, the sending device 100 executes the method during running. The method is applied to a sending device, and a schematic flowchart of the method is shown in FIG. 2.

[0019] 201. Obtain a target check matrix H B< by performing elementary transformation on an original check matrix H C of a code B.

[0020] In this embodiment of this application, the code B is a column code. First, elementary transformation needs to be performed on the original check matrix H C of the code B to obtain the target check matrix H B< , so as to subsequently obtain parity bits of codes B according to layers. A matrix expression of the H C is: … … … … … 1 α 5 α 10 … α 5 n B − 1 1 α 3 α 6 … α 3 n B − 1 1 α α 2 … α n B − 1 n B × n B , where α is a primitive element in a GF (2 l2< ) field.

[0021] A matrix expression of the H B< is: H B< =G×H C , where G is a row-elementary transformation matrix of n B ×n B .

[0022] 202. Obtain a parity bit of the code B by performing a first operation on the target check matrix H B< and an information bit of the code B.

[0023] A formula for the first operation is: H l B × R j , j ∈ 1 , … , k A l , where H l B represents an encoding matrix that is of a code B and that is at an l th< layer of a GEL codeword structure, R j represents an information bit of the code B, and K A 1< represents an information bit that is of a code A and that is at the l th< layer.

[0024] 203. Use the parity bit of the code B as an information bit of a code A to perform Reed-Solomon RS coding on the code A.

[0025] In the GEL codeword structure, the code A (which is a row code in this embodiment of this application) and the code B (a column code) are alternately encoded and alternately decoded. Therefore, the parity bit of the code B that is obtained through calculation is used as the information bit of the code A to perform RS coding on the code A.

[0026] A formula for RS coding is: r x = k x mod g x , r x = r 0 x 0 + ⋯ + r n A − k A − 1 x n A − k A − 1 , where r (x) represents a parity bit of the code A, k (x) represents the information bit of the code A, and g (x) represents a generator polynomial of RS coding.

[0027] 204. Obtain a check code of a GEL code by performing a second operation on the parity bit of the code B and a result obtained after RS coding is performed on the code A.

[0028] A formula for the second operation is: Parity l = r 0 + H l B × R k A − 1 , ⋯ , r n A − k A − 1 + H l B × R k A − 1 , where Parity l represents a check code that is of a GEL code and that is at the l th< layer.

[0029] 205. Add a Single bit Parity Check (SPC) parity bit, where the SPC parity bit is used to check an error location in codes A at a first layer during decoding.

[0030] To improve efficiency of decoding a code A at the first layer, the SPC parity bit is added to the entire GEL codeword structure, and is used by a receiving device to first check the error location in the codes A at the first layer according to the SPC parity bit in a decoding process.

[0031] It should be noted that the code A is defined in a finite field GF (2 l1< ), the code B is defined in a finite field GF (2 l2< ), and l 1 and l 2 , are positive integers. In this way, an exact division constraint does not exist between l 1 and l 2 , and values of l 1 and l 2 may be approximate or equal, so that a finite field of the code A and a finite field of the code B may be approximate or equal, thereby reducing complexity of implementation, and effectively improving performance of the GEL code. This meets requirements of the system for low power consumption of products, and also improves performance of a communications transmission system.

[0032] Optionally, a subcode constraint of the code A and a subcode constraint of the code B include: n A k A i d A i q A and n B k B i d B i q B r A i = n A − k A i and r B i = n B − k B i d A 1 ≥ d A 2 ≥ ⋯ ≥ d A m d B 1 ≤ d B 2 ≤ ⋯ ≤ d B m B 1 ⊂ B 2 ⊂ ⋯ ⊂ B m , where n A represents a code length of a code A, n B represents a code length of a code B, k Ai represents an information bit of a code A in an i th< row, k Bi represents an information bit of a code B in the i th< row, d Ai represents a minimum code distance between codes A in the i th< row, r Ai represents a length of a parity bit of a code A in the i th< row, and r Bi represents a length of a parity bit of a code B in the i th< row. An information bit of a code A and an information bit of a code B at each layer are designed in advance, and a minimum code distance between codes A and a minimum code distance between codes B at each layer are also designed in advance. In addition, a minimum code distance between codes A at the first layer is greater than or equal to a minimum code distance between codes A at a second layer, the minimum code distance between the codes A at the second layer is greater than or equal to a minimum code distance between codes A at a third layer, and so on. A minimum code distance between codes B at the first layer is less than or equal to a minimum code distance between codes B at the second layer, the minimum code distance between the codes B at the second layer is less than or equal to a minimum code distance between codes B at the third layer, and so on. As a result, after entire GEL coding is completed, check capabilities of all layers in the GEL codeword structure are equivalent. There is a subordinate relationship between all layers of codes B. The first layer belongs to the second layer, the second layer belongs to the third layer, and so on.

[0033] FIG. 3 shows a GEL codeword structure obtained by using a GEL codeword structure encoding method described in an embodiment of this application. FIG. 3 is a 4-layer GEL codeword structure. The GEL codeword structure encoding method described in this embodiment of this application is not limited to being used in the 4-layer GEL codeword structure, and is applicable to a GEL codeword structure with two or more layers. Each row represents a code A, each column represents a code B, the code B is in a matrix form, the code A includes an information bit and a parity bit, a parity bit obtained by performing an operation on the code B is used as an information bit of the code A, a parity bit that is of the code A and that is obtained by performing RS coding by using the information bit of the code A is added to a parity bit that is of the code B and that is obtained through calculation, to obtain a check code of GEL.

[0034] As shown in FIG. 4, in an embodiment of this application, an encoding sequence in a GEL codeword structure encoding method is that encoding is started from a last layer, until an SPC parity bit is added. As shown in FIG. 4, a 3-layer GEL codeword structure is encoded. A third layer is first encoded, a second layer is then encoded, and finally a first layer is encoded. An encoding sequence of each layer is to first calculate a parity bit of a code B at a current layer, then check a check code of the code B, and finally encode a code A at the current layer.

[0035] FIG. 5 is a schematic diagram of both a procedure of the GEL codeword structure encoding method in FIG. 2 and the GEL codeword structure shown in FIG. 3. I represents an information bit, P represents a parity bit, I11 and I12 represent locations of information bits at the third layer, I21 represents a location of an information bit at the second layer, P21 represents a location of a parity bit at the second layer, and so on. k(x) represents an information bit of a code A, r (x) represents a parity bit of the code A, and a parity bit of a code B is obtained by using H B< ×R described in the foregoing step 202.

[0036] FIG. 6 is a receiving device 600 provided in an embodiment of this application. The receiving device 600 includes a memory 601, a processor 602, and a transceiver 603. The memory 601, the processor 602, and the transceiver 603 are interconnected by using a bus 604, and the receiving device 600 may further include a communications interface 605.

[0037] The processor 602, the memory 601, the transceiver 603, and the communications interface 605 may implement mutual communication connections by using the bus 604, or may implement communication by using other means such as wireless transmission.

[0038] The memory 601 may include a volatile memory, for example, a random access memory; or the memory may include a nonvolatile memory, for example, a read-only memory, a flash memory, a hard disk, or a solid-state drive; or the memory 601 may include a combination of the memories of the foregoing types. When the technical solution provided in this application is implemented by using software, steps that need to be executed in the GEL codeword structure decoding method provided in FIG. 7 of this application are implemented. A computer instruction is stored in the memory 601 and is executed by the processor 602, and receiving and sending functions of the receiving device 600 are implemented by the processor 602 by invoking the computer instruction in the memory 601 to control the transceiver 603.

[0039] This application further provides a GEL codeword structure decoding method. In FIG. 6, the receiving device 600 executes the method during running. The method is applied to a receiving device, and a schematic flowchart of the method is shown in FIG. 7.

[0040] 701. Determine prior information of a code A at each layer, where the prior information of the code A at each layer is a location of an error occurring when a code B is decoded at an upper layer, prior information of a code A at a first layer is an SPC parity bit, and the SPC parity bit is a parity bit added when a sending device performs GEL coding.

[0041] In a GEL codeword structure of this application, when the sending device encodes data, the SPC parity bit is added to the GEL codeword structure, where the SPC parity bit is used as the prior information of the code A at the first layer during decoding. In a decoding process, decoding and error correction are started and performed at the first layer, and decoding and error correction are performed at all layers sequentially until decoding and error correction at a last layer are completed. Prior information needs to be obtained during decoding of each layer. The prior information is generally a location of an error occurring when a code B is decoded at an upper layer. However, there is no upper layer for the code A at the first layer. Therefore, in this embodiment of this application, the SPC parity bit is added to the GEL codeword structure during encoding, so that the SCP parity bit is used as the prior information of the code A at the first layer during decoding.

[0042] 702. Recover the code A at each layer by using a check matrix H B< that is of the code B and that is the same as that of the sending device.

[0043] 703. Decode the recovered code A at each layer, to obtain an erroneous column and a syndrome of the code B.

[0044] After the code A at each layer is recovered according to the check matrix H B< , the code A with the prior information is decoded, and an error value obtained by decoding the code A is the syndrome of the code B. Finally, an original syndrome of the code B is obtained through calculation by using the syndrome of the code B and a transformation matrix G. A function of the original syndrome of the code B is to provide corresponding error status information for decoding of the code B. The original syndrome is used for the code B to calculate an error location. A relationship among the original check matrix H c of the code B, the target check matrix H B< , and the transformation matrix G is H C =G×H B< .

[0045] 704. Decode the erroneous code B by using the syndrome of the code B, and correct the erroneous code B.

[0046] The code A is a row code, the code B is a column code, the code A is defined in a finite field GF (2 l1< ), the code B is defined in a finite field GF (2 l2< ), and l 1 and l 2 , are positive integers.

[0047] Optionally, when an error occurs when a code B is decoded at an upper layer, in a process of decoding a code B at a current layer, rollback is first performed to correct the code B at the upper layer, and then the code B at the current layer is decoded.

[0048] For example, a decoding process is specifically described below.

[0049] FIG. 8 is a schematic diagram of decoding by using an example in which a GEL codeword structure is a 3-layer codeword structure, and a specific decoding manner is as follows: A decoding process at a first layer is as follows: Step 1: Calculate an SPC parity bit (used as prior information of a code A) and recover a code A at the first layer. Step 2: Decode the code A at the first layer, so as to obtain a location (a column location) of an erroneous code B and a corresponding syndrome of the code B at the first layer. Step 3: Decode the erroneous code B by using the syndrome of the code B at the first layer, and correct the erroneous code B.

[0050] A decoding process at a second layer is as follows: Step 1: Collect a decoding error location (used as prior information of a code A at the second layer) in codes B at the first layer, and recover the code A at the second layer. Step 2: Decode the code A at the second layer, so as to obtain a location of an erroneous code B and a corresponding syndrome of the code B at the second layer. Step 3: When an error occurs when a code B at the first layer is decoded, first roll back to correct the code B at the first layer, then decode the erroneous code B by using the syndrome of the code B at the second layer, and correct the erroneous code B. ...

[0051] A decoding process at an m th< layer is as follows: Step 1: Collect a decoding error location (used as prior information of a code A at the m th< layer) of a code Bm-1 (i.e., in codes B at the (m-1) th< layer), and recover the code A at the m th< layer. Step 2: Decode the code A at the m th< layer, so as to obtain a location of an erroneous code B and a corresponding syndrome of the code B at the m th< layer. Step 3: When an error occurs when a code B at the (m-1) th< layer is decoded, first roll back to correct the code B at the (m-1) th< layer, then decode the erroneous code B by using the syndrome of the code B at the m th< layer, and correct the erroneous code B.

[0052] After GEL decoding at all layers is completed, the entire decoding process ends.

[0053] This application further provides a sending device 900, and the device may be implemented by using the sending device 100 shown in FIG. 1, or may be implemented by using an applicationspecific integrated circuit (ASIC) or a programmable logic device (PLD). The PLD may be a complex programmable logic device, CPLD), a field programmable gate array (FPGA), generic array logic (GAL), or any combination thereof. The sending device 900 is configured to implement the method executed by the sending device shown in FIG. 2. When the method executed by the sending device shown in FIG. 2 is implemented by using software, the sending device 900 may be alternatively a software module.

[0054] FIG. 9 is a schematic structural composition diagram of the sending device 900, and the sending device 900 includes a transformation unit 901, an operation unit 902, an encoding unit 903, and an adding unit 904. During working, the method executed by the sending device in the GEL codeword structure encoding method shown in FIG. 2 is executed.

[0055] This application further provides a receiving device 1000, and the device may be implemented by using the receiving device 600 shown in FIG. 6, or may be implemented by using an ASIC or a PLD. The PLD may be a CPLD, an FPGA, GAL, or any combination thereof. The receiving device 1000 is configured to implement the method executed by the receiving device shown in FIG. 7. When the method executed by the receiving device shown in FIG. 2 is implemented by using software, the receiving device 1000 may be alternatively a software module.

[0056] FIG. 10 is a schematic structural composition diagram of the receiving device 1000, and the receiving device 1000 includes a determining unit 1001, a recovery unit 1002, a decoding unit 1003, a correction unit 1004, and a rollback unit 1005. During working, the method executed by the receiving device in the GEL codeword structure decoding method shown in FIG. 7 is executed. An embodiment of this application further provides a computer storage medium. The computer storage medium may store a program. When being executed, the program includes all or some of the steps of the GEL codeword structure encoding and decoding method described in the foregoing method embodiments.

[0057] It may be clearly understood by persons skilled in the art that, for ease and brevity of description, for a detailed working process of the foregoing system, apparatus, and unit, refer to a corresponding process in the foregoing method embodiments, and details are not described herein again.

[0058] In the several embodiments provided in this application, it should be understood that the disclosed system, apparatus, and method may be implemented in other manners. For example, the described apparatus embodiment is merely an example. For example, the unit division is merely logical function division and may be other division in actual implementation. For example, a plurality of units or components may be combined or integrated into another system, or some features may be ignored or not performed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections may be implemented by using some interfaces. The indirect couplings or communication connections between the apparatuses or units may be implemented in electronic, mechanical, or other forms.

[0059] The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one position, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual requirements to achieve the objectives of the solutions of the embodiments.

[0060] In addition, functional units in the embodiments of this application may be integrated into one processing unit, or each of the units may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in a form of hardware, or may be implemented in a form of a software functional unit.

[0061] When the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, the integrated unit may be stored in a computer-readable storage medium. Based on such an understanding, the technical solutions of this application essentially, or the part contributing to the prior art, or all or some of the technical solutions may be implemented in the form of a software product. The software product is stored in a storage medium and includes several instructions for instructing a computer device (which may be a personal computer, a server, or a network device) to perform all or some of the steps of the methods described in the embodiments of this application. The foregoing storage medium includes: any medium that can store program code, such as a USB flash drive, a removable hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disc.

[0062] The foregoing embodiments are merely intended for describing the technical solutions of this application, but not for limiting this application.

Claims

1. A computer-implemented generalized error-locating, GEL, codeword structure encoding method, wherein the GEL codeword structure comprises a row code A with code length nA and a column code B with code length nB, the code A is defined in a finite field GF (2l1), the code B is defined in a finite field GF (2l2), and l1 and l2 are equal positive integers, wherein the method comprises: obtaining a target check matrix HB by performing an elementary transformation on an original check matrix HC of the code B, wherein the original check matrix HC is a nB×nB matrix and a relationship between the original check matrix HC of the code B and the target check matrix HB is HB = G×HC, wherein G is a nB×nB elementary row transformation matrix; performing a first operation on the target check matrix HB and an information bit of the code B, wherein a formula for performing the first operation on the target check matrix HB and the information bit of the code B comprises: H l B × R j , j ∈ 1 , … , k A l , wherein H 1 B represents a target check matrix HB of the code B at an lth layer of the GEL codeword structure, Rj represents information bits of a jth column of the code B, and kA1 represents a number of information bits of the code A at the lth layer; using the result of the first operation as information bits of the code A to perform Reed-Solomon, RS, coding on the information bits of code A, wherein a formula for performing the RS coding comprises: r x = k x mod g x and r x = r 0 x 0 + ⋯ + r n A − k A − 1 x n A − k A − 1 , wherein r (x) represents parity bits of the code A, k (x) represents information bits of the code A, and g (x) represents a generator polynomial of the RS coding; obtaining a check code of the GEL code by performing a second operation on the result of the first operation and the result of the RS coding, wherein a formula for performing the second operation comprises: Parity l = r 0 + H l B × R k A − 1 , ⋯ , r n A − k A − 1 + H l B × R k A − 1 , wherein Parityl represents a check code of the GEL code at the lth layer; and adding nA single parity check, SPC, parity bits, wherein the SPC parity bits are used to check an error location in code A at the first layer during decoding.

2. A sending device, wherein the sending device is configured to implement the method according to claim 1.

3. A computer program product comprising instructions which, when executed on a sending device, cause the sending device to implement the method according to claim 1.

4. A computer-readable storage medium comprising instructions which, when executed on a sending device, cause the sending device to implement the method according to claim 1.