METHOD FOR PRODUCING A RESISTIVE STORAGE

Description

TECHNICAL FIELD

[0001] The present invention relates to the field of resistive random access memories (RRAM). The invention relates more particularly to a method of manufacturing a resistive memory. STATE OF THE ART

[0002] Resistive memories, particularly Oxide-based Random Access Memories (OxRAM), are non-volatile memories designed to replace Flash memories. In addition to high integration density, they offer high operating speed, high endurance, and good compatibility with current manufacturing processes in the microelectronics industry, particularly the Back-End Of Line (BEOL) process of CMOS technology.

[0003] OxRAM resistive memories comprise a multitude of memory cells, also called memory points. Each OxRAM memory cell consists of a MIM (Metal-Insulator-Metal) capacitor comprising an active material of variable electrical resistance, generally a transition metal oxide, arranged between two metal electrodes. The oxide switches reversibly between two resistance states, which correspond to the logic values ​​"0" and "1" used to encode a bit of information. In some cases, more than two resistance states can be generated, which makes it possible to store several bits of information in a single memory cell.

[0004] Information is written to the memory cell by switching the oxide from a high resistance state (HRS), also called the OFF state, to a low resistance state (LRS), or ON state. Conversely, to erase information from the memory cell, the oxide is switched from the LRS to the HRS state. The write operation for an OxRAM resistive memory cell is called a SET operation, while the erase operation is called a RESET operation.

[0005] The change in oxide resistance is governed by the formation and rupture of a nanometer-sized conductive filament between the two electrodes. According to current knowledge, this filament appears to be due to the accumulation of oxygen vacancies (at least for the family of transition metal oxides), which may be accompanied by the movement of metal ions.

[0006] A disadvantage of resistive OxRAM memories is the high variability of the electrical resistance of a memory cell in the "OFF" state during write and erase cycles. For example, the resistance in the "OFF" state between several successive erase operations can vary by more than an order of magnitude. Although less marked, the phenomenon is also observable for the "ON" state. This variability is observed not only over endurance cycles on the same cell, but also from cell to cell.

[0007] This problem of variability of the electrical resistance is today a real obstacle to industrialization, because it induces a reduction of the programming window (difference in resistance between the “HRS” / “OFF” and “LRS” / “ON” states) and consequently a risk of losing the information stored in the memory cell. This concern remains despite numerous efforts made in the fields of manufacturing and programming of OxRAM resistive memories.

[0008] There Figure 1A schematically represents an OxRAM memory cell 10 according to the prior art. This cell 10 comprises a metal oxide layer 100 disposed between a first electrode 110 and a second electrode 120. A continuous conductive filament 130 between the electrodes 110-120 is formed through the oxide layer 100 when the memory cell is written.

[0009] According to several studies, one solution to reduce the variability of electrical performance would be to reduce the dimensions of the memory cell. In particular, the paper [“Conductive Filament Control in Highly Scalable Unipolar Resistive Switching Devices for Low-Power and High-density Next Generation Memory”, Ryoo Kyung-Chang et al., IEDM 2013] showed that a reduction in the contact area between one of the electrodes 110-120 and the oxide layer 100 made it possible to localize the formation (and breakage) of the conductive filament 130 and to reduce cell dispersion problems.

[0010] There Figure 1Bshows the OxRAM 10' memory cell proposed by Ryoo et al. in the aforementioned article. An electrically insulating pad 140 occupies a central portion of the oxide layer 100 in contact with the second electrode 120, which has the effect of limiting the contact surface between the second electrode 120 and the oxide layer 100 to an area 150 located at the periphery of the insulating pad 140. With such a cell configuration, it appears that the conductive filament 130 is directed towards the peripheral area 150, and consequently confined to one edge of the cell.

[0011] The manufacturing process for this 10' memory cell is, however, complex to implement. Indeed, it uses numerous lithography, deposition and planarization steps. Generally speaking, to reduce the contact surface, advanced lithography techniques, such as electron beam lithography (e-beam), are necessary. However, these techniques are cumbersome and expensive to implement. Furthermore, the electrical contact recovery of the second electrode 120, which is small in size, is difficult to obtain. The constraints for the industrialization of such a manufacturing process are therefore numerous.

[0012] US8872268 (Miller et al.) describes another technique for localizing the formation of the conductive filament in the metal oxide layer 100 of an OxRAM memory cell. A mask 200 comprising several recesses 210 is formed on the oxide layer 100, in order to delimit in the oxide layer protected areas and exposed areas. Then, the metal oxide layer 100 covered with the mask 200 is subjected to ion implantation 220. The ions are implanted only in the exposed areas of the oxide layer 100, thus forming several localized defect paths 230 in these same areas. The defects can be metal or oxygen atoms in an interstitial position, metal atoms in a substitutional position or oxygen vacancies. During subsequent operation of the memory cell, the conductive filament follows one of the localized defect paths formed in the oxide layer 100.

[0013] By thus realizing preferential conduction paths for the conductive filament, the resistance changes caused during SET and RESET operations can be achieved with lower voltages. Such localization of the conductive filament also has the effect of increasing the ratio of currents between the "ON" state and the "OFF" state.

[0014] The formation of the mask 200, the ion implantation 220 and the removal of the mask 200 before the deposition of the upper electrode, however, constitute additional steps compared to the conventional process for manufacturing OxRAM memories. Furthermore, to confine the filament in a restricted area, the mask 200 must have good resolution characteristics, which again requires the use of advanced lithography techniques. The solution proposed by patent US8872268 therefore does not make it possible to improve the performance of the cell at a lower cost.

[0015] Furthermore, document US2015 / 041750 describes a resistive memory device in which each memory cell is capable of storing several bits of information. The manufacturing method of this resistive memory device comprises: the formation of lower electrodes on a substrate; the deposition of a layer of active material on the lower electrodes and the substrate; the deposition of a layer of metal on the layer of active material; the etching of the layer of metal and the layer of active material between the lower electrodes, so as to delimit the different memory cells; the ion implantation of a doping element in a portion of the layer of active material of the memory cells, the ion beam being inclined at an angle of between 20° and 60°. SUMMARY OF THE INVENTION

[0016] There is therefore a need to provide a simple and economical resistive memory manufacturing method making it possible to confine the formation of the conductive filament to only a portion of the active material layer of variable electrical resistance, with the aim of improving the performance of the memory.

[0017] According to the invention, this need is tended to be satisfied by providing a manufacturing method comprising the following steps: depositing a layer of an active material of variable electrical resistance on a substrate containing a first electrode, called the lower electrode; depositing an electrically conductive layer on the layer of active material; etching the electrically conductive layer so as to delimit a second electrode, called the upper electrode, opposite the lower electrode; exposing at least one flank of the upper electrode to an ion beam inclined relative to the normal to the substrate at an angle of between 20° and 65°, so as to implant the ions in a portion of the layer of active material adjacent to said flank and located under the upper electrode, the ion implantation conditions being chosen so as to create defects in the structure of the active material and to obtain an average implantation width of between 5 nm and 10 nm and the ions being implanted at a dose of between 10 13< atoms.cm -2< and 10 16< atoms.cm -2< .

[0018] Exposing the flank(s) of the upper electrode to an inclined ion beam limits the formation of defects to a portion of the active material layer located in the immediate vicinity of the exposed flank. In fact, the rest of the active material layer is protected by the upper electrode which, by shadowing effect, prevents the implantation of ions.

[0019] Unlike the prior art method, the manufacturing method according to the invention does not require any photolithography step with strict specifications in terms of dimensions to delimit the defect zone in the active material layer. Furthermore, the only additional step compared to the conventional manufacturing method for resistive memories is the ion implantation step. The manufacturing cost of a resistive memory with the method of the invention is therefore lower than with the methods of the prior art. Finally, ion implantation is a widely used and perfectly mastered technique in the microelectric industry, in particular for the doping of semiconductor materials. It therefore poses no difficulty for the implementation of the manufacturing method according to the invention on an industrial scale.

[0020] The angle of inclination relative to the normal of the implanted ion beam is, in this resistive memory manufacturing process, much greater than that usually encountered in the microelectric industry. Indeed, for doping semiconductor layers, the ion beam is generally inclined by a few degrees (usually 7°) to avoid channeling effects in crystalline materials. Here, this angle would not allow the definition of a sufficiently large defect zone for the formation of the filament.

[0021] Preferably, the ion beam is inclined relative to the normal to the substrate by an angle between 40° and 50°.

[0022] In a preferred embodiment of the method, the active material layer serves as a barrier layer during the etching of the electrically conductive layer. Thus, only the electrically conductive layer is etched and the lower electrode is protected, at least partially, from ion implantation by the active material layer.

[0023] Advantageously, the ions are implanted with an energy such that the average penetration depth of the ions is located inside the layer of active material. Advantageously, the manufacturing method further comprises a step of depositing a protective material on the electrically conductive layer before the step of etching the electrically conductive layer (to delimit the upper electrode). This protective material prevents the ion implantation from degrading the upper face of the second electrode and reducing its electrical performance.

[0024] The method according to the invention may also have one or more of the characteristics below, considered individually or in all technically possible combinations: the implanted ions are metal ions, oxygen ions, halogen ions, silicon ions or argon ions; the electrically conductive layer is etched so as to delimit at least two upper electrodes and the tilt angle α of the ion beam is chosen such that: tan α ≤ S h S being the minimum distance separating two electrodes and h being the thickness of the electrically conductive layer; and the active material is a transition metal oxide. BRIEF DESCRIPTION OF THE FIGURES

[0025] Other characteristics and advantages of the invention will emerge clearly from the description given below, for information purposes only and in no way limiting, with reference to the appended figures, among which: THE Figures 1A and 1B , previously described, represent two types of resistive OxRAM memory cell according to the prior art; the figure 2 , previously described, illustrates the ion implantation step of a method for manufacturing OxRAM memory according to the prior art; figure 3 represents in cross-section a substrate serving as a starting point for the resistive memory manufacturing method according to the invention; the Figures 4A to 4C schematically represent steps S1 to S3 of a resistive memory manufacturing method, according to a preferred embodiment of the invention; Figure 5 is a cross-sectional view of the resistive memory cell after the manufacturing process. Figures 4A to 4C ; and the figure 6 illustrates two resistive memory cells spaced a sufficient distance apart to achieve ion implantation of the Figure 4C in each of the memory cells.

[0026] For clarity, identical or similar elements are identified by identical reference signs throughout the figures. DETAILED DESCRIPTION OF AT LEAST ONE EMBODIMENT

[0027] A preferred embodiment of the resistive memory manufacturing method according to the invention is described below with reference to figures 3 , 4A to 4C and 5. The figure 3 shows a substrate 300 that can serve as a starting point for the manufacturing process. The Figures 4A to 4C represent different steps S1 to S3 of the manufacturing process. Finally, the Figure 5 illustrates the resistive memory obtained at the end of the manufacturing process of Figures 4A to 4C .

[0028] The resistive memory may comprise a multitude of identical memory cells, for example organized in rows and columns. Each memory cell comprises a first electrode called the lower electrode, a second electrode called the upper electrode and an oxide layer arranged between the first and second electrodes. The oxide layer may be common to several memory cells, like one or other of the lower and upper electrodes. For example, in a cross-point memory cell matrix, the memory cells of the same row share the same lower electrode (formed by the bit line) and the memory cells of the same column share the same electrode (formed by the word line).

[0029] The substrate 300 advantageously comprises a CMOS circuit capable of addressing each memory cell and / or reading the data recorded in the memory cell, i.e. the electrical resistance value of the cell. This circuit comprises, for example, transistors electrically connected to the memory cells by one or more interconnection levels. On the figure 3 , only the last interconnection level before the memory cells is shown in cross section. It is formed of a layer of dielectric material 301 (for example SiO 2 or SiN) crossed by interconnection patterns 302, preferably made of metal (copper, aluminum, metal alloys, etc.) or titanium nitride. These interconnection patterns 302 are, for example, conductive vias or conductive lines and make it possible to electrically connect the memory cells to the underlying CMOS circuit.

[0030] For clarity, resistive memory shown at various stages of manufacture on the figures 3 to 5 comprises only one memory cell. Therefore, the substrate 300 of the figure 3 has only one interconnection pattern 302.

[0031] In this preferred embodiment, the interconnection pattern 302 of the substrate 300 constitutes the lower electrode of the memory cell. Alternatively, a metal pad (surrounded by another dielectric layer) may be formed on the interconnection pattern 302 and constitute the lower electrode of the cell.

[0032] At step S1 of the Figure 4A, the substrate 300 is successively covered with a layer 410 of an active material of variable electrical resistance and an electrically conductive layer 420 intended to form the upper electrode of the memory cell. The variable electrical resistance material of the layer 410 is a dielectric material capable of switching from a highly resistive state (“HRS”) to a low resistive state (“LRS”).

[0033] The resistive memory manufactured can be of the OxRAM (“Oxide-based Random Access Memories”), CBRAM (“Conductive Bridge Random Access Memory”) or HRAM (“Hybrid Random Access Memory”) type, depending on the nature of the active material used and the upper electrode.

[0034] Preferably, the active material is an oxide, and more preferably a transition metal oxide, for example hafnium oxide (HfO 2 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), nickel oxide (NiO) or zinc oxide (ZnO). The memory is then of the OxRAM type. The dielectric layer 410 can also be composed of several superimposed oxide sub-layers (for example of the Al 2 O 3 / HfO 2 type).

[0035] The electrically conductive layer 420 is formed from one or more superimposed conductive materials, preferably chosen from metals (platinum, titanium, tantalum, hafnium, zirconium), titanium nitride (TiN), tantalum nitride (TaN), doped polysilicon and metal silicides. In the example shown in the figure 3 , the conductive layer 420 consists of a stack of a titanium sub-layer 421 and a titanium nitride sub-layer 422.

[0036] The thickness of the active material layer 410 is between 1 nm and 20 nm, while the thickness of the conductive layer 420 is between 5 nm and 200 nm.

[0037] Advantageously, the conductive layer 420 is covered with a protective layer 430, for example made of SiO 2 or SiN. The purpose of this protective layer 430 is to protect the upper face of the upper electrode during the subsequent ion implantation step (cf. Fig.4C ). Thus, it has sufficient thickness to absorb all of the ions which will be directed towards the upper face of the electrode.

[0038] There Figure 4Brepresents a step S2 during which the conductive layer 420 is etched to delimit the upper electrode 440 of the memory cell. The conductive layer 420 is etched in the form of a mesa whose sides are advantageously vertical. The etching technique used is preferably a highly anisotropic dry etching, such as RIE plasma etching (“Reactive ion Etching” in English).

[0039] The protective layer 430 advantageously serves as a hard mask during the etching of the conductive layer 420. The hard mask is for example formed by optical or extreme UV photolithography and etching of the protective layer 430, then the conductive layer 420 is etched through this hard mask.

[0040] In the preferred mode of implementation of the Figure 4B, the conductive layer 420 is etched while leaving the underlying oxide layer 410 intact. This can be achieved by choosing an etching chemistry that is selective with respect to the oxide used. The etching chemistry depends on the materials constituting the conductive layer 420 and the oxide layer 410. In the particular case of a conductive layer 420 made of TiN or Ti and an oxide layer 410 made of Hf0 2 , the etching chemistry used to etch the conductive layer 420 selectively with respect to the layer 410 can be Cl 2 / HBr.

[0041] The oxide layer 410 then serves as an etching stop layer. Preserving the oxide layer 410 during the etching step S2 makes it possible to protect the lower electrode 302 from the subsequent ion implantation step ( Fig.4C ).

[0042] Conversely, in an alternative implementation, the oxide layer 410 is etched at the same time as the conductive layer 420.

[0043] Finally, at step S3 of the Figure 4C , an ion implantation step is carried out so as to create a defect zone located on an edge of the memory cell, that is, on an edge of the lower electrode 302 - oxide layer 410 - upper electrode 440 stack. To do this, one of the vertical sides of the upper electrode 440 (the right side in the example of the figure) is exposed to an oblique ion beam 450. The ion beam 450 is inclined relative to the perpendicular to the substrate 300 by an angle α of between 20° and 65°.

[0044] Due to the inclination of the beam 450, the ions arriving at the foot of the flank penetrate into the oxide layer 410 and generate structural defects in this oxide layer.

[0045] The desired effect of creating this localized defect zone is the confinement of the conductive filament in this same zone, during operation of the memory cell. Indeed, as mentioned in patent US8872268, the structural defects generated by the implantation of metal ions, oxygen ions, negatively charged halogen ions (F -< , CL -< ...), silicon ions or argon ions in the oxide layer promote the formation of the conductive filament. The defects can be in particular metal, silicon or oxygen atoms in interstitial position, metal or silicon atoms in substitutional position or oxygen vacancies. In the case of metal ions, it would seem that the implanted atoms constitute a part of the conductive filament of the memory cell.

[0046] The conductive filament is first formed during the memory cell forming process. The forming of a cell involves a reversible breakdown of the oxide, meaning that the oxide changes from an insulating state to a conducting state. After this breakdown of the oxide, the electrical resistance of the active material can change from a low-resistive (LRS) (conductive) state to a high-resistive (HRS) (insulating) state, through erase and write operations. During an erase and write cycle, the conductive filament is broken and then rebuilt. However, it does not disappear completely, nor does it change area in the oxide layer between the electrodes (it is rebuilt where it was initially formed, during the forming step).

[0047] Unlike the method according to the prior art, the method of manufacturing the Figures 4A-4Cdoes not require any mask for the S3 implantation step. The entire surface of the substrate can be exposed to the 450 ion beam under oblique incidence, which greatly simplifies the manufacture of the OxRAM memory. The delimitation of the defect zone located under the upper electrode results, as described below, solely from a shadowing effect of the upper electrode.

[0048] There Figure 5 schematically represents the state of the memory cell immediately after the ion implantation step S3.

[0049] An upper part of the protective layer 430, a lateral part of the protective layer 430 and a lateral part of the upper electrode 440, on the side of exposure to the ion beam 450 (here on the right side), have been implanted (all these parts do not in fact have the same thickness, because the density of the materials varies). The protective layer 430 prevents the ions from reaching the surface of the upper electrode 440, where the contact will be made. Thus, thanks to the protective layer 430, the quality of the electrical contact made on the upper electrode is not reduced by the implantation of ions and the formation of structural defects in the upper electrode 440.

[0050] Furthermore, two distinct zones can be distinguished in the oxide layer 410: a first zone 411 implanted by the ions and a second zone 412, adjacent to the first zone 411, but devoid of ions. The second zone 412 devoid of ions is located in the shadow of the upper electrode 440 relative to the ion beam 450. Conversely, the first implanted zone 411 corresponds to the unshaded zones of the oxide layer 410. The first zone 411 of the oxide layer extends outside the upper electrode 440 (to the left and right of the electrode) and comprises a portion 413 located under the edge of the upper electrode 440.

[0051] In other words, under the upper electrode, only the portion 413 of the oxide layer 410 immediately adjacent to the exposed flank of the upper electrode 440 is implanted, while the vast majority of the oxide layer located under the upper electrode 440 is not impacted by the ion implantation.

[0052] The shape and dimensions (width and depth) of the implanted area 413 depend on the implantation parameters (nature of the ion, dose, angle and energy). The average width of the implanted portion 413 here designates the transverse dimension measured (on average) parallel to the plane of the substrate 300 and located in the cross-sectional plane of the Figure 5 The depth of the implanted portion 413 is the dimension measured perpendicular to the plane of the substrate 300.

[0053] According to the invention, these conditions are chosen so as to obtain an average implantation width of the same order of magnitude (or even slightly greater) than the assumed size of the filament, i.e. typically between 5 nm and 10 nm. Advantageously, an angle α equal to 45° will be chosen and the implantation energy will be modulated to affect the implantation width.

[0054] In this preferred embodiment (where only the conductive layer 420 is etched, not the oxide layer 410), the ion implantation energy is preferably chosen (for a given type of ion) so that the average penetration depth of the ions is located inside the oxide layer 410. Thus, the ions hardly penetrate into the lower electrode 302 and do not risk altering its electrical behavior.

[0055] According to the invention, the implantation dose of the ions is, for its part, between 10 13< atoms.cm -2< and 10 16< atoms.cm -2< . Such a dose has the effect of reducing the forming voltage of the memory cell. For example, a dose of silicon ions implanted in a layer of HfO 2 between 2.10 15< cm -2< and 5.10 15< cm -2< makes it possible to reduce the forming voltage by more than 1 V.

[0056] There figure 6is a perspective view of two adjacent memory cells formed on the substrate 300. The two memory cells advantageously share the same lower electrode 302 (formed for example by a line) and the same oxide layer 410. They each have, however, a mesa-shaped upper electrode 440. The different upper electrodes have preferably been formed simultaneously from a single conductive layer 420, as described previously in relation to the Figure 4B The different cells or memory points of an OxRAM memory can thus be delimited only by their upper electrode 440.

[0057] The upper electrodes 440 advantageously have a width l of between 80 nm and 300 nm, and a length L (in the perpendicular direction) of between 80 nm and 300 nm. To achieve such dimensions, advanced lithography techniques, such as electron beam (e-beam) lithography, are not necessary.

[0058] The upper electrodes 440 of these two consecutive cells in the memory plane are spaced by a given distance S. The upper electrode of a memory cell must not obstruct the ion beam directed towards another memory cell. This condition on the implantation angle α can be approximated by the following relationship: tan α ≤ S h where h is the thickness of the upper electrode and S is the separation distance between the two electrodes.

[0059] Preferably, the ion beam is inclined relative to the exposed side of the electrode by an angle α of between 40° and 50°, for example 45°. This second, more restricted range makes it possible to simultaneously obtain localized areas of dimensions of the same order of magnitude as the thickness of the oxide layer and a high integration density of the memory cells.

[0060] Thus, this manufacturing process makes it possible to considerably limit the area of ​​formation of the conductive filament in the memory cell, also called the active area, thanks to an implantation of ions located under an edge of the upper electrode. For example, the surface area of ​​the active area of ​​a memory cell having a 5 nm thick oxide layer and implanted at an angle of 45° is equal to 1000 nm 2< (L = 200 nm xl 2 = 5 nm).

[0061] For comparison, the active area of ​​a memory cell measuring 200 nm on a side and in which no defect areas are expected has an area of ​​more than 40,000 nm 2< , at least 40 times larger than the implanted memory cell. To obtain the same active area with the conventional manufacturing process, it would be necessary to delimit a top electrode measuring about 30 nm on a side, which is complex and expensive to obtain in photolithography.

[0062] The manufacturing method may also comprise, after the ion implantation step S3, a step of encapsulating the memory cell, for example with silicon nitride (SiN) or silicon dioxide (SiO 2 ), and a step of resuming contact on the upper face of the upper electrode, for example by means of an interconnection pad (via) or an interconnection level (line).

[0063] Since there is no need to reduce the dimensions of the upper electrode to obtain a small active area, there are few constraints for performing the contact recovery on the upper electrode. The manufacturing method according to the invention therefore makes the end of memory integration easier.

[0064] Many variations and modifications of the manufacturing method described above will be apparent to those skilled in the art. In particular, in step S3 of the Figure 4C, the substrate 300 can be rotated during ion implantation. This has the effect of exposing all the sides of the upper electrode 440 to the inclined ion beam 450 and, consequently, of forming defects at the periphery of the memory cell (rather than on a single edge of the memory cell), i.e. on all the edges of the memory cell. The implantation step S3 can thus be implemented more easily. The surface area of ​​the active zone will, however, be larger.

[0065] Finally, although it is not necessary to make contact on the upper electrode, it is also possible to remove the protective layer 430 which served as an etching mask after the implantation step S3.

Claims

1. Process for manufacturing a resistive random access memory including the following steps: - depositing (S1) a layer made of an active material of variable electrical resistance (410) on a substrate (300) containing a first electrode (302), designated lower electrode; - depositing (S1) an electrically conductive layer (420) on the layer of active material; - etching (S2) the electrically conductive layer so as to delimit a second electrode (440), designated upper electrode, facing the lower electrode (302); - exposing (S3) at least one flank of the upper electrode (440) to an ion beam (450) inclined with respect to the normal to the substrate by an angle (α) comprised between 20° and 65°, so as to implant the ions in a portion (413) of the layer of active material (410) adjacent to said flank and situated under the upper electrode (440), characterized in that the ion implantation conditions are chosen so as to create defects in the structure of the active material and to obtain an average implantation width comprised between 5 nm and 10 nm and in that the ions are implanted at a dose comprised between 1013 atoms.cm-2 and 1016 atoms.cm-2.

2. Process according to claim 1, wherein the ion beam (450) is inclined with respect to the normal to the substrate (300) by an angle (α) comprised between 40° and 50°.

3. Process according to one of claims 1 and 2, wherein the layer of active material (410) serves as stop layer during the etching of the electrically conductive layer (420).

4. Process according to any of claims 1 to 3, wherein the ions are implanted with an energy such that the average penetration depth of the ions is situated within the layer of active material (410).

5. Process according to any of claims 1 to 4, including a step (S1) of depositing a protective material (430) on the electrically conductive layer (420) before the step (S2) of etching the electrically conductive layer.

6. Process according to any of claims 1 to 5, wherein the implanted ions are metal ions, oxygen ions, halogen ions, silicon ions or argon ions.

7. Process according to any of claims 1 to 6, wherein the electrically conductive layer (420) is etched so as to delimit at least two upper electrodes and wherein the angle of inclination α of the ion beam (450) is chosen such that tan α ≤ S h S being the minimum distance separating two electrodes and h the thickness of the electrically conductive layer.

8. Process according to any of claims 1 to 7, wherein the active material (410) is a transition metal oxide.